[deliverable/linux.git] / drivers / ata / pata_mpiix.c

/*
 * pata_mpiix.c 	- Intel MPIIX PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * The MPIIX is different enough to the PIIX4 and friends that we give it
 * a separate driver. The old ide/pci code handles this by just not tuning
 * MPIIX at all.
 *
 * The MPIIX also differs in another important way from the majority of PIIX
 * devices. The chip is a bridge (pardon the pun) between the old world of
 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
 * IDE controller is not decoded in PCI space and the chip does not claim to
 * be IDE class PCI. This requires slightly non-standard probe logic compared
 * with PCI IDE and also that we do not disable the device when our driver is
 * unloaded (as it has many other functions).
 *
 * The driver conciously keeps this logic internally to avoid pushing quirky
 * PATA history into the clean libata layer.
 *
 * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
 * hard disk present this driver will not detect it. This is not a bug. In this
 * configuration the secondary port of the MPIIX is disabled and the addresses
 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
 * to operate.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_mpiix"
#define DRV_VERSION "0.7.3"

enum {
	IDETIM = 0x6C,		/* IDE control register */
	IORDY = (1 << 1),
	PPE = (1 << 2),
	FTIM = (1 << 0),
	ENABLED = (1 << 15),
	SECONDARY = (1 << 14)
};

static int mpiix_pre_reset(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits mpiix_enable_bits[] = {
		{ 0x6D, 1, 0x80, 0x80 },
		{ 0x6F, 1, 0x80, 0x80 }
	};

	if (!pci_test_config_bits(pdev, &mpiix_enable_bits[ap->port_no]))
		return -ENOENT;
	ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}

/**
 *	mpiix_error_handler		-	probe reset
 *	@ap: ATA port
 *
 *	Perform the ATA probe and bus reset sequence plus specific handling
 *	for this hardware. The MPIIX has the enable bits in a different place
 *	to PIIX4 and friends. As a pure PIO device it has no cable detect
 */

static void mpiix_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	mpiix_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. The MPIIX allows us to program the
 *	IORDY sample point (2-5 clocks), recovery 1-4 clocks and whether
 *	prefetching or iordy are used.
 *
 *	This would get very ugly because we can only program timing for one
 *	device at a time, the other gets PIO0. Fortunately libata calls
 *	our qc_issue_prot command before a command is issued so we can
 *	flip the timings back and forth to reduce the pain.
 */

static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	int control = 0;
	int pio = adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 idetim;
	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pci_read_config_word(pdev, IDETIM, &idetim);
	/* Mask the IORDY/TIME/PPE0 bank for this device */
	if (adev->class == ATA_DEV_ATA)
		control |= PPE;		/* PPE enable for disk */
	if (ata_pio_need_iordy(adev))
		control |= IORDY;	/* IORDY */
	if (pio > 0)
		control |= FTIM;	/* This drive is on the fast timing bank */

	/* Mask out timing and clear both TIME bank selects */
	idetim &= 0xCCEE;
	idetim &= ~(0x07  << (2 * adev->devno));
	idetim |= (control << (2 * adev->devno));

	idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	pci_write_config_word(pdev, IDETIM, idetim);

	/* We use ap->private_data as a pointer to the device currently
	   loaded for timing */
	ap->private_data = adev;
}

/**
 *	mpiix_qc_issue_prot	-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	neccessary. Our logic also clears TIME0/TIME1 for the other device so
 *	that, even if we get this wrong, cycles to the other device will
 *	be made PIO0.
 */

static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	/* If modes have been configured and the channel data is not loaded
	   then load it. We have to check if pio_mode is set as the core code
	   does not set adev->pio_mode to XFER_PIO_0 while probing as would be
	   logical */

	if (adev->pio_mode && adev != ap->private_data)
		mpiix_set_piomode(ap, adev);

	return ata_qc_issue_prot(qc);
}

static struct scsi_host_template mpiix_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
};

static struct ata_port_operations mpiix_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= mpiix_set_piomode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= mpiix_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= mpiix_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
};

static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	/* Single threaded by the PCI probe logic */
	static struct ata_probe_ent probe;
	static int printed_version;
	void __iomem *cmd_addr, *ctl_addr;
	u16 idetim;
	int irq;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");

	/* MPIIX has many functions which can be turned on or off according
	   to other devices present. Make sure IDE is enabled before we try
	   and use it */

	pci_read_config_word(dev, IDETIM, &idetim);
	if (!(idetim & ENABLED))
		return -ENODEV;

	if (!(idetim & SECONDARY)) {
		irq = 14;
		cmd_addr = devm_ioport_map(&dev->dev, 0x1F0, 8);
		ctl_addr = devm_ioport_map(&dev->dev, 0x3F6, 1);
	} else {
		irq = 15;
		cmd_addr = devm_ioport_map(&dev->dev, 0x170, 8);
		ctl_addr = devm_ioport_map(&dev->dev, 0x376, 1);
	}

	if (!cmd_addr || !ctl_addr)
		return -ENOMEM;

	/* We do our own plumbing to avoid leaking special cases for whacko
	   ancient hardware into the core code. There are two issues to
	   worry about.  #1 The chip is a bridge so if in legacy mode and
	   without BARs set fools the setup.  #2 If you pci_disable_device
	   the MPIIX your box goes castors up */

	INIT_LIST_HEAD(&probe.node);
	probe.dev = pci_dev_to_dev(dev);
	probe.port_ops = &mpiix_port_ops;
	probe.sht = &mpiix_sht;
	probe.pio_mask = 0x1F;
	probe.irq = irq;
	probe.irq_flags = SA_SHIRQ;
	probe.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
	probe.n_ports = 1;
	probe.port[0].cmd_addr = cmd_addr;
	probe.port[0].ctl_addr = ctl_addr;
	probe.port[0].altstatus_addr = ctl_addr;

	/* Let libata fill in the port details */
	ata_std_ports(&probe.port[0]);

	/* Now add the port that is active */
	if (ata_device_add(&probe))
		return 0;
	return -ENODEV;
}

static const struct pci_device_id mpiix[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },

	{ },
};

static struct pci_driver mpiix_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= mpiix,
	.probe 		= mpiix_init_one,
	.remove		= ata_pci_remove_one,
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
};

static int __init mpiix_init(void)
{
	return pci_register_driver(&mpiix_pci_driver);
}

static void __exit mpiix_exit(void)
{
	pci_unregister_driver(&mpiix_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, mpiix);
MODULE_VERSION(DRV_VERSION);

module_init(mpiix_init);
module_exit(mpiix_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_mpiix.c - Intel MPIIX PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* The MPIIX is different enough to the PIIX4 and friends that we give it
	7	* a separate driver. The old ide/pci code handles this by just not tuning
	8	* MPIIX at all.
	9	*
	10	* The MPIIX also differs in another important way from the majority of PIIX
	11	* devices. The chip is a bridge (pardon the pun) between the old world of
	12	* ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
	13	* IDE controller is not decoded in PCI space and the chip does not claim to
	14	* be IDE class PCI. This requires slightly non-standard probe logic compared
	15	* with PCI IDE and also that we do not disable the device when our driver is
	16	* unloaded (as it has many other functions).
	17	*
	18	* The driver conciously keeps this logic internally to avoid pushing quirky
	19	* PATA history into the clean libata layer.
	20	*
c961922b	21	* Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
669a5db4 JG	22	* hard disk present this driver will not detect it. This is not a bug. In this
	23	* configuration the secondary port of the MPIIX is disabled and the addresses
	24	* are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
	25	* to operate.
	26	*/
	27
	28	#include <linux/kernel.h>
	29	#include <linux/module.h>
	30	#include <linux/pci.h>
	31	#include <linux/init.h>
	32	#include <linux/blkdev.h>
	33	#include <linux/delay.h>
	34	#include <scsi/scsi_host.h>
	35	#include <linux/libata.h>
	36
	37	#define DRV_NAME "pata_mpiix"
30ced0f0	38	#define DRV_VERSION "0.7.3"
669a5db4 JG	39
	40	enum {
	41	IDETIM = 0x6C, /* IDE control register */
	42	IORDY = (1 << 1),
	43	PPE = (1 << 2),
	44	FTIM = (1 << 0),
	45	ENABLED = (1 << 15),
	46	SECONDARY = (1 << 14)
	47	};
	48
	49	static int mpiix_pre_reset(struct ata_port *ap)
	50	{
	51	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	52	static const struct pci_bits mpiix_enable_bits[] = {
	53	{ 0x6D, 1, 0x80, 0x80 },
	54	{ 0x6F, 1, 0x80, 0x80 }
	55	};
	56
c961922b AC	57	if (!pci_test_config_bits(pdev, &mpiix_enable_bits[ap->port_no]))
c961922b AC	58	return -ENOENT;
669a5db4 JG	59	ap->cbl = ATA_CBL_PATA40;
	60	return ata_std_prereset(ap);
	61	}
	62
	63	/**
	64	* mpiix_error_handler - probe reset
	65	* @ap: ATA port
	66	*
	67	* Perform the ATA probe and bus reset sequence plus specific handling
	68	* for this hardware. The MPIIX has the enable bits in a different place
	69	* to PIIX4 and friends. As a pure PIO device it has no cable detect
	70	*/
	71
	72	static void mpiix_error_handler(struct ata_port *ap)
	73	{
	74	ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	75	}
	76
	77	/**
	78	* mpiix_set_piomode - set initial PIO mode data
	79	* @ap: ATA interface
	80	* @adev: ATA device
	81	*
	82	* Called to do the PIO mode setup. The MPIIX allows us to program the
	83	* IORDY sample point (2-5 clocks), recovery 1-4 clocks and whether
	84	* prefetching or iordy are used.
	85	*
	86	* This would get very ugly because we can only program timing for one
	87	* device at a time, the other gets PIO0. Fortunately libata calls
	88	* our qc_issue_prot command before a command is issued so we can
	89	* flip the timings back and forth to reduce the pain.
	90	*/
	91
	92	static void mpiix_set_piomode(struct ata_port ap, struct ata_device adev)
	93	{
	94	int control = 0;
	95	int pio = adev->pio_mode - XFER_PIO_0;
	96	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	97	u16 idetim;
	98	static const /* ISP RTC */
	99	u8 timings[][2] = { { 0, 0 },
	100	{ 0, 0 },
	101	{ 1, 0 },
	102	{ 2, 1 },
	103	{ 2, 3 }, };
	104
	105	pci_read_config_word(pdev, IDETIM, &idetim);
	106	/* Mask the IORDY/TIME/PPE0 bank for this device */
	107	if (adev->class == ATA_DEV_ATA)
	108	control \|= PPE; /* PPE enable for disk */
	109	if (ata_pio_need_iordy(adev))
	110	control \|= IORDY; /* IORDY */
	111	if (pio > 0)
	112	control \|= FTIM; /* This drive is on the fast timing bank */
	113
	114	/* Mask out timing and clear both TIME bank selects */
	115	idetim &= 0xCCEE;
	116	idetim &= ~(0x07 << (2 * adev->devno));
	117	idetim \|= (control << (2 * adev->devno));
	118
	119	idetim \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
	120	pci_write_config_word(pdev, IDETIM, idetim);
	121
	122	/* We use ap->private_data as a pointer to the device currently
123	loaded for timing */
124	ap->private_data = adev;
125	}
126
127	/**
128	* mpiix_qc_issue_prot - command issue
129	* @qc: command pending
130	*
131	* Called when the libata layer is about to issue a command. We wrap
132	* this interface so that we can load the correct ATA timings if
133	* neccessary. Our logic also clears TIME0/TIME1 for the other device so
134	* that, even if we get this wrong, cycles to the other device will
135	* be made PIO0.
136	*/
137
138	static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
139	{
140	struct ata_port *ap = qc->ap;
141	struct ata_device *adev = qc->dev;
142
143	/* If modes have been configured and the channel data is not loaded
144	then load it. We have to check if pio_mode is set as the core code
145	does not set adev->pio_mode to XFER_PIO_0 while probing as would be
146	logical */
147
148	if (adev->pio_mode && adev != ap->private_data)
149	mpiix_set_piomode(ap, adev);
150
151	return ata_qc_issue_prot(qc);
152	}
153
154	static struct scsi_host_template mpiix_sht = {
155	.module = THIS_MODULE,
156	.name = DRV_NAME,
157	.ioctl = ata_scsi_ioctl,
158	.queuecommand = ata_scsi_queuecmd,
159	.can_queue = ATA_DEF_QUEUE,
160	.this_id = ATA_SHT_THIS_ID,
161	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	162	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	163	.emulated = ATA_SHT_EMULATED,
	164	.use_clustering = ATA_SHT_USE_CLUSTERING,
	165	.proc_name = DRV_NAME,
	166	.dma_boundary = ATA_DMA_BOUNDARY,
	167	.slave_configure = ata_scsi_slave_config,
afdfe899	168	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	169	.bios_param = ata_std_bios_param,
30ced0f0 A	170	.resume = ata_scsi_device_resume,
30ced0f0 A	171	.suspend = ata_scsi_device_suspend,
669a5db4 JG	172	};
	173
	174	static struct ata_port_operations mpiix_port_ops = {
	175	.port_disable = ata_port_disable,
	176	.set_piomode = mpiix_set_piomode,
	177
	178	.tf_load = ata_tf_load,
	179	.tf_read = ata_tf_read,
	180	.check_status = ata_check_status,
	181	.exec_command = ata_exec_command,
	182	.dev_select = ata_std_dev_select,
	183
	184	.freeze = ata_bmdma_freeze,
	185	.thaw = ata_bmdma_thaw,
	186	.error_handler = mpiix_error_handler,
	187	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	188
	189	.qc_prep = ata_qc_prep,
	190	.qc_issue = mpiix_qc_issue_prot,
0d5ff566	191	.data_xfer = ata_data_xfer,
669a5db4 JG	192
	193	.irq_handler = ata_interrupt,
	194	.irq_clear = ata_bmdma_irq_clear,
	195
	196	.port_start = ata_port_start,
669a5db4 JG	197	};
	198
	199	static int mpiix_init_one(struct pci_dev dev, const struct pci_device_id id)
	200	{
	201	/* Single threaded by the PCI probe logic */
0d5ff566	202	static struct ata_probe_ent probe;
669a5db4	203	static int printed_version;
0d5ff566	204	void __iomem cmd_addr, ctl_addr;
669a5db4	205	u16 idetim;
0d5ff566	206	int irq;
669a5db4 JG	207
	208	if (!printed_version++)
	209	dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
	210
	211	/* MPIIX has many functions which can be turned on or off according
	212	to other devices present. Make sure IDE is enabled before we try
	213	and use it */
	214
	215	pci_read_config_word(dev, IDETIM, &idetim);
	216	if (!(idetim & ENABLED))
	217	return -ENODEV;
	218
0d5ff566 TH	219	if (!(idetim & SECONDARY)) {
	220	irq = 14;
	221	cmd_addr = devm_ioport_map(&dev->dev, 0x1F0, 8);
	222	ctl_addr = devm_ioport_map(&dev->dev, 0x3F6, 1);
	223	} else {
	224	irq = 15;
	225	cmd_addr = devm_ioport_map(&dev->dev, 0x170, 8);
	226	ctl_addr = devm_ioport_map(&dev->dev, 0x376, 1);
	227	}
	228
	229	if (!cmd_addr \|\| !ctl_addr)
	230	return -ENOMEM;
	231
669a5db4 JG	232	/* We do our own plumbing to avoid leaking special cases for whacko
	233	ancient hardware into the core code. There are two issues to
	234	worry about. #1 The chip is a bridge so if in legacy mode and
	235	without BARs set fools the setup. #2 If you pci_disable_device
	236	the MPIIX your box goes castors up */
	237
0d5ff566 TH	238	INIT_LIST_HEAD(&probe.node);
	239	probe.dev = pci_dev_to_dev(dev);
	240	probe.port_ops = &mpiix_port_ops;
	241	probe.sht = &mpiix_sht;
	242	probe.pio_mask = 0x1F;
	243	probe.irq = irq;
	244	probe.irq_flags = SA_SHIRQ;
	245	probe.port_flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST;
	246	probe.n_ports = 1;
	247	probe.port[0].cmd_addr = cmd_addr;
	248	probe.port[0].ctl_addr = ctl_addr;
	249	probe.port[0].altstatus_addr = ctl_addr;
669a5db4 JG	250
669a5db4 JG	251	/* Let libata fill in the port details */
0d5ff566	252	ata_std_ports(&probe.port[0]);
669a5db4 JG	253
669a5db4 JG	254	/* Now add the port that is active */
0d5ff566	255	if (ata_device_add(&probe))
669a5db4 JG	256	return 0;
	257	return -ENODEV;
	258	}
	259
669a5db4	260	static const struct pci_device_id mpiix[] = {
2d2744fc JG	261	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
	262
	263	{ },
669a5db4 JG	264	};
	265
	266	static struct pci_driver mpiix_pci_driver = {
	267	.name = DRV_NAME,
	268	.id_table = mpiix,
	269	.probe = mpiix_init_one,
24dc5f33	270	.remove = ata_pci_remove_one,
30ced0f0 A	271	.suspend = ata_pci_device_suspend,
30ced0f0 A	272	.resume = ata_pci_device_resume,
669a5db4 JG	273	};
	274
	275	static int __init mpiix_init(void)
	276	{
	277	return pci_register_driver(&mpiix_pci_driver);
	278	}
	279
669a5db4 JG	280	static void __exit mpiix_exit(void)
	281	{
	282	pci_unregister_driver(&mpiix_pci_driver);
	283	}
	284
669a5db4 JG	285	MODULE_AUTHOR("Alan Cox");
	286	MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
	287	MODULE_LICENSE("GPL");
	288	MODULE_DEVICE_TABLE(pci, mpiix);
	289	MODULE_VERSION(DRV_VERSION);
	290
	291	module_init(mpiix_init);
	292	module_exit(mpiix_exit);