[deliverable/linux.git] / drivers / ata / pata_pdc202xx_old.c

/*
 * pata_pdc202xx_old.c 	- Promise PDC202xx PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *			  (C) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
 *
 * First cut with LBA48/ATAPI
 *
 * TODO:
 *	Channel interlock/reset on both required ?
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_pdc202xx_old"
#define DRV_VERSION "0.4.3"

static int pdc2026x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 cis;

	pci_read_config_word(pdev, 0x50, &cis);
	if (cis & (1 << (10 + ap->port_no)))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	pdc202xx_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static u16 pio_timing[5] = {
		0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	};
	u8 r_ap, r_bp;

	pci_read_config_byte(pdev, port, &r_ap);
	pci_read_config_byte(pdev, port + 1, &r_bp);
	r_ap &= ~0x3F;	/* Preserve ERRDY_EN, SYNC_IN */
	r_bp &= ~0x1F;
	r_ap |= (pio_timing[pio] >> 8);
	r_bp |= (pio_timing[pio] & 0xFF);

	if (ata_pio_need_iordy(adev))
		r_ap |= 0x20;	/* IORDY enable */
	if (adev->class == ATA_DEV_ATA)
		r_ap |= 0x10;	/* FIFO enable */
	pci_write_config_byte(pdev, port, r_ap);
	pci_write_config_byte(pdev, port + 1, r_bp);
}

/**
 *	pdc202xx_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	pdc202xx_configure_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static u8 udma_timing[6][2] = {
		{ 0x60, 0x03 },	/* 33 Mhz Clock */
		{ 0x40, 0x02 },
		{ 0x20, 0x01 },
		{ 0x40, 0x02 },	/* 66 Mhz Clock */
		{ 0x20, 0x01 },
		{ 0x20, 0x01 }
	};
	static u8 mdma_timing[3][2] = {
		{ 0xe0, 0x0f },
		{ 0x60, 0x04 },
		{ 0x60, 0x03 },
	};
	u8 r_bp, r_cp;

	pci_read_config_byte(pdev, port + 1, &r_bp);
	pci_read_config_byte(pdev, port + 2, &r_cp);

	r_bp &= ~0xE0;
	r_cp &= ~0x0F;

	if (adev->dma_mode >= XFER_UDMA_0) {
		int speed = adev->dma_mode - XFER_UDMA_0;
		r_bp |= udma_timing[speed][0];
		r_cp |= udma_timing[speed][1];

	} else {
		int speed = adev->dma_mode - XFER_MW_DMA_0;
		r_bp |= mdma_timing[speed][0];
		r_cp |= mdma_timing[speed][1];
	}
	pci_write_config_byte(pdev, port + 1, r_bp);
	pci_write_config_byte(pdev, port + 2, r_cp);

}

/**
 *	pdc2026x_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	In UDMA3 or higher we have to clock switch for the duration of the
 *	DMA transfer sequence.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;
	int sel66 = ap->port_no ? 0x08: 0x02;

	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	u32 len;

	/* Check we keep host level locking here */
	if (adev->dma_mode >= XFER_UDMA_2)
		iowrite8(ioread8(clock) | sel66, clock);
	else
		iowrite8(ioread8(clock) & ~sel66, clock);

	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
	   and move to qc_issue ? */
	pdc202xx_set_dmamode(ap, qc->dev);

	/* Cases the state machine will not complete correctly without help */
	if ((tf->flags & ATA_TFLAG_LBA48) ||  tf->protocol == ATAPI_PROT_DMA) {
		len = qc->nbytes / 2;

		if (tf->flags & ATA_TFLAG_WRITE)
			len |= 0x06000000;
		else
			len |= 0x05000000;

		iowrite32(len, atapi_reg);
	}

	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	pdc2026x_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	After a DMA completes we need to put the clock back to 33MHz for
 *	PIO timings.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;

	int sel66 = ap->port_no ? 0x08: 0x02;
	/* The clock bits are in the same register for both channels */
	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	/* Cases the state machine will not complete correctly */
	if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
		iowrite32(0, atapi_reg);
		iowrite8(ioread8(clock) & ~sel66, clock);
	}
	/* Flip back to 33Mhz for PIO */
	if (adev->dma_mode >= XFER_UDMA_2)
		iowrite8(ioread8(clock) & ~sel66, clock);
	ata_bmdma_stop(qc);
	pdc202xx_set_piomode(ap, adev);
}

/**
 *	pdc2026x_dev_config	-	device setup hook
 *	@adev: newly found device
 *
 *	Perform chip specific early setup. We need to lock the transfer
 *	sizes to 8bit to avoid making the state engine on the 2026x cards
 *	barf.
 */

static void pdc2026x_dev_config(struct ata_device *adev)
{
	adev->max_sectors = 256;
}

static int pdc2026x_port_start(struct ata_port *ap)
{
	void __iomem *bmdma = ap->ioaddr.bmdma_addr;
	if (bmdma) {
		/* Enable burst mode */
		u8 burst = ioread8(bmdma + 0x1f);
		iowrite8(burst | 0x01, bmdma + 0x1f);
	}
	return ata_sff_port_start(ap);
}

/**
 *	pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
 *	@qc: Metadata associated with taskfile to check
 *
 *	Just say no - not supported on older Promise.
 *
 *	LOCKING:
 *	None (inherited from caller).
 *
 *	RETURNS: 0 when ATAPI DMA can be used
 *		 1 otherwise
 */

static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;
}

static struct scsi_host_template pdc202xx_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations pdc2024x_port_ops = {
	.set_piomode	= pdc202xx_set_piomode,
	.set_dmamode	= pdc202xx_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

static struct ata_port_operations pdc2026x_port_ops = {
	.set_piomode	= pdc202xx_set_piomode,
	.set_dmamode	= pdc202xx_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,
	.dev_config	= pdc2026x_dev_config,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= pdc2026x_cable_detect,

	.check_atapi_dma= pdc2026x_check_atapi_dma,
	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= pdc2026x_bmdma_start,
	.bmdma_stop	= pdc2026x_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= pdc2026x_port_start,
};

static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[3] = {
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA2,
			.port_ops = &pdc2024x_port_ops
		},
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,
			.port_ops = &pdc2026x_port_ops
		},
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,
			.port_ops = &pdc2026x_port_ops
		}

	};
	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };

	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;
		/* Don't grab anything behind a Promise I2O RAID */
		if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
			if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
				return -ENODEV;
			if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
				return -ENODEV;
		}
	}
	return ata_pci_init_one(dev, ppi);
}

static const struct pci_device_id pdc202xx[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },

	{ },
};

static struct pci_driver pdc202xx_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= pdc202xx,
	.probe 		= pdc202xx_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init pdc202xx_init(void)
{
	return pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pdc202xx);
MODULE_VERSION(DRV_VERSION);

module_init(pdc202xx_init);
module_exit(pdc202xx_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
63ed7101	5	* (C) 2007 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
	8	*
	9	* First cut with LBA48/ATAPI
	10	*
	11	* TODO:
06b74dd2	12	* Channel interlock/reset on both required ?
669a5db4	13	*/
85cd7251	14
669a5db4 JG	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/blkdev.h>
	20	#include <linux/delay.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
	23
	24	#define DRV_NAME "pata_pdc202xx_old"
06b74dd2	25	#define DRV_VERSION "0.4.3"
669a5db4	26
a0fcdc02	27	static int pdc2026x_cable_detect(struct ata_port *ap)
669a5db4 JG	28	{
	29	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	30	u16 cis;
85cd7251	31
669a5db4 JG	32	pci_read_config_word(pdev, 0x50, &cis);
669a5db4 JG	33	if (cis & (1 << (10 + ap->port_no)))
a0ac38f1 AC	34	return ATA_CBL_PATA40;
a0ac38f1 AC	35	return ATA_CBL_PATA80;
669a5db4 JG	36	}
	37
	38	/**
ada406c8	39	* pdc202xx_configure_piomode - set chip PIO timing
669a5db4 JG	40	* @ap: ATA interface
	41	* @adev: ATA device
	42	* @pio: PIO mode
	43	*
	44	* Called to do the PIO mode setup. Our timing registers are shared
	45	* so a configure_dmamode call will undo any work we do here and vice
	46	* versa
	47	*/
85cd7251	48
ada406c8	49	static void pdc202xx_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
669a5db4 JG	50	{
669a5db4 JG	51	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	52	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
669a5db4 JG	53	static u16 pio_timing[5] = {
	54	0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	55	};
	56	u8 r_ap, r_bp;
	57
	58	pci_read_config_byte(pdev, port, &r_ap);
	59	pci_read_config_byte(pdev, port + 1, &r_bp);
	60	r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
63ed7101	61	r_bp &= ~0x1F;
669a5db4 JG	62	r_ap \|= (pio_timing[pio] >> 8);
669a5db4 JG	63	r_bp \|= (pio_timing[pio] & 0xFF);
85cd7251	64
669a5db4 JG	65	if (ata_pio_need_iordy(adev))
	66	r_ap \|= 0x20; /* IORDY enable */
	67	if (adev->class == ATA_DEV_ATA)
	68	r_ap \|= 0x10; /* FIFO enable */
	69	pci_write_config_byte(pdev, port, r_ap);
	70	pci_write_config_byte(pdev, port + 1, r_bp);
	71	}
	72
	73	/**
ada406c8	74	* pdc202xx_set_piomode - set initial PIO mode data
669a5db4 JG	75	* @ap: ATA interface
	76	* @adev: ATA device
	77	*
	78	* Called to do the PIO mode setup. Our timing registers are shared
	79	* but we want to set the PIO timing by default.
	80	*/
85cd7251	81
ada406c8	82	static void pdc202xx_set_piomode(struct ata_port ap, struct ata_device adev)
669a5db4	83	{
ada406c8	84	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
669a5db4 JG	85	}
	86
	87	/**
ada406c8	88	* pdc202xx_configure_dmamode - set DMA mode in chip
669a5db4 JG	89	* @ap: ATA interface
	90	* @adev: ATA device
	91	*
	92	* Load DMA cycle times into the chip ready for a DMA transfer
	93	* to occur.
	94	*/
85cd7251	95
ada406c8	96	static void pdc202xx_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	97	{
669a5db4 JG	98	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	99	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
669a5db4 JG	100	static u8 udma_timing[6][2] = {
	101	{ 0x60, 0x03 }, /* 33 Mhz Clock */
	102	{ 0x40, 0x02 },
	103	{ 0x20, 0x01 },
	104	{ 0x40, 0x02 }, /* 66 Mhz Clock */
	105	{ 0x20, 0x01 },
85cd7251	106	{ 0x20, 0x01 }
669a5db4	107	};
63ed7101	108	static u8 mdma_timing[3][2] = {
63ed7101	109	{ 0xe0, 0x0f },
06b74dd2 AC	110	{ 0x60, 0x04 },
06b74dd2 AC	111	{ 0x60, 0x03 },
63ed7101	112	};
669a5db4	113	u8 r_bp, r_cp;
85cd7251	114
669a5db4 JG	115	pci_read_config_byte(pdev, port + 1, &r_bp);
669a5db4 JG	116	pci_read_config_byte(pdev, port + 2, &r_cp);
85cd7251	117
63ed7101	118	r_bp &= ~0xE0;
669a5db4	119	r_cp &= ~0x0F;
85cd7251	120
669a5db4 JG	121	if (adev->dma_mode >= XFER_UDMA_0) {
	122	int speed = adev->dma_mode - XFER_UDMA_0;
	123	r_bp \|= udma_timing[speed][0];
	124	r_cp \|= udma_timing[speed][1];
85cd7251	125
669a5db4 JG	126	} else {
669a5db4 JG	127	int speed = adev->dma_mode - XFER_MW_DMA_0;
63ed7101 BZ	128	r_bp \|= mdma_timing[speed][0];
63ed7101 BZ	129	r_cp \|= mdma_timing[speed][1];
669a5db4 JG	130	}
	131	pci_write_config_byte(pdev, port + 1, r_bp);
	132	pci_write_config_byte(pdev, port + 2, r_cp);
85cd7251	133
669a5db4 JG	134	}
	135
	136	/**
	137	* pdc2026x_bmdma_start - DMA engine begin
	138	* @qc: ATA command
	139	*
	140	* In UDMA3 or higher we have to clock switch for the duration of the
	141	* DMA transfer sequence.
06b74dd2 AC	142	*
	143	* Note: The host lock held by the libata layer protects
	144	* us from two channels both trying to set DMA bits at once
669a5db4	145	*/
85cd7251	146
669a5db4 JG	147	static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
	148	{
	149	struct ata_port *ap = qc->ap;
	150	struct ata_device *adev = qc->dev;
	151	struct ata_taskfile *tf = &qc->tf;
	152	int sel66 = ap->port_no ? 0x08: 0x02;
	153
0d5ff566 TH	154	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	155	void __iomem *clock = master + 0x11;
	156	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	157
669a5db4	158	u32 len;
85cd7251	159
669a5db4 JG	160	/* Check we keep host level locking here */
669a5db4 JG	161	if (adev->dma_mode >= XFER_UDMA_2)
0d5ff566	162	iowrite8(ioread8(clock) \| sel66, clock);
669a5db4	163	else
0d5ff566	164	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	165
85cd7251	166	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
669a5db4	167	and move to qc_issue ? */
ada406c8	168	pdc202xx_set_dmamode(ap, qc->dev);
669a5db4 JG	169
669a5db4 JG	170	/* Cases the state machine will not complete correctly without help */
0dc36888	171	if ((tf->flags & ATA_TFLAG_LBA48) \|\| tf->protocol == ATAPI_PROT_DMA) {
5e518810	172	len = qc->nbytes / 2;
85cd7251	173
669a5db4 JG	174	if (tf->flags & ATA_TFLAG_WRITE)
	175	len \|= 0x06000000;
	176	else
	177	len \|= 0x05000000;
85cd7251	178
0d5ff566	179	iowrite32(len, atapi_reg);
669a5db4	180	}
85cd7251 JG	181
85cd7251 JG	182	/* Activate DMA */
669a5db4 JG	183	ata_bmdma_start(qc);
	184	}
	185
	186	/**
	187	* pdc2026x_bmdma_end - DMA engine stop
	188	* @qc: ATA command
	189	*
	190	* After a DMA completes we need to put the clock back to 33MHz for
	191	* PIO timings.
06b74dd2 AC	192	*
	193	* Note: The host lock held by the libata layer protects
	194	* us from two channels both trying to set DMA bits at once
669a5db4	195	*/
85cd7251	196
669a5db4 JG	197	static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
	198	{
	199	struct ata_port *ap = qc->ap;
	200	struct ata_device *adev = qc->dev;
	201	struct ata_taskfile *tf = &qc->tf;
85cd7251	202
669a5db4 JG	203	int sel66 = ap->port_no ? 0x08: 0x02;
669a5db4 JG	204	/* The clock bits are in the same register for both channels */
0d5ff566 TH	205	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	206	void __iomem *clock = master + 0x11;
	207	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	208
669a5db4	209	/* Cases the state machine will not complete correctly */
0dc36888	210	if (tf->protocol == ATAPI_PROT_DMA \|\| (tf->flags & ATA_TFLAG_LBA48)) {
0d5ff566 TH	211	iowrite32(0, atapi_reg);
0d5ff566 TH	212	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	213	}
669a5db4 JG	214	/* Flip back to 33Mhz for PIO */
669a5db4 JG	215	if (adev->dma_mode >= XFER_UDMA_2)
0d5ff566	216	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	217	ata_bmdma_stop(qc);
36906d9b	218	pdc202xx_set_piomode(ap, adev);
669a5db4 JG	219	}
	220
	221	/**
	222	* pdc2026x_dev_config - device setup hook
669a5db4 JG	223	* @adev: newly found device
	224	*
	225	* Perform chip specific early setup. We need to lock the transfer
	226	* sizes to 8bit to avoid making the state engine on the 2026x cards
	227	* barf.
	228	*/
85cd7251	229
cd0d3bbc	230	static void pdc2026x_dev_config(struct ata_device *adev)
669a5db4 JG	231	{
	232	adev->max_sectors = 256;
	233	}
	234
36906d9b AC	235	static int pdc2026x_port_start(struct ata_port *ap)
	236	{
	237	void __iomem *bmdma = ap->ioaddr.bmdma_addr;
	238	if (bmdma) {
	239	/* Enable burst mode */
	240	u8 burst = ioread8(bmdma + 0x1f);
	241	iowrite8(burst \| 0x01, bmdma + 0x1f);
	242	}
	243	return ata_sff_port_start(ap);
	244	}
	245
aa8f2371 AC	246	/**
	247	* pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
	248	* @qc: Metadata associated with taskfile to check
	249	*
	250	* Just say no - not supported on older Promise.
	251	*
	252	* LOCKING:
	253	* None (inherited from caller).
	254	*
	255	* RETURNS: 0 when ATAPI DMA can be used
	256	* 1 otherwise
	257	*/
	258
	259	static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
	260	{
	261	return 1;
	262	}
	263
ada406c8	264	static struct scsi_host_template pdc202xx_sht = {
669a5db4 JG	265	.module = THIS_MODULE,
	266	.name = DRV_NAME,
	267	.ioctl = ata_scsi_ioctl,
	268	.queuecommand = ata_scsi_queuecmd,
	269	.can_queue = ATA_DEF_QUEUE,
	270	.this_id = ATA_SHT_THIS_ID,
	271	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	272	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	273	.emulated = ATA_SHT_EMULATED,
	274	.use_clustering = ATA_SHT_USE_CLUSTERING,
	275	.proc_name = DRV_NAME,
	276	.dma_boundary = ATA_DMA_BOUNDARY,
	277	.slave_configure = ata_scsi_slave_config,
afdfe899	278	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	279	.bios_param = ata_std_bios_param,
	280	};
	281
	282	static struct ata_port_operations pdc2024x_port_ops = {
ada406c8 AC	283	.set_piomode = pdc202xx_set_piomode,
ada406c8 AC	284	.set_dmamode = pdc202xx_set_dmamode,
669a5db4 JG	285	.mode_filter = ata_pci_default_filter,
	286	.tf_load = ata_tf_load,
	287	.tf_read = ata_tf_read,
	288	.check_status = ata_check_status,
	289	.exec_command = ata_exec_command,
	290	.dev_select = ata_std_dev_select,
	291
	292	.freeze = ata_bmdma_freeze,
	293	.thaw = ata_bmdma_thaw,
a0fcdc02	294	.error_handler = ata_bmdma_error_handler,
669a5db4	295	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	296	.cable_detect = ata_cable_40wire,
669a5db4 JG	297
	298	.bmdma_setup = ata_bmdma_setup,
	299	.bmdma_start = ata_bmdma_start,
	300	.bmdma_stop = ata_bmdma_stop,
	301	.bmdma_status = ata_bmdma_status,
	302
	303	.qc_prep = ata_qc_prep,
	304	.qc_issue = ata_qc_issue_prot,
0d5ff566	305	.data_xfer = ata_data_xfer,
669a5db4 JG	306
	307	.irq_handler = ata_interrupt,
	308	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	309	.irq_on = ata_irq_on,
85cd7251	310
81ad1837	311	.port_start = ata_sff_port_start,
85cd7251	312	};
669a5db4 JG	313
669a5db4 JG	314	static struct ata_port_operations pdc2026x_port_ops = {
ada406c8 AC	315	.set_piomode = pdc202xx_set_piomode,
ada406c8 AC	316	.set_dmamode = pdc202xx_set_dmamode,
669a5db4 JG	317	.mode_filter = ata_pci_default_filter,
	318	.tf_load = ata_tf_load,
	319	.tf_read = ata_tf_read,
	320	.check_status = ata_check_status,
	321	.exec_command = ata_exec_command,
	322	.dev_select = ata_std_dev_select,
	323	.dev_config = pdc2026x_dev_config,
	324
	325	.freeze = ata_bmdma_freeze,
	326	.thaw = ata_bmdma_thaw,
a0fcdc02	327	.error_handler = ata_bmdma_error_handler,
669a5db4	328	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	329	.cable_detect = pdc2026x_cable_detect,
669a5db4	330
aa8f2371	331	.check_atapi_dma= pdc2026x_check_atapi_dma,
669a5db4 JG	332	.bmdma_setup = ata_bmdma_setup,
	333	.bmdma_start = pdc2026x_bmdma_start,
	334	.bmdma_stop = pdc2026x_bmdma_stop,
	335	.bmdma_status = ata_bmdma_status,
	336
	337	.qc_prep = ata_qc_prep,
	338	.qc_issue = ata_qc_issue_prot,
0d5ff566	339	.data_xfer = ata_data_xfer,
669a5db4 JG	340
	341	.irq_handler = ata_interrupt,
	342	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	343	.irq_on = ata_irq_on,
85cd7251	344
36906d9b	345	.port_start = pdc2026x_port_start,
85cd7251	346	};
669a5db4	347
ada406c8	348	static int pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4	349	{
1626aeb8	350	static const struct ata_port_info info[3] = {
669a5db4	351	{
ada406c8	352	.sht = &pdc202xx_sht,
1d2808fd	353	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	354	.pio_mask = 0x1f,
	355	.mwdma_mask = 0x07,
	356	.udma_mask = ATA_UDMA2,
	357	.port_ops = &pdc2024x_port_ops
85cd7251	358	},
669a5db4	359	{
ada406c8	360	.sht = &pdc202xx_sht,
1d2808fd	361	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	362	.pio_mask = 0x1f,
	363	.mwdma_mask = 0x07,
	364	.udma_mask = ATA_UDMA4,
	365	.port_ops = &pdc2026x_port_ops
	366	},
	367	{
ada406c8	368	.sht = &pdc202xx_sht,
1d2808fd	369	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	370	.pio_mask = 0x1f,
	371	.mwdma_mask = 0x07,
	372	.udma_mask = ATA_UDMA5,
	373	.port_ops = &pdc2026x_port_ops
	374	}
85cd7251	375
669a5db4	376	};
1626aeb8	377	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
85cd7251	378
669a5db4 JG	379	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
	380	struct pci_dev *bridge = dev->bus->self;
	381	/* Don't grab anything behind a Promise I2O RAID */
	382	if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
b447916e	383	if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
669a5db4	384	return -ENODEV;
b447916e	385	if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
669a5db4 JG	386	return -ENODEV;
	387	}
	388	}
1626aeb8	389	return ata_pci_init_one(dev, ppi);
669a5db4 JG	390	}
669a5db4 JG	391
ada406c8	392	static const struct pci_device_id pdc202xx[] = {
2d2744fc JG	393	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	394	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	395	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	396	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	397	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	398
	399	{ },
669a5db4 JG	400	};
669a5db4 JG	401
ada406c8	402	static struct pci_driver pdc202xx_pci_driver = {
2d2744fc	403	.name = DRV_NAME,
ada406c8 AC	404	.id_table = pdc202xx,
ada406c8 AC	405	.probe = pdc202xx_init_one,
62d64ae0	406	.remove = ata_pci_remove_one,
438ac6d5	407	#ifdef CONFIG_PM
62d64ae0 A	408	.suspend = ata_pci_device_suspend,
62d64ae0 A	409	.resume = ata_pci_device_resume,
438ac6d5	410	#endif
669a5db4 JG	411	};
669a5db4 JG	412
ada406c8	413	static int __init pdc202xx_init(void)
669a5db4	414	{
ada406c8	415	return pci_register_driver(&pdc202xx_pci_driver);
669a5db4 JG	416	}
669a5db4 JG	417
ada406c8	418	static void __exit pdc202xx_exit(void)
669a5db4	419	{
ada406c8	420	pci_unregister_driver(&pdc202xx_pci_driver);
669a5db4 JG	421	}
669a5db4 JG	422
669a5db4 JG	423	MODULE_AUTHOR("Alan Cox");
	424	MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
	425	MODULE_LICENSE("GPL");
ada406c8	426	MODULE_DEVICE_TABLE(pci, pdc202xx);
669a5db4 JG	427	MODULE_VERSION(DRV_VERSION);
669a5db4 JG	428
ada406c8 AC	429	module_init(pdc202xx_init);
ada406c8 AC	430	module_exit(pdc202xx_exit);