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a619f981 AI |
1 | /* |
2 | * Support for IDE interfaces on Celleb platform | |
3 | * | |
4 | * (C) Copyright 2006 TOSHIBA CORPORATION | |
5 | * | |
6 | * This code is based on drivers/ata/ata_piix.c: | |
7 | * Copyright 2003-2005 Red Hat Inc | |
8 | * Copyright 2003-2005 Jeff Garzik | |
9 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
10 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
ab771630 | 11 | * Copyright (C) 2003 Red Hat Inc |
a619f981 AI |
12 | * |
13 | * and drivers/ata/ahci.c: | |
14 | * Copyright 2004-2005 Red Hat, Inc. | |
15 | * | |
16 | * and drivers/ata/libata-core.c: | |
17 | * Copyright 2003-2004 Red Hat, Inc. All rights reserved. | |
18 | * Copyright 2003-2004 Jeff Garzik | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License along | |
31 | * with this program; if not, write to the Free Software Foundation, Inc., | |
32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
a619f981 AI |
38 | #include <linux/blkdev.h> |
39 | #include <linux/delay.h> | |
40 | #include <linux/device.h> | |
41 | #include <scsi/scsi_host.h> | |
42 | #include <linux/libata.h> | |
43 | ||
44 | #define DRV_NAME "pata_scc" | |
2a3103ce | 45 | #define DRV_VERSION "0.3" |
a619f981 AI |
46 | |
47 | #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 | |
48 | ||
49 | /* PCI BARs */ | |
50 | #define SCC_CTRL_BAR 0 | |
51 | #define SCC_BMID_BAR 1 | |
52 | ||
53 | /* offset of CTRL registers */ | |
54 | #define SCC_CTL_PIOSHT 0x000 | |
55 | #define SCC_CTL_PIOCT 0x004 | |
56 | #define SCC_CTL_MDMACT 0x008 | |
57 | #define SCC_CTL_MCRCST 0x00C | |
58 | #define SCC_CTL_SDMACT 0x010 | |
59 | #define SCC_CTL_SCRCST 0x014 | |
60 | #define SCC_CTL_UDENVT 0x018 | |
61 | #define SCC_CTL_TDVHSEL 0x020 | |
62 | #define SCC_CTL_MODEREG 0x024 | |
63 | #define SCC_CTL_ECMODE 0xF00 | |
64 | #define SCC_CTL_MAEA0 0xF50 | |
65 | #define SCC_CTL_MAEC0 0xF54 | |
66 | #define SCC_CTL_CCKCTRL 0xFF0 | |
67 | ||
68 | /* offset of BMID registers */ | |
69 | #define SCC_DMA_CMD 0x000 | |
70 | #define SCC_DMA_STATUS 0x004 | |
71 | #define SCC_DMA_TABLE_OFS 0x008 | |
72 | #define SCC_DMA_INTMASK 0x010 | |
73 | #define SCC_DMA_INTST 0x014 | |
74 | #define SCC_DMA_PTERADD 0x018 | |
75 | #define SCC_REG_CMD_ADDR 0x020 | |
76 | #define SCC_REG_DATA 0x000 | |
77 | #define SCC_REG_ERR 0x004 | |
78 | #define SCC_REG_FEATURE 0x004 | |
79 | #define SCC_REG_NSECT 0x008 | |
80 | #define SCC_REG_LBAL 0x00C | |
81 | #define SCC_REG_LBAM 0x010 | |
82 | #define SCC_REG_LBAH 0x014 | |
83 | #define SCC_REG_DEVICE 0x018 | |
84 | #define SCC_REG_STATUS 0x01C | |
85 | #define SCC_REG_CMD 0x01C | |
86 | #define SCC_REG_ALTSTATUS 0x020 | |
87 | ||
88 | /* register value */ | |
89 | #define TDVHSEL_MASTER 0x00000001 | |
90 | #define TDVHSEL_SLAVE 0x00000004 | |
91 | ||
92 | #define MODE_JCUSFEN 0x00000080 | |
93 | ||
94 | #define ECMODE_VALUE 0x01 | |
95 | ||
96 | #define CCKCTRL_ATARESET 0x00040000 | |
97 | #define CCKCTRL_BUFCNT 0x00020000 | |
98 | #define CCKCTRL_CRST 0x00010000 | |
99 | #define CCKCTRL_OCLKEN 0x00000100 | |
100 | #define CCKCTRL_ATACLKOEN 0x00000002 | |
101 | #define CCKCTRL_LCLKEN 0x00000001 | |
102 | ||
103 | #define QCHCD_IOS_SS 0x00000001 | |
104 | ||
105 | #define QCHSD_STPDIAG 0x00020000 | |
106 | ||
107 | #define INTMASK_MSK 0xD1000012 | |
108 | #define INTSTS_SERROR 0x80000000 | |
109 | #define INTSTS_PRERR 0x40000000 | |
110 | #define INTSTS_RERR 0x10000000 | |
111 | #define INTSTS_ICERR 0x01000000 | |
112 | #define INTSTS_BMSINT 0x00000010 | |
113 | #define INTSTS_BMHE 0x00000008 | |
114 | #define INTSTS_IOIRQS 0x00000004 | |
115 | #define INTSTS_INTRQ 0x00000002 | |
116 | #define INTSTS_ACTEINT 0x00000001 | |
117 | ||
118 | ||
119 | /* PIO transfer mode table */ | |
120 | /* JCHST */ | |
121 | static const unsigned long JCHSTtbl[2][7] = { | |
122 | {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ | |
123 | {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ | |
124 | }; | |
125 | ||
126 | /* JCHHT */ | |
127 | static const unsigned long JCHHTtbl[2][7] = { | |
128 | {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ | |
129 | {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ | |
130 | }; | |
131 | ||
132 | /* JCHCT */ | |
133 | static const unsigned long JCHCTtbl[2][7] = { | |
134 | {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ | |
135 | {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ | |
136 | }; | |
137 | ||
138 | /* DMA transfer mode table */ | |
139 | /* JCHDCTM/JCHDCTS */ | |
140 | static const unsigned long JCHDCTxtbl[2][7] = { | |
141 | {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ | |
142 | {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ | |
143 | }; | |
144 | ||
145 | /* JCSTWTM/JCSTWTS */ | |
146 | static const unsigned long JCSTWTxtbl[2][7] = { | |
147 | {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ | |
148 | {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
149 | }; | |
150 | ||
151 | /* JCTSS */ | |
152 | static const unsigned long JCTSStbl[2][7] = { | |
153 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ | |
154 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ | |
155 | }; | |
156 | ||
157 | /* JCENVT */ | |
158 | static const unsigned long JCENVTtbl[2][7] = { | |
159 | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ | |
160 | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
161 | }; | |
162 | ||
163 | /* JCACTSELS/JCACTSELM */ | |
164 | static const unsigned long JCACTSELtbl[2][7] = { | |
165 | {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ | |
166 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ | |
167 | }; | |
168 | ||
169 | static const struct pci_device_id scc_pci_tbl[] = { | |
af4d6e25 | 170 | { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0}, |
a619f981 AI |
171 | { } /* terminate list */ |
172 | }; | |
173 | ||
174 | /** | |
175 | * scc_set_piomode - Initialize host controller PATA PIO timings | |
176 | * @ap: Port whose timings we are configuring | |
177 | * @adev: um | |
178 | * | |
179 | * Set PIO mode for device. | |
180 | * | |
181 | * LOCKING: | |
182 | * None (inherited from caller). | |
183 | */ | |
184 | ||
185 | static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
186 | { | |
187 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
188 | void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; | |
189 | void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; | |
190 | void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT; | |
191 | void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT; | |
192 | unsigned long reg; | |
193 | int offset; | |
194 | ||
195 | reg = in_be32(cckctrl_port); | |
196 | if (reg & CCKCTRL_ATACLKOEN) | |
197 | offset = 1; /* 133MHz */ | |
198 | else | |
199 | offset = 0; /* 100MHz */ | |
200 | ||
201 | reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; | |
202 | out_be32(piosht_port, reg); | |
203 | reg = JCHCTtbl[offset][pio]; | |
204 | out_be32(pioct_port, reg); | |
205 | } | |
206 | ||
207 | /** | |
208 | * scc_set_dmamode - Initialize host controller PATA DMA timings | |
209 | * @ap: Port whose timings we are configuring | |
210 | * @adev: um | |
a619f981 AI |
211 | * |
212 | * Set UDMA mode for device. | |
213 | * | |
214 | * LOCKING: | |
215 | * None (inherited from caller). | |
216 | */ | |
217 | ||
218 | static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
219 | { | |
220 | unsigned int udma = adev->dma_mode; | |
221 | unsigned int is_slave = (adev->devno != 0); | |
222 | u8 speed = udma; | |
223 | void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; | |
224 | void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; | |
225 | void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT; | |
226 | void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST; | |
227 | void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT; | |
228 | void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST; | |
229 | void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT; | |
230 | void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL; | |
231 | int offset, idx; | |
232 | ||
a84471fe | 233 | if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN) |
a619f981 AI |
234 | offset = 1; /* 133MHz */ |
235 | else | |
236 | offset = 0; /* 100MHz */ | |
237 | ||
238 | if (speed >= XFER_UDMA_0) | |
239 | idx = speed - XFER_UDMA_0; | |
240 | else | |
241 | return; | |
242 | ||
243 | if (is_slave) { | |
244 | out_be32(sdmact_port, JCHDCTxtbl[offset][idx]); | |
245 | out_be32(scrcst_port, JCSTWTxtbl[offset][idx]); | |
246 | out_be32(tdvhsel_port, | |
247 | (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2)); | |
248 | } else { | |
249 | out_be32(mdmact_port, JCHDCTxtbl[offset][idx]); | |
250 | out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]); | |
251 | out_be32(tdvhsel_port, | |
252 | (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]); | |
253 | } | |
254 | out_be32(udenvt_port, | |
255 | JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]); | |
256 | } | |
257 | ||
dcd03447 AI |
258 | unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask) |
259 | { | |
260 | /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */ | |
261 | if (adev->class == ATA_DEV_ATAPI && | |
262 | (mask & (0xE0 << ATA_SHIFT_UDMA))) { | |
263 | printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME); | |
264 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); | |
265 | } | |
c7087652 | 266 | return mask; |
dcd03447 AI |
267 | } |
268 | ||
a619f981 AI |
269 | /** |
270 | * scc_tf_load - send taskfile registers to host controller | |
271 | * @ap: Port to which output is sent | |
272 | * @tf: ATA taskfile register set | |
273 | * | |
9363c382 | 274 | * Note: Original code is ata_sff_tf_load(). |
a619f981 AI |
275 | */ |
276 | ||
277 | static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf) | |
278 | { | |
279 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
280 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
281 | ||
282 | if (tf->ctl != ap->last_ctl) { | |
283 | out_be32(ioaddr->ctl_addr, tf->ctl); | |
284 | ap->last_ctl = tf->ctl; | |
285 | ata_wait_idle(ap); | |
286 | } | |
287 | ||
288 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
289 | out_be32(ioaddr->feature_addr, tf->hob_feature); | |
290 | out_be32(ioaddr->nsect_addr, tf->hob_nsect); | |
291 | out_be32(ioaddr->lbal_addr, tf->hob_lbal); | |
292 | out_be32(ioaddr->lbam_addr, tf->hob_lbam); | |
293 | out_be32(ioaddr->lbah_addr, tf->hob_lbah); | |
294 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
295 | tf->hob_feature, | |
296 | tf->hob_nsect, | |
297 | tf->hob_lbal, | |
298 | tf->hob_lbam, | |
299 | tf->hob_lbah); | |
300 | } | |
301 | ||
302 | if (is_addr) { | |
303 | out_be32(ioaddr->feature_addr, tf->feature); | |
304 | out_be32(ioaddr->nsect_addr, tf->nsect); | |
305 | out_be32(ioaddr->lbal_addr, tf->lbal); | |
306 | out_be32(ioaddr->lbam_addr, tf->lbam); | |
307 | out_be32(ioaddr->lbah_addr, tf->lbah); | |
308 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
309 | tf->feature, | |
310 | tf->nsect, | |
311 | tf->lbal, | |
312 | tf->lbam, | |
313 | tf->lbah); | |
314 | } | |
315 | ||
316 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
317 | out_be32(ioaddr->device_addr, tf->device); | |
318 | VPRINTK("device 0x%X\n", tf->device); | |
319 | } | |
320 | ||
321 | ata_wait_idle(ap); | |
322 | } | |
323 | ||
324 | /** | |
325 | * scc_check_status - Read device status reg & clear interrupt | |
326 | * @ap: port where the device is | |
327 | * | |
328 | * Note: Original code is ata_check_status(). | |
329 | */ | |
330 | ||
331 | static u8 scc_check_status (struct ata_port *ap) | |
332 | { | |
333 | return in_be32(ap->ioaddr.status_addr); | |
334 | } | |
335 | ||
336 | /** | |
337 | * scc_tf_read - input device's ATA taskfile shadow registers | |
338 | * @ap: Port from which input is read | |
339 | * @tf: ATA taskfile register set for storing input | |
340 | * | |
9363c382 | 341 | * Note: Original code is ata_sff_tf_read(). |
a619f981 AI |
342 | */ |
343 | ||
344 | static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf) | |
345 | { | |
346 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
347 | ||
348 | tf->command = scc_check_status(ap); | |
349 | tf->feature = in_be32(ioaddr->error_addr); | |
350 | tf->nsect = in_be32(ioaddr->nsect_addr); | |
351 | tf->lbal = in_be32(ioaddr->lbal_addr); | |
352 | tf->lbam = in_be32(ioaddr->lbam_addr); | |
353 | tf->lbah = in_be32(ioaddr->lbah_addr); | |
354 | tf->device = in_be32(ioaddr->device_addr); | |
355 | ||
356 | if (tf->flags & ATA_TFLAG_LBA48) { | |
357 | out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB); | |
358 | tf->hob_feature = in_be32(ioaddr->error_addr); | |
359 | tf->hob_nsect = in_be32(ioaddr->nsect_addr); | |
360 | tf->hob_lbal = in_be32(ioaddr->lbal_addr); | |
361 | tf->hob_lbam = in_be32(ioaddr->lbam_addr); | |
362 | tf->hob_lbah = in_be32(ioaddr->lbah_addr); | |
fe36cb53 PV |
363 | out_be32(ioaddr->ctl_addr, tf->ctl); |
364 | ap->last_ctl = tf->ctl; | |
a619f981 AI |
365 | } |
366 | } | |
367 | ||
368 | /** | |
369 | * scc_exec_command - issue ATA command to host controller | |
370 | * @ap: port to which command is being issued | |
371 | * @tf: ATA taskfile register set | |
372 | * | |
9363c382 | 373 | * Note: Original code is ata_sff_exec_command(). |
a619f981 AI |
374 | */ |
375 | ||
376 | static void scc_exec_command (struct ata_port *ap, | |
377 | const struct ata_taskfile *tf) | |
378 | { | |
878d4fed | 379 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); |
a619f981 AI |
380 | |
381 | out_be32(ap->ioaddr.command_addr, tf->command); | |
9363c382 | 382 | ata_sff_pause(ap); |
a619f981 AI |
383 | } |
384 | ||
385 | /** | |
386 | * scc_check_altstatus - Read device alternate status reg | |
387 | * @ap: port where the device is | |
388 | */ | |
389 | ||
390 | static u8 scc_check_altstatus (struct ata_port *ap) | |
391 | { | |
392 | return in_be32(ap->ioaddr.altstatus_addr); | |
393 | } | |
394 | ||
395 | /** | |
9363c382 | 396 | * scc_dev_select - Select device 0/1 on ATA bus |
a619f981 AI |
397 | * @ap: ATA channel to manipulate |
398 | * @device: ATA device (numbered from zero) to select | |
399 | * | |
9363c382 | 400 | * Note: Original code is ata_sff_dev_select(). |
a619f981 AI |
401 | */ |
402 | ||
9363c382 | 403 | static void scc_dev_select (struct ata_port *ap, unsigned int device) |
a619f981 AI |
404 | { |
405 | u8 tmp; | |
406 | ||
407 | if (device == 0) | |
408 | tmp = ATA_DEVICE_OBS; | |
409 | else | |
410 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
411 | ||
412 | out_be32(ap->ioaddr.device_addr, tmp); | |
9363c382 | 413 | ata_sff_pause(ap); |
a619f981 AI |
414 | } |
415 | ||
41dec29b SS |
416 | /** |
417 | * scc_set_devctl - Write device control reg | |
418 | * @ap: port where the device is | |
419 | * @ctl: value to write | |
420 | */ | |
421 | ||
422 | static void scc_set_devctl(struct ata_port *ap, u8 ctl) | |
423 | { | |
424 | out_be32(ap->ioaddr.ctl_addr, ctl); | |
425 | } | |
426 | ||
a619f981 AI |
427 | /** |
428 | * scc_bmdma_setup - Set up PCI IDE BMDMA transaction | |
429 | * @qc: Info associated with this ATA transaction. | |
430 | * | |
431 | * Note: Original code is ata_bmdma_setup(). | |
432 | */ | |
433 | ||
434 | static void scc_bmdma_setup (struct ata_queued_cmd *qc) | |
435 | { | |
436 | struct ata_port *ap = qc->ap; | |
437 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
438 | u8 dmactl; | |
439 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
440 | ||
441 | /* load PRD table addr */ | |
f60d7011 | 442 | out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma); |
a619f981 AI |
443 | |
444 | /* specify data direction, triple-check start bit is clear */ | |
445 | dmactl = in_be32(mmio + SCC_DMA_CMD); | |
446 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
447 | if (!rw) | |
448 | dmactl |= ATA_DMA_WR; | |
449 | out_be32(mmio + SCC_DMA_CMD, dmactl); | |
450 | ||
451 | /* issue r/w command */ | |
5682ed33 | 452 | ap->ops->sff_exec_command(ap, &qc->tf); |
a619f981 AI |
453 | } |
454 | ||
455 | /** | |
456 | * scc_bmdma_start - Start a PCI IDE BMDMA transaction | |
457 | * @qc: Info associated with this ATA transaction. | |
458 | * | |
459 | * Note: Original code is ata_bmdma_start(). | |
460 | */ | |
461 | ||
462 | static void scc_bmdma_start (struct ata_queued_cmd *qc) | |
463 | { | |
464 | struct ata_port *ap = qc->ap; | |
465 | u8 dmactl; | |
466 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
467 | ||
468 | /* start host DMA transaction */ | |
469 | dmactl = in_be32(mmio + SCC_DMA_CMD); | |
470 | out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START); | |
471 | } | |
472 | ||
473 | /** | |
474 | * scc_devchk - PATA device presence detection | |
475 | * @ap: ATA channel to examine | |
476 | * @device: Device to examine (starting at zero) | |
477 | * | |
478 | * Note: Original code is ata_devchk(). | |
479 | */ | |
480 | ||
481 | static unsigned int scc_devchk (struct ata_port *ap, | |
482 | unsigned int device) | |
483 | { | |
484 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
485 | u8 nsect, lbal; | |
486 | ||
5682ed33 | 487 | ap->ops->sff_dev_select(ap, device); |
a619f981 AI |
488 | |
489 | out_be32(ioaddr->nsect_addr, 0x55); | |
490 | out_be32(ioaddr->lbal_addr, 0xaa); | |
491 | ||
492 | out_be32(ioaddr->nsect_addr, 0xaa); | |
493 | out_be32(ioaddr->lbal_addr, 0x55); | |
494 | ||
495 | out_be32(ioaddr->nsect_addr, 0x55); | |
496 | out_be32(ioaddr->lbal_addr, 0xaa); | |
497 | ||
498 | nsect = in_be32(ioaddr->nsect_addr); | |
499 | lbal = in_be32(ioaddr->lbal_addr); | |
500 | ||
501 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
502 | return 1; /* we found a device */ | |
503 | ||
504 | return 0; /* nothing found */ | |
505 | } | |
506 | ||
507 | /** | |
705e76be | 508 | * scc_wait_after_reset - wait for devices to become ready after reset |
a619f981 | 509 | * |
705e76be | 510 | * Note: Original code is ata_sff_wait_after_reset |
a619f981 AI |
511 | */ |
512 | ||
fe6005b8 SS |
513 | static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask, |
514 | unsigned long deadline) | |
a619f981 | 515 | { |
705e76be | 516 | struct ata_port *ap = link->ap; |
a619f981 AI |
517 | struct ata_ioports *ioaddr = &ap->ioaddr; |
518 | unsigned int dev0 = devmask & (1 << 0); | |
519 | unsigned int dev1 = devmask & (1 << 1); | |
705e76be TH |
520 | int rc, ret = 0; |
521 | ||
522 | /* Spec mandates ">= 2ms" before checking status. We wait | |
523 | * 150ms, because that was the magic delay used for ATAPI | |
524 | * devices in Hale Landis's ATADRVR, for the period of time | |
525 | * between when the ATA command register is written, and then | |
526 | * status is checked. Because waiting for "a while" before | |
527 | * checking status is fine, post SRST, we perform this magic | |
528 | * delay here as well. | |
529 | * | |
530 | * Old drivers/ide uses the 2mS rule and then waits for ready. | |
531 | */ | |
97750ceb | 532 | ata_msleep(ap, 150); |
a619f981 | 533 | |
705e76be TH |
534 | /* always check readiness of the master device */ |
535 | rc = ata_sff_wait_ready(link, deadline); | |
536 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
537 | * and TF status is 0xff, bail out on it too. | |
a619f981 | 538 | */ |
705e76be TH |
539 | if (rc) |
540 | return rc; | |
a619f981 | 541 | |
705e76be TH |
542 | /* if device 1 was found in ata_devchk, wait for register |
543 | * access briefly, then wait for BSY to clear. | |
a619f981 | 544 | */ |
705e76be TH |
545 | if (dev1) { |
546 | int i; | |
a619f981 | 547 | |
5682ed33 | 548 | ap->ops->sff_dev_select(ap, 1); |
705e76be TH |
549 | |
550 | /* Wait for register access. Some ATAPI devices fail | |
551 | * to set nsect/lbal after reset, so don't waste too | |
552 | * much time on it. We're gonna wait for !BSY anyway. | |
553 | */ | |
554 | for (i = 0; i < 2; i++) { | |
555 | u8 nsect, lbal; | |
556 | ||
557 | nsect = in_be32(ioaddr->nsect_addr); | |
558 | lbal = in_be32(ioaddr->lbal_addr); | |
559 | if ((nsect == 1) && (lbal == 1)) | |
560 | break; | |
97750ceb | 561 | ata_msleep(ap, 50); /* give drive a breather */ |
705e76be TH |
562 | } |
563 | ||
564 | rc = ata_sff_wait_ready(link, deadline); | |
565 | if (rc) { | |
566 | if (rc != -ENODEV) | |
567 | return rc; | |
568 | ret = rc; | |
569 | } | |
7e068376 | 570 | } |
a619f981 AI |
571 | |
572 | /* is all this really necessary? */ | |
5682ed33 | 573 | ap->ops->sff_dev_select(ap, 0); |
a619f981 | 574 | if (dev1) |
5682ed33 | 575 | ap->ops->sff_dev_select(ap, 1); |
a619f981 | 576 | if (dev0) |
5682ed33 | 577 | ap->ops->sff_dev_select(ap, 0); |
7e068376 | 578 | |
705e76be | 579 | return ret; |
a619f981 AI |
580 | } |
581 | ||
582 | /** | |
583 | * scc_bus_softreset - PATA device software reset | |
584 | * | |
585 | * Note: Original code is ata_bus_softreset(). | |
586 | */ | |
587 | ||
4dc7c76c | 588 | static int scc_bus_softreset(struct ata_port *ap, unsigned int devmask, |
7e068376 | 589 | unsigned long deadline) |
a619f981 AI |
590 | { |
591 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
592 | ||
878d4fed | 593 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
a619f981 AI |
594 | |
595 | /* software reset. causes dev0 to be selected */ | |
596 | out_be32(ioaddr->ctl_addr, ap->ctl); | |
597 | udelay(20); | |
598 | out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST); | |
599 | udelay(20); | |
600 | out_be32(ioaddr->ctl_addr, ap->ctl); | |
601 | ||
4dc7c76c | 602 | return scc_wait_after_reset(&ap->link, devmask, deadline); |
a619f981 AI |
603 | } |
604 | ||
605 | /** | |
9363c382 | 606 | * scc_softreset - reset host port via ATA SRST |
a619f981 AI |
607 | * @ap: port to reset |
608 | * @classes: resulting classes of attached devices | |
7e068376 | 609 | * @deadline: deadline jiffies for the operation |
a619f981 | 610 | * |
9363c382 | 611 | * Note: Original code is ata_sff_softreset(). |
a619f981 AI |
612 | */ |
613 | ||
9363c382 TH |
614 | static int scc_softreset(struct ata_link *link, unsigned int *classes, |
615 | unsigned long deadline) | |
a619f981 | 616 | { |
b90fe23b | 617 | struct ata_port *ap = link->ap; |
a619f981 | 618 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; |
4dc7c76c AS |
619 | unsigned int devmask = 0; |
620 | int rc; | |
a619f981 AI |
621 | u8 err; |
622 | ||
623 | DPRINTK("ENTER\n"); | |
624 | ||
a619f981 AI |
625 | /* determine if device 0/1 are present */ |
626 | if (scc_devchk(ap, 0)) | |
627 | devmask |= (1 << 0); | |
628 | if (slave_possible && scc_devchk(ap, 1)) | |
629 | devmask |= (1 << 1); | |
630 | ||
631 | /* select device 0 again */ | |
5682ed33 | 632 | ap->ops->sff_dev_select(ap, 0); |
a619f981 AI |
633 | |
634 | /* issue bus reset */ | |
635 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
4dc7c76c AS |
636 | rc = scc_bus_softreset(ap, devmask, deadline); |
637 | if (rc) { | |
638 | ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", rc); | |
a619f981 AI |
639 | return -EIO; |
640 | } | |
641 | ||
642 | /* determine by signature whether we have ATA or ATAPI devices */ | |
9363c382 | 643 | classes[0] = ata_sff_dev_classify(&ap->link.device[0], |
3f19859e | 644 | devmask & (1 << 0), &err); |
a619f981 | 645 | if (slave_possible && err != 0x81) |
9363c382 | 646 | classes[1] = ata_sff_dev_classify(&ap->link.device[1], |
3f19859e | 647 | devmask & (1 << 1), &err); |
a619f981 | 648 | |
a619f981 AI |
649 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
650 | return 0; | |
651 | } | |
652 | ||
653 | /** | |
654 | * scc_bmdma_stop - Stop PCI IDE BMDMA transfer | |
655 | * @qc: Command we are ending DMA for | |
656 | */ | |
657 | ||
658 | static void scc_bmdma_stop (struct ata_queued_cmd *qc) | |
659 | { | |
660 | struct ata_port *ap = qc->ap; | |
661 | void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; | |
662 | void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR]; | |
663 | u32 reg; | |
664 | ||
665 | while (1) { | |
666 | reg = in_be32(bmid_base + SCC_DMA_INTST); | |
667 | ||
668 | if (reg & INTSTS_SERROR) { | |
669 | printk(KERN_WARNING "%s: SERROR\n", DRV_NAME); | |
670 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT); | |
671 | out_be32(bmid_base + SCC_DMA_CMD, | |
672 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
673 | continue; | |
674 | } | |
675 | ||
676 | if (reg & INTSTS_PRERR) { | |
677 | u32 maea0, maec0; | |
678 | maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0); | |
679 | maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0); | |
680 | printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0); | |
681 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT); | |
682 | out_be32(bmid_base + SCC_DMA_CMD, | |
683 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
684 | continue; | |
685 | } | |
686 | ||
687 | if (reg & INTSTS_RERR) { | |
688 | printk(KERN_WARNING "%s: Response Error\n", DRV_NAME); | |
689 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT); | |
690 | out_be32(bmid_base + SCC_DMA_CMD, | |
691 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
692 | continue; | |
693 | } | |
694 | ||
695 | if (reg & INTSTS_ICERR) { | |
696 | out_be32(bmid_base + SCC_DMA_CMD, | |
697 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
698 | printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME); | |
699 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT); | |
700 | continue; | |
701 | } | |
702 | ||
703 | if (reg & INTSTS_BMSINT) { | |
704 | unsigned int classes; | |
341c2c95 | 705 | unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT); |
a619f981 AI |
706 | printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME); |
707 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT); | |
708 | /* TBD: SW reset */ | |
9363c382 | 709 | scc_softreset(&ap->link, &classes, deadline); |
a619f981 AI |
710 | continue; |
711 | } | |
712 | ||
713 | if (reg & INTSTS_BMHE) { | |
714 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE); | |
715 | continue; | |
716 | } | |
717 | ||
718 | if (reg & INTSTS_ACTEINT) { | |
719 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT); | |
720 | continue; | |
721 | } | |
722 | ||
723 | if (reg & INTSTS_IOIRQS) { | |
724 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS); | |
725 | continue; | |
726 | } | |
727 | break; | |
728 | } | |
729 | ||
730 | /* clear start/stop bit */ | |
731 | out_be32(bmid_base + SCC_DMA_CMD, | |
732 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
733 | ||
734 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
a57c1bad | 735 | ata_sff_dma_pause(ap); /* dummy read */ |
a619f981 AI |
736 | } |
737 | ||
738 | /** | |
739 | * scc_bmdma_status - Read PCI IDE BMDMA status | |
740 | * @ap: Port associated with this ATA transaction. | |
741 | */ | |
742 | ||
743 | static u8 scc_bmdma_status (struct ata_port *ap) | |
744 | { | |
a619f981 | 745 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
fae57d34 AI |
746 | u8 host_stat = in_be32(mmio + SCC_DMA_STATUS); |
747 | u32 int_status = in_be32(mmio + SCC_DMA_INTST); | |
b90fe23b | 748 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); |
fae57d34 AI |
749 | static int retry = 0; |
750 | ||
751 | /* return if IOS_SS is cleared */ | |
752 | if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START)) | |
753 | return host_stat; | |
754 | ||
755 | /* errata A252,A308 workaround: Step4 */ | |
a57c1bad AC |
756 | if ((scc_check_altstatus(ap) & ATA_ERR) |
757 | && (int_status & INTSTS_INTRQ)) | |
fae57d34 AI |
758 | return (host_stat | ATA_DMA_INTR); |
759 | ||
760 | /* errata A308 workaround Step5 */ | |
761 | if (int_status & INTSTS_IOIRQS) { | |
762 | host_stat |= ATA_DMA_INTR; | |
763 | ||
764 | /* We don't check ATAPI DMA because it is limited to UDMA4 */ | |
765 | if ((qc->tf.protocol == ATA_PROT_DMA && | |
766 | qc->dev->xfer_mode > XFER_UDMA_4)) { | |
767 | if (!(int_status & INTSTS_ACTEINT)) { | |
dcd03447 AI |
768 | printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n", |
769 | ap->print_id); | |
fae57d34 AI |
770 | host_stat |= ATA_DMA_ERR; |
771 | if (retry++) | |
dcd03447 | 772 | ap->udma_mask &= ~(1 << qc->dev->xfer_mode); |
fae57d34 AI |
773 | } else |
774 | retry = 0; | |
775 | } | |
a619f981 AI |
776 | } |
777 | ||
778 | return host_stat; | |
779 | } | |
780 | ||
781 | /** | |
782 | * scc_data_xfer - Transfer data by PIO | |
55dba312 | 783 | * @dev: device for this I/O |
a619f981 AI |
784 | * @buf: data buffer |
785 | * @buflen: buffer length | |
55dba312 | 786 | * @rw: read/write |
a619f981 | 787 | * |
9363c382 | 788 | * Note: Original code is ata_sff_data_xfer(). |
a619f981 AI |
789 | */ |
790 | ||
55dba312 TH |
791 | static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf, |
792 | unsigned int buflen, int rw) | |
a619f981 | 793 | { |
55dba312 | 794 | struct ata_port *ap = dev->link->ap; |
a619f981 AI |
795 | unsigned int words = buflen >> 1; |
796 | unsigned int i; | |
826cd156 | 797 | __le16 *buf16 = (__le16 *) buf; |
a619f981 AI |
798 | void __iomem *mmio = ap->ioaddr.data_addr; |
799 | ||
800 | /* Transfer multiple of 2 bytes */ | |
55dba312 | 801 | if (rw == READ) |
a619f981 | 802 | for (i = 0; i < words; i++) |
826cd156 | 803 | buf16[i] = cpu_to_le16(in_be32(mmio)); |
55dba312 TH |
804 | else |
805 | for (i = 0; i < words; i++) | |
826cd156 | 806 | out_be32(mmio, le16_to_cpu(buf16[i])); |
a619f981 AI |
807 | |
808 | /* Transfer trailing 1 byte, if any. */ | |
809 | if (unlikely(buflen & 0x01)) { | |
826cd156 | 810 | __le16 align_buf[1] = { 0 }; |
a619f981 AI |
811 | unsigned char *trailing_buf = buf + buflen - 1; |
812 | ||
55dba312 | 813 | if (rw == READ) { |
826cd156 | 814 | align_buf[0] = cpu_to_le16(in_be32(mmio)); |
a619f981 | 815 | memcpy(trailing_buf, align_buf, 1); |
55dba312 TH |
816 | } else { |
817 | memcpy(align_buf, trailing_buf, 1); | |
826cd156 | 818 | out_be32(mmio, le16_to_cpu(align_buf[0])); |
a619f981 | 819 | } |
55dba312 | 820 | words++; |
a619f981 | 821 | } |
55dba312 TH |
822 | |
823 | return words << 1; | |
a619f981 AI |
824 | } |
825 | ||
a619f981 | 826 | /** |
9363c382 | 827 | * scc_postreset - standard postreset callback |
a619f981 AI |
828 | * @ap: the target ata_port |
829 | * @classes: classes of attached devices | |
830 | * | |
9363c382 | 831 | * Note: Original code is ata_sff_postreset(). |
a619f981 AI |
832 | */ |
833 | ||
9363c382 | 834 | static void scc_postreset(struct ata_link *link, unsigned int *classes) |
a619f981 | 835 | { |
b90fe23b SS |
836 | struct ata_port *ap = link->ap; |
837 | ||
a619f981 AI |
838 | DPRINTK("ENTER\n"); |
839 | ||
a619f981 AI |
840 | /* is double-select really necessary? */ |
841 | if (classes[0] != ATA_DEV_NONE) | |
5682ed33 | 842 | ap->ops->sff_dev_select(ap, 1); |
a619f981 | 843 | if (classes[1] != ATA_DEV_NONE) |
5682ed33 | 844 | ap->ops->sff_dev_select(ap, 0); |
a619f981 AI |
845 | |
846 | /* bail out if no device is present */ | |
847 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
848 | DPRINTK("EXIT, no device\n"); | |
849 | return; | |
850 | } | |
851 | ||
852 | /* set up device control */ | |
ec86c81d | 853 | out_be32(ap->ioaddr.ctl_addr, ap->ctl); |
a619f981 AI |
854 | |
855 | DPRINTK("EXIT\n"); | |
856 | } | |
857 | ||
a619f981 | 858 | /** |
9363c382 | 859 | * scc_irq_clear - Clear PCI IDE BMDMA interrupt. |
a619f981 AI |
860 | * @ap: Port associated with this ATA transaction. |
861 | * | |
37f65b8b | 862 | * Note: Original code is ata_bmdma_irq_clear(). |
a619f981 AI |
863 | */ |
864 | ||
9363c382 | 865 | static void scc_irq_clear (struct ata_port *ap) |
a619f981 AI |
866 | { |
867 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
868 | ||
869 | if (!mmio) | |
870 | return; | |
871 | ||
872 | out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS)); | |
873 | } | |
874 | ||
875 | /** | |
876 | * scc_port_start - Set port up for dma. | |
877 | * @ap: Port to initialize | |
878 | * | |
c7087652 | 879 | * Allocate space for PRD table using ata_bmdma_port_start(). |
a619f981 AI |
880 | * Set PRD table address for PTERADD. (PRD Transfer End Read) |
881 | */ | |
882 | ||
883 | static int scc_port_start (struct ata_port *ap) | |
884 | { | |
885 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
886 | int rc; | |
887 | ||
c7087652 | 888 | rc = ata_bmdma_port_start(ap); |
a619f981 AI |
889 | if (rc) |
890 | return rc; | |
891 | ||
f60d7011 | 892 | out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma); |
a619f981 AI |
893 | return 0; |
894 | } | |
895 | ||
896 | /** | |
897 | * scc_port_stop - Undo scc_port_start() | |
898 | * @ap: Port to shut down | |
899 | * | |
900 | * Reset PTERADD. | |
901 | */ | |
902 | ||
903 | static void scc_port_stop (struct ata_port *ap) | |
904 | { | |
905 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
906 | ||
907 | out_be32(mmio + SCC_DMA_PTERADD, 0); | |
908 | } | |
909 | ||
910 | static struct scsi_host_template scc_sht = { | |
68d1d07b | 911 | ATA_BMDMA_SHT(DRV_NAME), |
a619f981 AI |
912 | }; |
913 | ||
c1796d98 | 914 | static struct ata_port_operations scc_pata_ops = { |
029cfd6b TH |
915 | .inherits = &ata_bmdma_port_ops, |
916 | ||
a619f981 AI |
917 | .set_piomode = scc_set_piomode, |
918 | .set_dmamode = scc_set_dmamode, | |
dcd03447 | 919 | .mode_filter = scc_mode_filter, |
a619f981 | 920 | |
5682ed33 TH |
921 | .sff_tf_load = scc_tf_load, |
922 | .sff_tf_read = scc_tf_read, | |
923 | .sff_exec_command = scc_exec_command, | |
924 | .sff_check_status = scc_check_status, | |
925 | .sff_check_altstatus = scc_check_altstatus, | |
926 | .sff_dev_select = scc_dev_select, | |
41dec29b | 927 | .sff_set_devctl = scc_set_devctl, |
a619f981 AI |
928 | |
929 | .bmdma_setup = scc_bmdma_setup, | |
930 | .bmdma_start = scc_bmdma_start, | |
931 | .bmdma_stop = scc_bmdma_stop, | |
932 | .bmdma_status = scc_bmdma_status, | |
5682ed33 | 933 | .sff_data_xfer = scc_data_xfer, |
a619f981 | 934 | |
9f8abf82 | 935 | .cable_detect = ata_cable_80wire, |
9363c382 TH |
936 | .softreset = scc_softreset, |
937 | .postreset = scc_postreset, | |
a619f981 | 938 | |
5682ed33 | 939 | .sff_irq_clear = scc_irq_clear, |
a619f981 AI |
940 | |
941 | .port_start = scc_port_start, | |
942 | .port_stop = scc_port_stop, | |
943 | }; | |
944 | ||
945 | static struct ata_port_info scc_port_info[] = { | |
946 | { | |
9cbe056f | 947 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
948 | .pio_mask = ATA_PIO4, |
949 | /* No MWDMA */ | |
a619f981 AI |
950 | .udma_mask = ATA_UDMA6, |
951 | .port_ops = &scc_pata_ops, | |
952 | }, | |
953 | }; | |
954 | ||
955 | /** | |
956 | * scc_reset_controller - initialize SCC PATA controller. | |
957 | */ | |
958 | ||
5d728824 | 959 | static int scc_reset_controller(struct ata_host *host) |
a619f981 | 960 | { |
5d728824 TH |
961 | void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR]; |
962 | void __iomem *bmid_base = host->iomap[SCC_BMID_BAR]; | |
a619f981 AI |
963 | void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; |
964 | void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG; | |
965 | void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE; | |
966 | void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK; | |
967 | void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS; | |
968 | u32 reg = 0; | |
969 | ||
970 | out_be32(cckctrl_port, reg); | |
971 | reg |= CCKCTRL_ATACLKOEN; | |
972 | out_be32(cckctrl_port, reg); | |
973 | reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; | |
974 | out_be32(cckctrl_port, reg); | |
975 | reg |= CCKCTRL_CRST; | |
976 | out_be32(cckctrl_port, reg); | |
977 | ||
978 | for (;;) { | |
979 | reg = in_be32(cckctrl_port); | |
980 | if (reg & CCKCTRL_CRST) | |
981 | break; | |
982 | udelay(5000); | |
983 | } | |
984 | ||
985 | reg |= CCKCTRL_ATARESET; | |
986 | out_be32(cckctrl_port, reg); | |
987 | out_be32(ecmode_port, ECMODE_VALUE); | |
988 | out_be32(mode_port, MODE_JCUSFEN); | |
989 | out_be32(intmask_port, INTMASK_MSK); | |
990 | ||
991 | if (in_be32(dmastatus_port) & QCHSD_STPDIAG) { | |
992 | printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME); | |
993 | return -EIO; | |
994 | } | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
999 | /** | |
1000 | * scc_setup_ports - initialize ioaddr with SCC PATA port offsets. | |
1001 | * @ioaddr: IO address structure to be initialized | |
1002 | * @base: base address of BMID region | |
1003 | */ | |
1004 | ||
1005 | static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base) | |
1006 | { | |
1007 | ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR; | |
1008 | ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS; | |
1009 | ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS; | |
1010 | ioaddr->bmdma_addr = base; | |
1011 | ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA; | |
1012 | ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR; | |
1013 | ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE; | |
1014 | ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT; | |
1015 | ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL; | |
1016 | ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM; | |
1017 | ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH; | |
1018 | ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE; | |
1019 | ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS; | |
1020 | ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD; | |
1021 | } | |
1022 | ||
5d728824 | 1023 | static int scc_host_init(struct ata_host *host) |
a619f981 | 1024 | { |
5d728824 | 1025 | struct pci_dev *pdev = to_pci_dev(host->dev); |
a619f981 AI |
1026 | int rc; |
1027 | ||
5d728824 | 1028 | rc = scc_reset_controller(host); |
a619f981 AI |
1029 | if (rc) |
1030 | return rc; | |
1031 | ||
a619f981 AI |
1032 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1033 | if (rc) | |
1034 | return rc; | |
1035 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1036 | if (rc) | |
1037 | return rc; | |
1038 | ||
5d728824 | 1039 | scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]); |
a619f981 AI |
1040 | |
1041 | pci_set_master(pdev); | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
1046 | /** | |
1047 | * scc_init_one - Register SCC PATA device with kernel services | |
1048 | * @pdev: PCI device to register | |
1049 | * @ent: Entry in scc_pci_tbl matching with @pdev | |
1050 | * | |
1051 | * LOCKING: | |
1052 | * Inherited from PCI layer (may sleep). | |
1053 | * | |
1054 | * RETURNS: | |
1055 | * Zero on success, or -ERRNO value. | |
1056 | */ | |
1057 | ||
1058 | static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1059 | { | |
a619f981 | 1060 | unsigned int board_idx = (unsigned int) ent->driver_data; |
5d728824 | 1061 | const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL }; |
0397bad5 | 1062 | struct ata_host *host; |
a619f981 AI |
1063 | int rc; |
1064 | ||
06296a1e | 1065 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
a619f981 | 1066 | |
0397bad5 | 1067 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1); |
5d728824 TH |
1068 | if (!host) |
1069 | return -ENOMEM; | |
1070 | ||
a619f981 AI |
1071 | rc = pcim_enable_device(pdev); |
1072 | if (rc) | |
1073 | return rc; | |
1074 | ||
1075 | rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME); | |
1076 | if (rc == -EBUSY) | |
1077 | pcim_pin_device(pdev); | |
1078 | if (rc) | |
1079 | return rc; | |
5d728824 | 1080 | host->iomap = pcim_iomap_table(pdev); |
a619f981 | 1081 | |
cbcdd875 TH |
1082 | ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl"); |
1083 | ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid"); | |
1084 | ||
5d728824 | 1085 | rc = scc_host_init(host); |
a619f981 AI |
1086 | if (rc) |
1087 | return rc; | |
1088 | ||
c3b28894 | 1089 | return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
9363c382 | 1090 | IRQF_SHARED, &scc_sht); |
a619f981 AI |
1091 | } |
1092 | ||
1093 | static struct pci_driver scc_pci_driver = { | |
1094 | .name = DRV_NAME, | |
1095 | .id_table = scc_pci_tbl, | |
1096 | .probe = scc_init_one, | |
1097 | .remove = ata_pci_remove_one, | |
58eb8cd5 | 1098 | #ifdef CONFIG_PM_SLEEP |
a619f981 AI |
1099 | .suspend = ata_pci_device_suspend, |
1100 | .resume = ata_pci_device_resume, | |
1101 | #endif | |
1102 | }; | |
1103 | ||
2fc75da0 | 1104 | module_pci_driver(scc_pci_driver); |
a619f981 AI |
1105 | |
1106 | MODULE_AUTHOR("Toshiba corp"); | |
1107 | MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller"); | |
1108 | MODULE_LICENSE("GPL"); | |
1109 | MODULE_DEVICE_TABLE(pci, scc_pci_tbl); | |
1110 | MODULE_VERSION(DRV_VERSION); |