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669a5db4 | 1 | /* |
a0fcdc02 | 2 | * pata_serverworks.c - Serverworks PATA for new ATA layer |
669a5db4 JG |
3 | * (C) 2005 Red Hat Inc |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * based upon | |
7 | * | |
8 | * serverworks.c | |
85cd7251 | 9 | * |
669a5db4 JG |
10 | * Copyright (C) 1998-2000 Michel Aubry |
11 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz | |
12 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
13 | * Portions copyright (c) 2001 Sun Microsystems | |
14 | * | |
15 | * | |
16 | * RCC/ServerWorks IDE driver for Linux | |
17 | * | |
18 | * OSB4: `Open South Bridge' IDE Interface (fn 1) | |
19 | * supports UDMA mode 2 (33 MB/s) | |
20 | * | |
21 | * CSB5: `Champion South Bridge' IDE Interface (fn 1) | |
22 | * all revisions support UDMA mode 4 (66 MB/s) | |
23 | * revision A2.0 and up support UDMA mode 5 (100 MB/s) | |
24 | * | |
25 | * *** The CSB5 does not provide ANY register *** | |
26 | * *** to detect 80-conductor cable presence. *** | |
27 | * | |
28 | * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) | |
29 | * | |
30 | * Documentation: | |
31 | * Available under NDA only. Errata info very hard to get. | |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <scsi/scsi_host.h> | |
41 | #include <linux/libata.h> | |
42 | ||
43 | #define DRV_NAME "pata_serverworks" | |
cb48cab7 | 44 | #define DRV_VERSION "0.4.0" |
669a5db4 JG |
45 | |
46 | #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ | |
47 | #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ | |
48 | ||
49 | /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 | |
50 | * can overrun their FIFOs when used with the CSB5 */ | |
51 | ||
52 | static const char *csb_bad_ata100[] = { | |
53 | "ST320011A", | |
54 | "ST340016A", | |
55 | "ST360021A", | |
56 | "ST380021A", | |
57 | NULL | |
58 | }; | |
59 | ||
60 | /** | |
61 | * dell_cable - Dell serverworks cable detection | |
62 | * @ap: ATA port to do cable detect | |
63 | * | |
64 | * Dell hide the 40/80 pin select for their interfaces in the top two | |
85cd7251 | 65 | * bits of the subsystem ID. |
669a5db4 | 66 | */ |
85cd7251 | 67 | |
669a5db4 JG |
68 | static int dell_cable(struct ata_port *ap) { |
69 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 70 | |
669a5db4 JG |
71 | if (pdev->subsystem_device & (1 << (ap->port_no + 14))) |
72 | return ATA_CBL_PATA80; | |
73 | return ATA_CBL_PATA40; | |
74 | } | |
75 | ||
76 | /** | |
77 | * sun_cable - Sun Cobalt 'Alpine' cable detection | |
78 | * @ap: ATA port to do cable select | |
79 | * | |
80 | * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the | |
81 | * subsystem ID the same as dell. We could use one function but we may | |
82 | * need to extend the Dell one in future | |
83 | */ | |
85cd7251 | 84 | |
669a5db4 JG |
85 | static int sun_cable(struct ata_port *ap) { |
86 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 87 | |
669a5db4 JG |
88 | if (pdev->subsystem_device & (1 << (ap->port_no + 14))) |
89 | return ATA_CBL_PATA80; | |
90 | return ATA_CBL_PATA40; | |
91 | } | |
92 | ||
93 | /** | |
94 | * osb4_cable - OSB4 cable detect | |
95 | * @ap: ATA port to check | |
96 | * | |
97 | * The OSB4 isn't UDMA66 capable so this is easy | |
98 | */ | |
99 | ||
100 | static int osb4_cable(struct ata_port *ap) { | |
101 | return ATA_CBL_PATA40; | |
102 | } | |
103 | ||
104 | /** | |
105 | * csb4_cable - CSB5/6 cable detect | |
106 | * @ap: ATA port to check | |
107 | * | |
108 | * Serverworks default arrangement is to use the drive side detection | |
109 | * only. | |
110 | */ | |
111 | ||
112 | static int csb_cable(struct ata_port *ap) { | |
113 | return ATA_CBL_PATA80; | |
114 | } | |
115 | ||
116 | struct sv_cable_table { | |
117 | int device; | |
118 | int subvendor; | |
119 | int (*cable_detect)(struct ata_port *ap); | |
120 | }; | |
121 | ||
122 | /* | |
123 | * Note that we don't copy the old serverworks code because the old | |
124 | * code contains obvious mistakes | |
125 | */ | |
85cd7251 | 126 | |
669a5db4 JG |
127 | static struct sv_cable_table cable_detect[] = { |
128 | { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable }, | |
129 | { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable }, | |
130 | { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable }, | |
68d0d7ab | 131 | { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable }, |
669a5db4 JG |
132 | { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable }, |
133 | { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable }, | |
134 | { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable }, | |
135 | { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable }, | |
136 | { } | |
137 | }; | |
138 | ||
139 | /** | |
a0fcdc02 | 140 | * serverworks_cable_detect - cable detection |
669a5db4 | 141 | * @ap: ATA port |
d4b2bab4 | 142 | * @deadline: deadline jiffies for the operation |
669a5db4 | 143 | * |
85cd7251 | 144 | * Perform cable detection according to the device and subvendor |
669a5db4 JG |
145 | * identifications |
146 | */ | |
85cd7251 | 147 | |
d4b2bab4 TH |
148 | static int serverworks_cable_detect(struct ata_port *ap) |
149 | { | |
669a5db4 JG |
150 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
151 | struct sv_cable_table *cb = cable_detect; | |
152 | ||
153 | while(cb->device) { | |
85cd7251 | 154 | if (cb->device == pdev->device && |
669a5db4 JG |
155 | (cb->subvendor == pdev->subsystem_vendor || |
156 | cb->subvendor == PCI_ANY_ID)) { | |
a0fcdc02 | 157 | return cb->cable_detect(ap); |
669a5db4 JG |
158 | } |
159 | cb++; | |
160 | } | |
161 | ||
162 | BUG(); | |
163 | return -1; /* kill compiler warning */ | |
164 | } | |
165 | ||
669a5db4 JG |
166 | /** |
167 | * serverworks_is_csb - Check for CSB or OSB | |
168 | * @pdev: PCI device to check | |
169 | * | |
170 | * Returns true if the device being checked is known to be a CSB | |
171 | * series device. | |
172 | */ | |
85cd7251 | 173 | |
669a5db4 JG |
174 | static u8 serverworks_is_csb(struct pci_dev *pdev) |
175 | { | |
176 | switch (pdev->device) { | |
177 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
178 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
179 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
180 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: | |
181 | return 1; | |
182 | default: | |
183 | break; | |
184 | } | |
185 | return 0; | |
186 | } | |
187 | ||
188 | /** | |
189 | * serverworks_osb4_filter - mode selection filter | |
669a5db4 | 190 | * @adev: ATA device |
a76b62ca | 191 | * @mask: Mask of proposed modes |
669a5db4 JG |
192 | * |
193 | * Filter the offered modes for the device to apply controller | |
194 | * specific rules. OSB4 requires no UDMA for disks due to a FIFO | |
195 | * bug we hit. | |
196 | */ | |
85cd7251 | 197 | |
a76b62ca | 198 | static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 JG |
199 | { |
200 | if (adev->class == ATA_DEV_ATA) | |
201 | mask &= ~ATA_MASK_UDMA; | |
a76b62ca | 202 | return ata_pci_default_filter(adev, mask); |
669a5db4 JG |
203 | } |
204 | ||
205 | ||
206 | /** | |
207 | * serverworks_csb_filter - mode selection filter | |
669a5db4 | 208 | * @adev: ATA device |
a76b62ca | 209 | * @mask: Mask of proposed modes |
669a5db4 JG |
210 | * |
211 | * Check the blacklist and disable UDMA5 if matched | |
212 | */ | |
213 | ||
a76b62ca | 214 | static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 JG |
215 | { |
216 | const char *p; | |
8bfa79fc TH |
217 | char model_num[ATA_ID_PROD_LEN + 1]; |
218 | int i; | |
669a5db4 | 219 | |
85cd7251 | 220 | /* Disk, UDMA */ |
669a5db4 | 221 | if (adev->class != ATA_DEV_ATA) |
a76b62ca | 222 | return ata_pci_default_filter(adev, mask); |
669a5db4 JG |
223 | |
224 | /* Actually do need to check */ | |
8bfa79fc | 225 | ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
85cd7251 | 226 | |
8bfa79fc TH |
227 | for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) { |
228 | if (!strcmp(p, model_num)) | |
669a5db4 JG |
229 | mask &= ~(0x1F << ATA_SHIFT_UDMA); |
230 | } | |
a76b62ca | 231 | return ata_pci_default_filter(adev, mask); |
669a5db4 JG |
232 | } |
233 | ||
234 | ||
235 | /** | |
236 | * serverworks_set_piomode - set initial PIO mode data | |
237 | * @ap: ATA interface | |
238 | * @adev: ATA device | |
239 | * | |
240 | * Program the OSB4/CSB5 timing registers for PIO. The PIO register | |
241 | * load is done as a simple lookup. | |
242 | */ | |
243 | static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
244 | { | |
245 | static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; | |
246 | int offset = 1 + (2 * ap->port_no) - adev->devno; | |
247 | int devbits = (2 * ap->port_no + adev->devno) * 4; | |
248 | u16 csb5_pio; | |
249 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
250 | int pio = adev->pio_mode - XFER_PIO_0; | |
251 | ||
252 | pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]); | |
85cd7251 | 253 | |
669a5db4 JG |
254 | /* The OSB4 just requires the timing but the CSB series want the |
255 | mode number as well */ | |
256 | if (serverworks_is_csb(pdev)) { | |
257 | pci_read_config_word(pdev, 0x4A, &csb5_pio); | |
258 | csb5_pio &= ~(0x0F << devbits); | |
259 | pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits)); | |
260 | } | |
261 | } | |
262 | ||
263 | /** | |
264 | * serverworks_set_dmamode - set initial DMA mode data | |
265 | * @ap: ATA interface | |
266 | * @adev: ATA device | |
267 | * | |
268 | * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5 | |
269 | * chipset. The MWDMA mode values are pulled from a lookup table | |
270 | * while the chipset uses mode number for UDMA. | |
271 | */ | |
272 | ||
273 | static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
274 | { | |
275 | static const u8 dma_mode[] = { 0x77, 0x21, 0x20 }; | |
276 | int offset = 1 + 2 * ap->port_no - adev->devno; | |
277 | int devbits = (2 * ap->port_no + adev->devno); | |
278 | u8 ultra; | |
279 | u8 ultra_cfg; | |
280 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
281 | ||
282 | pci_read_config_byte(pdev, 0x54, &ultra_cfg); | |
283 | ||
284 | if (adev->dma_mode >= XFER_UDMA_0) { | |
285 | pci_write_config_byte(pdev, 0x44 + offset, 0x20); | |
286 | ||
287 | pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra); | |
288 | ultra &= ~(0x0F << (ap->port_no * 4)); | |
289 | ultra |= (adev->dma_mode - XFER_UDMA_0) | |
290 | << (ap->port_no * 4); | |
291 | pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra); | |
292 | ||
293 | ultra_cfg |= (1 << devbits); | |
294 | } else { | |
85cd7251 | 295 | pci_write_config_byte(pdev, 0x44 + offset, |
669a5db4 JG |
296 | dma_mode[adev->dma_mode - XFER_MW_DMA_0]); |
297 | ultra_cfg &= ~(1 << devbits); | |
298 | } | |
299 | pci_write_config_byte(pdev, 0x54, ultra_cfg); | |
300 | } | |
301 | ||
302 | static struct scsi_host_template serverworks_sht = { | |
303 | .module = THIS_MODULE, | |
304 | .name = DRV_NAME, | |
305 | .ioctl = ata_scsi_ioctl, | |
306 | .queuecommand = ata_scsi_queuecmd, | |
307 | .can_queue = ATA_DEF_QUEUE, | |
308 | .this_id = ATA_SHT_THIS_ID, | |
309 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
310 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
311 | .emulated = ATA_SHT_EMULATED, | |
312 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
313 | .proc_name = DRV_NAME, | |
314 | .dma_boundary = ATA_DMA_BOUNDARY, | |
315 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 316 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 | 317 | .bios_param = ata_std_bios_param, |
438ac6d5 | 318 | #ifdef CONFIG_PM |
38e0d56e A |
319 | .resume = ata_scsi_device_resume, |
320 | .suspend = ata_scsi_device_suspend, | |
438ac6d5 | 321 | #endif |
669a5db4 JG |
322 | }; |
323 | ||
324 | static struct ata_port_operations serverworks_osb4_port_ops = { | |
325 | .port_disable = ata_port_disable, | |
326 | .set_piomode = serverworks_set_piomode, | |
327 | .set_dmamode = serverworks_set_dmamode, | |
328 | .mode_filter = serverworks_osb4_filter, | |
85cd7251 | 329 | |
669a5db4 JG |
330 | .tf_load = ata_tf_load, |
331 | .tf_read = ata_tf_read, | |
332 | .check_status = ata_check_status, | |
333 | .exec_command = ata_exec_command, | |
334 | .dev_select = ata_std_dev_select, | |
335 | ||
336 | .freeze = ata_bmdma_freeze, | |
337 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 338 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 339 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 340 | .cable_detect = serverworks_cable_detect, |
669a5db4 JG |
341 | |
342 | .bmdma_setup = ata_bmdma_setup, | |
343 | .bmdma_start = ata_bmdma_start, | |
344 | .bmdma_stop = ata_bmdma_stop, | |
345 | .bmdma_status = ata_bmdma_status, | |
346 | ||
347 | .qc_prep = ata_qc_prep, | |
348 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 349 | |
0d5ff566 | 350 | .data_xfer = ata_data_xfer, |
85cd7251 | 351 | |
669a5db4 | 352 | .irq_handler = ata_interrupt, |
efbf3f14 | 353 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 AI |
354 | .irq_on = ata_irq_on, |
355 | .irq_ack = ata_irq_ack, | |
efbf3f14 | 356 | |
669a5db4 | 357 | .port_start = ata_port_start, |
85cd7251 | 358 | }; |
669a5db4 JG |
359 | |
360 | static struct ata_port_operations serverworks_csb_port_ops = { | |
361 | .port_disable = ata_port_disable, | |
362 | .set_piomode = serverworks_set_piomode, | |
363 | .set_dmamode = serverworks_set_dmamode, | |
364 | .mode_filter = serverworks_csb_filter, | |
85cd7251 | 365 | |
669a5db4 JG |
366 | .tf_load = ata_tf_load, |
367 | .tf_read = ata_tf_read, | |
368 | .check_status = ata_check_status, | |
369 | .exec_command = ata_exec_command, | |
370 | .dev_select = ata_std_dev_select, | |
371 | ||
372 | .freeze = ata_bmdma_freeze, | |
373 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 374 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 375 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 376 | .cable_detect = serverworks_cable_detect, |
669a5db4 JG |
377 | |
378 | .bmdma_setup = ata_bmdma_setup, | |
379 | .bmdma_start = ata_bmdma_start, | |
380 | .bmdma_stop = ata_bmdma_stop, | |
381 | .bmdma_status = ata_bmdma_status, | |
382 | ||
383 | .qc_prep = ata_qc_prep, | |
384 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 385 | |
0d5ff566 | 386 | .data_xfer = ata_data_xfer, |
85cd7251 | 387 | |
669a5db4 | 388 | .irq_handler = ata_interrupt, |
efbf3f14 | 389 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 AI |
390 | .irq_on = ata_irq_on, |
391 | .irq_ack = ata_irq_ack, | |
efbf3f14 | 392 | |
669a5db4 | 393 | .port_start = ata_port_start, |
85cd7251 | 394 | }; |
669a5db4 JG |
395 | |
396 | static int serverworks_fixup_osb4(struct pci_dev *pdev) | |
397 | { | |
398 | u32 reg; | |
399 | struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
400 | PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); | |
401 | if (isa_dev) { | |
402 | pci_read_config_dword(isa_dev, 0x64, ®); | |
403 | reg &= ~0x00002000; /* disable 600ns interrupt mask */ | |
404 | if (!(reg & 0x00004000)) | |
405 | printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n"); | |
406 | reg |= 0x00004000; /* enable UDMA/33 support */ | |
407 | pci_write_config_dword(isa_dev, 0x64, reg); | |
408 | pci_dev_put(isa_dev); | |
409 | return 0; | |
410 | } | |
411 | printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n"); | |
412 | return -ENODEV; | |
413 | } | |
414 | ||
415 | static int serverworks_fixup_csb(struct pci_dev *pdev) | |
416 | { | |
417 | u8 rev; | |
418 | u8 btr; | |
85cd7251 | 419 | |
669a5db4 JG |
420 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
421 | ||
422 | /* Third Channel Test */ | |
423 | if (!(PCI_FUNC(pdev->devfn) & 1)) { | |
424 | struct pci_dev * findev = NULL; | |
425 | u32 reg4c = 0; | |
426 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
427 | PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); | |
428 | if (findev) { | |
429 | pci_read_config_dword(findev, 0x4C, ®4c); | |
430 | reg4c &= ~0x000007FF; | |
431 | reg4c |= 0x00000040; | |
432 | reg4c |= 0x00000020; | |
433 | pci_write_config_dword(findev, 0x4C, reg4c); | |
434 | pci_dev_put(findev); | |
435 | } | |
436 | } else { | |
437 | struct pci_dev * findev = NULL; | |
438 | u8 reg41 = 0; | |
439 | ||
440 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
441 | PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); | |
442 | if (findev) { | |
443 | pci_read_config_byte(findev, 0x41, ®41); | |
444 | reg41 &= ~0x40; | |
445 | pci_write_config_byte(findev, 0x41, reg41); | |
446 | pci_dev_put(findev); | |
447 | } | |
448 | } | |
449 | /* setup the UDMA Control register | |
450 | * | |
451 | * 1. clear bit 6 to enable DMA | |
452 | * 2. enable DMA modes with bits 0-1 | |
453 | * 00 : legacy | |
454 | * 01 : udma2 | |
455 | * 10 : udma2/udma4 | |
456 | * 11 : udma2/udma4/udma5 | |
457 | */ | |
458 | pci_read_config_byte(pdev, 0x5A, &btr); | |
459 | btr &= ~0x40; | |
460 | if (!(PCI_FUNC(pdev->devfn) & 1)) | |
461 | btr |= 0x2; | |
462 | else | |
463 | btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; | |
464 | pci_write_config_byte(pdev, 0x5A, btr); | |
85cd7251 | 465 | |
669a5db4 JG |
466 | return btr; |
467 | } | |
468 | ||
469 | static void serverworks_fixup_ht1000(struct pci_dev *pdev) | |
470 | { | |
471 | u8 btr; | |
472 | /* Setup HT1000 SouthBridge Controller - Single Channel Only */ | |
473 | pci_read_config_byte(pdev, 0x5A, &btr); | |
474 | btr &= ~0x40; | |
475 | btr |= 0x3; | |
476 | pci_write_config_byte(pdev, 0x5A, btr); | |
477 | } | |
478 | ||
479 | ||
480 | static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
481 | { | |
482 | int ports = 2; | |
483 | static struct ata_port_info info[4] = { | |
484 | { /* OSB4 */ | |
485 | .sht = &serverworks_sht, | |
486 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
487 | .pio_mask = 0x1f, | |
488 | .mwdma_mask = 0x07, | |
489 | .udma_mask = 0x07, | |
490 | .port_ops = &serverworks_osb4_port_ops | |
491 | }, { /* OSB4 no UDMA */ | |
492 | .sht = &serverworks_sht, | |
493 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
494 | .pio_mask = 0x1f, | |
495 | .mwdma_mask = 0x07, | |
496 | .udma_mask = 0x00, | |
497 | .port_ops = &serverworks_osb4_port_ops | |
498 | }, { /* CSB5 */ | |
499 | .sht = &serverworks_sht, | |
500 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
501 | .pio_mask = 0x1f, | |
502 | .mwdma_mask = 0x07, | |
503 | .udma_mask = 0x1f, | |
504 | .port_ops = &serverworks_csb_port_ops | |
505 | }, { /* CSB5 - later revisions*/ | |
506 | .sht = &serverworks_sht, | |
507 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
508 | .pio_mask = 0x1f, | |
509 | .mwdma_mask = 0x07, | |
510 | .udma_mask = 0x3f, | |
511 | .port_ops = &serverworks_csb_port_ops | |
512 | } | |
513 | }; | |
514 | static struct ata_port_info *port_info[2]; | |
515 | struct ata_port_info *devinfo = &info[id->driver_data]; | |
85cd7251 | 516 | |
669a5db4 JG |
517 | /* Force master latency timer to 64 PCI clocks */ |
518 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); | |
519 | ||
520 | /* OSB4 : South Bridge and IDE */ | |
521 | if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { | |
522 | /* Select non UDMA capable OSB4 if we can't do fixups */ | |
523 | if ( serverworks_fixup_osb4(pdev) < 0) | |
524 | devinfo = &info[1]; | |
525 | } | |
526 | /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ | |
527 | else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || | |
528 | (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
529 | (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { | |
85cd7251 | 530 | |
669a5db4 JG |
531 | /* If the returned btr is the newer revision then |
532 | select the right info block */ | |
533 | if (serverworks_fixup_csb(pdev) == 3) | |
534 | devinfo = &info[3]; | |
85cd7251 | 535 | |
669a5db4 JG |
536 | /* Is this the 3rd channel CSB6 IDE ? */ |
537 | if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) | |
538 | ports = 1; | |
539 | } | |
540 | /* setup HT1000E */ | |
541 | else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) | |
542 | serverworks_fixup_ht1000(pdev); | |
85cd7251 | 543 | |
669a5db4 JG |
544 | if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) |
545 | ata_pci_clear_simplex(pdev); | |
85cd7251 | 546 | |
669a5db4 JG |
547 | port_info[0] = port_info[1] = devinfo; |
548 | return ata_pci_init_one(pdev, port_info, ports); | |
549 | } | |
550 | ||
438ac6d5 | 551 | #ifdef CONFIG_PM |
38e0d56e A |
552 | static int serverworks_reinit_one(struct pci_dev *pdev) |
553 | { | |
554 | /* Force master latency timer to 64 PCI clocks */ | |
555 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); | |
f20b16ff | 556 | |
38e0d56e A |
557 | switch (pdev->device) |
558 | { | |
559 | case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: | |
560 | serverworks_fixup_osb4(pdev); | |
561 | break; | |
562 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
563 | ata_pci_clear_simplex(pdev); | |
564 | /* fall through */ | |
565 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
566 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
567 | serverworks_fixup_csb(pdev); | |
568 | break; | |
569 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: | |
570 | serverworks_fixup_ht1000(pdev); | |
571 | break; | |
572 | } | |
573 | return ata_pci_device_resume(pdev); | |
574 | } | |
438ac6d5 | 575 | #endif |
38e0d56e | 576 | |
2d2744fc JG |
577 | static const struct pci_device_id serverworks[] = { |
578 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0}, | |
579 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2}, | |
580 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2}, | |
581 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2}, | |
582 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2}, | |
583 | ||
584 | { }, | |
669a5db4 JG |
585 | }; |
586 | ||
587 | static struct pci_driver serverworks_pci_driver = { | |
588 | .name = DRV_NAME, | |
589 | .id_table = serverworks, | |
590 | .probe = serverworks_init_one, | |
38e0d56e | 591 | .remove = ata_pci_remove_one, |
438ac6d5 | 592 | #ifdef CONFIG_PM |
38e0d56e A |
593 | .suspend = ata_pci_device_suspend, |
594 | .resume = serverworks_reinit_one, | |
438ac6d5 | 595 | #endif |
669a5db4 JG |
596 | }; |
597 | ||
598 | static int __init serverworks_init(void) | |
599 | { | |
600 | return pci_register_driver(&serverworks_pci_driver); | |
601 | } | |
602 | ||
669a5db4 JG |
603 | static void __exit serverworks_exit(void) |
604 | { | |
605 | pci_unregister_driver(&serverworks_pci_driver); | |
606 | } | |
607 | ||
669a5db4 JG |
608 | MODULE_AUTHOR("Alan Cox"); |
609 | MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6"); | |
610 | MODULE_LICENSE("GPL"); | |
611 | MODULE_DEVICE_TABLE(pci, serverworks); | |
612 | MODULE_VERSION(DRV_VERSION); | |
613 | ||
614 | module_init(serverworks_init); | |
615 | module_exit(serverworks_exit); |