Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_sil680.c - SIL680 PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * based upon | |
7 | * | |
8 | * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003 | |
9 | * | |
10 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
11 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
12 | * | |
13 | * May be copied or modified under the terms of the GNU General Public License | |
14 | * | |
15 | * Documentation publically available. | |
16 | * | |
17 | * If you have strange problems with nVidia chipset systems please | |
18 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 19 | * if necessary |
669a5db4 JG |
20 | * |
21 | * TODO | |
22 | * If we know all our devices are LBA28 (or LBA28 sized) we could use | |
23 | * the command fifo mode. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/blkdev.h> | |
31 | #include <linux/delay.h> | |
32 | #include <scsi/scsi_host.h> | |
33 | #include <linux/libata.h> | |
34 | ||
35 | #define DRV_NAME "pata_sil680" | |
dd05c199 | 36 | #define DRV_VERSION "0.4.8" |
669a5db4 | 37 | |
79b0bde1 JG |
38 | #define SIL680_MMIO_BAR 5 |
39 | ||
669a5db4 JG |
40 | /** |
41 | * sil680_selreg - return register base | |
42 | * @hwif: interface | |
43 | * @r: config offset | |
44 | * | |
45 | * Turn a config register offset into the right address in either | |
46 | * PCI space or MMIO space to access the control register in question | |
47 | * Thankfully this is a configuration operation so isnt performance | |
48 | * criticial. | |
49 | */ | |
50 | ||
51 | static unsigned long sil680_selreg(struct ata_port *ap, int r) | |
52 | { | |
53 | unsigned long base = 0xA0 + r; | |
54 | base += (ap->port_no << 4); | |
55 | return base; | |
56 | } | |
57 | ||
58 | /** | |
59 | * sil680_seldev - return register base | |
60 | * @hwif: interface | |
61 | * @r: config offset | |
62 | * | |
63 | * Turn a config register offset into the right address in either | |
64 | * PCI space or MMIO space to access the control register in question | |
65 | * including accounting for the unit shift. | |
66 | */ | |
67 | ||
68 | static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r) | |
69 | { | |
70 | unsigned long base = 0xA0 + r; | |
71 | base += (ap->port_no << 4); | |
72 | base |= adev->devno ? 2 : 0; | |
73 | return base; | |
74 | } | |
75 | ||
76 | ||
77 | /** | |
78 | * sil680_cable_detect - cable detection | |
79 | * @ap: ATA port | |
80 | * | |
81 | * Perform cable detection. The SIL680 stores this in PCI config | |
82 | * space for us. | |
83 | */ | |
84 | ||
85 | static int sil680_cable_detect(struct ata_port *ap) { | |
86 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
87 | unsigned long addr = sil680_selreg(ap, 0); | |
88 | u8 ata66; | |
89 | pci_read_config_byte(pdev, addr, &ata66); | |
90 | if (ata66 & 1) | |
91 | return ATA_CBL_PATA80; | |
92 | else | |
93 | return ATA_CBL_PATA40; | |
94 | } | |
95 | ||
669a5db4 JG |
96 | /** |
97 | * sil680_set_piomode - set initial PIO mode data | |
98 | * @ap: ATA interface | |
99 | * @adev: ATA device | |
100 | * | |
101 | * Program the SIL680 registers for PIO mode. Note that the task speed | |
102 | * registers are shared between the devices so we must pick the lowest | |
103 | * mode for command work. | |
104 | */ | |
105 | ||
106 | static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
107 | { | |
108 | static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 }; | |
5dcade90 | 109 | static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 }; |
669a5db4 JG |
110 | |
111 | unsigned long tfaddr = sil680_selreg(ap, 0x02); | |
112 | unsigned long addr = sil680_seldev(ap, adev, 0x04); | |
cb0e34ba | 113 | unsigned long addr_mask = 0x80 + 4 * ap->port_no; |
669a5db4 JG |
114 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
115 | int pio = adev->pio_mode - XFER_PIO_0; | |
116 | int lowest_pio = pio; | |
cb0e34ba | 117 | int port_shift = 4 * adev->devno; |
669a5db4 | 118 | u16 reg; |
cb0e34ba | 119 | u8 mode; |
669a5db4 JG |
120 | |
121 | struct ata_device *pair = ata_dev_pair(adev); | |
122 | ||
123 | if (pair != NULL && adev->pio_mode > pair->pio_mode) | |
124 | lowest_pio = pair->pio_mode - XFER_PIO_0; | |
125 | ||
126 | pci_write_config_word(pdev, addr, speed_p[pio]); | |
127 | pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]); | |
128 | ||
129 | pci_read_config_word(pdev, tfaddr-2, ®); | |
cb0e34ba | 130 | pci_read_config_byte(pdev, addr_mask, &mode); |
a84471fe | 131 | |
669a5db4 | 132 | reg &= ~0x0200; /* Clear IORDY */ |
cb0e34ba | 133 | mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */ |
a84471fe | 134 | |
cb0e34ba | 135 | if (ata_pio_need_iordy(adev)) { |
669a5db4 | 136 | reg |= 0x0200; /* Enable IORDY */ |
cb0e34ba A |
137 | mode |= 1 << port_shift; |
138 | } | |
669a5db4 | 139 | pci_write_config_word(pdev, tfaddr-2, reg); |
cb0e34ba | 140 | pci_write_config_byte(pdev, addr_mask, mode); |
669a5db4 JG |
141 | } |
142 | ||
143 | /** | |
144 | * sil680_set_dmamode - set initial DMA mode data | |
145 | * @ap: ATA interface | |
146 | * @adev: ATA device | |
147 | * | |
148 | * Program the MWDMA/UDMA modes for the sil680 k | |
149 | * chipset. The MWDMA mode values are pulled from a lookup table | |
150 | * while the chipset uses mode number for UDMA. | |
151 | */ | |
152 | ||
153 | static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
154 | { | |
155 | static u8 ultra_table[2][7] = { | |
156 | { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */ | |
157 | { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */ | |
158 | }; | |
159 | static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 }; | |
160 | ||
161 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
162 | unsigned long ma = sil680_seldev(ap, adev, 0x08); | |
163 | unsigned long ua = sil680_seldev(ap, adev, 0x0C); | |
164 | unsigned long addr_mask = 0x80 + 4 * ap->port_no; | |
165 | int port_shift = adev->devno * 4; | |
166 | u8 scsc, mode; | |
167 | u16 multi, ultra; | |
168 | ||
169 | pci_read_config_byte(pdev, 0x8A, &scsc); | |
170 | pci_read_config_byte(pdev, addr_mask, &mode); | |
171 | pci_read_config_word(pdev, ma, &multi); | |
172 | pci_read_config_word(pdev, ua, &ultra); | |
173 | ||
174 | /* Mask timing bits */ | |
175 | ultra &= ~0x3F; | |
176 | mode &= ~(0x03 << port_shift); | |
177 | ||
178 | /* Extract scsc */ | |
179 | scsc = (scsc & 0x30) ? 1: 0; | |
180 | ||
181 | if (adev->dma_mode >= XFER_UDMA_0) { | |
182 | multi = 0x10C1; | |
183 | ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0]; | |
184 | mode |= (0x03 << port_shift); | |
185 | } else { | |
186 | multi = dma_table[adev->dma_mode - XFER_MW_DMA_0]; | |
187 | mode |= (0x02 << port_shift); | |
188 | } | |
189 | pci_write_config_byte(pdev, addr_mask, mode); | |
190 | pci_write_config_word(pdev, ma, multi); | |
191 | pci_write_config_word(pdev, ua, ultra); | |
192 | } | |
193 | ||
194 | static struct scsi_host_template sil680_sht = { | |
68d1d07b | 195 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
196 | }; |
197 | ||
198 | static struct ata_port_operations sil680_port_ops = { | |
029cfd6b TH |
199 | .inherits = &ata_bmdma_port_ops, |
200 | .cable_detect = sil680_cable_detect, | |
669a5db4 JG |
201 | .set_piomode = sil680_set_piomode, |
202 | .set_dmamode = sil680_set_dmamode, | |
669a5db4 JG |
203 | }; |
204 | ||
8550c163 A |
205 | /** |
206 | * sil680_init_chip - chip setup | |
207 | * @pdev: PCI device | |
208 | * | |
209 | * Perform all the chip setup which must be done both when the device | |
210 | * is powered up on boot and when we resume in case we resumed from RAM. | |
211 | * Returns the final clock settings. | |
212 | */ | |
f20b16ff | 213 | |
2b9e68f7 | 214 | static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio) |
669a5db4 | 215 | { |
669a5db4 JG |
216 | u32 class_rev = 0; |
217 | u8 tmpbyte = 0; | |
218 | ||
669a5db4 JG |
219 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); |
220 | class_rev &= 0xff; | |
221 | /* FIXME: double check */ | |
222 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); | |
223 | ||
224 | pci_write_config_byte(pdev, 0x80, 0x00); | |
225 | pci_write_config_byte(pdev, 0x84, 0x00); | |
226 | ||
227 | pci_read_config_byte(pdev, 0x8A, &tmpbyte); | |
228 | ||
79b0bde1 JG |
229 | dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
230 | tmpbyte & 1, tmpbyte & 0x30); | |
669a5db4 | 231 | |
0f436eff | 232 | *try_mmio = 0; |
119b3aa6 | 233 | #ifdef CONFIG_PPC_MERGE |
0f436eff BH |
234 | if (machine_is(cell)) |
235 | *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5); | |
236 | #endif | |
2b9e68f7 | 237 | |
669a5db4 JG |
238 | switch(tmpbyte & 0x30) { |
239 | case 0x00: | |
240 | /* 133 clock attempt to force it on */ | |
241 | pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10); | |
242 | break; | |
243 | case 0x30: | |
244 | /* if clocking is disabled */ | |
245 | /* 133 clock attempt to force it on */ | |
246 | pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20); | |
247 | break; | |
248 | case 0x10: | |
249 | /* 133 already */ | |
250 | break; | |
251 | case 0x20: | |
252 | /* BIOS set PCI x2 clocking */ | |
253 | break; | |
254 | } | |
255 | ||
256 | pci_read_config_byte(pdev, 0x8A, &tmpbyte); | |
79b0bde1 JG |
257 | dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
258 | tmpbyte & 1, tmpbyte & 0x30); | |
669a5db4 JG |
259 | |
260 | pci_write_config_byte(pdev, 0xA1, 0x72); | |
261 | pci_write_config_word(pdev, 0xA2, 0x328A); | |
262 | pci_write_config_dword(pdev, 0xA4, 0x62DD62DD); | |
263 | pci_write_config_dword(pdev, 0xA8, 0x43924392); | |
264 | pci_write_config_dword(pdev, 0xAC, 0x40094009); | |
265 | pci_write_config_byte(pdev, 0xB1, 0x72); | |
266 | pci_write_config_word(pdev, 0xB2, 0x328A); | |
267 | pci_write_config_dword(pdev, 0xB4, 0x62DD62DD); | |
268 | pci_write_config_dword(pdev, 0xB8, 0x43924392); | |
269 | pci_write_config_dword(pdev, 0xBC, 0x40094009); | |
270 | ||
271 | switch(tmpbyte & 0x30) { | |
272 | case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break; | |
273 | case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break; | |
274 | case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break; | |
275 | /* This last case is _NOT_ ok */ | |
276 | case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n"); | |
8550c163 A |
277 | } |
278 | return tmpbyte & 0x30; | |
279 | } | |
280 | ||
79b0bde1 JG |
281 | static int __devinit sil680_init_one(struct pci_dev *pdev, |
282 | const struct pci_device_id *id) | |
8550c163 | 283 | { |
1626aeb8 | 284 | static const struct ata_port_info info = { |
1d2808fd | 285 | .flags = ATA_FLAG_SLAVE_POSS, |
8550c163 A |
286 | .pio_mask = 0x1f, |
287 | .mwdma_mask = 0x07, | |
bf6263a8 | 288 | .udma_mask = ATA_UDMA6, |
8550c163 A |
289 | .port_ops = &sil680_port_ops |
290 | }; | |
1626aeb8 | 291 | static const struct ata_port_info info_slow = { |
1d2808fd | 292 | .flags = ATA_FLAG_SLAVE_POSS, |
8550c163 A |
293 | .pio_mask = 0x1f, |
294 | .mwdma_mask = 0x07, | |
bf6263a8 | 295 | .udma_mask = ATA_UDMA5, |
8550c163 A |
296 | .port_ops = &sil680_port_ops |
297 | }; | |
1626aeb8 | 298 | const struct ata_port_info *ppi[] = { &info, NULL }; |
8550c163 | 299 | static int printed_version; |
2b9e68f7 BH |
300 | struct ata_host *host; |
301 | void __iomem *mmio_base; | |
302 | int rc, try_mmio; | |
8550c163 A |
303 | |
304 | if (!printed_version++) | |
305 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
306 | ||
f08048e9 TH |
307 | rc = pcim_enable_device(pdev); |
308 | if (rc) | |
309 | return rc; | |
310 | ||
2b9e68f7 | 311 | switch (sil680_init_chip(pdev, &try_mmio)) { |
8550c163 | 312 | case 0: |
1626aeb8 | 313 | ppi[0] = &info_slow; |
8550c163 A |
314 | break; |
315 | case 0x30: | |
316 | return -ENODEV; | |
669a5db4 | 317 | } |
2b9e68f7 BH |
318 | |
319 | if (!try_mmio) | |
320 | goto use_ioports; | |
321 | ||
322 | /* Try to acquire MMIO resources and fallback to PIO if | |
323 | * that fails | |
324 | */ | |
325 | rc = pcim_enable_device(pdev); | |
326 | if (rc) | |
327 | return rc; | |
328 | rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME); | |
329 | if (rc) | |
330 | goto use_ioports; | |
331 | ||
332 | /* Allocate host and set it up */ | |
333 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
334 | if (!host) | |
335 | return -ENOMEM; | |
336 | host->iomap = pcim_iomap_table(pdev); | |
337 | ||
338 | /* Setup DMA masks */ | |
339 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
340 | if (rc) | |
341 | return rc; | |
342 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
343 | if (rc) | |
344 | return rc; | |
345 | pci_set_master(pdev); | |
346 | ||
347 | /* Get MMIO base and initialize port addresses */ | |
348 | mmio_base = host->iomap[SIL680_MMIO_BAR]; | |
349 | host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; | |
350 | host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; | |
351 | host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; | |
352 | host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; | |
9363c382 | 353 | ata_sff_std_ports(&host->ports[0]->ioaddr); |
2b9e68f7 BH |
354 | host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; |
355 | host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; | |
356 | host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; | |
357 | host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; | |
9363c382 | 358 | ata_sff_std_ports(&host->ports[1]->ioaddr); |
2b9e68f7 BH |
359 | |
360 | /* Register & activate */ | |
9363c382 TH |
361 | return ata_host_activate(host, pdev->irq, ata_sff_interrupt, |
362 | IRQF_SHARED, &sil680_sht); | |
2b9e68f7 BH |
363 | |
364 | use_ioports: | |
9363c382 | 365 | return ata_pci_sff_init_one(pdev, ppi, &sil680_sht, NULL); |
669a5db4 JG |
366 | } |
367 | ||
438ac6d5 | 368 | #ifdef CONFIG_PM |
8550c163 A |
369 | static int sil680_reinit_one(struct pci_dev *pdev) |
370 | { | |
f08048e9 TH |
371 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
372 | int try_mmio, rc; | |
2b9e68f7 | 373 | |
f08048e9 TH |
374 | rc = ata_pci_device_do_resume(pdev); |
375 | if (rc) | |
376 | return rc; | |
2b9e68f7 | 377 | sil680_init_chip(pdev, &try_mmio); |
f08048e9 TH |
378 | ata_host_resume(host); |
379 | return 0; | |
8550c163 | 380 | } |
438ac6d5 | 381 | #endif |
8550c163 | 382 | |
669a5db4 | 383 | static const struct pci_device_id sil680[] = { |
2d2744fc JG |
384 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, |
385 | ||
386 | { }, | |
669a5db4 JG |
387 | }; |
388 | ||
389 | static struct pci_driver sil680_pci_driver = { | |
2d2744fc | 390 | .name = DRV_NAME, |
669a5db4 JG |
391 | .id_table = sil680, |
392 | .probe = sil680_init_one, | |
8550c163 | 393 | .remove = ata_pci_remove_one, |
438ac6d5 | 394 | #ifdef CONFIG_PM |
8550c163 A |
395 | .suspend = ata_pci_device_suspend, |
396 | .resume = sil680_reinit_one, | |
438ac6d5 | 397 | #endif |
669a5db4 JG |
398 | }; |
399 | ||
400 | static int __init sil680_init(void) | |
401 | { | |
402 | return pci_register_driver(&sil680_pci_driver); | |
403 | } | |
404 | ||
669a5db4 JG |
405 | static void __exit sil680_exit(void) |
406 | { | |
407 | pci_unregister_driver(&sil680_pci_driver); | |
408 | } | |
409 | ||
669a5db4 JG |
410 | MODULE_AUTHOR("Alan Cox"); |
411 | MODULE_DESCRIPTION("low-level driver for SI680 PATA"); | |
412 | MODULE_LICENSE("GPL"); | |
413 | MODULE_DEVICE_TABLE(pci, sil680); | |
414 | MODULE_VERSION(DRV_VERSION); | |
415 | ||
416 | module_init(sil680_init); | |
417 | module_exit(sil680_exit); |