[deliverable/linux.git] / drivers / ata / pata_sil680.c

/*
 * pata_sil680.c 	- SIL680 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon
 *
 * linux/drivers/ide/pci/siimage.c		Version 1.07	Nov 30, 2003
 *
 * Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2003		Red Hat <alan@redhat.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  Documentation publically available.
 *
 *	If you have strange problems with nVidia chipset systems please
 *	see the SI support documentation and update your system BIOS
 *	if neccessary
 *
 * TODO
 *	If we know all our devices are LBA28 (or LBA28 sized)  we could use
 *	the command fifo mode.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sil680"
#define DRV_VERSION "0.4.6"

/**
 *	sil680_selreg		-	return register base
 *	@hwif: interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in either
 *	PCI space or MMIO space to access the control register in question
 *	Thankfully this is a configuration operation so isnt performance
 *	criticial.
 */

static unsigned long sil680_selreg(struct ata_port *ap, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	return base;
}

/**
 *	sil680_seldev		-	return register base
 *	@hwif: interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in either
 *	PCI space or MMIO space to access the control register in question
 *	including accounting for the unit shift.
 */

static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	base |= adev->devno ? 2 : 0;
	return base;
}


/**
 *	sil680_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. The SIL680 stores this in PCI config
 *	space for us.
 */

static int sil680_cable_detect(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long addr = sil680_selreg(ap, 0);
	u8 ata66;
	pci_read_config_byte(pdev, addr, &ata66);
	if (ata66 & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

/**
 *	sil680_bus_reset	-	reset the SIL680 bus
 *	@ap: ATA port to reset
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform the SIL680 housekeeping when doing an ATA bus reset
 */

static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes,
			    unsigned long deadline)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long addr = sil680_selreg(ap, 0);
	u8 reset;

	pci_read_config_byte(pdev, addr, &reset);
	pci_write_config_byte(pdev, addr, reset | 0x03);
	udelay(25);
	pci_write_config_byte(pdev, addr, reset);
	return ata_std_softreset(ap, classes, deadline);
}

static void sil680_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, ata_std_prereset, sil680_bus_reset, NULL, ata_std_postreset);
}

/**
 *	sil680_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the SIL680 registers for PIO mode. Note that the task speed
 *	registers are shared between the devices so we must pick the lowest
 *	mode for command work.
 */

static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
	static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };

	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	unsigned long addr = sil680_seldev(ap, adev, 0x04);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int lowest_pio = pio;
	int port_shift = 4 * adev->devno;
	u16 reg;
	u8 mode;

	struct ata_device *pair = ata_dev_pair(adev);

	if (pair != NULL && adev->pio_mode > pair->pio_mode)
		lowest_pio = pair->pio_mode - XFER_PIO_0;

	pci_write_config_word(pdev, addr, speed_p[pio]);
	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);

	pci_read_config_word(pdev, tfaddr-2, &reg);
	pci_read_config_byte(pdev, addr_mask, &mode);

	reg &= ~0x0200;			/* Clear IORDY */
	mode &= ~(3 << port_shift);	/* Clear IORDY and DMA bits */

	if (ata_pio_need_iordy(adev)) {
		reg |= 0x0200;		/* Enable IORDY */
		mode |= 1 << port_shift;
	}
	pci_write_config_word(pdev, tfaddr-2, reg);
	pci_write_config_byte(pdev, addr_mask, mode);
}

/**
 *	sil680_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the sil680 k
 *	chipset. The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static u8 ultra_table[2][7] = {
		{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },	/* 100MHz */
		{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },	/* 133Mhz */
	};
	static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	int port_shift = adev->devno * 4;
	u8 scsc, mode;
	u16 multi, ultra;

	pci_read_config_byte(pdev, 0x8A, &scsc);
	pci_read_config_byte(pdev, addr_mask, &mode);
	pci_read_config_word(pdev, ma, &multi);
	pci_read_config_word(pdev, ua, &ultra);

	/* Mask timing bits */
	ultra &= ~0x3F;
	mode &= ~(0x03 << port_shift);

	/* Extract scsc */
	scsc = (scsc & 0x30) ? 1: 0;

	if (adev->dma_mode >= XFER_UDMA_0) {
		multi = 0x10C1;
		ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
		mode |= (0x03 << port_shift);
	} else {
		multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
		mode |= (0x02 << port_shift);
	}
	pci_write_config_byte(pdev, addr_mask, mode);
	pci_write_config_word(pdev, ma, multi);
	pci_write_config_word(pdev, ua, ultra);
}

static struct scsi_host_template sil680_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations sil680_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= sil680_set_piomode,
	.set_dmamode	= sil680_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= sil680_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= sil680_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

/**
 *	sil680_init_chip		-	chip setup
 *	@pdev: PCI device
 *
 *	Perform all the chip setup which must be done both when the device
 *	is powered up on boot and when we resume in case we resumed from RAM.
 *	Returns the final clock settings.
 */

static u8 sil680_init_chip(struct pci_dev *pdev)
{
	u32 class_rev	= 0;
	u8 tmpbyte	= 0;

        pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
        class_rev &= 0xff;
        /* FIXME: double check */
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);

	pci_write_config_byte(pdev, 0x80, 0x00);
	pci_write_config_byte(pdev, 0x84, 0x00);

	pci_read_config_byte(pdev, 0x8A, &tmpbyte);

	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
			tmpbyte & 1, tmpbyte & 0x30);

	switch(tmpbyte & 0x30) {
		case 0x00:
			/* 133 clock attempt to force it on */
			pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
			break;
		case 0x30:
			/* if clocking is disabled */
			/* 133 clock attempt to force it on */
			pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
			break;
		case 0x10:
			/* 133 already */
			break;
		case 0x20:
			/* BIOS set PCI x2 clocking */
			break;
	}

	pci_read_config_byte(pdev,   0x8A, &tmpbyte);
	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
			tmpbyte & 1, tmpbyte & 0x30);

	pci_write_config_byte(pdev,  0xA1, 0x72);
	pci_write_config_word(pdev,  0xA2, 0x328A);
	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	pci_write_config_byte(pdev,  0xB1, 0x72);
	pci_write_config_word(pdev,  0xB2, 0x328A);
	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	pci_write_config_dword(pdev, 0xBC, 0x40094009);

	switch(tmpbyte & 0x30) {
		case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
		case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
		case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
		/* This last case is _NOT_ ok */
		case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
	}
	return tmpbyte & 0x30;
}

static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.sht = &sil680_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x7f,
		.port_ops = &sil680_port_ops
	};
	static const struct ata_port_info info_slow = {
		.sht = &sil680_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x3f,
		.port_ops = &sil680_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };
	static int printed_version;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	switch(sil680_init_chip(pdev))
	{
		case 0:
			ppi[0] = &info_slow;
			break;
		case 0x30:
			return -ENODEV;
	}
	return ata_pci_init_one(pdev, ppi);
}

#ifdef CONFIG_PM
static int sil680_reinit_one(struct pci_dev *pdev)
{
	sil680_init_chip(pdev);
	return ata_pci_device_resume(pdev);
}
#endif

static const struct pci_device_id sil680[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },

	{ },
};

static struct pci_driver sil680_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sil680,
	.probe 		= sil680_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= sil680_reinit_one,
#endif
};

static int __init sil680_init(void)
{
	return pci_register_driver(&sil680_pci_driver);
}

static void __exit sil680_exit(void)
{
	pci_unregister_driver(&sil680_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for SI680 PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil680);
MODULE_VERSION(DRV_VERSION);

module_init(sil680_init);
module_exit(sil680_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sil680.c - SIL680 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon
	7	*
	8	* linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
	9	*
	10	* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
	11	* Copyright (C) 2003 Red Hat <alan@redhat.com>
	12	*
	13	* May be copied or modified under the terms of the GNU General Public License
	14	*
	15	* Documentation publically available.
	16	*
	17	* If you have strange problems with nVidia chipset systems please
	18	* see the SI support documentation and update your system BIOS
	19	* if neccessary
	20	*
	21	* TODO
	22	* If we know all our devices are LBA28 (or LBA28 sized) we could use
	23	* the command fifo mode.
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34
	35	#define DRV_NAME "pata_sil680"
a0fcdc02	36	#define DRV_VERSION "0.4.6"
669a5db4 JG	37
	38	/**
	39	* sil680_selreg - return register base
	40	* @hwif: interface
	41	* @r: config offset
	42	*
	43	* Turn a config register offset into the right address in either
	44	* PCI space or MMIO space to access the control register in question
	45	* Thankfully this is a configuration operation so isnt performance
	46	* criticial.
	47	*/
	48
	49	static unsigned long sil680_selreg(struct ata_port *ap, int r)
	50	{
	51	unsigned long base = 0xA0 + r;
	52	base += (ap->port_no << 4);
	53	return base;
	54	}
	55
	56	/**
	57	* sil680_seldev - return register base
	58	* @hwif: interface
	59	* @r: config offset
	60	*
	61	* Turn a config register offset into the right address in either
	62	* PCI space or MMIO space to access the control register in question
	63	* including accounting for the unit shift.
	64	*/
	65
	66	static unsigned long sil680_seldev(struct ata_port ap, struct ata_device adev, int r)
	67	{
	68	unsigned long base = 0xA0 + r;
	69	base += (ap->port_no << 4);
	70	base \|= adev->devno ? 2 : 0;
	71	return base;
	72	}
	73
	74
	75	/**
	76	* sil680_cable_detect - cable detection
	77	* @ap: ATA port
	78	*
	79	* Perform cable detection. The SIL680 stores this in PCI config
	80	* space for us.
	81	*/
	82
	83	static int sil680_cable_detect(struct ata_port *ap) {
	84	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	85	unsigned long addr = sil680_selreg(ap, 0);
	86	u8 ata66;
	87	pci_read_config_byte(pdev, addr, &ata66);
	88	if (ata66 & 1)
	89	return ATA_CBL_PATA80;
	90	else
	91	return ATA_CBL_PATA40;
	92	}
	93
669a5db4 JG	94	/**
	95	* sil680_bus_reset - reset the SIL680 bus
	96	* @ap: ATA port to reset
d4b2bab4	97	* @deadline: deadline jiffies for the operation
669a5db4 JG	98	*
	99	* Perform the SIL680 housekeeping when doing an ATA bus reset
	100	*/
	101
d4b2bab4 TH	102	static int sil680_bus_reset(struct ata_port ap,unsigned int classes,
d4b2bab4 TH	103	unsigned long deadline)
669a5db4 JG	104	{
	105	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	106	unsigned long addr = sil680_selreg(ap, 0);
	107	u8 reset;
	108
	109	pci_read_config_byte(pdev, addr, &reset);
	110	pci_write_config_byte(pdev, addr, reset \| 0x03);
	111	udelay(25);
	112	pci_write_config_byte(pdev, addr, reset);
d4b2bab4	113	return ata_std_softreset(ap, classes, deadline);
669a5db4 JG	114	}
	115
	116	static void sil680_error_handler(struct ata_port *ap)
	117	{
a0fcdc02	118	ata_bmdma_drive_eh(ap, ata_std_prereset, sil680_bus_reset, NULL, ata_std_postreset);
669a5db4 JG	119	}
	120
	121	/**
	122	* sil680_set_piomode - set initial PIO mode data
	123	* @ap: ATA interface
	124	* @adev: ATA device
	125	*
	126	* Program the SIL680 registers for PIO mode. Note that the task speed
	127	* registers are shared between the devices so we must pick the lowest
	128	* mode for command work.
	129	*/
	130
	131	static void sil680_set_piomode(struct ata_port ap, struct ata_device adev)
	132	{
	133	static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
5dcade90	134	static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
669a5db4 JG	135
	136	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	137	unsigned long addr = sil680_seldev(ap, adev, 0x04);
cb0e34ba	138	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
669a5db4 JG	139	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	140	int pio = adev->pio_mode - XFER_PIO_0;
	141	int lowest_pio = pio;
cb0e34ba	142	int port_shift = 4 * adev->devno;
669a5db4	143	u16 reg;
cb0e34ba	144	u8 mode;
669a5db4 JG	145
	146	struct ata_device *pair = ata_dev_pair(adev);
	147
	148	if (pair != NULL && adev->pio_mode > pair->pio_mode)
	149	lowest_pio = pair->pio_mode - XFER_PIO_0;
	150
	151	pci_write_config_word(pdev, addr, speed_p[pio]);
	152	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
	153
	154	pci_read_config_word(pdev, tfaddr-2, &reg);
cb0e34ba	155	pci_read_config_byte(pdev, addr_mask, &mode);
a84471fe	156
669a5db4	157	reg &= ~0x0200; /* Clear IORDY */
cb0e34ba	158	mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
a84471fe	159
cb0e34ba	160	if (ata_pio_need_iordy(adev)) {
669a5db4	161	reg \|= 0x0200; /* Enable IORDY */
cb0e34ba A	162	mode \|= 1 << port_shift;
cb0e34ba A	163	}
669a5db4	164	pci_write_config_word(pdev, tfaddr-2, reg);
cb0e34ba	165	pci_write_config_byte(pdev, addr_mask, mode);
669a5db4 JG	166	}
	167
	168	/**
	169	* sil680_set_dmamode - set initial DMA mode data
	170	* @ap: ATA interface
	171	* @adev: ATA device
	172	*
	173	* Program the MWDMA/UDMA modes for the sil680 k
	174	* chipset. The MWDMA mode values are pulled from a lookup table
	175	* while the chipset uses mode number for UDMA.
	176	*/
	177
	178	static void sil680_set_dmamode(struct ata_port ap, struct ata_device adev)
	179	{
	180	static u8 ultra_table[2][7] = {
	181	{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
	182	{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
	183	};
	184	static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
	185
	186	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	187	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	188	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	189	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	190	int port_shift = adev->devno * 4;
	191	u8 scsc, mode;
	192	u16 multi, ultra;
	193
	194	pci_read_config_byte(pdev, 0x8A, &scsc);
	195	pci_read_config_byte(pdev, addr_mask, &mode);
	196	pci_read_config_word(pdev, ma, &multi);
	197	pci_read_config_word(pdev, ua, &ultra);
	198
	199	/* Mask timing bits */
	200	ultra &= ~0x3F;
	201	mode &= ~(0x03 << port_shift);
	202
	203	/* Extract scsc */
	204	scsc = (scsc & 0x30) ? 1: 0;
	205
	206	if (adev->dma_mode >= XFER_UDMA_0) {
	207	multi = 0x10C1;
	208	ultra \|= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
	209	mode \|= (0x03 << port_shift);
	210	} else {
	211	multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
	212	mode \|= (0x02 << port_shift);
	213	}
	214	pci_write_config_byte(pdev, addr_mask, mode);
	215	pci_write_config_word(pdev, ma, multi);
	216	pci_write_config_word(pdev, ua, ultra);
	217	}
	218
	219	static struct scsi_host_template sil680_sht = {
	220	.module = THIS_MODULE,
	221	.name = DRV_NAME,
	222	.ioctl = ata_scsi_ioctl,
	223	.queuecommand = ata_scsi_queuecmd,
	224	.can_queue = ATA_DEF_QUEUE,
	225	.this_id = ATA_SHT_THIS_ID,
	226	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	227	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	228	.emulated = ATA_SHT_EMULATED,
	229	.use_clustering = ATA_SHT_USE_CLUSTERING,
	230	.proc_name = DRV_NAME,
	231	.dma_boundary = ATA_DMA_BOUNDARY,
	232	.slave_configure = ata_scsi_slave_config,
afdfe899	233	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	234	.bios_param = ata_std_bios_param,
	235	};
	236
	237	static struct ata_port_operations sil680_port_ops = {
	238	.port_disable = ata_port_disable,
	239	.set_piomode = sil680_set_piomode,
	240	.set_dmamode = sil680_set_dmamode,
	241	.mode_filter = ata_pci_default_filter,
	242	.tf_load = ata_tf_load,
	243	.tf_read = ata_tf_read,
	244	.check_status = ata_check_status,
	245	.exec_command = ata_exec_command,
	246	.dev_select = ata_std_dev_select,
	247
	248	.freeze = ata_bmdma_freeze,
	249	.thaw = ata_bmdma_thaw,
	250	.error_handler = sil680_error_handler,
	251	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	252	.cable_detect = sil680_cable_detect,
669a5db4 JG	253
	254	.bmdma_setup = ata_bmdma_setup,
	255	.bmdma_start = ata_bmdma_start,
	256	.bmdma_stop = ata_bmdma_stop,
	257	.bmdma_status = ata_bmdma_status,
	258
	259	.qc_prep = ata_qc_prep,
	260	.qc_issue = ata_qc_issue_prot,
bda30288	261
0d5ff566	262	.data_xfer = ata_data_xfer,
669a5db4 JG	263
	264	.irq_handler = ata_interrupt,
	265	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	266	.irq_on = ata_irq_on,
246ce3b6 AI	267	.irq_ack = ata_irq_ack,
669a5db4 JG	268
669a5db4 JG	269	.port_start = ata_port_start,
669a5db4 JG	270	};
669a5db4 JG	271
8550c163 A	272	/**
	273	* sil680_init_chip - chip setup
	274	* @pdev: PCI device
	275	*
	276	* Perform all the chip setup which must be done both when the device
	277	* is powered up on boot and when we resume in case we resumed from RAM.
	278	* Returns the final clock settings.
	279	*/
f20b16ff	280
8550c163	281	static u8 sil680_init_chip(struct pci_dev *pdev)
669a5db4	282	{
669a5db4 JG	283	u32 class_rev = 0;
	284	u8 tmpbyte = 0;
	285
669a5db4 JG	286	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	287	class_rev &= 0xff;
	288	/* FIXME: double check */
	289	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
	290
	291	pci_write_config_byte(pdev, 0x80, 0x00);
	292	pci_write_config_byte(pdev, 0x84, 0x00);
	293
	294	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
	295
	296	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
	297	tmpbyte & 1, tmpbyte & 0x30);
	298
	299	switch(tmpbyte & 0x30) {
	300	case 0x00:
	301	/* 133 clock attempt to force it on */
	302	pci_write_config_byte(pdev, 0x8A, tmpbyte\|0x10);
	303	break;
	304	case 0x30:
	305	/* if clocking is disabled */
	306	/* 133 clock attempt to force it on */
	307	pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
	308	break;
	309	case 0x10:
	310	/* 133 already */
	311	break;
	312	case 0x20:
	313	/* BIOS set PCI x2 clocking */
	314	break;
	315	}
	316
	317	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
	318	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
	319	tmpbyte & 1, tmpbyte & 0x30);
669a5db4 JG	320
	321	pci_write_config_byte(pdev, 0xA1, 0x72);
	322	pci_write_config_word(pdev, 0xA2, 0x328A);
	323	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	324	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	325	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	326	pci_write_config_byte(pdev, 0xB1, 0x72);
	327	pci_write_config_word(pdev, 0xB2, 0x328A);
	328	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	329	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	330	pci_write_config_dword(pdev, 0xBC, 0x40094009);
	331
	332	switch(tmpbyte & 0x30) {
	333	case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
	334	case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
	335	case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
	336	/* This last case is _NOT_ ok */
	337	case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
8550c163 A	338	}
	339	return tmpbyte & 0x30;
	340	}
	341
	342	static int sil680_init_one(struct pci_dev pdev, const struct pci_device_id id)
	343	{
1626aeb8	344	static const struct ata_port_info info = {
8550c163 A	345	.sht = &sil680_sht,
	346	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	347	.pio_mask = 0x1f,
	348	.mwdma_mask = 0x07,
	349	.udma_mask = 0x7f,
	350	.port_ops = &sil680_port_ops
	351	};
1626aeb8	352	static const struct ata_port_info info_slow = {
8550c163 A	353	.sht = &sil680_sht,
	354	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	355	.pio_mask = 0x1f,
	356	.mwdma_mask = 0x07,
	357	.udma_mask = 0x3f,
	358	.port_ops = &sil680_port_ops
	359	};
1626aeb8	360	const struct ata_port_info *ppi[] = { &info, NULL };
8550c163 A	361	static int printed_version;
	362
	363	if (!printed_version++)
	364	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	365
	366	switch(sil680_init_chip(pdev))
	367	{
	368	case 0:
1626aeb8	369	ppi[0] = &info_slow;
8550c163 A	370	break;
	371	case 0x30:
	372	return -ENODEV;
669a5db4	373	}
1626aeb8	374	return ata_pci_init_one(pdev, ppi);
669a5db4 JG	375	}
669a5db4 JG	376
438ac6d5	377	#ifdef CONFIG_PM
8550c163 A	378	static int sil680_reinit_one(struct pci_dev *pdev)
	379	{
	380	sil680_init_chip(pdev);
	381	return ata_pci_device_resume(pdev);
	382	}
438ac6d5	383	#endif
8550c163	384
669a5db4	385	static const struct pci_device_id sil680[] = {
2d2744fc JG	386	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
	387
	388	{ },
669a5db4 JG	389	};
	390
	391	static struct pci_driver sil680_pci_driver = {
2d2744fc	392	.name = DRV_NAME,
669a5db4 JG	393	.id_table = sil680,
669a5db4 JG	394	.probe = sil680_init_one,
8550c163	395	.remove = ata_pci_remove_one,
438ac6d5	396	#ifdef CONFIG_PM
8550c163 A	397	.suspend = ata_pci_device_suspend,
8550c163 A	398	.resume = sil680_reinit_one,
438ac6d5	399	#endif
669a5db4 JG	400	};
	401
	402	static int __init sil680_init(void)
	403	{
	404	return pci_register_driver(&sil680_pci_driver);
	405	}
	406
669a5db4 JG	407	static void __exit sil680_exit(void)
	408	{
	409	pci_unregister_driver(&sil680_pci_driver);
	410	}
	411
669a5db4 JG	412	MODULE_AUTHOR("Alan Cox");
	413	MODULE_DESCRIPTION("low-level driver for SI680 PATA");
	414	MODULE_LICENSE("GPL");
	415	MODULE_DEVICE_TABLE(pci, sil680);
	416	MODULE_VERSION(DRV_VERSION);
	417
	418	module_init(sil680_init);
	419	module_exit(sil680_exit);