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669a5db4 JG |
1 | /* |
2 | * pata_sis.c - SiS ATA driver | |
3 | * | |
4 | * (C) 2005 Red Hat <alan@redhat.com> | |
4761c06c | 5 | * (C) 2007 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
6 | * |
7 | * Based upon linux/drivers/ide/pci/sis5513.c | |
8 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
9 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
10 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
11 | * SiS Taiwan : for direct support and hardware. | |
12 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
13 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
14 | * for checking code correctness, providing patches. | |
15 | * Original tests and design on the SiS620 chipset. | |
16 | * ATA100 tests and design on the SiS735 chipset. | |
17 | * ATA16/33 support from specs | |
18 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
19 | * | |
20 | * | |
21 | * TODO | |
22 | * Check MWDMA on drives that don't support MWDMA speed pio cycles ? | |
23 | * More Testing | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/blkdev.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/device.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <linux/libata.h> | |
35 | #include <linux/ata.h> | |
4bb64fb9 | 36 | #include "sis.h" |
669a5db4 JG |
37 | |
38 | #define DRV_NAME "pata_sis" | |
4761c06c | 39 | #define DRV_VERSION "0.5.2" |
669a5db4 JG |
40 | |
41 | struct sis_chipset { | |
1626aeb8 TH |
42 | u16 device; /* PCI host ID */ |
43 | const struct ata_port_info *info; /* Info block */ | |
669a5db4 JG |
44 | /* Probably add family, cable detect type etc here to clean |
45 | up code later */ | |
46 | }; | |
47 | ||
7dcbc1f2 JJ |
48 | struct sis_laptop { |
49 | u16 device; | |
50 | u16 subvendor; | |
51 | u16 subdevice; | |
52 | }; | |
53 | ||
54 | static const struct sis_laptop sis_laptop[] = { | |
55 | /* devid, subvendor, subdev */ | |
56 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ | |
4f2d47cf | 57 | { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ |
7dcbc1f2 JJ |
58 | /* end marker */ |
59 | { 0, } | |
60 | }; | |
61 | ||
62 | static int sis_short_ata40(struct pci_dev *dev) | |
63 | { | |
64 | const struct sis_laptop *lap = &sis_laptop[0]; | |
65 | ||
66 | while (lap->device) { | |
67 | if (lap->device == dev->device && | |
68 | lap->subvendor == dev->subsystem_vendor && | |
69 | lap->subdevice == dev->subsystem_device) | |
70 | return 1; | |
71 | lap++; | |
72 | } | |
73 | ||
74 | return 0; | |
75 | } | |
76 | ||
669a5db4 | 77 | /** |
dd668d15 | 78 | * sis_old_port_base - return PCI configuration base for dev |
669a5db4 JG |
79 | * @adev: device |
80 | * | |
81 | * Returns the base of the PCI configuration registers for this port | |
82 | * number. | |
83 | */ | |
84 | ||
dd668d15 | 85 | static int sis_old_port_base(struct ata_device *adev) |
669a5db4 JG |
86 | { |
87 | return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno); | |
88 | } | |
89 | ||
90 | /** | |
2e413f51 | 91 | * sis_133_cable_detect - check for 40/80 pin |
669a5db4 | 92 | * @ap: Port |
d4b2bab4 | 93 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
94 | * |
95 | * Perform cable detection for the later UDMA133 capable | |
96 | * SiS chipset. | |
97 | */ | |
98 | ||
2e413f51 | 99 | static int sis_133_cable_detect(struct ata_port *ap) |
669a5db4 | 100 | { |
669a5db4 JG |
101 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
102 | u16 tmp; | |
103 | ||
669a5db4 JG |
104 | /* The top bit of this register is the cable detect bit */ |
105 | pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); | |
7dcbc1f2 | 106 | if ((tmp & 0x8000) && !sis_short_ata40(pdev)) |
2e413f51 AC |
107 | return ATA_CBL_PATA40; |
108 | return ATA_CBL_PATA80; | |
669a5db4 JG |
109 | } |
110 | ||
111 | /** | |
2e413f51 | 112 | * sis_66_cable_detect - check for 40/80 pin |
669a5db4 | 113 | * @ap: Port |
d4b2bab4 | 114 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
115 | * |
116 | * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 | |
117 | * SiS IDE controllers. | |
118 | */ | |
119 | ||
2e413f51 | 120 | static int sis_66_cable_detect(struct ata_port *ap) |
669a5db4 | 121 | { |
669a5db4 JG |
122 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
123 | u8 tmp; | |
124 | ||
669a5db4 JG |
125 | /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ |
126 | pci_read_config_byte(pdev, 0x48, &tmp); | |
127 | tmp >>= ap->port_no; | |
7dcbc1f2 | 128 | if ((tmp & 0x10) && !sis_short_ata40(pdev)) |
2e413f51 AC |
129 | return ATA_CBL_PATA40; |
130 | return ATA_CBL_PATA80; | |
669a5db4 JG |
131 | } |
132 | ||
669a5db4 JG |
133 | |
134 | /** | |
2e413f51 | 135 | * sis_pre_reset - probe begin |
669a5db4 | 136 | * @ap: ATA port |
d4b2bab4 | 137 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
138 | * |
139 | * Set up cable type and use generic probe init | |
140 | */ | |
141 | ||
27c78b37 | 142 | static int sis_pre_reset(struct ata_port *ap, unsigned long deadline) |
669a5db4 JG |
143 | { |
144 | static const struct pci_bits sis_enable_bits[] = { | |
145 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
146 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
147 | }; | |
85cd7251 | 148 | |
669a5db4 JG |
149 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
150 | ||
2e413f51 AC |
151 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) |
152 | return -ENOENT; | |
d4b2bab4 | 153 | |
15ce0943 AC |
154 | /* Clear the FIFO settings. We can't enable the FIFO until |
155 | we know we are poking at a disk */ | |
156 | pci_write_config_byte(pdev, 0x4B, 0); | |
d4b2bab4 | 157 | return ata_std_prereset(ap, deadline); |
669a5db4 JG |
158 | } |
159 | ||
160 | ||
161 | /** | |
2e413f51 | 162 | * sis_error_handler - Probe specified port on PATA host controller |
669a5db4 JG |
163 | * @ap: Port to probe |
164 | * | |
165 | * LOCKING: | |
166 | * None (inherited from caller). | |
167 | */ | |
168 | ||
2e413f51 | 169 | static void sis_error_handler(struct ata_port *ap) |
669a5db4 | 170 | { |
2e413f51 | 171 | ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset); |
669a5db4 JG |
172 | } |
173 | ||
174 | /** | |
175 | * sis_set_fifo - Set RWP fifo bits for this device | |
176 | * @ap: Port | |
177 | * @adev: Device | |
178 | * | |
179 | * SIS chipsets implement prefetch/postwrite bits for each device | |
180 | * on both channels. This functionality is not ATAPI compatible and | |
181 | * must be configured according to the class of device present | |
182 | */ | |
183 | ||
184 | static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) | |
185 | { | |
186 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
187 | u8 fifoctrl; | |
188 | u8 mask = 0x11; | |
189 | ||
190 | mask <<= (2 * ap->port_no); | |
191 | mask <<= adev->devno; | |
192 | ||
193 | /* This holds various bits including the FIFO control */ | |
194 | pci_read_config_byte(pdev, 0x4B, &fifoctrl); | |
195 | fifoctrl &= ~mask; | |
196 | ||
197 | /* Enable for ATA (disk) only */ | |
198 | if (adev->class == ATA_DEV_ATA) | |
199 | fifoctrl |= mask; | |
200 | pci_write_config_byte(pdev, 0x4B, fifoctrl); | |
201 | } | |
202 | ||
203 | /** | |
204 | * sis_old_set_piomode - Initialize host controller PATA PIO timings | |
205 | * @ap: Port whose timings we are configuring | |
206 | * @adev: Device we are configuring for. | |
207 | * | |
208 | * Set PIO mode for device, in host controller PCI config space. This | |
209 | * function handles PIO set up for all chips that are pre ATA100 and | |
210 | * also early ATA100 devices. | |
211 | * | |
212 | * LOCKING: | |
213 | * None (inherited from caller). | |
214 | */ | |
215 | ||
216 | static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
217 | { | |
218 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 219 | int port = sis_old_port_base(adev); |
669a5db4 JG |
220 | u8 t1, t2; |
221 | int speed = adev->pio_mode - XFER_PIO_0; | |
222 | ||
223 | const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; | |
224 | const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; | |
225 | ||
226 | sis_set_fifo(ap, adev); | |
227 | ||
228 | pci_read_config_byte(pdev, port, &t1); | |
229 | pci_read_config_byte(pdev, port + 1, &t2); | |
230 | ||
231 | t1 &= ~0x0F; /* Clear active/recovery timings */ | |
232 | t2 &= ~0x07; | |
233 | ||
234 | t1 |= active[speed]; | |
235 | t2 |= recovery[speed]; | |
236 | ||
237 | pci_write_config_byte(pdev, port, t1); | |
238 | pci_write_config_byte(pdev, port + 1, t2); | |
239 | } | |
240 | ||
241 | /** | |
4761c06c | 242 | * sis_100_set_piomode - Initialize host controller PATA PIO timings |
669a5db4 JG |
243 | * @ap: Port whose timings we are configuring |
244 | * @adev: Device we are configuring for. | |
245 | * | |
246 | * Set PIO mode for device, in host controller PCI config space. This | |
247 | * function handles PIO set up for ATA100 devices and early ATA133. | |
248 | * | |
249 | * LOCKING: | |
250 | * None (inherited from caller). | |
251 | */ | |
252 | ||
253 | static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
254 | { | |
255 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 256 | int port = sis_old_port_base(adev); |
669a5db4 JG |
257 | int speed = adev->pio_mode - XFER_PIO_0; |
258 | ||
259 | const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; | |
260 | ||
261 | sis_set_fifo(ap, adev); | |
262 | ||
263 | pci_write_config_byte(pdev, port, actrec[speed]); | |
264 | } | |
265 | ||
266 | /** | |
4761c06c | 267 | * sis_133_set_piomode - Initialize host controller PATA PIO timings |
669a5db4 JG |
268 | * @ap: Port whose timings we are configuring |
269 | * @adev: Device we are configuring for. | |
270 | * | |
271 | * Set PIO mode for device, in host controller PCI config space. This | |
272 | * function handles PIO set up for the later ATA133 devices. | |
273 | * | |
274 | * LOCKING: | |
275 | * None (inherited from caller). | |
276 | */ | |
277 | ||
278 | static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
279 | { | |
280 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
281 | int port = 0x40; | |
282 | u32 t1; | |
283 | u32 reg54; | |
284 | int speed = adev->pio_mode - XFER_PIO_0; | |
285 | ||
286 | const u32 timing133[] = { | |
287 | 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
288 | 0x0C266000, | |
289 | 0x04263000, | |
290 | 0x0C0A3000, | |
291 | 0x05093000 | |
292 | }; | |
293 | const u32 timing100[] = { | |
294 | 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
295 | 0x091C4000, | |
296 | 0x031C2000, | |
297 | 0x09072000, | |
298 | 0x04062000 | |
299 | }; | |
300 | ||
301 | sis_set_fifo(ap, adev); | |
302 | ||
303 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
304 | pci_read_config_dword(pdev, 0x54, ®54); | |
305 | if (reg54 & 0x40000000) | |
306 | port = 0x70; | |
307 | port += 8 * ap->port_no + 4 * adev->devno; | |
308 | ||
309 | pci_read_config_dword(pdev, port, &t1); | |
310 | t1 &= 0xC0C00FFF; /* Mask out timing */ | |
311 | ||
312 | if (t1 & 0x08) /* 100 or 133 ? */ | |
313 | t1 |= timing133[speed]; | |
314 | else | |
315 | t1 |= timing100[speed]; | |
316 | pci_write_config_byte(pdev, port, t1); | |
317 | } | |
318 | ||
319 | /** | |
320 | * sis_old_set_dmamode - Initialize host controller PATA DMA timings | |
321 | * @ap: Port whose timings we are configuring | |
322 | * @adev: Device to program | |
323 | * | |
324 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
325 | * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike | |
326 | * the old ide/pci driver. | |
327 | * | |
328 | * LOCKING: | |
329 | * None (inherited from caller). | |
330 | */ | |
331 | ||
332 | static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
333 | { | |
334 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
335 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 336 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
337 | u16 timing; |
338 | ||
4761c06c | 339 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
669a5db4 JG |
340 | const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; |
341 | ||
342 | pci_read_config_word(pdev, drive_pci, &timing); | |
343 | ||
344 | if (adev->dma_mode < XFER_UDMA_0) { | |
345 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
346 | the higer bits are dependant on the device */ | |
4761c06c | 347 | timing &= ~0x870F; |
669a5db4 | 348 | timing |= mwdma_bits[speed]; |
669a5db4 JG |
349 | } else { |
350 | /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ | |
351 | speed = adev->dma_mode - XFER_UDMA_0; | |
352 | timing &= ~0x6000; | |
353 | timing |= udma_bits[speed]; | |
354 | } | |
4761c06c | 355 | pci_write_config_word(pdev, drive_pci, timing); |
669a5db4 JG |
356 | } |
357 | ||
358 | /** | |
359 | * sis_66_set_dmamode - Initialize host controller PATA DMA timings | |
360 | * @ap: Port whose timings we are configuring | |
361 | * @adev: Device to program | |
362 | * | |
363 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
364 | * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike | |
365 | * the old ide/pci driver. | |
366 | * | |
367 | * LOCKING: | |
368 | * None (inherited from caller). | |
369 | */ | |
370 | ||
371 | static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
372 | { | |
373 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
374 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 375 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
376 | u16 timing; |
377 | ||
4761c06c | 378 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
669a5db4 JG |
379 | const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000}; |
380 | ||
381 | pci_read_config_word(pdev, drive_pci, &timing); | |
382 | ||
383 | if (adev->dma_mode < XFER_UDMA_0) { | |
384 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
385 | the higer bits are dependant on the device, bit 15 udma */ | |
dd668d15 | 386 | timing &= ~0x870F; |
669a5db4 JG |
387 | timing |= mwdma_bits[speed]; |
388 | } else { | |
389 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ | |
390 | speed = adev->dma_mode - XFER_UDMA_0; | |
dd668d15 | 391 | timing &= ~0xF000; |
669a5db4 JG |
392 | timing |= udma_bits[speed]; |
393 | } | |
394 | pci_write_config_word(pdev, drive_pci, timing); | |
395 | } | |
396 | ||
397 | /** | |
398 | * sis_100_set_dmamode - Initialize host controller PATA DMA timings | |
399 | * @ap: Port whose timings we are configuring | |
400 | * @adev: Device to program | |
401 | * | |
402 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
403 | * Handles UDMA66 and early UDMA100 devices. | |
404 | * | |
405 | * LOCKING: | |
406 | * None (inherited from caller). | |
407 | */ | |
408 | ||
409 | static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
410 | { | |
411 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
412 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 AC |
413 | int drive_pci = sis_old_port_base(adev); |
414 | u8 timing; | |
669a5db4 | 415 | |
dd668d15 | 416 | const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; |
669a5db4 | 417 | |
dd668d15 | 418 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
669a5db4 JG |
419 | |
420 | if (adev->dma_mode < XFER_UDMA_0) { | |
421 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
422 | } else { | |
dd668d15 | 423 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 424 | speed = adev->dma_mode - XFER_UDMA_0; |
dd668d15 | 425 | timing &= ~0x8F; |
669a5db4 JG |
426 | timing |= udma_bits[speed]; |
427 | } | |
dd668d15 | 428 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
669a5db4 JG |
429 | } |
430 | ||
431 | /** | |
432 | * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings | |
433 | * @ap: Port whose timings we are configuring | |
434 | * @adev: Device to program | |
435 | * | |
436 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
4761c06c | 437 | * Handles early SiS 961 bridges. |
669a5db4 JG |
438 | * |
439 | * LOCKING: | |
440 | * None (inherited from caller). | |
441 | */ | |
442 | ||
443 | static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
444 | { | |
445 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
446 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 AC |
447 | int drive_pci = sis_old_port_base(adev); |
448 | u8 timing; | |
449 | /* Low 4 bits are timing */ | |
450 | static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; | |
669a5db4 | 451 | |
dd668d15 | 452 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
669a5db4 JG |
453 | |
454 | if (adev->dma_mode < XFER_UDMA_0) { | |
455 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
456 | } else { | |
dd668d15 | 457 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 458 | speed = adev->dma_mode - XFER_UDMA_0; |
dd668d15 | 459 | timing &= ~0x8F; |
669a5db4 JG |
460 | timing |= udma_bits[speed]; |
461 | } | |
dd668d15 | 462 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
669a5db4 JG |
463 | } |
464 | ||
465 | /** | |
466 | * sis_133_set_dmamode - Initialize host controller PATA DMA timings | |
467 | * @ap: Port whose timings we are configuring | |
468 | * @adev: Device to program | |
469 | * | |
470 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
669a5db4 JG |
471 | * |
472 | * LOCKING: | |
473 | * None (inherited from caller). | |
474 | */ | |
475 | ||
476 | static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
477 | { | |
478 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
479 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
480 | int port = 0x40; | |
481 | u32 t1; | |
482 | u32 reg54; | |
483 | ||
484 | /* bits 4- cycle time 8 - cvs time */ | |
2e413f51 AC |
485 | static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; |
486 | static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; | |
669a5db4 JG |
487 | |
488 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
489 | pci_read_config_dword(pdev, 0x54, ®54); | |
490 | if (reg54 & 0x40000000) | |
491 | port = 0x70; | |
492 | port += (8 * ap->port_no) + (4 * adev->devno); | |
493 | ||
494 | pci_read_config_dword(pdev, port, &t1); | |
495 | ||
496 | if (adev->dma_mode < XFER_UDMA_0) { | |
497 | t1 &= ~0x00000004; | |
498 | /* FIXME: need data sheet to add MWDMA here. Also lacking on | |
499 | ide/pci driver */ | |
500 | } else { | |
501 | speed = adev->dma_mode - XFER_UDMA_0; | |
502 | /* if & 8 no UDMA133 - need info for ... */ | |
503 | t1 &= ~0x00000FF0; | |
504 | t1 |= 0x00000004; | |
505 | if (t1 & 0x08) | |
506 | t1 |= timing_u133[speed]; | |
507 | else | |
508 | t1 |= timing_u100[speed]; | |
509 | } | |
510 | pci_write_config_dword(pdev, port, t1); | |
511 | } | |
512 | ||
513 | static struct scsi_host_template sis_sht = { | |
514 | .module = THIS_MODULE, | |
515 | .name = DRV_NAME, | |
516 | .ioctl = ata_scsi_ioctl, | |
517 | .queuecommand = ata_scsi_queuecmd, | |
518 | .can_queue = ATA_DEF_QUEUE, | |
519 | .this_id = ATA_SHT_THIS_ID, | |
520 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
521 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
522 | .emulated = ATA_SHT_EMULATED, | |
523 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
524 | .proc_name = DRV_NAME, | |
525 | .dma_boundary = ATA_DMA_BOUNDARY, | |
526 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 527 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
528 | .bios_param = ata_std_bios_param, |
529 | }; | |
530 | ||
531 | static const struct ata_port_operations sis_133_ops = { | |
532 | .port_disable = ata_port_disable, | |
533 | .set_piomode = sis_133_set_piomode, | |
534 | .set_dmamode = sis_133_set_dmamode, | |
535 | .mode_filter = ata_pci_default_filter, | |
536 | ||
537 | .tf_load = ata_tf_load, | |
538 | .tf_read = ata_tf_read, | |
539 | .check_status = ata_check_status, | |
540 | .exec_command = ata_exec_command, | |
541 | .dev_select = ata_std_dev_select, | |
542 | ||
543 | .freeze = ata_bmdma_freeze, | |
544 | .thaw = ata_bmdma_thaw, | |
2e413f51 | 545 | .error_handler = sis_error_handler, |
669a5db4 | 546 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
2e413f51 | 547 | .cable_detect = sis_133_cable_detect, |
669a5db4 JG |
548 | |
549 | .bmdma_setup = ata_bmdma_setup, | |
550 | .bmdma_start = ata_bmdma_start, | |
551 | .bmdma_stop = ata_bmdma_stop, | |
552 | .bmdma_status = ata_bmdma_status, | |
553 | .qc_prep = ata_qc_prep, | |
554 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 555 | .data_xfer = ata_data_xfer, |
669a5db4 | 556 | |
669a5db4 JG |
557 | .irq_handler = ata_interrupt, |
558 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
559 | .irq_on = ata_irq_on, |
560 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
561 | |
562 | .port_start = ata_port_start, | |
669a5db4 JG |
563 | }; |
564 | ||
a3cabb27 UK |
565 | static const struct ata_port_operations sis_133_for_sata_ops = { |
566 | .port_disable = ata_port_disable, | |
567 | .set_piomode = sis_133_set_piomode, | |
568 | .set_dmamode = sis_133_set_dmamode, | |
569 | .mode_filter = ata_pci_default_filter, | |
570 | ||
571 | .tf_load = ata_tf_load, | |
572 | .tf_read = ata_tf_read, | |
573 | .check_status = ata_check_status, | |
574 | .exec_command = ata_exec_command, | |
575 | .dev_select = ata_std_dev_select, | |
576 | ||
577 | .freeze = ata_bmdma_freeze, | |
578 | .thaw = ata_bmdma_thaw, | |
579 | .error_handler = ata_bmdma_error_handler, | |
580 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
581 | .cable_detect = sis_133_cable_detect, | |
582 | ||
583 | .bmdma_setup = ata_bmdma_setup, | |
584 | .bmdma_start = ata_bmdma_start, | |
585 | .bmdma_stop = ata_bmdma_stop, | |
586 | .bmdma_status = ata_bmdma_status, | |
587 | .qc_prep = ata_qc_prep, | |
588 | .qc_issue = ata_qc_issue_prot, | |
589 | .data_xfer = ata_data_xfer, | |
590 | ||
591 | .irq_handler = ata_interrupt, | |
592 | .irq_clear = ata_bmdma_irq_clear, | |
593 | .irq_on = ata_irq_on, | |
594 | .irq_ack = ata_irq_ack, | |
595 | ||
596 | .port_start = ata_port_start, | |
597 | }; | |
598 | ||
669a5db4 JG |
599 | static const struct ata_port_operations sis_133_early_ops = { |
600 | .port_disable = ata_port_disable, | |
601 | .set_piomode = sis_100_set_piomode, | |
602 | .set_dmamode = sis_133_early_set_dmamode, | |
603 | .mode_filter = ata_pci_default_filter, | |
604 | ||
605 | .tf_load = ata_tf_load, | |
606 | .tf_read = ata_tf_read, | |
607 | .check_status = ata_check_status, | |
608 | .exec_command = ata_exec_command, | |
609 | .dev_select = ata_std_dev_select, | |
610 | ||
611 | .freeze = ata_bmdma_freeze, | |
612 | .thaw = ata_bmdma_thaw, | |
2e413f51 | 613 | .error_handler = sis_error_handler, |
669a5db4 | 614 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
2e413f51 | 615 | .cable_detect = sis_66_cable_detect, |
85cd7251 | 616 | |
669a5db4 JG |
617 | .bmdma_setup = ata_bmdma_setup, |
618 | .bmdma_start = ata_bmdma_start, | |
619 | .bmdma_stop = ata_bmdma_stop, | |
620 | .bmdma_status = ata_bmdma_status, | |
621 | .qc_prep = ata_qc_prep, | |
622 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 623 | .data_xfer = ata_data_xfer, |
669a5db4 | 624 | |
669a5db4 JG |
625 | .irq_handler = ata_interrupt, |
626 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
627 | .irq_on = ata_irq_on, |
628 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
629 | |
630 | .port_start = ata_port_start, | |
669a5db4 JG |
631 | }; |
632 | ||
633 | static const struct ata_port_operations sis_100_ops = { | |
634 | .port_disable = ata_port_disable, | |
635 | .set_piomode = sis_100_set_piomode, | |
636 | .set_dmamode = sis_100_set_dmamode, | |
637 | .mode_filter = ata_pci_default_filter, | |
638 | ||
639 | .tf_load = ata_tf_load, | |
640 | .tf_read = ata_tf_read, | |
641 | .check_status = ata_check_status, | |
642 | .exec_command = ata_exec_command, | |
643 | .dev_select = ata_std_dev_select, | |
644 | ||
645 | .freeze = ata_bmdma_freeze, | |
646 | .thaw = ata_bmdma_thaw, | |
2e413f51 | 647 | .error_handler = sis_error_handler, |
669a5db4 | 648 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
2e413f51 | 649 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
650 | |
651 | .bmdma_setup = ata_bmdma_setup, | |
652 | .bmdma_start = ata_bmdma_start, | |
653 | .bmdma_stop = ata_bmdma_stop, | |
654 | .bmdma_status = ata_bmdma_status, | |
655 | .qc_prep = ata_qc_prep, | |
656 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 657 | .data_xfer = ata_data_xfer, |
669a5db4 | 658 | |
669a5db4 JG |
659 | .irq_handler = ata_interrupt, |
660 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
661 | .irq_on = ata_irq_on, |
662 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
663 | |
664 | .port_start = ata_port_start, | |
669a5db4 JG |
665 | }; |
666 | ||
667 | static const struct ata_port_operations sis_66_ops = { | |
668 | .port_disable = ata_port_disable, | |
669 | .set_piomode = sis_old_set_piomode, | |
670 | .set_dmamode = sis_66_set_dmamode, | |
671 | .mode_filter = ata_pci_default_filter, | |
672 | ||
673 | .tf_load = ata_tf_load, | |
674 | .tf_read = ata_tf_read, | |
675 | .check_status = ata_check_status, | |
676 | .exec_command = ata_exec_command, | |
677 | .dev_select = ata_std_dev_select, | |
2e413f51 | 678 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
679 | |
680 | .freeze = ata_bmdma_freeze, | |
681 | .thaw = ata_bmdma_thaw, | |
2e413f51 | 682 | .error_handler = sis_error_handler, |
669a5db4 JG |
683 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
684 | ||
685 | .bmdma_setup = ata_bmdma_setup, | |
686 | .bmdma_start = ata_bmdma_start, | |
687 | .bmdma_stop = ata_bmdma_stop, | |
688 | .bmdma_status = ata_bmdma_status, | |
689 | .qc_prep = ata_qc_prep, | |
690 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 691 | .data_xfer = ata_data_xfer, |
669a5db4 | 692 | |
669a5db4 JG |
693 | .irq_handler = ata_interrupt, |
694 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
695 | .irq_on = ata_irq_on, |
696 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
697 | |
698 | .port_start = ata_port_start, | |
669a5db4 JG |
699 | }; |
700 | ||
701 | static const struct ata_port_operations sis_old_ops = { | |
702 | .port_disable = ata_port_disable, | |
703 | .set_piomode = sis_old_set_piomode, | |
704 | .set_dmamode = sis_old_set_dmamode, | |
705 | .mode_filter = ata_pci_default_filter, | |
706 | ||
707 | .tf_load = ata_tf_load, | |
708 | .tf_read = ata_tf_read, | |
709 | .check_status = ata_check_status, | |
710 | .exec_command = ata_exec_command, | |
711 | .dev_select = ata_std_dev_select, | |
712 | ||
713 | .freeze = ata_bmdma_freeze, | |
714 | .thaw = ata_bmdma_thaw, | |
2e413f51 | 715 | .error_handler = sis_error_handler, |
669a5db4 | 716 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
2e413f51 | 717 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
718 | |
719 | .bmdma_setup = ata_bmdma_setup, | |
720 | .bmdma_start = ata_bmdma_start, | |
721 | .bmdma_stop = ata_bmdma_stop, | |
722 | .bmdma_status = ata_bmdma_status, | |
723 | .qc_prep = ata_qc_prep, | |
724 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 725 | .data_xfer = ata_data_xfer, |
669a5db4 | 726 | |
669a5db4 JG |
727 | .irq_handler = ata_interrupt, |
728 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
729 | .irq_on = ata_irq_on, |
730 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
731 | |
732 | .port_start = ata_port_start, | |
669a5db4 JG |
733 | }; |
734 | ||
1626aeb8 | 735 | static const struct ata_port_info sis_info = { |
669a5db4 | 736 | .sht = &sis_sht, |
1d2808fd | 737 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
738 | .pio_mask = 0x1f, /* pio0-4 */ |
739 | .mwdma_mask = 0x07, | |
740 | .udma_mask = 0, | |
741 | .port_ops = &sis_old_ops, | |
742 | }; | |
1626aeb8 | 743 | static const struct ata_port_info sis_info33 = { |
669a5db4 | 744 | .sht = &sis_sht, |
1d2808fd | 745 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
746 | .pio_mask = 0x1f, /* pio0-4 */ |
747 | .mwdma_mask = 0x07, | |
748 | .udma_mask = ATA_UDMA2, /* UDMA 33 */ | |
749 | .port_ops = &sis_old_ops, | |
750 | }; | |
1626aeb8 | 751 | static const struct ata_port_info sis_info66 = { |
669a5db4 | 752 | .sht = &sis_sht, |
1d2808fd | 753 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
754 | .pio_mask = 0x1f, /* pio0-4 */ |
755 | .udma_mask = ATA_UDMA4, /* UDMA 66 */ | |
756 | .port_ops = &sis_66_ops, | |
757 | }; | |
1626aeb8 | 758 | static const struct ata_port_info sis_info100 = { |
669a5db4 | 759 | .sht = &sis_sht, |
1d2808fd | 760 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
761 | .pio_mask = 0x1f, /* pio0-4 */ |
762 | .udma_mask = ATA_UDMA5, | |
763 | .port_ops = &sis_100_ops, | |
764 | }; | |
1626aeb8 | 765 | static const struct ata_port_info sis_info100_early = { |
669a5db4 | 766 | .sht = &sis_sht, |
1d2808fd | 767 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
768 | .udma_mask = ATA_UDMA5, |
769 | .pio_mask = 0x1f, /* pio0-4 */ | |
770 | .port_ops = &sis_66_ops, | |
771 | }; | |
a3cabb27 | 772 | static const struct ata_port_info sis_info133 = { |
669a5db4 | 773 | .sht = &sis_sht, |
1d2808fd | 774 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
775 | .pio_mask = 0x1f, /* pio0-4 */ |
776 | .udma_mask = ATA_UDMA6, | |
777 | .port_ops = &sis_133_ops, | |
778 | }; | |
a3cabb27 UK |
779 | const struct ata_port_info sis_info133_for_sata = { |
780 | .sht = &sis_sht, | |
781 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
782 | .pio_mask = 0x1f, /* pio0-4 */ | |
783 | .udma_mask = ATA_UDMA6, | |
784 | .port_ops = &sis_133_for_sata_ops, | |
785 | }; | |
1626aeb8 | 786 | static const struct ata_port_info sis_info133_early = { |
669a5db4 | 787 | .sht = &sis_sht, |
1d2808fd | 788 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
789 | .pio_mask = 0x1f, /* pio0-4 */ |
790 | .udma_mask = ATA_UDMA6, | |
791 | .port_ops = &sis_133_early_ops, | |
792 | }; | |
793 | ||
9b14dec5 | 794 | /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ |
a3cabb27 | 795 | EXPORT_SYMBOL_GPL(sis_info133_for_sata); |
669a5db4 JG |
796 | |
797 | static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) | |
798 | { | |
799 | u16 regw; | |
800 | u8 reg; | |
801 | ||
802 | if (sis->info == &sis_info133) { | |
803 | pci_read_config_word(pdev, 0x50, ®w); | |
804 | if (regw & 0x08) | |
805 | pci_write_config_word(pdev, 0x50, regw & ~0x08); | |
806 | pci_read_config_word(pdev, 0x52, ®w); | |
807 | if (regw & 0x08) | |
808 | pci_write_config_word(pdev, 0x52, regw & ~0x08); | |
809 | return; | |
810 | } | |
811 | ||
812 | if (sis->info == &sis_info133_early || sis->info == &sis_info100) { | |
813 | /* Fix up latency */ | |
814 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
815 | /* Set compatibility bit */ | |
816 | pci_read_config_byte(pdev, 0x49, ®); | |
817 | if (!(reg & 0x01)) | |
818 | pci_write_config_byte(pdev, 0x49, reg | 0x01); | |
819 | return; | |
820 | } | |
821 | ||
822 | if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { | |
823 | /* Fix up latency */ | |
824 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
825 | /* Set compatibility bit */ | |
826 | pci_read_config_byte(pdev, 0x52, ®); | |
827 | if (!(reg & 0x04)) | |
828 | pci_write_config_byte(pdev, 0x52, reg | 0x04); | |
829 | return; | |
830 | } | |
831 | ||
832 | if (sis->info == &sis_info33) { | |
833 | pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); | |
834 | if (( reg & 0x0F ) != 0x00) | |
835 | pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); | |
836 | /* Fall through to ATA16 fixup below */ | |
837 | } | |
838 | ||
839 | if (sis->info == &sis_info || sis->info == &sis_info33) { | |
840 | /* force per drive recovery and active timings | |
841 | needed on ATA_33 and below chips */ | |
842 | pci_read_config_byte(pdev, 0x52, ®); | |
843 | if (!(reg & 0x08)) | |
844 | pci_write_config_byte(pdev, 0x52, reg|0x08); | |
845 | return; | |
846 | } | |
847 | ||
848 | BUG(); | |
849 | } | |
850 | ||
851 | /** | |
852 | * sis_init_one - Register SiS ATA PCI device with kernel services | |
853 | * @pdev: PCI device to register | |
854 | * @ent: Entry in sis_pci_tbl matching with @pdev | |
855 | * | |
856 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
857 | * and then hand over control to libata, for it to do the rest. | |
858 | * | |
859 | * LOCKING: | |
860 | * Inherited from PCI layer (may sleep). | |
861 | * | |
862 | * RETURNS: | |
863 | * Zero on success, or -ERRNO value. | |
864 | */ | |
865 | ||
866 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
867 | { | |
868 | static int printed_version; | |
1626aeb8 TH |
869 | struct ata_port_info port; |
870 | const struct ata_port_info *ppi[] = { &port, NULL }; | |
669a5db4 JG |
871 | struct pci_dev *host = NULL; |
872 | struct sis_chipset *chipset = NULL; | |
f3769e9d | 873 | struct sis_chipset *sets; |
669a5db4 JG |
874 | |
875 | static struct sis_chipset sis_chipsets[] = { | |
f20b16ff | 876 | |
af323a2f AC |
877 | { 0x0968, &sis_info133 }, |
878 | { 0x0966, &sis_info133 }, | |
879 | { 0x0965, &sis_info133 }, | |
669a5db4 JG |
880 | { 0x0745, &sis_info100 }, |
881 | { 0x0735, &sis_info100 }, | |
882 | { 0x0733, &sis_info100 }, | |
883 | { 0x0635, &sis_info100 }, | |
884 | { 0x0633, &sis_info100 }, | |
885 | ||
886 | { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
887 | { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
888 | ||
889 | { 0x0640, &sis_info66 }, | |
890 | { 0x0630, &sis_info66 }, | |
891 | { 0x0620, &sis_info66 }, | |
892 | { 0x0540, &sis_info66 }, | |
893 | { 0x0530, &sis_info66 }, | |
894 | ||
895 | { 0x5600, &sis_info33 }, | |
896 | { 0x5598, &sis_info33 }, | |
897 | { 0x5597, &sis_info33 }, | |
898 | { 0x5591, &sis_info33 }, | |
899 | { 0x5582, &sis_info33 }, | |
900 | { 0x5581, &sis_info33 }, | |
901 | ||
902 | { 0x5596, &sis_info }, | |
903 | { 0x5571, &sis_info }, | |
904 | { 0x5517, &sis_info }, | |
905 | { 0x5511, &sis_info }, | |
906 | ||
907 | {0} | |
908 | }; | |
909 | static struct sis_chipset sis133_early = { | |
910 | 0x0, &sis_info133_early | |
911 | }; | |
912 | static struct sis_chipset sis133 = { | |
913 | 0x0, &sis_info133 | |
914 | }; | |
915 | static struct sis_chipset sis100_early = { | |
916 | 0x0, &sis_info100_early | |
917 | }; | |
918 | static struct sis_chipset sis100 = { | |
919 | 0x0, &sis_info100 | |
920 | }; | |
921 | ||
922 | if (!printed_version++) | |
923 | dev_printk(KERN_DEBUG, &pdev->dev, | |
924 | "version " DRV_VERSION "\n"); | |
925 | ||
926 | /* We have to find the bridge first */ | |
927 | ||
f3769e9d AC |
928 | for (sets = &sis_chipsets[0]; sets->device; sets++) { |
929 | host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); | |
669a5db4 | 930 | if (host != NULL) { |
f3769e9d AC |
931 | chipset = sets; /* Match found */ |
932 | if (sets->device == 0x630) { /* SIS630 */ | |
44c10138 | 933 | if (host->revision >= 0x30) /* 630 ET */ |
669a5db4 JG |
934 | chipset = &sis100_early; |
935 | } | |
936 | break; | |
937 | } | |
938 | } | |
939 | ||
940 | /* Look for concealed bridges */ | |
f3769e9d | 941 | if (chipset == NULL) { |
669a5db4 JG |
942 | /* Second check */ |
943 | u32 idemisc; | |
944 | u16 trueid; | |
945 | ||
946 | /* Disable ID masking and register remapping then | |
947 | see what the real ID is */ | |
948 | ||
949 | pci_read_config_dword(pdev, 0x54, &idemisc); | |
950 | pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); | |
951 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
952 | pci_write_config_dword(pdev, 0x54, idemisc); | |
953 | ||
954 | switch(trueid) { | |
955 | case 0x5518: /* SIS 962/963 */ | |
956 | chipset = &sis133; | |
957 | if ((idemisc & 0x40000000) == 0) { | |
958 | pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); | |
959 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
960 | } | |
961 | break; | |
962 | case 0x0180: /* SIS 965/965L */ | |
963 | chipset = &sis133; | |
964 | break; | |
965 | case 0x1180: /* SIS 966/966L */ | |
966 | chipset = &sis133; | |
967 | break; | |
968 | } | |
969 | } | |
970 | ||
971 | /* Further check */ | |
972 | if (chipset == NULL) { | |
973 | struct pci_dev *lpc_bridge; | |
974 | u16 trueid; | |
975 | u8 prefctl; | |
976 | u8 idecfg; | |
669a5db4 JG |
977 | |
978 | /* Try the second unmasking technique */ | |
979 | pci_read_config_byte(pdev, 0x4a, &idecfg); | |
980 | pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); | |
981 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
982 | pci_write_config_byte(pdev, 0x4a, idecfg); | |
983 | ||
984 | switch(trueid) { | |
985 | case 0x5517: | |
986 | lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ | |
987 | if (lpc_bridge == NULL) | |
988 | break; | |
669a5db4 JG |
989 | pci_read_config_byte(pdev, 0x49, &prefctl); |
990 | pci_dev_put(lpc_bridge); | |
991 | ||
44c10138 | 992 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
669a5db4 JG |
993 | chipset = &sis133_early; |
994 | break; | |
995 | } | |
996 | chipset = &sis100; | |
997 | break; | |
998 | } | |
999 | } | |
1000 | pci_dev_put(host); | |
1001 | ||
1002 | /* No chipset info, no support */ | |
1003 | if (chipset == NULL) | |
1004 | return -ENODEV; | |
1005 | ||
1626aeb8 TH |
1006 | port = *chipset->info; |
1007 | port.private_data = chipset; | |
669a5db4 JG |
1008 | |
1009 | sis_fixup(pdev, chipset); | |
1010 | ||
1626aeb8 | 1011 | return ata_pci_init_one(pdev, ppi); |
669a5db4 JG |
1012 | } |
1013 | ||
1014 | static const struct pci_device_id sis_pci_tbl[] = { | |
2d2744fc JG |
1015 | { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ |
1016 | { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ | |
a3cabb27 | 1017 | { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ |
2d2744fc | 1018 | |
669a5db4 JG |
1019 | { } |
1020 | }; | |
1021 | ||
1022 | static struct pci_driver sis_pci_driver = { | |
1023 | .name = DRV_NAME, | |
1024 | .id_table = sis_pci_tbl, | |
1025 | .probe = sis_init_one, | |
1026 | .remove = ata_pci_remove_one, | |
438ac6d5 | 1027 | #ifdef CONFIG_PM |
62d64ae0 A |
1028 | .suspend = ata_pci_device_suspend, |
1029 | .resume = ata_pci_device_resume, | |
438ac6d5 | 1030 | #endif |
669a5db4 JG |
1031 | }; |
1032 | ||
1033 | static int __init sis_init(void) | |
1034 | { | |
1035 | return pci_register_driver(&sis_pci_driver); | |
1036 | } | |
1037 | ||
1038 | static void __exit sis_exit(void) | |
1039 | { | |
1040 | pci_unregister_driver(&sis_pci_driver); | |
1041 | } | |
1042 | ||
669a5db4 JG |
1043 | module_init(sis_init); |
1044 | module_exit(sis_exit); | |
1045 | ||
1046 | MODULE_AUTHOR("Alan Cox"); | |
1047 | MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); | |
1048 | MODULE_LICENSE("GPL"); | |
1049 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
1050 | MODULE_VERSION(DRV_VERSION); | |
1051 |