Commit | Line | Data |
---|---|---|
669a5db4 JG |
1 | /* |
2 | * pata_sis.c - SiS ATA driver | |
3 | * | |
4 | * (C) 2005 Red Hat <alan@redhat.com> | |
4761c06c | 5 | * (C) 2007 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
6 | * |
7 | * Based upon linux/drivers/ide/pci/sis5513.c | |
8 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
9 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
10 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
11 | * SiS Taiwan : for direct support and hardware. | |
12 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
13 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
14 | * for checking code correctness, providing patches. | |
15 | * Original tests and design on the SiS620 chipset. | |
16 | * ATA100 tests and design on the SiS735 chipset. | |
17 | * ATA16/33 support from specs | |
18 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
19 | * | |
20 | * | |
21 | * TODO | |
22 | * Check MWDMA on drives that don't support MWDMA speed pio cycles ? | |
23 | * More Testing | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/blkdev.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/device.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <linux/libata.h> | |
35 | #include <linux/ata.h> | |
4bb64fb9 | 36 | #include "sis.h" |
669a5db4 JG |
37 | |
38 | #define DRV_NAME "pata_sis" | |
4761c06c | 39 | #define DRV_VERSION "0.5.2" |
669a5db4 JG |
40 | |
41 | struct sis_chipset { | |
1626aeb8 TH |
42 | u16 device; /* PCI host ID */ |
43 | const struct ata_port_info *info; /* Info block */ | |
669a5db4 JG |
44 | /* Probably add family, cable detect type etc here to clean |
45 | up code later */ | |
46 | }; | |
47 | ||
7dcbc1f2 JJ |
48 | struct sis_laptop { |
49 | u16 device; | |
50 | u16 subvendor; | |
51 | u16 subdevice; | |
52 | }; | |
53 | ||
54 | static const struct sis_laptop sis_laptop[] = { | |
55 | /* devid, subvendor, subdev */ | |
56 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ | |
4f2d47cf | 57 | { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ |
1f71d067 | 58 | { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ |
7dcbc1f2 JJ |
59 | /* end marker */ |
60 | { 0, } | |
61 | }; | |
62 | ||
63 | static int sis_short_ata40(struct pci_dev *dev) | |
64 | { | |
65 | const struct sis_laptop *lap = &sis_laptop[0]; | |
66 | ||
67 | while (lap->device) { | |
68 | if (lap->device == dev->device && | |
69 | lap->subvendor == dev->subsystem_vendor && | |
70 | lap->subdevice == dev->subsystem_device) | |
71 | return 1; | |
72 | lap++; | |
73 | } | |
74 | ||
75 | return 0; | |
76 | } | |
77 | ||
669a5db4 | 78 | /** |
dd668d15 | 79 | * sis_old_port_base - return PCI configuration base for dev |
669a5db4 JG |
80 | * @adev: device |
81 | * | |
82 | * Returns the base of the PCI configuration registers for this port | |
83 | * number. | |
84 | */ | |
85 | ||
dd668d15 | 86 | static int sis_old_port_base(struct ata_device *adev) |
669a5db4 | 87 | { |
9af5c9c9 | 88 | return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); |
669a5db4 JG |
89 | } |
90 | ||
91 | /** | |
2e413f51 | 92 | * sis_133_cable_detect - check for 40/80 pin |
669a5db4 | 93 | * @ap: Port |
d4b2bab4 | 94 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
95 | * |
96 | * Perform cable detection for the later UDMA133 capable | |
97 | * SiS chipset. | |
98 | */ | |
99 | ||
2e413f51 | 100 | static int sis_133_cable_detect(struct ata_port *ap) |
669a5db4 | 101 | { |
669a5db4 JG |
102 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
103 | u16 tmp; | |
104 | ||
669a5db4 JG |
105 | /* The top bit of this register is the cable detect bit */ |
106 | pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); | |
7dcbc1f2 | 107 | if ((tmp & 0x8000) && !sis_short_ata40(pdev)) |
2e413f51 AC |
108 | return ATA_CBL_PATA40; |
109 | return ATA_CBL_PATA80; | |
669a5db4 JG |
110 | } |
111 | ||
112 | /** | |
2e413f51 | 113 | * sis_66_cable_detect - check for 40/80 pin |
669a5db4 | 114 | * @ap: Port |
d4b2bab4 | 115 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
116 | * |
117 | * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 | |
118 | * SiS IDE controllers. | |
119 | */ | |
120 | ||
2e413f51 | 121 | static int sis_66_cable_detect(struct ata_port *ap) |
669a5db4 | 122 | { |
669a5db4 JG |
123 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
124 | u8 tmp; | |
125 | ||
669a5db4 JG |
126 | /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ |
127 | pci_read_config_byte(pdev, 0x48, &tmp); | |
128 | tmp >>= ap->port_no; | |
7dcbc1f2 | 129 | if ((tmp & 0x10) && !sis_short_ata40(pdev)) |
2e413f51 AC |
130 | return ATA_CBL_PATA40; |
131 | return ATA_CBL_PATA80; | |
669a5db4 JG |
132 | } |
133 | ||
669a5db4 JG |
134 | |
135 | /** | |
2e413f51 | 136 | * sis_pre_reset - probe begin |
cc0680a5 | 137 | * @link: ATA link |
d4b2bab4 | 138 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
139 | * |
140 | * Set up cable type and use generic probe init | |
141 | */ | |
142 | ||
cc0680a5 | 143 | static int sis_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 JG |
144 | { |
145 | static const struct pci_bits sis_enable_bits[] = { | |
146 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
147 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
148 | }; | |
85cd7251 | 149 | |
cc0680a5 | 150 | struct ata_port *ap = link->ap; |
669a5db4 JG |
151 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
152 | ||
2e413f51 AC |
153 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) |
154 | return -ENOENT; | |
d4b2bab4 | 155 | |
15ce0943 AC |
156 | /* Clear the FIFO settings. We can't enable the FIFO until |
157 | we know we are poking at a disk */ | |
158 | pci_write_config_byte(pdev, 0x4B, 0); | |
9363c382 | 159 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
160 | } |
161 | ||
162 | ||
669a5db4 JG |
163 | /** |
164 | * sis_set_fifo - Set RWP fifo bits for this device | |
165 | * @ap: Port | |
166 | * @adev: Device | |
167 | * | |
168 | * SIS chipsets implement prefetch/postwrite bits for each device | |
169 | * on both channels. This functionality is not ATAPI compatible and | |
170 | * must be configured according to the class of device present | |
171 | */ | |
172 | ||
173 | static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) | |
174 | { | |
175 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
176 | u8 fifoctrl; | |
177 | u8 mask = 0x11; | |
178 | ||
179 | mask <<= (2 * ap->port_no); | |
180 | mask <<= adev->devno; | |
181 | ||
182 | /* This holds various bits including the FIFO control */ | |
183 | pci_read_config_byte(pdev, 0x4B, &fifoctrl); | |
184 | fifoctrl &= ~mask; | |
185 | ||
186 | /* Enable for ATA (disk) only */ | |
187 | if (adev->class == ATA_DEV_ATA) | |
188 | fifoctrl |= mask; | |
189 | pci_write_config_byte(pdev, 0x4B, fifoctrl); | |
190 | } | |
191 | ||
192 | /** | |
193 | * sis_old_set_piomode - Initialize host controller PATA PIO timings | |
194 | * @ap: Port whose timings we are configuring | |
195 | * @adev: Device we are configuring for. | |
196 | * | |
197 | * Set PIO mode for device, in host controller PCI config space. This | |
198 | * function handles PIO set up for all chips that are pre ATA100 and | |
199 | * also early ATA100 devices. | |
200 | * | |
201 | * LOCKING: | |
202 | * None (inherited from caller). | |
203 | */ | |
204 | ||
205 | static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
206 | { | |
207 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 208 | int port = sis_old_port_base(adev); |
669a5db4 JG |
209 | u8 t1, t2; |
210 | int speed = adev->pio_mode - XFER_PIO_0; | |
211 | ||
212 | const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; | |
213 | const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; | |
214 | ||
215 | sis_set_fifo(ap, adev); | |
216 | ||
217 | pci_read_config_byte(pdev, port, &t1); | |
218 | pci_read_config_byte(pdev, port + 1, &t2); | |
219 | ||
220 | t1 &= ~0x0F; /* Clear active/recovery timings */ | |
221 | t2 &= ~0x07; | |
222 | ||
223 | t1 |= active[speed]; | |
224 | t2 |= recovery[speed]; | |
225 | ||
226 | pci_write_config_byte(pdev, port, t1); | |
227 | pci_write_config_byte(pdev, port + 1, t2); | |
228 | } | |
229 | ||
230 | /** | |
4761c06c | 231 | * sis_100_set_piomode - Initialize host controller PATA PIO timings |
669a5db4 JG |
232 | * @ap: Port whose timings we are configuring |
233 | * @adev: Device we are configuring for. | |
234 | * | |
235 | * Set PIO mode for device, in host controller PCI config space. This | |
236 | * function handles PIO set up for ATA100 devices and early ATA133. | |
237 | * | |
238 | * LOCKING: | |
239 | * None (inherited from caller). | |
240 | */ | |
241 | ||
242 | static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
243 | { | |
244 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 245 | int port = sis_old_port_base(adev); |
669a5db4 JG |
246 | int speed = adev->pio_mode - XFER_PIO_0; |
247 | ||
248 | const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; | |
249 | ||
250 | sis_set_fifo(ap, adev); | |
251 | ||
252 | pci_write_config_byte(pdev, port, actrec[speed]); | |
253 | } | |
254 | ||
255 | /** | |
4761c06c | 256 | * sis_133_set_piomode - Initialize host controller PATA PIO timings |
669a5db4 JG |
257 | * @ap: Port whose timings we are configuring |
258 | * @adev: Device we are configuring for. | |
259 | * | |
260 | * Set PIO mode for device, in host controller PCI config space. This | |
261 | * function handles PIO set up for the later ATA133 devices. | |
262 | * | |
263 | * LOCKING: | |
264 | * None (inherited from caller). | |
265 | */ | |
266 | ||
267 | static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
268 | { | |
269 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
270 | int port = 0x40; | |
271 | u32 t1; | |
272 | u32 reg54; | |
273 | int speed = adev->pio_mode - XFER_PIO_0; | |
274 | ||
275 | const u32 timing133[] = { | |
276 | 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
277 | 0x0C266000, | |
278 | 0x04263000, | |
279 | 0x0C0A3000, | |
280 | 0x05093000 | |
281 | }; | |
282 | const u32 timing100[] = { | |
283 | 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
284 | 0x091C4000, | |
285 | 0x031C2000, | |
286 | 0x09072000, | |
287 | 0x04062000 | |
288 | }; | |
289 | ||
290 | sis_set_fifo(ap, adev); | |
291 | ||
292 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
293 | pci_read_config_dword(pdev, 0x54, ®54); | |
294 | if (reg54 & 0x40000000) | |
295 | port = 0x70; | |
296 | port += 8 * ap->port_no + 4 * adev->devno; | |
297 | ||
298 | pci_read_config_dword(pdev, port, &t1); | |
299 | t1 &= 0xC0C00FFF; /* Mask out timing */ | |
300 | ||
301 | if (t1 & 0x08) /* 100 or 133 ? */ | |
302 | t1 |= timing133[speed]; | |
303 | else | |
304 | t1 |= timing100[speed]; | |
305 | pci_write_config_byte(pdev, port, t1); | |
306 | } | |
307 | ||
308 | /** | |
309 | * sis_old_set_dmamode - Initialize host controller PATA DMA timings | |
310 | * @ap: Port whose timings we are configuring | |
311 | * @adev: Device to program | |
312 | * | |
313 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
314 | * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike | |
315 | * the old ide/pci driver. | |
316 | * | |
317 | * LOCKING: | |
318 | * None (inherited from caller). | |
319 | */ | |
320 | ||
321 | static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
322 | { | |
323 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
324 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 325 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
326 | u16 timing; |
327 | ||
4761c06c | 328 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
669a5db4 JG |
329 | const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; |
330 | ||
331 | pci_read_config_word(pdev, drive_pci, &timing); | |
332 | ||
333 | if (adev->dma_mode < XFER_UDMA_0) { | |
334 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
1967b7ff | 335 | the higher bits are dependant on the device */ |
4761c06c | 336 | timing &= ~0x870F; |
669a5db4 | 337 | timing |= mwdma_bits[speed]; |
669a5db4 JG |
338 | } else { |
339 | /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ | |
340 | speed = adev->dma_mode - XFER_UDMA_0; | |
341 | timing &= ~0x6000; | |
342 | timing |= udma_bits[speed]; | |
343 | } | |
4761c06c | 344 | pci_write_config_word(pdev, drive_pci, timing); |
669a5db4 JG |
345 | } |
346 | ||
347 | /** | |
348 | * sis_66_set_dmamode - Initialize host controller PATA DMA timings | |
349 | * @ap: Port whose timings we are configuring | |
350 | * @adev: Device to program | |
351 | * | |
352 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
353 | * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike | |
354 | * the old ide/pci driver. | |
355 | * | |
356 | * LOCKING: | |
357 | * None (inherited from caller). | |
358 | */ | |
359 | ||
360 | static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
361 | { | |
362 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
363 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 364 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
365 | u16 timing; |
366 | ||
edeb614c | 367 | /* MWDMA 0-2 and UDMA 0-5 */ |
4761c06c | 368 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
edeb614c | 369 | const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; |
669a5db4 JG |
370 | |
371 | pci_read_config_word(pdev, drive_pci, &timing); | |
372 | ||
373 | if (adev->dma_mode < XFER_UDMA_0) { | |
374 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
1967b7ff | 375 | the higher bits are dependant on the device, bit 15 udma */ |
dd668d15 | 376 | timing &= ~0x870F; |
669a5db4 JG |
377 | timing |= mwdma_bits[speed]; |
378 | } else { | |
379 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ | |
380 | speed = adev->dma_mode - XFER_UDMA_0; | |
dd668d15 | 381 | timing &= ~0xF000; |
669a5db4 JG |
382 | timing |= udma_bits[speed]; |
383 | } | |
384 | pci_write_config_word(pdev, drive_pci, timing); | |
385 | } | |
386 | ||
387 | /** | |
388 | * sis_100_set_dmamode - Initialize host controller PATA DMA timings | |
389 | * @ap: Port whose timings we are configuring | |
390 | * @adev: Device to program | |
391 | * | |
392 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
393 | * Handles UDMA66 and early UDMA100 devices. | |
394 | * | |
395 | * LOCKING: | |
396 | * None (inherited from caller). | |
397 | */ | |
398 | ||
399 | static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
400 | { | |
401 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
402 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 AC |
403 | int drive_pci = sis_old_port_base(adev); |
404 | u8 timing; | |
669a5db4 | 405 | |
dd668d15 | 406 | const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; |
669a5db4 | 407 | |
dd668d15 | 408 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
669a5db4 JG |
409 | |
410 | if (adev->dma_mode < XFER_UDMA_0) { | |
411 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
412 | } else { | |
dd668d15 | 413 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 414 | speed = adev->dma_mode - XFER_UDMA_0; |
dd668d15 | 415 | timing &= ~0x8F; |
669a5db4 JG |
416 | timing |= udma_bits[speed]; |
417 | } | |
dd668d15 | 418 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
669a5db4 JG |
419 | } |
420 | ||
421 | /** | |
422 | * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings | |
423 | * @ap: Port whose timings we are configuring | |
424 | * @adev: Device to program | |
425 | * | |
426 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
4761c06c | 427 | * Handles early SiS 961 bridges. |
669a5db4 JG |
428 | * |
429 | * LOCKING: | |
430 | * None (inherited from caller). | |
431 | */ | |
432 | ||
433 | static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
434 | { | |
435 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
436 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 AC |
437 | int drive_pci = sis_old_port_base(adev); |
438 | u8 timing; | |
439 | /* Low 4 bits are timing */ | |
440 | static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; | |
669a5db4 | 441 | |
dd668d15 | 442 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
669a5db4 JG |
443 | |
444 | if (adev->dma_mode < XFER_UDMA_0) { | |
445 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
446 | } else { | |
dd668d15 | 447 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 448 | speed = adev->dma_mode - XFER_UDMA_0; |
dd668d15 | 449 | timing &= ~0x8F; |
669a5db4 JG |
450 | timing |= udma_bits[speed]; |
451 | } | |
dd668d15 | 452 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
669a5db4 JG |
453 | } |
454 | ||
455 | /** | |
456 | * sis_133_set_dmamode - Initialize host controller PATA DMA timings | |
457 | * @ap: Port whose timings we are configuring | |
458 | * @adev: Device to program | |
459 | * | |
460 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
669a5db4 JG |
461 | * |
462 | * LOCKING: | |
463 | * None (inherited from caller). | |
464 | */ | |
465 | ||
466 | static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
467 | { | |
468 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
469 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
470 | int port = 0x40; | |
471 | u32 t1; | |
472 | u32 reg54; | |
473 | ||
474 | /* bits 4- cycle time 8 - cvs time */ | |
2e413f51 AC |
475 | static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; |
476 | static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; | |
669a5db4 JG |
477 | |
478 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
479 | pci_read_config_dword(pdev, 0x54, ®54); | |
480 | if (reg54 & 0x40000000) | |
481 | port = 0x70; | |
482 | port += (8 * ap->port_no) + (4 * adev->devno); | |
483 | ||
484 | pci_read_config_dword(pdev, port, &t1); | |
485 | ||
486 | if (adev->dma_mode < XFER_UDMA_0) { | |
487 | t1 &= ~0x00000004; | |
488 | /* FIXME: need data sheet to add MWDMA here. Also lacking on | |
489 | ide/pci driver */ | |
490 | } else { | |
491 | speed = adev->dma_mode - XFER_UDMA_0; | |
492 | /* if & 8 no UDMA133 - need info for ... */ | |
493 | t1 &= ~0x00000FF0; | |
494 | t1 |= 0x00000004; | |
495 | if (t1 & 0x08) | |
496 | t1 |= timing_u133[speed]; | |
497 | else | |
498 | t1 |= timing_u100[speed]; | |
499 | } | |
500 | pci_write_config_dword(pdev, port, t1); | |
501 | } | |
502 | ||
503 | static struct scsi_host_template sis_sht = { | |
68d1d07b | 504 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
505 | }; |
506 | ||
029cfd6b TH |
507 | static struct ata_port_operations sis_133_for_sata_ops = { |
508 | .inherits = &ata_bmdma_port_ops, | |
669a5db4 JG |
509 | .set_piomode = sis_133_set_piomode, |
510 | .set_dmamode = sis_133_set_dmamode, | |
2e413f51 | 511 | .cable_detect = sis_133_cable_detect, |
029cfd6b | 512 | }; |
669a5db4 | 513 | |
029cfd6b TH |
514 | static struct ata_port_operations sis_base_ops = { |
515 | .inherits = &ata_bmdma_port_ops, | |
a1efdaba | 516 | .prereset = sis_pre_reset, |
669a5db4 JG |
517 | }; |
518 | ||
029cfd6b TH |
519 | static struct ata_port_operations sis_133_ops = { |
520 | .inherits = &sis_base_ops, | |
a3cabb27 UK |
521 | .set_piomode = sis_133_set_piomode, |
522 | .set_dmamode = sis_133_set_dmamode, | |
a3cabb27 | 523 | .cable_detect = sis_133_cable_detect, |
a3cabb27 UK |
524 | }; |
525 | ||
029cfd6b TH |
526 | static struct ata_port_operations sis_133_early_ops = { |
527 | .inherits = &sis_base_ops, | |
669a5db4 JG |
528 | .set_piomode = sis_100_set_piomode, |
529 | .set_dmamode = sis_133_early_set_dmamode, | |
2e413f51 | 530 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
531 | }; |
532 | ||
029cfd6b TH |
533 | static struct ata_port_operations sis_100_ops = { |
534 | .inherits = &sis_base_ops, | |
669a5db4 JG |
535 | .set_piomode = sis_100_set_piomode, |
536 | .set_dmamode = sis_100_set_dmamode, | |
2e413f51 | 537 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
538 | }; |
539 | ||
029cfd6b TH |
540 | static struct ata_port_operations sis_66_ops = { |
541 | .inherits = &sis_base_ops, | |
669a5db4 JG |
542 | .set_piomode = sis_old_set_piomode, |
543 | .set_dmamode = sis_66_set_dmamode, | |
2e413f51 | 544 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
545 | }; |
546 | ||
029cfd6b TH |
547 | static struct ata_port_operations sis_old_ops = { |
548 | .inherits = &sis_base_ops, | |
669a5db4 JG |
549 | .set_piomode = sis_old_set_piomode, |
550 | .set_dmamode = sis_old_set_dmamode, | |
2e413f51 | 551 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
552 | }; |
553 | ||
1626aeb8 | 554 | static const struct ata_port_info sis_info = { |
1d2808fd | 555 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
556 | .pio_mask = 0x1f, /* pio0-4 */ |
557 | .mwdma_mask = 0x07, | |
558 | .udma_mask = 0, | |
559 | .port_ops = &sis_old_ops, | |
560 | }; | |
1626aeb8 | 561 | static const struct ata_port_info sis_info33 = { |
1d2808fd | 562 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
563 | .pio_mask = 0x1f, /* pio0-4 */ |
564 | .mwdma_mask = 0x07, | |
565 | .udma_mask = ATA_UDMA2, /* UDMA 33 */ | |
566 | .port_ops = &sis_old_ops, | |
567 | }; | |
1626aeb8 | 568 | static const struct ata_port_info sis_info66 = { |
1d2808fd | 569 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
570 | .pio_mask = 0x1f, /* pio0-4 */ |
571 | .udma_mask = ATA_UDMA4, /* UDMA 66 */ | |
572 | .port_ops = &sis_66_ops, | |
573 | }; | |
1626aeb8 | 574 | static const struct ata_port_info sis_info100 = { |
1d2808fd | 575 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
576 | .pio_mask = 0x1f, /* pio0-4 */ |
577 | .udma_mask = ATA_UDMA5, | |
578 | .port_ops = &sis_100_ops, | |
579 | }; | |
1626aeb8 | 580 | static const struct ata_port_info sis_info100_early = { |
1d2808fd | 581 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
582 | .udma_mask = ATA_UDMA5, |
583 | .pio_mask = 0x1f, /* pio0-4 */ | |
584 | .port_ops = &sis_66_ops, | |
585 | }; | |
a3cabb27 | 586 | static const struct ata_port_info sis_info133 = { |
1d2808fd | 587 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
588 | .pio_mask = 0x1f, /* pio0-4 */ |
589 | .udma_mask = ATA_UDMA6, | |
590 | .port_ops = &sis_133_ops, | |
591 | }; | |
a3cabb27 | 592 | const struct ata_port_info sis_info133_for_sata = { |
a3cabb27 UK |
593 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
594 | .pio_mask = 0x1f, /* pio0-4 */ | |
595 | .udma_mask = ATA_UDMA6, | |
596 | .port_ops = &sis_133_for_sata_ops, | |
597 | }; | |
1626aeb8 | 598 | static const struct ata_port_info sis_info133_early = { |
1d2808fd | 599 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
600 | .pio_mask = 0x1f, /* pio0-4 */ |
601 | .udma_mask = ATA_UDMA6, | |
602 | .port_ops = &sis_133_early_ops, | |
603 | }; | |
604 | ||
9b14dec5 | 605 | /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ |
a3cabb27 | 606 | EXPORT_SYMBOL_GPL(sis_info133_for_sata); |
669a5db4 JG |
607 | |
608 | static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) | |
609 | { | |
610 | u16 regw; | |
611 | u8 reg; | |
612 | ||
613 | if (sis->info == &sis_info133) { | |
614 | pci_read_config_word(pdev, 0x50, ®w); | |
615 | if (regw & 0x08) | |
616 | pci_write_config_word(pdev, 0x50, regw & ~0x08); | |
617 | pci_read_config_word(pdev, 0x52, ®w); | |
618 | if (regw & 0x08) | |
619 | pci_write_config_word(pdev, 0x52, regw & ~0x08); | |
620 | return; | |
621 | } | |
622 | ||
623 | if (sis->info == &sis_info133_early || sis->info == &sis_info100) { | |
624 | /* Fix up latency */ | |
625 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
626 | /* Set compatibility bit */ | |
627 | pci_read_config_byte(pdev, 0x49, ®); | |
628 | if (!(reg & 0x01)) | |
629 | pci_write_config_byte(pdev, 0x49, reg | 0x01); | |
630 | return; | |
631 | } | |
632 | ||
633 | if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { | |
634 | /* Fix up latency */ | |
635 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
636 | /* Set compatibility bit */ | |
637 | pci_read_config_byte(pdev, 0x52, ®); | |
638 | if (!(reg & 0x04)) | |
639 | pci_write_config_byte(pdev, 0x52, reg | 0x04); | |
640 | return; | |
641 | } | |
642 | ||
643 | if (sis->info == &sis_info33) { | |
644 | pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); | |
645 | if (( reg & 0x0F ) != 0x00) | |
646 | pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); | |
647 | /* Fall through to ATA16 fixup below */ | |
648 | } | |
649 | ||
650 | if (sis->info == &sis_info || sis->info == &sis_info33) { | |
651 | /* force per drive recovery and active timings | |
652 | needed on ATA_33 and below chips */ | |
653 | pci_read_config_byte(pdev, 0x52, ®); | |
654 | if (!(reg & 0x08)) | |
655 | pci_write_config_byte(pdev, 0x52, reg|0x08); | |
656 | return; | |
657 | } | |
658 | ||
659 | BUG(); | |
660 | } | |
661 | ||
662 | /** | |
663 | * sis_init_one - Register SiS ATA PCI device with kernel services | |
664 | * @pdev: PCI device to register | |
665 | * @ent: Entry in sis_pci_tbl matching with @pdev | |
666 | * | |
667 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
668 | * and then hand over control to libata, for it to do the rest. | |
669 | * | |
670 | * LOCKING: | |
671 | * Inherited from PCI layer (may sleep). | |
672 | * | |
673 | * RETURNS: | |
674 | * Zero on success, or -ERRNO value. | |
675 | */ | |
676 | ||
677 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
678 | { | |
679 | static int printed_version; | |
887125e3 | 680 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
669a5db4 JG |
681 | struct pci_dev *host = NULL; |
682 | struct sis_chipset *chipset = NULL; | |
f3769e9d | 683 | struct sis_chipset *sets; |
f08048e9 | 684 | int rc; |
669a5db4 JG |
685 | |
686 | static struct sis_chipset sis_chipsets[] = { | |
f20b16ff | 687 | |
af323a2f AC |
688 | { 0x0968, &sis_info133 }, |
689 | { 0x0966, &sis_info133 }, | |
690 | { 0x0965, &sis_info133 }, | |
669a5db4 JG |
691 | { 0x0745, &sis_info100 }, |
692 | { 0x0735, &sis_info100 }, | |
693 | { 0x0733, &sis_info100 }, | |
694 | { 0x0635, &sis_info100 }, | |
695 | { 0x0633, &sis_info100 }, | |
696 | ||
697 | { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
698 | { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
699 | ||
700 | { 0x0640, &sis_info66 }, | |
701 | { 0x0630, &sis_info66 }, | |
702 | { 0x0620, &sis_info66 }, | |
703 | { 0x0540, &sis_info66 }, | |
704 | { 0x0530, &sis_info66 }, | |
705 | ||
706 | { 0x5600, &sis_info33 }, | |
707 | { 0x5598, &sis_info33 }, | |
708 | { 0x5597, &sis_info33 }, | |
709 | { 0x5591, &sis_info33 }, | |
710 | { 0x5582, &sis_info33 }, | |
711 | { 0x5581, &sis_info33 }, | |
712 | ||
713 | { 0x5596, &sis_info }, | |
714 | { 0x5571, &sis_info }, | |
715 | { 0x5517, &sis_info }, | |
716 | { 0x5511, &sis_info }, | |
717 | ||
718 | {0} | |
719 | }; | |
720 | static struct sis_chipset sis133_early = { | |
721 | 0x0, &sis_info133_early | |
722 | }; | |
723 | static struct sis_chipset sis133 = { | |
724 | 0x0, &sis_info133 | |
725 | }; | |
726 | static struct sis_chipset sis100_early = { | |
727 | 0x0, &sis_info100_early | |
728 | }; | |
729 | static struct sis_chipset sis100 = { | |
730 | 0x0, &sis_info100 | |
731 | }; | |
732 | ||
733 | if (!printed_version++) | |
734 | dev_printk(KERN_DEBUG, &pdev->dev, | |
735 | "version " DRV_VERSION "\n"); | |
736 | ||
f08048e9 TH |
737 | rc = pcim_enable_device(pdev); |
738 | if (rc) | |
739 | return rc; | |
669a5db4 | 740 | |
f08048e9 | 741 | /* We have to find the bridge first */ |
f3769e9d AC |
742 | for (sets = &sis_chipsets[0]; sets->device; sets++) { |
743 | host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); | |
669a5db4 | 744 | if (host != NULL) { |
f3769e9d AC |
745 | chipset = sets; /* Match found */ |
746 | if (sets->device == 0x630) { /* SIS630 */ | |
44c10138 | 747 | if (host->revision >= 0x30) /* 630 ET */ |
669a5db4 JG |
748 | chipset = &sis100_early; |
749 | } | |
750 | break; | |
751 | } | |
752 | } | |
753 | ||
754 | /* Look for concealed bridges */ | |
f3769e9d | 755 | if (chipset == NULL) { |
669a5db4 JG |
756 | /* Second check */ |
757 | u32 idemisc; | |
758 | u16 trueid; | |
759 | ||
760 | /* Disable ID masking and register remapping then | |
761 | see what the real ID is */ | |
762 | ||
763 | pci_read_config_dword(pdev, 0x54, &idemisc); | |
764 | pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); | |
765 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
766 | pci_write_config_dword(pdev, 0x54, idemisc); | |
767 | ||
768 | switch(trueid) { | |
769 | case 0x5518: /* SIS 962/963 */ | |
770 | chipset = &sis133; | |
771 | if ((idemisc & 0x40000000) == 0) { | |
772 | pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); | |
773 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
774 | } | |
775 | break; | |
776 | case 0x0180: /* SIS 965/965L */ | |
777 | chipset = &sis133; | |
778 | break; | |
779 | case 0x1180: /* SIS 966/966L */ | |
780 | chipset = &sis133; | |
781 | break; | |
782 | } | |
783 | } | |
784 | ||
785 | /* Further check */ | |
786 | if (chipset == NULL) { | |
787 | struct pci_dev *lpc_bridge; | |
788 | u16 trueid; | |
789 | u8 prefctl; | |
790 | u8 idecfg; | |
669a5db4 JG |
791 | |
792 | /* Try the second unmasking technique */ | |
793 | pci_read_config_byte(pdev, 0x4a, &idecfg); | |
794 | pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); | |
795 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
796 | pci_write_config_byte(pdev, 0x4a, idecfg); | |
797 | ||
798 | switch(trueid) { | |
799 | case 0x5517: | |
800 | lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ | |
801 | if (lpc_bridge == NULL) | |
802 | break; | |
669a5db4 JG |
803 | pci_read_config_byte(pdev, 0x49, &prefctl); |
804 | pci_dev_put(lpc_bridge); | |
805 | ||
44c10138 | 806 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
669a5db4 JG |
807 | chipset = &sis133_early; |
808 | break; | |
809 | } | |
810 | chipset = &sis100; | |
811 | break; | |
812 | } | |
813 | } | |
814 | pci_dev_put(host); | |
815 | ||
816 | /* No chipset info, no support */ | |
817 | if (chipset == NULL) | |
818 | return -ENODEV; | |
819 | ||
887125e3 | 820 | ppi[0] = chipset->info; |
669a5db4 JG |
821 | |
822 | sis_fixup(pdev, chipset); | |
823 | ||
9363c382 | 824 | return ata_pci_sff_init_one(pdev, ppi, &sis_sht, chipset); |
669a5db4 JG |
825 | } |
826 | ||
827 | static const struct pci_device_id sis_pci_tbl[] = { | |
2d2744fc JG |
828 | { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ |
829 | { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ | |
a3cabb27 | 830 | { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ |
2d2744fc | 831 | |
669a5db4 JG |
832 | { } |
833 | }; | |
834 | ||
835 | static struct pci_driver sis_pci_driver = { | |
836 | .name = DRV_NAME, | |
837 | .id_table = sis_pci_tbl, | |
838 | .probe = sis_init_one, | |
839 | .remove = ata_pci_remove_one, | |
438ac6d5 | 840 | #ifdef CONFIG_PM |
62d64ae0 A |
841 | .suspend = ata_pci_device_suspend, |
842 | .resume = ata_pci_device_resume, | |
438ac6d5 | 843 | #endif |
669a5db4 JG |
844 | }; |
845 | ||
846 | static int __init sis_init(void) | |
847 | { | |
848 | return pci_register_driver(&sis_pci_driver); | |
849 | } | |
850 | ||
851 | static void __exit sis_exit(void) | |
852 | { | |
853 | pci_unregister_driver(&sis_pci_driver); | |
854 | } | |
855 | ||
669a5db4 JG |
856 | module_init(sis_init); |
857 | module_exit(sis_exit); | |
858 | ||
859 | MODULE_AUTHOR("Alan Cox"); | |
860 | MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); | |
861 | MODULE_LICENSE("GPL"); | |
862 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
863 | MODULE_VERSION(DRV_VERSION); | |
864 |