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libata: implement HDIO_GET_IDENTITY
[deliverable/linux.git] / drivers / ata / pata_sis.c
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669a5db4
JG		 1/*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Based upon linux/drivers/ide/pci/sis5513.c
7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
10 * SiS Taiwan : for direct support and hardware.
11 * Daniela Engert : for initial ATA100 advices and numerous others.
12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
13 * for checking code correctness, providing patches.
14 * Original tests and design on the SiS620 chipset.
15 * ATA100 tests and design on the SiS735 chipset.
16 * ATA16/33 support from specs
17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
18 *
19 *
20 * TODO
21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
22 * More Testing
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/ata.h>
35
36#define DRV_NAME "pata_sis"
62d64ae0 37#define DRV_VERSION "0.4.5"
669a5db4
JG		 38
39struct sis_chipset {
40 u16 device; /* PCI host ID */
41 struct ata_port_info *info; /* Info block */
42 /* Probably add family, cable detect type etc here to clean
43 up code later */
44};
45
7dcbc1f2
JJ		 46struct sis_laptop {
47 u16 device;
48 u16 subvendor;
49 u16 subdevice;
50};
51
52static const struct sis_laptop sis_laptop[] = {
53 /* devid, subvendor, subdev */
54 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
55 /* end marker */
56 { 0, }
57};
58
59static int sis_short_ata40(struct pci_dev *dev)
60{
61 const struct sis_laptop *lap = &sis_laptop[0];
62
63 while (lap->device) {
64 if (lap->device == dev->device &&
65 lap->subvendor == dev->subsystem_vendor &&
66 lap->subdevice == dev->subsystem_device)
67 return 1;
68 lap++;
69 }
70
71 return 0;
72}
73
669a5db4
JG		 74/**
75 * sis_port_base - return PCI configuration base for dev
76 * @adev: device
77 *
78 * Returns the base of the PCI configuration registers for this port
79 * number.
80 */
81
82static int sis_port_base(struct ata_device *adev)
83{
84 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
85}
86
87/**
88 * sis_133_pre_reset - check for 40/80 pin
89 * @ap: Port
90 *
91 * Perform cable detection for the later UDMA133 capable
92 * SiS chipset.
93 */
94
95static int sis_133_pre_reset(struct ata_port *ap)
96{
97 static const struct pci_bits sis_enable_bits[] = {
98 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
99 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
100 };
85cd7251 101
669a5db4
JG		 102 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
103 u16 tmp;
104
c961922b
AC		 105 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
106 return -ENOENT;
107
669a5db4
JG		 108 /* The top bit of this register is the cable detect bit */
109 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
7dcbc1f2 110 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
669a5db4
JG		 111 ap->cbl = ATA_CBL_PATA40;
112 else
113 ap->cbl = ATA_CBL_PATA80;
114
115 return ata_std_prereset(ap);
116}
117
118/**
119 * sis_error_handler - Probe specified port on PATA host controller
120 * @ap: Port to probe
121 *
122 * LOCKING:
123 * None (inherited from caller).
124 */
125
126static void sis_133_error_handler(struct ata_port *ap)
127{
128 ata_bmdma_drive_eh(ap, sis_133_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
129}
130
131
132/**
133 * sis_66_pre_reset - check for 40/80 pin
134 * @ap: Port
135 *
136 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
137 * SiS IDE controllers.
138 */
139
140static int sis_66_pre_reset(struct ata_port *ap)
141{
142 static const struct pci_bits sis_enable_bits[] = {
143 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
144 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
145 };
146
147 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
148 u8 tmp;
149
150 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
151 ata_port_disable(ap);
152 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
153 return 0;
154 }
155 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
156 pci_read_config_byte(pdev, 0x48, &tmp);
157 tmp >>= ap->port_no;
7dcbc1f2 158 if ((tmp & 0x10) && !sis_short_ata40(pdev))
669a5db4
JG		 159 ap->cbl = ATA_CBL_PATA40;
160 else
161 ap->cbl = ATA_CBL_PATA80;
162
163 return ata_std_prereset(ap);
164}
165
166/**
167 * sis_66_error_handler - Probe specified port on PATA host controller
168 * @ap: Port to probe
169 * @classes:
170 *
171 * LOCKING:
172 * None (inherited from caller).
173 */
174
175static void sis_66_error_handler(struct ata_port *ap)
176{
177 ata_bmdma_drive_eh(ap, sis_66_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
178}
179
180/**
181 * sis_old_pre_reset - probe begin
182 * @ap: ATA port
183 *
184 * Set up cable type and use generic probe init
185 */
186
187static int sis_old_pre_reset(struct ata_port *ap)
188{
189 static const struct pci_bits sis_enable_bits[] = {
190 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
191 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
192 };
85cd7251 193
669a5db4
JG		 194 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
195
196 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
197 ata_port_disable(ap);
198 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
199 return 0;
200 }
201 ap->cbl = ATA_CBL_PATA40;
202 return ata_std_prereset(ap);
203}
204
205
206/**
207 * sis_old_error_handler - Probe specified port on PATA host controller
208 * @ap: Port to probe
209 *
210 * LOCKING:
211 * None (inherited from caller).
212 */
213
214static void sis_old_error_handler(struct ata_port *ap)
215{
216 ata_bmdma_drive_eh(ap, sis_old_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
217}
218
219/**
220 * sis_set_fifo - Set RWP fifo bits for this device
221 * @ap: Port
222 * @adev: Device
223 *
224 * SIS chipsets implement prefetch/postwrite bits for each device
225 * on both channels. This functionality is not ATAPI compatible and
226 * must be configured according to the class of device present
227 */
228
229static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
230{
231 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
232 u8 fifoctrl;
233 u8 mask = 0x11;
234
235 mask <<= (2 * ap->port_no);
236 mask <<= adev->devno;
237
238 /* This holds various bits including the FIFO control */
239 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
240 fifoctrl &= ~mask;
241
242 /* Enable for ATA (disk) only */
243 if (adev->class == ATA_DEV_ATA)
244 fifoctrl |= mask;
245 pci_write_config_byte(pdev, 0x4B, fifoctrl);
246}
247
248/**
249 * sis_old_set_piomode - Initialize host controller PATA PIO timings
250 * @ap: Port whose timings we are configuring
251 * @adev: Device we are configuring for.
252 *
253 * Set PIO mode for device, in host controller PCI config space. This
254 * function handles PIO set up for all chips that are pre ATA100 and
255 * also early ATA100 devices.
256 *
257 * LOCKING:
258 * None (inherited from caller).
259 */
260
261static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
262{
263 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
264 int port = sis_port_base(adev);
265 u8 t1, t2;
266 int speed = adev->pio_mode - XFER_PIO_0;
267
268 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
269 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
270
271 sis_set_fifo(ap, adev);
272
273 pci_read_config_byte(pdev, port, &t1);
274 pci_read_config_byte(pdev, port + 1, &t2);
275
276 t1 &= ~0x0F; /* Clear active/recovery timings */
277 t2 &= ~0x07;
278
279 t1 |= active[speed];
280 t2 |= recovery[speed];
281
282 pci_write_config_byte(pdev, port, t1);
283 pci_write_config_byte(pdev, port + 1, t2);
284}
285
286/**
287 * sis_100_set_pioode - Initialize host controller PATA PIO timings
288 * @ap: Port whose timings we are configuring
289 * @adev: Device we are configuring for.
290 *
291 * Set PIO mode for device, in host controller PCI config space. This
292 * function handles PIO set up for ATA100 devices and early ATA133.
293 *
294 * LOCKING:
295 * None (inherited from caller).
296 */
297
298static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
299{
300 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
301 int port = sis_port_base(adev);
302 int speed = adev->pio_mode - XFER_PIO_0;
303
304 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
305
306 sis_set_fifo(ap, adev);
307
308 pci_write_config_byte(pdev, port, actrec[speed]);
309}
310
311/**
312 * sis_133_set_pioode - Initialize host controller PATA PIO timings
313 * @ap: Port whose timings we are configuring
314 * @adev: Device we are configuring for.
315 *
316 * Set PIO mode for device, in host controller PCI config space. This
317 * function handles PIO set up for the later ATA133 devices.
318 *
319 * LOCKING:
320 * None (inherited from caller).
321 */
322
323static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
324{
325 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
326 int port = 0x40;
327 u32 t1;
328 u32 reg54;
329 int speed = adev->pio_mode - XFER_PIO_0;
330
331 const u32 timing133[] = {
332 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
333 0x0C266000,
334 0x04263000,
335 0x0C0A3000,
336 0x05093000
337 };
338 const u32 timing100[] = {
339 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
340 0x091C4000,
341 0x031C2000,
342 0x09072000,
343 0x04062000
344 };
345
346 sis_set_fifo(ap, adev);
347
348 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
349 pci_read_config_dword(pdev, 0x54, &reg54);
350 if (reg54 & 0x40000000)
351 port = 0x70;
352 port += 8 * ap->port_no + 4 * adev->devno;
353
354 pci_read_config_dword(pdev, port, &t1);
355 t1 &= 0xC0C00FFF; /* Mask out timing */
356
357 if (t1 & 0x08) /* 100 or 133 ? */
358 t1 |= timing133[speed];
359 else
360 t1 |= timing100[speed];
361 pci_write_config_byte(pdev, port, t1);
362}
363
364/**
365 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
366 * @ap: Port whose timings we are configuring
367 * @adev: Device to program
368 *
369 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
370 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
371 * the old ide/pci driver.
372 *
373 * LOCKING:
374 * None (inherited from caller).
375 */
376
377static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
378{
379 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
380 int speed = adev->dma_mode - XFER_MW_DMA_0;
381 int drive_pci = sis_port_base(adev);
382 u16 timing;
383
384 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
385 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
386
387 pci_read_config_word(pdev, drive_pci, &timing);
388
389 if (adev->dma_mode < XFER_UDMA_0) {
390 /* bits 3-0 hold recovery timing bits 8-10 active timing and
391 the higer bits are dependant on the device */
392 timing &= ~ 0x870F;
393 timing |= mwdma_bits[speed];
394 pci_write_config_word(pdev, drive_pci, timing);
395 } else {
396 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
397 speed = adev->dma_mode - XFER_UDMA_0;
398 timing &= ~0x6000;
399 timing |= udma_bits[speed];
400 }
401}
402
403/**
404 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
405 * @ap: Port whose timings we are configuring
406 * @adev: Device to program
407 *
408 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
409 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
410 * the old ide/pci driver.
411 *
412 * LOCKING:
413 * None (inherited from caller).
414 */
415
416static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
417{
418 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
419 int speed = adev->dma_mode - XFER_MW_DMA_0;
420 int drive_pci = sis_port_base(adev);
421 u16 timing;
422
423 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
424 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
425
426 pci_read_config_word(pdev, drive_pci, &timing);
427
428 if (adev->dma_mode < XFER_UDMA_0) {
429 /* bits 3-0 hold recovery timing bits 8-10 active timing and
430 the higer bits are dependant on the device, bit 15 udma */
431 timing &= ~ 0x870F;
432 timing |= mwdma_bits[speed];
433 } else {
434 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
435 speed = adev->dma_mode - XFER_UDMA_0;
436 timing &= ~0x6000;
437 timing |= udma_bits[speed];
438 }
439 pci_write_config_word(pdev, drive_pci, timing);
440}
441
442/**
443 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
444 * @ap: Port whose timings we are configuring
445 * @adev: Device to program
446 *
447 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
448 * Handles UDMA66 and early UDMA100 devices.
449 *
450 * LOCKING:
451 * None (inherited from caller).
452 */
453
454static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
455{
456 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
457 int speed = adev->dma_mode - XFER_MW_DMA_0;
458 int drive_pci = sis_port_base(adev);
459 u16 timing;
460
461 const u16 udma_bits[] = { 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
462
463 pci_read_config_word(pdev, drive_pci, &timing);
464
465 if (adev->dma_mode < XFER_UDMA_0) {
466 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
467 } else {
468 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
469 speed = adev->dma_mode - XFER_UDMA_0;
470 timing &= ~0x0F00;
471 timing |= udma_bits[speed];
472 }
473 pci_write_config_word(pdev, drive_pci, timing);
474}
475
476/**
477 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
478 * @ap: Port whose timings we are configuring
479 * @adev: Device to program
480 *
481 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
482 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
483 * the old ide/pci driver.
484 *
485 * LOCKING:
486 * None (inherited from caller).
487 */
488
489static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
490{
491 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
492 int speed = adev->dma_mode - XFER_MW_DMA_0;
493 int drive_pci = sis_port_base(adev);
494 u16 timing;
495
496 const u16 udma_bits[] = { 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
497
498 pci_read_config_word(pdev, drive_pci, &timing);
499
500 if (adev->dma_mode < XFER_UDMA_0) {
501 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
502 } else {
503 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
504 speed = adev->dma_mode - XFER_UDMA_0;
505 timing &= ~0x0F00;
506 timing |= udma_bits[speed];
507 }
508 pci_write_config_word(pdev, drive_pci, timing);
509}
510
511/**
512 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
513 * @ap: Port whose timings we are configuring
514 * @adev: Device to program
515 *
516 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
517 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
518 * the old ide/pci driver.
519 *
520 * LOCKING:
521 * None (inherited from caller).
522 */
523
524static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
525{
526 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
527 int speed = adev->dma_mode - XFER_MW_DMA_0;
528 int port = 0x40;
529 u32 t1;
530 u32 reg54;
531
532 /* bits 4- cycle time 8 - cvs time */
533 const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
534 const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
535
536 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
537 pci_read_config_dword(pdev, 0x54, &reg54);
538 if (reg54 & 0x40000000)
539 port = 0x70;
540 port += (8 * ap->port_no) + (4 * adev->devno);
541
542 pci_read_config_dword(pdev, port, &t1);
543
544 if (adev->dma_mode < XFER_UDMA_0) {
545 t1 &= ~0x00000004;
546 /* FIXME: need data sheet to add MWDMA here. Also lacking on
547 ide/pci driver */
548 } else {
549 speed = adev->dma_mode - XFER_UDMA_0;
550 /* if & 8 no UDMA133 - need info for ... */
551 t1 &= ~0x00000FF0;
552 t1 |= 0x00000004;
553 if (t1 & 0x08)
554 t1 |= timing_u133[speed];
555 else
556 t1 |= timing_u100[speed];
557 }
558 pci_write_config_dword(pdev, port, t1);
559}
560
561static struct scsi_host_template sis_sht = {
562 .module = THIS_MODULE,
563 .name = DRV_NAME,
564 .ioctl = ata_scsi_ioctl,
565 .queuecommand = ata_scsi_queuecmd,
566 .can_queue = ATA_DEF_QUEUE,
567 .this_id = ATA_SHT_THIS_ID,
568 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 569 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
570 .emulated = ATA_SHT_EMULATED,
571 .use_clustering = ATA_SHT_USE_CLUSTERING,
572 .proc_name = DRV_NAME,
573 .dma_boundary = ATA_DMA_BOUNDARY,
574 .slave_configure = ata_scsi_slave_config,
afdfe899 575 .slave_destroy = ata_scsi_slave_destroy,
669a5db4 576 .bios_param = ata_std_bios_param,
62d64ae0
A		 577 .resume = ata_scsi_device_resume,
578 .suspend = ata_scsi_device_suspend,
669a5db4
JG		 579};
580
581static const struct ata_port_operations sis_133_ops = {
582 .port_disable = ata_port_disable,
583 .set_piomode = sis_133_set_piomode,
584 .set_dmamode = sis_133_set_dmamode,
585 .mode_filter = ata_pci_default_filter,
586
587 .tf_load = ata_tf_load,
588 .tf_read = ata_tf_read,
589 .check_status = ata_check_status,
590 .exec_command = ata_exec_command,
591 .dev_select = ata_std_dev_select,
592
593 .freeze = ata_bmdma_freeze,
594 .thaw = ata_bmdma_thaw,
595 .error_handler = sis_133_error_handler,
596 .post_internal_cmd = ata_bmdma_post_internal_cmd,
597
598 .bmdma_setup = ata_bmdma_setup,
599 .bmdma_start = ata_bmdma_start,
600 .bmdma_stop = ata_bmdma_stop,
601 .bmdma_status = ata_bmdma_status,
602 .qc_prep = ata_qc_prep,
603 .qc_issue = ata_qc_issue_prot,
604 .data_xfer = ata_pio_data_xfer,
605
669a5db4
JG		 606 .irq_handler = ata_interrupt,
607 .irq_clear = ata_bmdma_irq_clear,
608
609 .port_start = ata_port_start,
610 .port_stop = ata_port_stop,
611 .host_stop = ata_host_stop,
612};
613
614static const struct ata_port_operations sis_133_early_ops = {
615 .port_disable = ata_port_disable,
616 .set_piomode = sis_100_set_piomode,
617 .set_dmamode = sis_133_early_set_dmamode,
618 .mode_filter = ata_pci_default_filter,
619
620 .tf_load = ata_tf_load,
621 .tf_read = ata_tf_read,
622 .check_status = ata_check_status,
623 .exec_command = ata_exec_command,
624 .dev_select = ata_std_dev_select,
625
626 .freeze = ata_bmdma_freeze,
627 .thaw = ata_bmdma_thaw,
628 .error_handler = sis_66_error_handler,
629 .post_internal_cmd = ata_bmdma_post_internal_cmd,
85cd7251 630
669a5db4
JG		 631 .bmdma_setup = ata_bmdma_setup,
632 .bmdma_start = ata_bmdma_start,
633 .bmdma_stop = ata_bmdma_stop,
634 .bmdma_status = ata_bmdma_status,
635 .qc_prep = ata_qc_prep,
636 .qc_issue = ata_qc_issue_prot,
637 .data_xfer = ata_pio_data_xfer,
638
669a5db4
JG		 639 .irq_handler = ata_interrupt,
640 .irq_clear = ata_bmdma_irq_clear,
641
642 .port_start = ata_port_start,
643 .port_stop = ata_port_stop,
644 .host_stop = ata_host_stop,
645};
646
647static const struct ata_port_operations sis_100_ops = {
648 .port_disable = ata_port_disable,
649 .set_piomode = sis_100_set_piomode,
650 .set_dmamode = sis_100_set_dmamode,
651 .mode_filter = ata_pci_default_filter,
652
653 .tf_load = ata_tf_load,
654 .tf_read = ata_tf_read,
655 .check_status = ata_check_status,
656 .exec_command = ata_exec_command,
657 .dev_select = ata_std_dev_select,
658
659 .freeze = ata_bmdma_freeze,
660 .thaw = ata_bmdma_thaw,
661 .error_handler = sis_66_error_handler,
662 .post_internal_cmd = ata_bmdma_post_internal_cmd,
85cd7251 663
669a5db4
JG		 664
665 .bmdma_setup = ata_bmdma_setup,
666 .bmdma_start = ata_bmdma_start,
667 .bmdma_stop = ata_bmdma_stop,
668 .bmdma_status = ata_bmdma_status,
669 .qc_prep = ata_qc_prep,
670 .qc_issue = ata_qc_issue_prot,
671 .data_xfer = ata_pio_data_xfer,
672
669a5db4
JG		 673 .irq_handler = ata_interrupt,
674 .irq_clear = ata_bmdma_irq_clear,
675
676 .port_start = ata_port_start,
677 .port_stop = ata_port_stop,
678 .host_stop = ata_host_stop,
679};
680
681static const struct ata_port_operations sis_66_ops = {
682 .port_disable = ata_port_disable,
683 .set_piomode = sis_old_set_piomode,
684 .set_dmamode = sis_66_set_dmamode,
685 .mode_filter = ata_pci_default_filter,
686
687 .tf_load = ata_tf_load,
688 .tf_read = ata_tf_read,
689 .check_status = ata_check_status,
690 .exec_command = ata_exec_command,
691 .dev_select = ata_std_dev_select,
692
693 .freeze = ata_bmdma_freeze,
694 .thaw = ata_bmdma_thaw,
695 .error_handler = sis_66_error_handler,
696 .post_internal_cmd = ata_bmdma_post_internal_cmd,
697
698 .bmdma_setup = ata_bmdma_setup,
699 .bmdma_start = ata_bmdma_start,
700 .bmdma_stop = ata_bmdma_stop,
701 .bmdma_status = ata_bmdma_status,
702 .qc_prep = ata_qc_prep,
703 .qc_issue = ata_qc_issue_prot,
704 .data_xfer = ata_pio_data_xfer,
705
669a5db4
JG		 706 .irq_handler = ata_interrupt,
707 .irq_clear = ata_bmdma_irq_clear,
708
709 .port_start = ata_port_start,
710 .port_stop = ata_port_stop,
711 .host_stop = ata_host_stop,
712};
713
714static const struct ata_port_operations sis_old_ops = {
715 .port_disable = ata_port_disable,
716 .set_piomode = sis_old_set_piomode,
717 .set_dmamode = sis_old_set_dmamode,
718 .mode_filter = ata_pci_default_filter,
719
720 .tf_load = ata_tf_load,
721 .tf_read = ata_tf_read,
722 .check_status = ata_check_status,
723 .exec_command = ata_exec_command,
724 .dev_select = ata_std_dev_select,
725
726 .freeze = ata_bmdma_freeze,
727 .thaw = ata_bmdma_thaw,
728 .error_handler = sis_old_error_handler,
729 .post_internal_cmd = ata_bmdma_post_internal_cmd,
730
731 .bmdma_setup = ata_bmdma_setup,
732 .bmdma_start = ata_bmdma_start,
733 .bmdma_stop = ata_bmdma_stop,
734 .bmdma_status = ata_bmdma_status,
735 .qc_prep = ata_qc_prep,
736 .qc_issue = ata_qc_issue_prot,
737 .data_xfer = ata_pio_data_xfer,
738
669a5db4
JG		 739 .irq_handler = ata_interrupt,
740 .irq_clear = ata_bmdma_irq_clear,
741
742 .port_start = ata_port_start,
743 .port_stop = ata_port_stop,
744 .host_stop = ata_host_stop,
745};
746
747static struct ata_port_info sis_info = {
748 .sht = &sis_sht,
749 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
750 .pio_mask = 0x1f, /* pio0-4 */
751 .mwdma_mask = 0x07,
752 .udma_mask = 0,
753 .port_ops = &sis_old_ops,
754};
755static struct ata_port_info sis_info33 = {
756 .sht = &sis_sht,
757 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
758 .pio_mask = 0x1f, /* pio0-4 */
759 .mwdma_mask = 0x07,
760 .udma_mask = ATA_UDMA2, /* UDMA 33 */
761 .port_ops = &sis_old_ops,
762};
763static struct ata_port_info sis_info66 = {
764 .sht = &sis_sht,
765 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
766 .pio_mask = 0x1f, /* pio0-4 */
767 .udma_mask = ATA_UDMA4, /* UDMA 66 */
768 .port_ops = &sis_66_ops,
769};
770static struct ata_port_info sis_info100 = {
771 .sht = &sis_sht,
772 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
773 .pio_mask = 0x1f, /* pio0-4 */
774 .udma_mask = ATA_UDMA5,
775 .port_ops = &sis_100_ops,
776};
777static struct ata_port_info sis_info100_early = {
778 .sht = &sis_sht,
779 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
780 .udma_mask = ATA_UDMA5,
781 .pio_mask = 0x1f, /* pio0-4 */
782 .port_ops = &sis_66_ops,
783};
784static struct ata_port_info sis_info133 = {
785 .sht = &sis_sht,
786 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
787 .pio_mask = 0x1f, /* pio0-4 */
788 .udma_mask = ATA_UDMA6,
789 .port_ops = &sis_133_ops,
790};
791static struct ata_port_info sis_info133_early = {
792 .sht = &sis_sht,
793 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
794 .pio_mask = 0x1f, /* pio0-4 */
795 .udma_mask = ATA_UDMA6,
796 .port_ops = &sis_133_early_ops,
797};
798
799
800static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
801{
802 u16 regw;
803 u8 reg;
804
805 if (sis->info == &sis_info133) {
806 pci_read_config_word(pdev, 0x50, &regw);
807 if (regw & 0x08)
808 pci_write_config_word(pdev, 0x50, regw & ~0x08);
809 pci_read_config_word(pdev, 0x52, &regw);
810 if (regw & 0x08)
811 pci_write_config_word(pdev, 0x52, regw & ~0x08);
812 return;
813 }
814
815 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
816 /* Fix up latency */
817 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
818 /* Set compatibility bit */
819 pci_read_config_byte(pdev, 0x49, &reg);
820 if (!(reg & 0x01))
821 pci_write_config_byte(pdev, 0x49, reg | 0x01);
822 return;
823 }
824
825 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
826 /* Fix up latency */
827 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
828 /* Set compatibility bit */
829 pci_read_config_byte(pdev, 0x52, &reg);
830 if (!(reg & 0x04))
831 pci_write_config_byte(pdev, 0x52, reg | 0x04);
832 return;
833 }
834
835 if (sis->info == &sis_info33) {
836 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
837 if (( reg & 0x0F ) != 0x00)
838 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
839 /* Fall through to ATA16 fixup below */
840 }
841
842 if (sis->info == &sis_info || sis->info == &sis_info33) {
843 /* force per drive recovery and active timings
844 needed on ATA_33 and below chips */
845 pci_read_config_byte(pdev, 0x52, &reg);
846 if (!(reg & 0x08))
847 pci_write_config_byte(pdev, 0x52, reg|0x08);
848 return;
849 }
850
851 BUG();
852}
853
854/**
855 * sis_init_one - Register SiS ATA PCI device with kernel services
856 * @pdev: PCI device to register
857 * @ent: Entry in sis_pci_tbl matching with @pdev
858 *
859 * Called from kernel PCI layer. We probe for combined mode (sigh),
860 * and then hand over control to libata, for it to do the rest.
861 *
862 * LOCKING:
863 * Inherited from PCI layer (may sleep).
864 *
865 * RETURNS:
866 * Zero on success, or -ERRNO value.
867 */
868
869static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
870{
871 static int printed_version;
872 static struct ata_port_info *port_info[2];
873 struct ata_port_info *port;
874 struct pci_dev *host = NULL;
875 struct sis_chipset *chipset = NULL;
876
877 static struct sis_chipset sis_chipsets[] = {
f20b16ff 878
af323a2f
AC		 879 { 0x0968, &sis_info133 },
880 { 0x0966, &sis_info133 },
881 { 0x0965, &sis_info133 },
669a5db4
JG		 882 { 0x0745, &sis_info100 },
883 { 0x0735, &sis_info100 },
884 { 0x0733, &sis_info100 },
885 { 0x0635, &sis_info100 },
886 { 0x0633, &sis_info100 },
887
888 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
889 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
890
891 { 0x0640, &sis_info66 },
892 { 0x0630, &sis_info66 },
893 { 0x0620, &sis_info66 },
894 { 0x0540, &sis_info66 },
895 { 0x0530, &sis_info66 },
896
897 { 0x5600, &sis_info33 },
898 { 0x5598, &sis_info33 },
899 { 0x5597, &sis_info33 },
900 { 0x5591, &sis_info33 },
901 { 0x5582, &sis_info33 },
902 { 0x5581, &sis_info33 },
903
904 { 0x5596, &sis_info },
905 { 0x5571, &sis_info },
906 { 0x5517, &sis_info },
907 { 0x5511, &sis_info },
908
909 {0}
910 };
911 static struct sis_chipset sis133_early = {
912 0x0, &sis_info133_early
913 };
914 static struct sis_chipset sis133 = {
915 0x0, &sis_info133
916 };
917 static struct sis_chipset sis100_early = {
918 0x0, &sis_info100_early
919 };
920 static struct sis_chipset sis100 = {
921 0x0, &sis_info100
922 };
923
924 if (!printed_version++)
925 dev_printk(KERN_DEBUG, &pdev->dev,
926 "version " DRV_VERSION "\n");
927
928 /* We have to find the bridge first */
929
930 for (chipset = &sis_chipsets[0]; chipset->device; chipset++) {
931 host = pci_get_device(PCI_VENDOR_ID_SI, chipset->device, NULL);
932 if (host != NULL) {
933 if (chipset->device == 0x630) { /* SIS630 */
934 u8 host_rev;
935 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
936 if (host_rev >= 0x30) /* 630 ET */
937 chipset = &sis100_early;
938 }
939 break;
940 }
941 }
942
943 /* Look for concealed bridges */
944 if (host == NULL) {
945 /* Second check */
946 u32 idemisc;
947 u16 trueid;
948
949 /* Disable ID masking and register remapping then
950 see what the real ID is */
951
952 pci_read_config_dword(pdev, 0x54, &idemisc);
953 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
954 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
955 pci_write_config_dword(pdev, 0x54, idemisc);
956
957 switch(trueid) {
958 case 0x5518: /* SIS 962/963 */
959 chipset = &sis133;
960 if ((idemisc & 0x40000000) == 0) {
961 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
962 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
963 }
964 break;
965 case 0x0180: /* SIS 965/965L */
966 chipset = &sis133;
967 break;
968 case 0x1180: /* SIS 966/966L */
969 chipset = &sis133;
970 break;
971 }
972 }
973
974 /* Further check */
975 if (chipset == NULL) {
976 struct pci_dev *lpc_bridge;
977 u16 trueid;
978 u8 prefctl;
979 u8 idecfg;
980 u8 sbrev;
981
982 /* Try the second unmasking technique */
983 pci_read_config_byte(pdev, 0x4a, &idecfg);
984 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
985 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
986 pci_write_config_byte(pdev, 0x4a, idecfg);
987
988 switch(trueid) {
989 case 0x5517:
990 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
991 if (lpc_bridge == NULL)
992 break;
993 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
994 pci_read_config_byte(pdev, 0x49, &prefctl);
995 pci_dev_put(lpc_bridge);
996
997 if (sbrev == 0x10 && (prefctl & 0x80)) {
998 chipset = &sis133_early;
999 break;
1000 }
1001 chipset = &sis100;
1002 break;
1003 }
1004 }
1005 pci_dev_put(host);
1006
1007 /* No chipset info, no support */
1008 if (chipset == NULL)
1009 return -ENODEV;
1010
1011 port = chipset->info;
1012 port->private_data = chipset;
1013
1014 sis_fixup(pdev, chipset);
1015
1016 port_info[0] = port_info[1] = port;
1017 return ata_pci_init_one(pdev, port_info, 2);
1018}
1019
1020static const struct pci_device_id sis_pci_tbl[] = {
2d2744fc
JG		 1021 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
1022 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
1023
669a5db4
JG		 1024 { }
1025};
1026
1027static struct pci_driver sis_pci_driver = {
1028 .name = DRV_NAME,
1029 .id_table = sis_pci_tbl,
1030 .probe = sis_init_one,
1031 .remove = ata_pci_remove_one,
62d64ae0
A		 1032 .suspend = ata_pci_device_suspend,
1033 .resume = ata_pci_device_resume,
669a5db4
JG		 1034};
1035
1036static int __init sis_init(void)
1037{
1038 return pci_register_driver(&sis_pci_driver);
1039}
1040
1041static void __exit sis_exit(void)
1042{
1043 pci_unregister_driver(&sis_pci_driver);
1044}
1045
669a5db4
JG		 1046module_init(sis_init);
1047module_exit(sis_exit);
1048
1049MODULE_AUTHOR("Alan Cox");
1050MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1051MODULE_LICENSE("GPL");
1052MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1053MODULE_VERSION(DRV_VERSION);
1054
Linux kernel - Deliverables
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