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cache_k8_northbridges() overflows beyond allocation
[deliverable/linux.git] / drivers / ata / pata_sis.c
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669a5db4
JG		 1/*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Based upon linux/drivers/ide/pci/sis5513.c
7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
10 * SiS Taiwan : for direct support and hardware.
11 * Daniela Engert : for initial ATA100 advices and numerous others.
12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
13 * for checking code correctness, providing patches.
14 * Original tests and design on the SiS620 chipset.
15 * ATA100 tests and design on the SiS735 chipset.
16 * ATA16/33 support from specs
17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
18 *
19 *
20 * TODO
21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
22 * More Testing
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/ata.h>
4bb64fb9 35#include "sis.h"
669a5db4
JG		 36
37#define DRV_NAME "pata_sis"
cb48cab7 38#define DRV_VERSION "0.5.0"
669a5db4
JG		 39
40struct sis_chipset {
41 u16 device; /* PCI host ID */
42 struct ata_port_info *info; /* Info block */
43 /* Probably add family, cable detect type etc here to clean
44 up code later */
45};
46
7dcbc1f2
JJ		 47struct sis_laptop {
48 u16 device;
49 u16 subvendor;
50 u16 subdevice;
51};
52
53static const struct sis_laptop sis_laptop[] = {
54 /* devid, subvendor, subdev */
55 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
56 /* end marker */
57 { 0, }
58};
59
60static int sis_short_ata40(struct pci_dev *dev)
61{
62 const struct sis_laptop *lap = &sis_laptop[0];
63
64 while (lap->device) {
65 if (lap->device == dev->device &&
66 lap->subvendor == dev->subsystem_vendor &&
67 lap->subdevice == dev->subsystem_device)
68 return 1;
69 lap++;
70 }
71
72 return 0;
73}
74
669a5db4
JG		 75/**
76 * sis_port_base - return PCI configuration base for dev
77 * @adev: device
78 *
79 * Returns the base of the PCI configuration registers for this port
80 * number.
81 */
82
83static int sis_port_base(struct ata_device *adev)
84{
85 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
86}
87
88/**
89 * sis_133_pre_reset - check for 40/80 pin
90 * @ap: Port
91 *
92 * Perform cable detection for the later UDMA133 capable
93 * SiS chipset.
94 */
95
96static int sis_133_pre_reset(struct ata_port *ap)
97{
98 static const struct pci_bits sis_enable_bits[] = {
99 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
100 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
101 };
85cd7251 102
669a5db4
JG		 103 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
104 u16 tmp;
105
c961922b
AC		 106 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
107 return -ENOENT;
108
669a5db4
JG		 109 /* The top bit of this register is the cable detect bit */
110 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
7dcbc1f2 111 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
669a5db4
JG		 112 ap->cbl = ATA_CBL_PATA40;
113 else
114 ap->cbl = ATA_CBL_PATA80;
115
116 return ata_std_prereset(ap);
117}
118
119/**
120 * sis_error_handler - Probe specified port on PATA host controller
121 * @ap: Port to probe
122 *
123 * LOCKING:
124 * None (inherited from caller).
125 */
126
127static void sis_133_error_handler(struct ata_port *ap)
128{
129 ata_bmdma_drive_eh(ap, sis_133_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
130}
131
132
133/**
134 * sis_66_pre_reset - check for 40/80 pin
135 * @ap: Port
136 *
137 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
138 * SiS IDE controllers.
139 */
140
141static int sis_66_pre_reset(struct ata_port *ap)
142{
143 static const struct pci_bits sis_enable_bits[] = {
144 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
145 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
146 };
147
148 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
149 u8 tmp;
150
151 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
152 ata_port_disable(ap);
44877b4e 153 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
669a5db4
JG		 154 return 0;
155 }
156 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
157 pci_read_config_byte(pdev, 0x48, &tmp);
158 tmp >>= ap->port_no;
7dcbc1f2 159 if ((tmp & 0x10) && !sis_short_ata40(pdev))
669a5db4
JG		 160 ap->cbl = ATA_CBL_PATA40;
161 else
162 ap->cbl = ATA_CBL_PATA80;
163
164 return ata_std_prereset(ap);
165}
166
167/**
168 * sis_66_error_handler - Probe specified port on PATA host controller
169 * @ap: Port to probe
170 * @classes:
171 *
172 * LOCKING:
173 * None (inherited from caller).
174 */
175
176static void sis_66_error_handler(struct ata_port *ap)
177{
178 ata_bmdma_drive_eh(ap, sis_66_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
179}
180
181/**
182 * sis_old_pre_reset - probe begin
183 * @ap: ATA port
184 *
185 * Set up cable type and use generic probe init
186 */
187
188static int sis_old_pre_reset(struct ata_port *ap)
189{
190 static const struct pci_bits sis_enable_bits[] = {
191 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
192 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
193 };
85cd7251 194
669a5db4
JG		 195 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
196
197 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
198 ata_port_disable(ap);
44877b4e 199 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
669a5db4
JG		 200 return 0;
201 }
202 ap->cbl = ATA_CBL_PATA40;
203 return ata_std_prereset(ap);
204}
205
206
207/**
208 * sis_old_error_handler - Probe specified port on PATA host controller
209 * @ap: Port to probe
210 *
211 * LOCKING:
212 * None (inherited from caller).
213 */
214
215static void sis_old_error_handler(struct ata_port *ap)
216{
217 ata_bmdma_drive_eh(ap, sis_old_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
218}
219
220/**
221 * sis_set_fifo - Set RWP fifo bits for this device
222 * @ap: Port
223 * @adev: Device
224 *
225 * SIS chipsets implement prefetch/postwrite bits for each device
226 * on both channels. This functionality is not ATAPI compatible and
227 * must be configured according to the class of device present
228 */
229
230static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
231{
232 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
233 u8 fifoctrl;
234 u8 mask = 0x11;
235
236 mask <<= (2 * ap->port_no);
237 mask <<= adev->devno;
238
239 /* This holds various bits including the FIFO control */
240 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
241 fifoctrl &= ~mask;
242
243 /* Enable for ATA (disk) only */
244 if (adev->class == ATA_DEV_ATA)
245 fifoctrl |= mask;
246 pci_write_config_byte(pdev, 0x4B, fifoctrl);
247}
248
249/**
250 * sis_old_set_piomode - Initialize host controller PATA PIO timings
251 * @ap: Port whose timings we are configuring
252 * @adev: Device we are configuring for.
253 *
254 * Set PIO mode for device, in host controller PCI config space. This
255 * function handles PIO set up for all chips that are pre ATA100 and
256 * also early ATA100 devices.
257 *
258 * LOCKING:
259 * None (inherited from caller).
260 */
261
262static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
263{
264 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
265 int port = sis_port_base(adev);
266 u8 t1, t2;
267 int speed = adev->pio_mode - XFER_PIO_0;
268
269 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
270 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
271
272 sis_set_fifo(ap, adev);
273
274 pci_read_config_byte(pdev, port, &t1);
275 pci_read_config_byte(pdev, port + 1, &t2);
276
277 t1 &= ~0x0F; /* Clear active/recovery timings */
278 t2 &= ~0x07;
279
280 t1 |= active[speed];
281 t2 |= recovery[speed];
282
283 pci_write_config_byte(pdev, port, t1);
284 pci_write_config_byte(pdev, port + 1, t2);
285}
286
287/**
288 * sis_100_set_pioode - Initialize host controller PATA PIO timings
289 * @ap: Port whose timings we are configuring
290 * @adev: Device we are configuring for.
291 *
292 * Set PIO mode for device, in host controller PCI config space. This
293 * function handles PIO set up for ATA100 devices and early ATA133.
294 *
295 * LOCKING:
296 * None (inherited from caller).
297 */
298
299static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
300{
301 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
302 int port = sis_port_base(adev);
303 int speed = adev->pio_mode - XFER_PIO_0;
304
305 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
306
307 sis_set_fifo(ap, adev);
308
309 pci_write_config_byte(pdev, port, actrec[speed]);
310}
311
312/**
313 * sis_133_set_pioode - Initialize host controller PATA PIO timings
314 * @ap: Port whose timings we are configuring
315 * @adev: Device we are configuring for.
316 *
317 * Set PIO mode for device, in host controller PCI config space. This
318 * function handles PIO set up for the later ATA133 devices.
319 *
320 * LOCKING:
321 * None (inherited from caller).
322 */
323
324static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
325{
326 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
327 int port = 0x40;
328 u32 t1;
329 u32 reg54;
330 int speed = adev->pio_mode - XFER_PIO_0;
331
332 const u32 timing133[] = {
333 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
334 0x0C266000,
335 0x04263000,
336 0x0C0A3000,
337 0x05093000
338 };
339 const u32 timing100[] = {
340 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
341 0x091C4000,
342 0x031C2000,
343 0x09072000,
344 0x04062000
345 };
346
347 sis_set_fifo(ap, adev);
348
349 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
350 pci_read_config_dword(pdev, 0x54, &reg54);
351 if (reg54 & 0x40000000)
352 port = 0x70;
353 port += 8 * ap->port_no + 4 * adev->devno;
354
355 pci_read_config_dword(pdev, port, &t1);
356 t1 &= 0xC0C00FFF; /* Mask out timing */
357
358 if (t1 & 0x08) /* 100 or 133 ? */
359 t1 |= timing133[speed];
360 else
361 t1 |= timing100[speed];
362 pci_write_config_byte(pdev, port, t1);
363}
364
365/**
366 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
367 * @ap: Port whose timings we are configuring
368 * @adev: Device to program
369 *
370 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
371 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
372 * the old ide/pci driver.
373 *
374 * LOCKING:
375 * None (inherited from caller).
376 */
377
378static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
379{
380 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
381 int speed = adev->dma_mode - XFER_MW_DMA_0;
382 int drive_pci = sis_port_base(adev);
383 u16 timing;
384
385 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
386 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
387
388 pci_read_config_word(pdev, drive_pci, &timing);
389
390 if (adev->dma_mode < XFER_UDMA_0) {
391 /* bits 3-0 hold recovery timing bits 8-10 active timing and
392 the higer bits are dependant on the device */
393 timing &= ~ 0x870F;
394 timing |= mwdma_bits[speed];
395 pci_write_config_word(pdev, drive_pci, timing);
396 } else {
397 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
398 speed = adev->dma_mode - XFER_UDMA_0;
399 timing &= ~0x6000;
400 timing |= udma_bits[speed];
401 }
402}
403
404/**
405 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
406 * @ap: Port whose timings we are configuring
407 * @adev: Device to program
408 *
409 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
410 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
411 * the old ide/pci driver.
412 *
413 * LOCKING:
414 * None (inherited from caller).
415 */
416
417static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
418{
419 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
420 int speed = adev->dma_mode - XFER_MW_DMA_0;
421 int drive_pci = sis_port_base(adev);
422 u16 timing;
423
424 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
425 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
426
427 pci_read_config_word(pdev, drive_pci, &timing);
428
429 if (adev->dma_mode < XFER_UDMA_0) {
430 /* bits 3-0 hold recovery timing bits 8-10 active timing and
431 the higer bits are dependant on the device, bit 15 udma */
432 timing &= ~ 0x870F;
433 timing |= mwdma_bits[speed];
434 } else {
435 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
436 speed = adev->dma_mode - XFER_UDMA_0;
437 timing &= ~0x6000;
438 timing |= udma_bits[speed];
439 }
440 pci_write_config_word(pdev, drive_pci, timing);
441}
442
443/**
444 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
445 * @ap: Port whose timings we are configuring
446 * @adev: Device to program
447 *
448 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
449 * Handles UDMA66 and early UDMA100 devices.
450 *
451 * LOCKING:
452 * None (inherited from caller).
453 */
454
455static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
456{
457 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
458 int speed = adev->dma_mode - XFER_MW_DMA_0;
459 int drive_pci = sis_port_base(adev);
460 u16 timing;
461
462 const u16 udma_bits[] = { 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
463
464 pci_read_config_word(pdev, drive_pci, &timing);
465
466 if (adev->dma_mode < XFER_UDMA_0) {
467 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
468 } else {
469 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
470 speed = adev->dma_mode - XFER_UDMA_0;
471 timing &= ~0x0F00;
472 timing |= udma_bits[speed];
473 }
474 pci_write_config_word(pdev, drive_pci, timing);
475}
476
477/**
478 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
479 * @ap: Port whose timings we are configuring
480 * @adev: Device to program
481 *
482 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
483 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
484 * the old ide/pci driver.
485 *
486 * LOCKING:
487 * None (inherited from caller).
488 */
489
490static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
491{
492 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
493 int speed = adev->dma_mode - XFER_MW_DMA_0;
494 int drive_pci = sis_port_base(adev);
495 u16 timing;
496
497 const u16 udma_bits[] = { 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
498
499 pci_read_config_word(pdev, drive_pci, &timing);
500
501 if (adev->dma_mode < XFER_UDMA_0) {
502 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
503 } else {
504 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
505 speed = adev->dma_mode - XFER_UDMA_0;
506 timing &= ~0x0F00;
507 timing |= udma_bits[speed];
508 }
509 pci_write_config_word(pdev, drive_pci, timing);
510}
511
512/**
513 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
514 * @ap: Port whose timings we are configuring
515 * @adev: Device to program
516 *
517 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
518 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
519 * the old ide/pci driver.
520 *
521 * LOCKING:
522 * None (inherited from caller).
523 */
524
525static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
526{
527 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
528 int speed = adev->dma_mode - XFER_MW_DMA_0;
529 int port = 0x40;
530 u32 t1;
531 u32 reg54;
532
533 /* bits 4- cycle time 8 - cvs time */
534 const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
535 const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
536
537 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
538 pci_read_config_dword(pdev, 0x54, &reg54);
539 if (reg54 & 0x40000000)
540 port = 0x70;
541 port += (8 * ap->port_no) + (4 * adev->devno);
542
543 pci_read_config_dword(pdev, port, &t1);
544
545 if (adev->dma_mode < XFER_UDMA_0) {
546 t1 &= ~0x00000004;
547 /* FIXME: need data sheet to add MWDMA here. Also lacking on
548 ide/pci driver */
549 } else {
550 speed = adev->dma_mode - XFER_UDMA_0;
551 /* if & 8 no UDMA133 - need info for ... */
552 t1 &= ~0x00000FF0;
553 t1 |= 0x00000004;
554 if (t1 & 0x08)
555 t1 |= timing_u133[speed];
556 else
557 t1 |= timing_u100[speed];
558 }
559 pci_write_config_dword(pdev, port, t1);
560}
561
562static struct scsi_host_template sis_sht = {
563 .module = THIS_MODULE,
564 .name = DRV_NAME,
565 .ioctl = ata_scsi_ioctl,
566 .queuecommand = ata_scsi_queuecmd,
567 .can_queue = ATA_DEF_QUEUE,
568 .this_id = ATA_SHT_THIS_ID,
569 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 570 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
571 .emulated = ATA_SHT_EMULATED,
572 .use_clustering = ATA_SHT_USE_CLUSTERING,
573 .proc_name = DRV_NAME,
574 .dma_boundary = ATA_DMA_BOUNDARY,
575 .slave_configure = ata_scsi_slave_config,
afdfe899 576 .slave_destroy = ata_scsi_slave_destroy,
669a5db4 577 .bios_param = ata_std_bios_param,
438ac6d5 578#ifdef CONFIG_PM
62d64ae0
A		 579 .resume = ata_scsi_device_resume,
580 .suspend = ata_scsi_device_suspend,
438ac6d5 581#endif
669a5db4
JG		 582};
583
584static const struct ata_port_operations sis_133_ops = {
585 .port_disable = ata_port_disable,
586 .set_piomode = sis_133_set_piomode,
587 .set_dmamode = sis_133_set_dmamode,
588 .mode_filter = ata_pci_default_filter,
589
590 .tf_load = ata_tf_load,
591 .tf_read = ata_tf_read,
592 .check_status = ata_check_status,
593 .exec_command = ata_exec_command,
594 .dev_select = ata_std_dev_select,
595
596 .freeze = ata_bmdma_freeze,
597 .thaw = ata_bmdma_thaw,
598 .error_handler = sis_133_error_handler,
599 .post_internal_cmd = ata_bmdma_post_internal_cmd,
600
601 .bmdma_setup = ata_bmdma_setup,
602 .bmdma_start = ata_bmdma_start,
603 .bmdma_stop = ata_bmdma_stop,
604 .bmdma_status = ata_bmdma_status,
605 .qc_prep = ata_qc_prep,
606 .qc_issue = ata_qc_issue_prot,
0d5ff566 607 .data_xfer = ata_data_xfer,
669a5db4 608
669a5db4
JG		 609 .irq_handler = ata_interrupt,
610 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 611 .irq_on = ata_irq_on,
612 .irq_ack = ata_irq_ack,
669a5db4
JG		 613
614 .port_start = ata_port_start,
669a5db4
JG		 615};
616
617static const struct ata_port_operations sis_133_early_ops = {
618 .port_disable = ata_port_disable,
619 .set_piomode = sis_100_set_piomode,
620 .set_dmamode = sis_133_early_set_dmamode,
621 .mode_filter = ata_pci_default_filter,
622
623 .tf_load = ata_tf_load,
624 .tf_read = ata_tf_read,
625 .check_status = ata_check_status,
626 .exec_command = ata_exec_command,
627 .dev_select = ata_std_dev_select,
628
629 .freeze = ata_bmdma_freeze,
630 .thaw = ata_bmdma_thaw,
631 .error_handler = sis_66_error_handler,
632 .post_internal_cmd = ata_bmdma_post_internal_cmd,
85cd7251 633
669a5db4
JG		 634 .bmdma_setup = ata_bmdma_setup,
635 .bmdma_start = ata_bmdma_start,
636 .bmdma_stop = ata_bmdma_stop,
637 .bmdma_status = ata_bmdma_status,
638 .qc_prep = ata_qc_prep,
639 .qc_issue = ata_qc_issue_prot,
0d5ff566 640 .data_xfer = ata_data_xfer,
669a5db4 641
669a5db4
JG		 642 .irq_handler = ata_interrupt,
643 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 644 .irq_on = ata_irq_on,
645 .irq_ack = ata_irq_ack,
669a5db4
JG		 646
647 .port_start = ata_port_start,
669a5db4
JG		 648};
649
650static const struct ata_port_operations sis_100_ops = {
651 .port_disable = ata_port_disable,
652 .set_piomode = sis_100_set_piomode,
653 .set_dmamode = sis_100_set_dmamode,
654 .mode_filter = ata_pci_default_filter,
655
656 .tf_load = ata_tf_load,
657 .tf_read = ata_tf_read,
658 .check_status = ata_check_status,
659 .exec_command = ata_exec_command,
660 .dev_select = ata_std_dev_select,
661
662 .freeze = ata_bmdma_freeze,
663 .thaw = ata_bmdma_thaw,
664 .error_handler = sis_66_error_handler,
665 .post_internal_cmd = ata_bmdma_post_internal_cmd,
85cd7251 666
669a5db4
JG		 667
668 .bmdma_setup = ata_bmdma_setup,
669 .bmdma_start = ata_bmdma_start,
670 .bmdma_stop = ata_bmdma_stop,
671 .bmdma_status = ata_bmdma_status,
672 .qc_prep = ata_qc_prep,
673 .qc_issue = ata_qc_issue_prot,
0d5ff566 674 .data_xfer = ata_data_xfer,
669a5db4 675
669a5db4
JG		 676 .irq_handler = ata_interrupt,
677 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 678 .irq_on = ata_irq_on,
679 .irq_ack = ata_irq_ack,
669a5db4
JG		 680
681 .port_start = ata_port_start,
669a5db4
JG		 682};
683
684static const struct ata_port_operations sis_66_ops = {
685 .port_disable = ata_port_disable,
686 .set_piomode = sis_old_set_piomode,
687 .set_dmamode = sis_66_set_dmamode,
688 .mode_filter = ata_pci_default_filter,
689
690 .tf_load = ata_tf_load,
691 .tf_read = ata_tf_read,
692 .check_status = ata_check_status,
693 .exec_command = ata_exec_command,
694 .dev_select = ata_std_dev_select,
695
696 .freeze = ata_bmdma_freeze,
697 .thaw = ata_bmdma_thaw,
698 .error_handler = sis_66_error_handler,
699 .post_internal_cmd = ata_bmdma_post_internal_cmd,
700
701 .bmdma_setup = ata_bmdma_setup,
702 .bmdma_start = ata_bmdma_start,
703 .bmdma_stop = ata_bmdma_stop,
704 .bmdma_status = ata_bmdma_status,
705 .qc_prep = ata_qc_prep,
706 .qc_issue = ata_qc_issue_prot,
0d5ff566 707 .data_xfer = ata_data_xfer,
669a5db4 708
669a5db4
JG		 709 .irq_handler = ata_interrupt,
710 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 711 .irq_on = ata_irq_on,
712 .irq_ack = ata_irq_ack,
669a5db4
JG		 713
714 .port_start = ata_port_start,
669a5db4
JG		 715};
716
717static const struct ata_port_operations sis_old_ops = {
718 .port_disable = ata_port_disable,
719 .set_piomode = sis_old_set_piomode,
720 .set_dmamode = sis_old_set_dmamode,
721 .mode_filter = ata_pci_default_filter,
722
723 .tf_load = ata_tf_load,
724 .tf_read = ata_tf_read,
725 .check_status = ata_check_status,
726 .exec_command = ata_exec_command,
727 .dev_select = ata_std_dev_select,
728
729 .freeze = ata_bmdma_freeze,
730 .thaw = ata_bmdma_thaw,
731 .error_handler = sis_old_error_handler,
732 .post_internal_cmd = ata_bmdma_post_internal_cmd,
733
734 .bmdma_setup = ata_bmdma_setup,
735 .bmdma_start = ata_bmdma_start,
736 .bmdma_stop = ata_bmdma_stop,
737 .bmdma_status = ata_bmdma_status,
738 .qc_prep = ata_qc_prep,
739 .qc_issue = ata_qc_issue_prot,
0d5ff566 740 .data_xfer = ata_data_xfer,
669a5db4 741
669a5db4
JG		 742 .irq_handler = ata_interrupt,
743 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 744 .irq_on = ata_irq_on,
745 .irq_ack = ata_irq_ack,
669a5db4
JG		 746
747 .port_start = ata_port_start,
669a5db4
JG		 748};
749
750static struct ata_port_info sis_info = {
751 .sht = &sis_sht,
752 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
753 .pio_mask = 0x1f, /* pio0-4 */
754 .mwdma_mask = 0x07,
755 .udma_mask = 0,
756 .port_ops = &sis_old_ops,
757};
758static struct ata_port_info sis_info33 = {
759 .sht = &sis_sht,
760 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
761 .pio_mask = 0x1f, /* pio0-4 */
762 .mwdma_mask = 0x07,
763 .udma_mask = ATA_UDMA2, /* UDMA 33 */
764 .port_ops = &sis_old_ops,
765};
766static struct ata_port_info sis_info66 = {
767 .sht = &sis_sht,
768 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
769 .pio_mask = 0x1f, /* pio0-4 */
770 .udma_mask = ATA_UDMA4, /* UDMA 66 */
771 .port_ops = &sis_66_ops,
772};
773static struct ata_port_info sis_info100 = {
774 .sht = &sis_sht,
775 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
776 .pio_mask = 0x1f, /* pio0-4 */
777 .udma_mask = ATA_UDMA5,
778 .port_ops = &sis_100_ops,
779};
780static struct ata_port_info sis_info100_early = {
781 .sht = &sis_sht,
782 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
783 .udma_mask = ATA_UDMA5,
784 .pio_mask = 0x1f, /* pio0-4 */
785 .port_ops = &sis_66_ops,
786};
77a527ea 787struct ata_port_info sis_info133 = {
669a5db4
JG		 788 .sht = &sis_sht,
789 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
790 .pio_mask = 0x1f, /* pio0-4 */
791 .udma_mask = ATA_UDMA6,
792 .port_ops = &sis_133_ops,
793};
794static struct ata_port_info sis_info133_early = {
795 .sht = &sis_sht,
796 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
797 .pio_mask = 0x1f, /* pio0-4 */
798 .udma_mask = ATA_UDMA6,
799 .port_ops = &sis_133_early_ops,
800};
801
9b14dec5
A		 802/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
803EXPORT_SYMBOL_GPL(sis_info133);
669a5db4
JG		 804
805static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
806{
807 u16 regw;
808 u8 reg;
809
810 if (sis->info == &sis_info133) {
811 pci_read_config_word(pdev, 0x50, &regw);
812 if (regw & 0x08)
813 pci_write_config_word(pdev, 0x50, regw & ~0x08);
814 pci_read_config_word(pdev, 0x52, &regw);
815 if (regw & 0x08)
816 pci_write_config_word(pdev, 0x52, regw & ~0x08);
817 return;
818 }
819
820 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
821 /* Fix up latency */
822 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
823 /* Set compatibility bit */
824 pci_read_config_byte(pdev, 0x49, &reg);
825 if (!(reg & 0x01))
826 pci_write_config_byte(pdev, 0x49, reg | 0x01);
827 return;
828 }
829
830 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
831 /* Fix up latency */
832 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
833 /* Set compatibility bit */
834 pci_read_config_byte(pdev, 0x52, &reg);
835 if (!(reg & 0x04))
836 pci_write_config_byte(pdev, 0x52, reg | 0x04);
837 return;
838 }
839
840 if (sis->info == &sis_info33) {
841 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
842 if (( reg & 0x0F ) != 0x00)
843 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
844 /* Fall through to ATA16 fixup below */
845 }
846
847 if (sis->info == &sis_info || sis->info == &sis_info33) {
848 /* force per drive recovery and active timings
849 needed on ATA_33 and below chips */
850 pci_read_config_byte(pdev, 0x52, &reg);
851 if (!(reg & 0x08))
852 pci_write_config_byte(pdev, 0x52, reg|0x08);
853 return;
854 }
855
856 BUG();
857}
858
859/**
860 * sis_init_one - Register SiS ATA PCI device with kernel services
861 * @pdev: PCI device to register
862 * @ent: Entry in sis_pci_tbl matching with @pdev
863 *
864 * Called from kernel PCI layer. We probe for combined mode (sigh),
865 * and then hand over control to libata, for it to do the rest.
866 *
867 * LOCKING:
868 * Inherited from PCI layer (may sleep).
869 *
870 * RETURNS:
871 * Zero on success, or -ERRNO value.
872 */
873
874static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
875{
876 static int printed_version;
877 static struct ata_port_info *port_info[2];
878 struct ata_port_info *port;
879 struct pci_dev *host = NULL;
880 struct sis_chipset *chipset = NULL;
881
882 static struct sis_chipset sis_chipsets[] = {
f20b16ff 883
af323a2f
AC		 884 { 0x0968, &sis_info133 },
885 { 0x0966, &sis_info133 },
886 { 0x0965, &sis_info133 },
669a5db4
JG		 887 { 0x0745, &sis_info100 },
888 { 0x0735, &sis_info100 },
889 { 0x0733, &sis_info100 },
890 { 0x0635, &sis_info100 },
891 { 0x0633, &sis_info100 },
892
893 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
894 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
895
896 { 0x0640, &sis_info66 },
897 { 0x0630, &sis_info66 },
898 { 0x0620, &sis_info66 },
899 { 0x0540, &sis_info66 },
900 { 0x0530, &sis_info66 },
901
902 { 0x5600, &sis_info33 },
903 { 0x5598, &sis_info33 },
904 { 0x5597, &sis_info33 },
905 { 0x5591, &sis_info33 },
906 { 0x5582, &sis_info33 },
907 { 0x5581, &sis_info33 },
908
909 { 0x5596, &sis_info },
910 { 0x5571, &sis_info },
911 { 0x5517, &sis_info },
912 { 0x5511, &sis_info },
913
914 {0}
915 };
916 static struct sis_chipset sis133_early = {
917 0x0, &sis_info133_early
918 };
919 static struct sis_chipset sis133 = {
920 0x0, &sis_info133
921 };
922 static struct sis_chipset sis100_early = {
923 0x0, &sis_info100_early
924 };
925 static struct sis_chipset sis100 = {
926 0x0, &sis_info100
927 };
928
929 if (!printed_version++)
930 dev_printk(KERN_DEBUG, &pdev->dev,
931 "version " DRV_VERSION "\n");
932
933 /* We have to find the bridge first */
934
935 for (chipset = &sis_chipsets[0]; chipset->device; chipset++) {
936 host = pci_get_device(PCI_VENDOR_ID_SI, chipset->device, NULL);
937 if (host != NULL) {
938 if (chipset->device == 0x630) { /* SIS630 */
939 u8 host_rev;
940 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
941 if (host_rev >= 0x30) /* 630 ET */
942 chipset = &sis100_early;
943 }
944 break;
945 }
946 }
947
948 /* Look for concealed bridges */
949 if (host == NULL) {
950 /* Second check */
951 u32 idemisc;
952 u16 trueid;
953
954 /* Disable ID masking and register remapping then
955 see what the real ID is */
956
957 pci_read_config_dword(pdev, 0x54, &idemisc);
958 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
959 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
960 pci_write_config_dword(pdev, 0x54, idemisc);
961
962 switch(trueid) {
963 case 0x5518: /* SIS 962/963 */
964 chipset = &sis133;
965 if ((idemisc & 0x40000000) == 0) {
966 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
967 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
968 }
969 break;
970 case 0x0180: /* SIS 965/965L */
971 chipset = &sis133;
972 break;
973 case 0x1180: /* SIS 966/966L */
974 chipset = &sis133;
975 break;
976 }
977 }
978
979 /* Further check */
980 if (chipset == NULL) {
981 struct pci_dev *lpc_bridge;
982 u16 trueid;
983 u8 prefctl;
984 u8 idecfg;
985 u8 sbrev;
986
987 /* Try the second unmasking technique */
988 pci_read_config_byte(pdev, 0x4a, &idecfg);
989 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
990 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
991 pci_write_config_byte(pdev, 0x4a, idecfg);
992
993 switch(trueid) {
994 case 0x5517:
995 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
996 if (lpc_bridge == NULL)
997 break;
998 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
999 pci_read_config_byte(pdev, 0x49, &prefctl);
1000 pci_dev_put(lpc_bridge);
1001
1002 if (sbrev == 0x10 && (prefctl & 0x80)) {
1003 chipset = &sis133_early;
1004 break;
1005 }
1006 chipset = &sis100;
1007 break;
1008 }
1009 }
1010 pci_dev_put(host);
1011
1012 /* No chipset info, no support */
1013 if (chipset == NULL)
1014 return -ENODEV;
1015
1016 port = chipset->info;
1017 port->private_data = chipset;
1018
1019 sis_fixup(pdev, chipset);
1020
1021 port_info[0] = port_info[1] = port;
1022 return ata_pci_init_one(pdev, port_info, 2);
1023}
1024
1025static const struct pci_device_id sis_pci_tbl[] = {
2d2744fc
JG		 1026 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
1027 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
1028
669a5db4
JG		 1029 { }
1030};
1031
1032static struct pci_driver sis_pci_driver = {
1033 .name = DRV_NAME,
1034 .id_table = sis_pci_tbl,
1035 .probe = sis_init_one,
1036 .remove = ata_pci_remove_one,
438ac6d5 1037#ifdef CONFIG_PM
62d64ae0
A		 1038 .suspend = ata_pci_device_suspend,
1039 .resume = ata_pci_device_resume,
438ac6d5 1040#endif
669a5db4
JG		 1041};
1042
1043static int __init sis_init(void)
1044{
1045 return pci_register_driver(&sis_pci_driver);
1046}
1047
1048static void __exit sis_exit(void)
1049{
1050 pci_unregister_driver(&sis_pci_driver);
1051}
1052
669a5db4
JG		 1053module_init(sis_init);
1054module_exit(sis_exit);
1055
1056MODULE_AUTHOR("Alan Cox");
1057MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1058MODULE_LICENSE("GPL");
1059MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1060MODULE_VERSION(DRV_VERSION);
1061
Linux kernel - Deliverables
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