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ata/sata_fsl: Kill ata_sg_is_last()
[deliverable/linux.git] / drivers / ata / sata_fsl.c
CommitLineData
faf0b2e5
LY		 1/*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21
22#include <scsi/scsi_host.h>
23#include <scsi/scsi_cmnd.h>
24#include <linux/libata.h>
25#include <asm/io.h>
26#include <linux/of_platform.h>
27
28/* Controller information */
29enum {
30 SATA_FSL_QUEUE_DEPTH = 16,
31 SATA_FSL_MAX_PRD = 63,
32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
1bf617b7
LY		 37 ATA_FLAG_NCQ),
38 SATA_FSL_HOST_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
faf0b2e5
LY		 39
40 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
41 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
42 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
43
44 /*
45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
46 * chained indirect PRDEs upto a max count of 63.
47 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
48 * be setup as an indirect descriptor, pointing to it's next
49 * (contigious) PRDE. Though chained indirect PRDE arrays are
50 * supported,it will be more efficient to use a direct PRDT and
51 * a single chain/link to indirect PRDE array/PRDT.
52 */
53
54 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
56 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
57 SATA_FSL_CMD_DESC_RSRVD = 16,
58
59 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
60 SATA_FSL_CMD_DESC_SFIS_SZ +
61 SATA_FSL_CMD_DESC_ACMD_SZ +
62 SATA_FSL_CMD_DESC_RSRVD +
63 SATA_FSL_MAX_PRD * 16),
64
65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
66 (SATA_FSL_CMD_DESC_CFIS_SZ +
67 SATA_FSL_CMD_DESC_SFIS_SZ +
68 SATA_FSL_CMD_DESC_ACMD_SZ +
69 SATA_FSL_CMD_DESC_RSRVD),
70
71 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
72 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
73 SATA_FSL_CMD_DESC_AR_SZ),
74
75 /*
76 * MPC8315 has two SATA controllers, SATA1 & SATA2
77 * (one port per controller)
78 * MPC837x has 2/4 controllers, one port per controller
79 */
80
81 SATA_FSL_MAX_PORTS = 1,
82
83 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
84};
85
86/*
87* Host Controller command register set - per port
88*/
89enum {
90 CQ = 0,
91 CA = 8,
92 CC = 0x10,
93 CE = 0x18,
94 DE = 0x20,
95 CHBA = 0x24,
96 HSTATUS = 0x28,
97 HCONTROL = 0x2C,
98 CQPMP = 0x30,
99 SIGNATURE = 0x34,
100 ICC = 0x38,
101
102 /*
103 * Host Status Register (HStatus) bitdefs
104 */
105 ONLINE = (1 << 31),
106 GOING_OFFLINE = (1 << 30),
107 BIST_ERR = (1 << 29),
108
109 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
110 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
111 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
112 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
113 FATAL_ERR_DATA_OVERRUN = (1 << 12),
114 FATAL_ERR_CRC_ERR_TX = (1 << 11),
115 FATAL_ERR_CRC_ERR_RX = (1 << 10),
116 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
117 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
118
119 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
120 FATAL_ERR_PARITY_ERR_TX |
121 FATAL_ERR_PARITY_ERR_RX |
122 FATAL_ERR_DATA_UNDERRUN |
123 FATAL_ERR_DATA_OVERRUN |
124 FATAL_ERR_CRC_ERR_TX |
125 FATAL_ERR_CRC_ERR_RX |
126 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
127
128 INT_ON_FATAL_ERR = (1 << 5),
129 INT_ON_PHYRDY_CHG = (1 << 4),
130
131 INT_ON_SIGNATURE_UPDATE = (1 << 3),
132 INT_ON_SNOTIFY_UPDATE = (1 << 2),
133 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
134 INT_ON_CMD_COMPLETE = 1,
135
136 INT_ON_ERROR = INT_ON_FATAL_ERR |
137 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
138
139 /*
140 * Host Control Register (HControl) bitdefs
141 */
142 HCONTROL_ONLINE_PHY_RST = (1 << 31),
143 HCONTROL_FORCE_OFFLINE = (1 << 30),
144 HCONTROL_PARITY_PROT_MOD = (1 << 14),
145 HCONTROL_DPATH_PARITY = (1 << 12),
146 HCONTROL_SNOOP_ENABLE = (1 << 10),
147 HCONTROL_PMP_ATTACHED = (1 << 9),
148 HCONTROL_COPYOUT_STATFIS = (1 << 8),
149 IE_ON_FATAL_ERR = (1 << 5),
150 IE_ON_PHYRDY_CHG = (1 << 4),
151 IE_ON_SIGNATURE_UPDATE = (1 << 3),
152 IE_ON_SNOTIFY_UPDATE = (1 << 2),
153 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
154 IE_ON_CMD_COMPLETE = 1,
155
156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
157 IE_ON_SIGNATURE_UPDATE |
158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
159
160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
161 DATA_SNOOP_ENABLE = (1 << 22),
162};
163
164/*
165 * SATA Superset Registers
166 */
167enum {
168 SSTATUS = 0,
169 SERROR = 4,
170 SCONTROL = 8,
171 SNOTIFY = 0xC,
172};
173
174/*
175 * Control Status Register Set
176 */
177enum {
178 TRANSCFG = 0,
179 TRANSSTATUS = 4,
180 LINKCFG = 8,
181 LINKCFG1 = 0xC,
182 LINKCFG2 = 0x10,
183 LINKSTATUS = 0x14,
184 LINKSTATUS1 = 0x18,
185 PHYCTRLCFG = 0x1C,
186 COMMANDSTAT = 0x20,
187};
188
189/* PHY (link-layer) configuration control */
190enum {
191 PHY_BIST_ENABLE = 0x01,
192};
193
194/*
195 * Command Header Table entry, i.e, command slot
196 * 4 Dwords per command slot, command header size == 64 Dwords.
197 */
198struct cmdhdr_tbl_entry {
199 u32 cda;
200 u32 prde_fis_len;
201 u32 ttl;
202 u32 desc_info;
203};
204
205/*
206 * Description information bitdefs
207 */
208enum {
209 VENDOR_SPECIFIC_BIST = (1 << 10),
210 CMD_DESC_SNOOP_ENABLE = (1 << 9),
211 FPDMA_QUEUED_CMD = (1 << 8),
212 SRST_CMD = (1 << 7),
213 BIST = (1 << 6),
214 ATAPI_CMD = (1 << 5),
215};
216
217/*
218 * Command Descriptor
219 */
220struct command_desc {
221 u8 cfis[8 * 4];
222 u8 sfis[8 * 4];
223 u8 acmd[4 * 4];
224 u8 fill[4 * 4];
225 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
226 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
227};
228
229/*
230 * Physical region table descriptor(PRD)
231 */
232
233struct prde {
234 u32 dba;
235 u8 fill[2 * 4];
236 u32 ddc_and_ext;
237};
238
239/*
240 * ata_port private data
241 * This is our per-port instance data.
242 */
243struct sata_fsl_port_priv {
244 struct cmdhdr_tbl_entry *cmdslot;
245 dma_addr_t cmdslot_paddr;
246 struct command_desc *cmdentry;
247 dma_addr_t cmdentry_paddr;
248
249 /*
250 * SATA FSL controller has a Status FIS which should contain the
251 * received D2H FIS & taskfile registers. This SFIS is present in
252 * the command descriptor, and to have a ready reference to it,
253 * we are caching it here, quite similar to what is done in H/W on
254 * AHCI compliant devices by copying taskfile fields to a 32-bit
255 * register.
256 */
257
258 struct ata_taskfile tf;
259};
260
261/*
262 * ata_port->host_set private data
263 */
264struct sata_fsl_host_priv {
265 void __iomem *hcr_base;
266 void __iomem *ssr_base;
267 void __iomem *csr_base;
79b3edc9 268 int irq;
faf0b2e5
LY		 269};
270
271static inline unsigned int sata_fsl_tag(unsigned int tag,
272 void __iomem * hcr_base)
273{
274 /* We let libATA core do actual (queue) tag allocation */
275
276 /* all non NCQ/queued commands should have tag#0 */
277 if (ata_tag_internal(tag)) {
278 DPRINTK("mapping internal cmds to tag#0\n");
279 return 0;
280 }
281
282 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
283 DPRINTK("tag %d invalid : out of range\n", tag);
284 return 0;
285 }
286
287 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
288 DPRINTK("tag %d invalid : in use!!\n", tag);
289 return 0;
290 }
291
292 return tag;
293}
294
295static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
296 unsigned int tag, u32 desc_info,
297 u32 data_xfer_len, u8 num_prde,
298 u8 fis_len)
299{
300 dma_addr_t cmd_descriptor_address;
301
302 cmd_descriptor_address = pp->cmdentry_paddr +
303 tag * SATA_FSL_CMD_DESC_SIZE;
304
305 /* NOTE: both data_xfer_len & fis_len are Dword counts */
306
307 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
308 pp->cmdslot[tag].prde_fis_len =
309 cpu_to_le32((num_prde << 16) | (fis_len << 2));
310 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
311 pp->cmdslot[tag].desc_info = cpu_to_le32((desc_info | (tag & 0x1F)));
312
313 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
314 pp->cmdslot[tag].cda,
315 pp->cmdslot[tag].prde_fis_len,
316 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
317
318}
319
320static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
321 u32 * ttl, dma_addr_t cmd_desc_paddr)
322{
323 struct scatterlist *sg;
324 unsigned int num_prde = 0;
325 u32 ttl_dwords = 0;
326
327 /*
328 * NOTE : direct & indirect prdt's are contigiously allocated
329 */
330 struct prde *prd = (struct prde *)&((struct command_desc *)
331 cmd_desc)->prdt;
332
333 struct prde *prd_ptr_to_indirect_ext = NULL;
334 unsigned indirect_ext_segment_sz = 0;
335 dma_addr_t indirect_ext_segment_paddr;
336
337 VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd);
338
339 indirect_ext_segment_paddr = cmd_desc_paddr +
340 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
341
342 ata_for_each_sg(sg, qc) {
343 dma_addr_t sg_addr = sg_dma_address(sg);
344 u32 sg_len = sg_dma_len(sg);
345
346 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
347 sg_addr, sg_len);
348
349 /* warn if each s/g element is not dword aligned */
350 if (sg_addr & 0x03)
351 ata_port_printk(qc->ap, KERN_ERR,
352 "s/g addr unaligned : 0x%x\n", sg_addr);
353 if (sg_len & 0x03)
354 ata_port_printk(qc->ap, KERN_ERR,
355 "s/g len unaligned : 0x%x\n", sg_len);
356
357 if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) &&
a2962dd0 358 (qc->n_iter + 1 != qc->n_elem)) {
faf0b2e5
LY		 359 VPRINTK("setting indirect prde\n");
360 prd_ptr_to_indirect_ext = prd;
361 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
362 indirect_ext_segment_sz = 0;
363 ++prd;
364 ++num_prde;
365 }
366
367 ttl_dwords += sg_len;
368 prd->dba = cpu_to_le32(sg_addr);
369 prd->ddc_and_ext =
370 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
371
372 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
373 ttl_dwords, prd->dba, prd->ddc_and_ext);
374
375 ++num_prde;
376 ++prd;
377 if (prd_ptr_to_indirect_ext)
378 indirect_ext_segment_sz += sg_len;
379 }
380
381 if (prd_ptr_to_indirect_ext) {
382 /* set indirect extension flag along with indirect ext. size */
383 prd_ptr_to_indirect_ext->ddc_and_ext =
384 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
385 DATA_SNOOP_ENABLE |
386 (indirect_ext_segment_sz & ~0x03)));
387 }
388
389 *ttl = ttl_dwords;
390 return num_prde;
391}
392
393static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
394{
395 struct ata_port *ap = qc->ap;
396 struct sata_fsl_port_priv *pp = ap->private_data;
397 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
398 void __iomem *hcr_base = host_priv->hcr_base;
399 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
400 struct command_desc *cd;
401 u32 desc_info = CMD_DESC_SNOOP_ENABLE;
402 u32 num_prde = 0;
403 u32 ttl_dwords = 0;
404 dma_addr_t cd_paddr;
405
406 cd = (struct command_desc *)pp->cmdentry + tag;
407 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
408
409 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) & cd->cfis);
410
411 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
412 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
413
414 if (qc->tf.protocol == ATA_PROT_NCQ) {
415 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
416 cd->cfis[3], cd->cfis[11]);
417 }
418
419 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
420 if (is_atapi_taskfile(&qc->tf)) {
421 desc_info |= ATAPI_CMD;
422 memset((void *)&cd->acmd, 0, 32);
423 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
424 }
425
426 if (qc->flags & ATA_QCFLAG_DMAMAP)
427 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
428 &ttl_dwords, cd_paddr);
429
430 if (qc->tf.protocol == ATA_PROT_NCQ)
431 desc_info |= FPDMA_QUEUED_CMD;
432
433 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
434 num_prde, 5);
435
436 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
437 desc_info, ttl_dwords, num_prde);
438}
439
440static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
441{
442 struct ata_port *ap = qc->ap;
443 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
444 void __iomem *hcr_base = host_priv->hcr_base;
445 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
446
447 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
448 ioread32(CQ + hcr_base),
449 ioread32(CA + hcr_base),
450 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
451
452 /* Simply queue command to the controller/device */
453 iowrite32(1 << tag, CQ + hcr_base);
454
455 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
456 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
457
458 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
459 ioread32(CE + hcr_base),
460 ioread32(DE + hcr_base),
461 ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base));
462
463 return 0;
464}
465
466static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
467 u32 val)
468{
469 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
470 void __iomem *ssr_base = host_priv->ssr_base;
471 unsigned int sc_reg;
472
473 switch (sc_reg_in) {
474 case SCR_STATUS:
475 sc_reg = 0;
476 break;
477 case SCR_ERROR:
478 sc_reg = 1;
479 break;
480 case SCR_CONTROL:
481 sc_reg = 2;
482 break;
483 case SCR_ACTIVE:
484 sc_reg = 3;
485 break;
486 default:
487 return -EINVAL;
488 }
489
490 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
491
492 iowrite32(val, (void __iomem *)ssr_base + (sc_reg * 4));
493 return 0;
494}
495
496static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
497 u32 *val)
498{
499 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
500 void __iomem *ssr_base = host_priv->ssr_base;
501 unsigned int sc_reg;
502
503 switch (sc_reg_in) {
504 case SCR_STATUS:
505 sc_reg = 0;
506 break;
507 case SCR_ERROR:
508 sc_reg = 1;
509 break;
510 case SCR_CONTROL:
511 sc_reg = 2;
512 break;
513 case SCR_ACTIVE:
514 sc_reg = 3;
515 break;
516 default:
517 return -EINVAL;
518 }
519
520 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
521
522 *val = ioread32((void __iomem *)ssr_base + (sc_reg * 4));
523 return 0;
524}
525
526static void sata_fsl_freeze(struct ata_port *ap)
527{
528 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
529 void __iomem *hcr_base = host_priv->hcr_base;
530 u32 temp;
531
532 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
533 ioread32(CQ + hcr_base),
534 ioread32(CA + hcr_base),
535 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
536 VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT));
537
538 /* disable interrupts on the controller/port */
539 temp = ioread32(hcr_base + HCONTROL);
540 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
541
542 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
543 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
544}
545
546static void sata_fsl_thaw(struct ata_port *ap)
547{
548 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
549 void __iomem *hcr_base = host_priv->hcr_base;
550 u32 temp;
551
552 /* ack. any pending IRQs for this controller/port */
553 temp = ioread32(hcr_base + HSTATUS);
554
555 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
556
557 if (temp & 0x3F)
558 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
559
560 /* enable interrupts on the controller/port */
561 temp = ioread32(hcr_base + HCONTROL);
562 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
563
564 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
565 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
566}
567
568/*
569 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
570 */
571static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
572 *qc,
573 struct ata_port *ap)
574{
575 struct sata_fsl_port_priv *pp = ap->private_data;
576 u8 fis[6 * 4];
577 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
578 void __iomem *hcr_base = host_priv->hcr_base;
579 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
580 struct command_desc *cd;
581
582 cd = pp->cmdentry + tag;
583
584 memcpy(fis, &cd->sfis, 6 * 4); /* should we use memcpy_from_io() */
585 ata_tf_from_fis(fis, &pp->tf);
586}
587
588static u8 sata_fsl_check_status(struct ata_port *ap)
589{
590 struct sata_fsl_port_priv *pp = ap->private_data;
591
592 return pp->tf.command;
593}
594
595static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
596{
597 struct sata_fsl_port_priv *pp = ap->private_data;
598
599 *tf = pp->tf;
600}
601
602static int sata_fsl_port_start(struct ata_port *ap)
603{
604 struct device *dev = ap->host->dev;
605 struct sata_fsl_port_priv *pp;
606 int retval;
607 void *mem;
608 dma_addr_t mem_dma;
609 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
610 void __iomem *hcr_base = host_priv->hcr_base;
611 u32 temp;
612
613 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
614 if (!pp)
615 return -ENOMEM;
616
617 /*
618 * allocate per command dma alignment pad buffer, which is used
619 * internally by libATA to ensure that all transfers ending on
620 * unaligned boundaries are padded, to align on Dword boundaries
621 */
622 retval = ata_pad_alloc(ap, dev);
623 if (retval) {
624 kfree(pp);
625 return retval;
626 }
627
628 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
629 GFP_KERNEL);
630 if (!mem) {
631 ata_pad_free(ap, dev);
632 kfree(pp);
633 return -ENOMEM;
634 }
635 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
636
637 pp->cmdslot = mem;
638 pp->cmdslot_paddr = mem_dma;
639
640 mem += SATA_FSL_CMD_SLOT_SIZE;
641 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
642
643 pp->cmdentry = mem;
644 pp->cmdentry_paddr = mem_dma;
645
646 ap->private_data = pp;
647
648 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
649 pp->cmdslot_paddr, pp->cmdentry_paddr);
650
651 /* Now, update the CHBA register in host controller cmd register set */
652 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
653
654 /*
655 * Now, we can bring the controller on-line & also initiate
656 * the COMINIT sequence, we simply return here and the boot-probing
657 * & device discovery process is re-initiated by libATA using a
658 * Softreset EH (dummy) session. Hence, boot probing and device
659 * discovey will be part of sata_fsl_softreset() callback.
660 */
661
662 temp = ioread32(hcr_base + HCONTROL);
663 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
664
665 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
666 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
667 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
668
669 /*
670 * Workaround for 8315DS board 3gbps link-up issue,
671 * currently limit SATA port to GEN1 speed
672 */
673 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
674 temp &= ~(0xF << 4);
675 temp |= (0x1 << 4);
676 sata_fsl_scr_write(ap, SCR_CONTROL, temp);
677
678 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
679 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
680 temp);
681
682 return 0;
683}
684
685static void sata_fsl_port_stop(struct ata_port *ap)
686{
687 struct device *dev = ap->host->dev;
688 struct sata_fsl_port_priv *pp = ap->private_data;
689 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
690 void __iomem *hcr_base = host_priv->hcr_base;
691 u32 temp;
692
693 /*
694 * Force host controller to go off-line, aborting current operations
695 */
696 temp = ioread32(hcr_base + HCONTROL);
697 temp &= ~HCONTROL_ONLINE_PHY_RST;
698 temp |= HCONTROL_FORCE_OFFLINE;
699 iowrite32(temp, hcr_base + HCONTROL);
700
701 /* Poll for controller to go offline - should happen immediately */
702 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
703
704 ap->private_data = NULL;
705 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
706 pp->cmdslot, pp->cmdslot_paddr);
707
708 ata_pad_free(ap, dev);
709 kfree(pp);
710}
711
712static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
713{
714 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
715 void __iomem *hcr_base = host_priv->hcr_base;
716 struct ata_taskfile tf;
717 u32 temp;
718
719 temp = ioread32(hcr_base + SIGNATURE);
720
721 VPRINTK("raw sig = 0x%x\n", temp);
722 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
723 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
724
725 tf.lbah = (temp >> 24) & 0xff;
726 tf.lbam = (temp >> 16) & 0xff;
727 tf.lbal = (temp >> 8) & 0xff;
728 tf.nsect = temp & 0xff;
729
730 return ata_dev_classify(&tf);
731}
732
1bf617b7 733static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
faf0b2e5
LY		 734 unsigned long deadline)
735{
1bf617b7 736 struct ata_port *ap = link->ap;
faf0b2e5
LY		 737 struct sata_fsl_port_priv *pp = ap->private_data;
738 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
739 void __iomem *hcr_base = host_priv->hcr_base;
740 u32 temp;
741 struct ata_taskfile tf;
742 u8 *cfis;
743 u32 Serror;
744 int i = 0;
745 struct ata_queued_cmd qc;
746 u8 *buf;
747 dma_addr_t dma_address;
748 struct scatterlist *sg;
749 unsigned long start_jiffies;
750
751 DPRINTK("in xx_softreset\n");
752
753try_offline_again:
754 /*
755 * Force host controller to go off-line, aborting current operations
756 */
757 temp = ioread32(hcr_base + HCONTROL);
758 temp &= ~HCONTROL_ONLINE_PHY_RST;
759 iowrite32(temp, hcr_base + HCONTROL);
760
761 /* Poll for controller to go offline */
762 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
763
764 if (temp & ONLINE) {
765 ata_port_printk(ap, KERN_ERR,
766 "Softreset failed, not off-lined %d\n", i);
767
768 /*
769 * Try to offline controller atleast twice
770 */
771 i++;
772 if (i == 2)
773 goto err;
774 else
775 goto try_offline_again;
776 }
777
778 DPRINTK("softreset, controller off-lined\n");
779 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
780 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
781
782 /*
783 * PHY reset should remain asserted for atleast 1ms
784 */
785 msleep(1);
786
787 /*
788 * Now, bring the host controller online again, this can take time
789 * as PHY reset and communication establishment, 1st D2H FIS and
790 * device signature update is done, on safe side assume 500ms
791 * NOTE : Host online status may be indicated immediately!!
792 */
793
794 temp = ioread32(hcr_base + HCONTROL);
795 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
796 iowrite32(temp, hcr_base + HCONTROL);
797
798 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
799
800 if (!(temp & ONLINE)) {
801 ata_port_printk(ap, KERN_ERR,
802 "Softreset failed, not on-lined\n");
803 goto err;
804 }
805
806 DPRINTK("softreset, controller off-lined & on-lined\n");
807 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
808 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
809
810 /*
811 * First, wait for the PHYRDY change to occur before waiting for
812 * the signature, and also verify if SStatus indicates device
813 * presence
814 */
815
816 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
1bf617b7 817 if ((!(temp & 0x10)) || ata_link_offline(link)) {
faf0b2e5
LY		 818 ata_port_printk(ap, KERN_WARNING,
819 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
820 ioread32(hcr_base + HSTATUS));
821 goto err;
822 }
823
824 /*
825 * Wait for the first D2H from device,i.e,signature update notification
826 */
827 start_jiffies = jiffies;
828 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
829 500, jiffies_to_msecs(deadline - start_jiffies));
830
831 if ((temp & 0xFF) != 0x18) {
832 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
833 goto err;
834 } else {
835 ata_port_printk(ap, KERN_INFO,
836 "Signature Update detected @ %d msecs\n",
837 jiffies_to_msecs(jiffies - start_jiffies));
838 }
839
840 /*
841 * Send a device reset (SRST) explicitly on command slot #0
842 * Check : will the command queue (reg) be cleared during offlining ??
843 * Also we will be online only if Phy commn. has been established
844 * and device presence has been detected, therefore if we have
845 * reached here, we can send a command to the target device
846 */
847
1bf617b7 848 if (link->sactive)
faf0b2e5
LY		 849 goto skip_srst_do_ncq_error_handling;
850
851 DPRINTK("Sending SRST/device reset\n");
852
1bf617b7 853 ata_tf_init(link->device, &tf);
faf0b2e5
LY		 854 cfis = (u8 *) & pp->cmdentry->cfis;
855
856 /* device reset/SRST is a control register update FIS, uses tag0 */
857 sata_fsl_setup_cmd_hdr_entry(pp, 0,
858 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
859
860 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
861 ata_tf_to_fis(&tf, 0, 0, cfis);
862
863 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
864 cfis[0], cfis[1], cfis[2], cfis[3]);
865
866 /*
867 * Queue SRST command to the controller/device, ensure that no
868 * other commands are active on the controller/device
869 */
870
871 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
872 ioread32(CQ + hcr_base),
873 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
874
875 iowrite32(0xFFFF, CC + hcr_base);
876 iowrite32(1, CQ + hcr_base);
877
878 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
879 if (temp & 0x1) {
880 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
881
882 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
883 ioread32(CQ + hcr_base),
884 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
885
886 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
887
888 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
889 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
890 DPRINTK("Serror = 0x%x\n", Serror);
891 goto err;
892 }
893
894 msleep(1);
895
896 /*
897 * SATA device enters reset state after receving a Control register
898 * FIS with SRST bit asserted and it awaits another H2D Control reg.
899 * FIS with SRST bit cleared, then the device does internal diags &
900 * initialization, followed by indicating it's initialization status
901 * using ATA signature D2H register FIS to the host controller.
902 */
903
904 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
905
906 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
907 ata_tf_to_fis(&tf, 0, 0, cfis);
908
909 iowrite32(1, CQ + hcr_base);
910 msleep(150); /* ?? */
911
912 /*
913 * The above command would have signalled an interrupt on command
914 * complete, which needs special handling, by clearing the Nth
915 * command bit of the CCreg
916 */
917 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
918 goto check_device_signature;
919
920skip_srst_do_ncq_error_handling:
921
922 VPRINTK("Sending read log ext(10h) command\n");
923
924 memset(&qc, 0, sizeof(struct ata_queued_cmd));
1bf617b7 925 ata_tf_init(link->device, &tf);
faf0b2e5
LY		 926
927 tf.command = ATA_CMD_READ_LOG_EXT;
928 tf.lbal = ATA_LOG_SATA_NCQ;
929 tf.nsect = 1;
930 tf.hob_nsect = 0;
931 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_LBA48 | ATA_TFLAG_DEVICE;
932 tf.protocol = ATA_PROT_PIO;
933
934 qc.tag = ATA_TAG_INTERNAL;
935 qc.scsicmd = NULL;
936 qc.ap = ap;
1bf617b7 937 qc.dev = link->device;
faf0b2e5
LY		 938
939 qc.tf = tf;
940 qc.flags |= ATA_QCFLAG_RESULT_TF;
941 qc.dma_dir = DMA_FROM_DEVICE;
942
943 buf = ap->sector_buf;
944 ata_sg_init_one(&qc, buf, 1 * ATA_SECT_SIZE);
945
946 /*
947 * Need to DMA-map the memory buffer associated with the command
948 */
949
950 sg = qc.__sg;
951 dma_address = dma_map_single(ap->dev, qc.buf_virt,
952 sg->length, DMA_FROM_DEVICE);
953
954 sg_dma_address(sg) = dma_address;
955 sg_dma_len(sg) = sg->length;
956
957 VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address, sg->length);
958
959 sata_fsl_qc_prep(&qc);
960 sata_fsl_qc_issue(&qc);
961
962 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
963 if (temp & 0x1) {
964 VPRINTK("READ_LOG_EXT_10H issue failed\n");
965
966 VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
967 ioread32(CQ + hcr_base),
968 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
969
970 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
971
972 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
973 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
974 VPRINTK("Serror = 0x%x\n", Serror);
975 goto err;
976 }
977
978 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
979
980 check_device_signature:
981
982 DPRINTK("SATA FSL : Now checking device signature\n");
983
984 *class = ATA_DEV_NONE;
985
986 /* Verify if SStatus indicates device presence */
1bf617b7 987 if (ata_link_online(link)) {
faf0b2e5
LY		 988 /*
989 * if we are here, device presence has been detected,
990 * 1st D2H FIS would have been received, but sfis in
991 * command desc. is not updated, but signature register
992 * would have been updated
993 */
994
995 *class = sata_fsl_dev_classify(ap);
996
997 DPRINTK("class = %d\n", *class);
998 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
999 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1000 }
1001
1002 return 0;
1003
1004err:
1005 return -EIO;
1006}
1007
1008static int sata_fsl_hardreset(struct ata_port *ap, unsigned int *class,
1009 unsigned long deadline)
1010{
1011 int retval;
1012
1013 retval = sata_std_hardreset(ap, class, deadline);
1014
1015 DPRINTK("SATA FSL : in xx_hardreset, retval = 0x%d\n", retval);
1016
1017 return retval;
1018}
1019
1020static void sata_fsl_error_handler(struct ata_port *ap)
1021{
1022
1023 DPRINTK("in xx_error_handler\n");
1024
1025 /* perform recovery */
1026 ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_fsl_hardreset,
1027 ata_std_postreset);
1028}
1029
1030static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1031{
1032 if (qc->flags & ATA_QCFLAG_FAILED)
1033 qc->err_mask |= AC_ERR_OTHER;
1034
1035 if (qc->err_mask) {
1036 /* make DMA engine forget about the failed command */
1037
1038 }
1039}
1040
1041static void sata_fsl_irq_clear(struct ata_port *ap)
1042{
1043 /* unused */
1044}
1045
1046static void sata_fsl_error_intr(struct ata_port *ap)
1047{
1bf617b7
LY		 1048 struct ata_link *link = &ap->link;
1049 struct ata_eh_info *ehi = &link->eh_info;
faf0b2e5
LY		 1050 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1051 void __iomem *hcr_base = host_priv->hcr_base;
1052 u32 hstatus, dereg, cereg = 0, SError = 0;
1053 unsigned int err_mask = 0, action = 0;
1054 struct ata_queued_cmd *qc;
1055 int freeze = 0;
1056
1057 hstatus = ioread32(hcr_base + HSTATUS);
1058 cereg = ioread32(hcr_base + CE);
1059
1060 ata_ehi_clear_desc(ehi);
1061
1062 /*
1063 * Handle & Clear SError
1064 */
1065
1066 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1067 if (unlikely(SError & 0xFFFF0000)) {
1068 sata_fsl_scr_write(ap, SCR_ERROR, SError);
1069 err_mask |= AC_ERR_ATA_BUS;
1070 }
1071
1072 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1073 hstatus, cereg, ioread32(hcr_base + DE), SError);
1074
1075 /* handle single device errors */
1076 if (cereg) {
1077 /*
1078 * clear the command error, also clears queue to the device
1079 * in error, and we can (re)issue commands to this device.
1080 * When a device is in error all commands queued into the
1081 * host controller and at the device are considered aborted
1082 * and the queue for that device is stopped. Now, after
1083 * clearing the device error, we can issue commands to the
1084 * device to interrogate it to find the source of the error.
1085 */
1086 dereg = ioread32(hcr_base + DE);
1087 iowrite32(dereg, hcr_base + DE);
1088 iowrite32(cereg, hcr_base + CE);
1089
1090 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1091 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1092 /*
1093 * We should consider this as non fatal error, and TF must
1094 * be updated as done below.
1095 */
1096
1097 err_mask |= AC_ERR_DEV;
1098 }
1099
1100 /* handle fatal errors */
1101 if (hstatus & FATAL_ERROR_DECODE) {
1102 err_mask |= AC_ERR_ATA_BUS;
1103 action |= ATA_EH_SOFTRESET;
1104 /* how will fatal error interrupts be completed ?? */
1105 freeze = 1;
1106 }
1107
1108 /* Handle PHYRDY change notification */
1109 if (hstatus & INT_ON_PHYRDY_CHG) {
1110 DPRINTK("SATA FSL: PHYRDY change indication\n");
1111
1112 /* Setup a soft-reset EH action */
1113 ata_ehi_hotplugged(ehi);
1114 freeze = 1;
1115 }
1116
1117 /* record error info */
1bf617b7 1118 qc = ata_qc_from_tag(ap, link->active_tag);
faf0b2e5
LY		 1119
1120 if (qc) {
1121 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1122 qc->err_mask |= err_mask;
1123 } else
1124 ehi->err_mask |= err_mask;
1125
1126 ehi->action |= action;
1127 ehi->serror |= SError;
1128
1129 /* freeze or abort */
1130 if (freeze)
1131 ata_port_freeze(ap);
1132 else
1133 ata_port_abort(ap);
1134}
1135
1136static void sata_fsl_qc_complete(struct ata_queued_cmd *qc)
1137{
1138 if (qc->flags & ATA_QCFLAG_RESULT_TF) {
1139 DPRINTK("xx_qc_complete called\n");
1140 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1141 }
1142}
1143
1144static void sata_fsl_host_intr(struct ata_port *ap)
1145{
1bf617b7 1146 struct ata_link *link = &ap->link;
faf0b2e5
LY		 1147 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1148 void __iomem *hcr_base = host_priv->hcr_base;
1149 u32 hstatus, qc_active = 0;
1150 struct ata_queued_cmd *qc;
1151 u32 SError;
1152
1153 hstatus = ioread32(hcr_base + HSTATUS);
1154
1155 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1156
1157 if (unlikely(SError & 0xFFFF0000)) {
1158 DPRINTK("serror @host_intr : 0x%x\n", SError);
1159 sata_fsl_error_intr(ap);
1160
1161 }
1162
1163 if (unlikely(hstatus & INT_ON_ERROR)) {
1164 DPRINTK("error interrupt!!\n");
1165 sata_fsl_error_intr(ap);
1166 return;
1167 }
1168
1bf617b7 1169 if (link->sactive) { /* only true for NCQ commands */
faf0b2e5
LY		 1170 int i;
1171 /* Read command completed register */
1172 qc_active = ioread32(hcr_base + CC);
1173 /* clear CC bit, this will also complete the interrupt */
1174 iowrite32(qc_active, hcr_base + CC);
1175
1176 DPRINTK("Status of all queues :\n");
1177 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1178 qc_active, ioread32(hcr_base + CA),
1179 ioread32(hcr_base + CE));
1180
1181 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1182 if (qc_active & (1 << i)) {
1183 qc = ata_qc_from_tag(ap, i);
1184 if (qc) {
1185 sata_fsl_qc_complete(qc);
1186 ata_qc_complete(qc);
1187 }
1188 DPRINTK
1189 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1190 i, ioread32(hcr_base + CC),
1191 ioread32(hcr_base + CA));
1192 }
1193 }
1194 return;
1195
1196 } else if (ap->qc_active) {
1197 iowrite32(1, hcr_base + CC);
1bf617b7 1198 qc = ata_qc_from_tag(ap, link->active_tag);
faf0b2e5
LY		 1199
1200 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1bf617b7 1201 link->active_tag, ioread32(hcr_base + CC));
faf0b2e5
LY		 1202
1203 if (qc) {
1204 sata_fsl_qc_complete(qc);
1205 ata_qc_complete(qc);
1206 }
1207 } else {
1208 /* Spurious Interrupt!! */
1209 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1210 ioread32(hcr_base + CC));
1211 return;
1212 }
1213}
1214
1215static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1216{
1217 struct ata_host *host = dev_instance;
1218 struct sata_fsl_host_priv *host_priv = host->private_data;
1219 void __iomem *hcr_base = host_priv->hcr_base;
1220 u32 interrupt_enables;
1221 unsigned handled = 0;
1222 struct ata_port *ap;
1223
1224 /* ack. any pending IRQs for this controller/port */
1225 interrupt_enables = ioread32(hcr_base + HSTATUS);
1226 interrupt_enables &= 0x3F;
1227
1228 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1229
1230 if (!interrupt_enables)
1231 return IRQ_NONE;
1232
1233 spin_lock(&host->lock);
1234
1235 /* Assuming one port per host controller */
1236
1237 ap = host->ports[0];
1238 if (ap) {
1239 sata_fsl_host_intr(ap);
1240 } else {
1241 dev_printk(KERN_WARNING, host->dev,
1242 "interrupt on disabled port 0\n");
1243 }
1244
1245 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1246 handled = 1;
1247
1248 spin_unlock(&host->lock);
1249
1250 return IRQ_RETVAL(handled);
1251}
1252
1253/*
1254 * Multiple ports are represented by multiple SATA controllers with
1255 * one port per controller
1256 */
1257static int sata_fsl_init_controller(struct ata_host *host)
1258{
1259 struct sata_fsl_host_priv *host_priv = host->private_data;
1260 void __iomem *hcr_base = host_priv->hcr_base;
1261 u32 temp;
1262
1263 /*
1264 * NOTE : We cannot bring the controller online before setting
1265 * the CHBA, hence main controller initialization is done as
1266 * part of the port_start() callback
1267 */
1268
1269 /* ack. any pending IRQs for this controller/port */
1270 temp = ioread32(hcr_base + HSTATUS);
1271 if (temp & 0x3F)
1272 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1273
1274 /* Keep interrupts disabled on the controller */
1275 temp = ioread32(hcr_base + HCONTROL);
1276 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1277
1278 /* Disable interrupt coalescing control(icc), for the moment */
1279 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1280 iowrite32(0x01000000, hcr_base + ICC);
1281
1282 /* clear error registers, SError is cleared by libATA */
1283 iowrite32(0x00000FFFF, hcr_base + CE);
1284 iowrite32(0x00000FFFF, hcr_base + DE);
1285
1286 /* initially assuming no Port multiplier, set CQPMP to 0 */
1287 iowrite32(0x0, hcr_base + CQPMP);
1288
1289 /*
1290 * host controller will be brought on-line, during xx_port_start()
1291 * callback, that should also initiate the OOB, COMINIT sequence
1292 */
1293
1294 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1295 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1296
1297 return 0;
1298}
1299
1300/*
1301 * scsi mid-layer and libata interface structures
1302 */
1303static struct scsi_host_template sata_fsl_sht = {
1304 .module = THIS_MODULE,
1305 .name = "sata_fsl",
1306 .ioctl = ata_scsi_ioctl,
1307 .queuecommand = ata_scsi_queuecmd,
1308 .change_queue_depth = ata_scsi_change_queue_depth,
1309 .can_queue = SATA_FSL_QUEUE_DEPTH,
1310 .this_id = ATA_SHT_THIS_ID,
1311 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1312 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
1313 .emulated = ATA_SHT_EMULATED,
1314 .use_clustering = ATA_SHT_USE_CLUSTERING,
1315 .proc_name = "sata_fsl",
1316 .dma_boundary = ATA_DMA_BOUNDARY,
1317 .slave_configure = ata_scsi_slave_config,
1318 .slave_destroy = ata_scsi_slave_destroy,
1319 .bios_param = ata_std_bios_param,
1320#ifdef CONFIG_PM
1321 .suspend = ata_scsi_device_suspend,
1322 .resume = ata_scsi_device_resume,
1323#endif
1324};
1325
1326static const struct ata_port_operations sata_fsl_ops = {
faf0b2e5
LY		 1327 .check_status = sata_fsl_check_status,
1328 .check_altstatus = sata_fsl_check_status,
1329 .dev_select = ata_noop_dev_select,
1330
1331 .tf_read = sata_fsl_tf_read,
1332
1333 .qc_prep = sata_fsl_qc_prep,
1334 .qc_issue = sata_fsl_qc_issue,
1335 .irq_clear = sata_fsl_irq_clear,
faf0b2e5
LY		 1336
1337 .scr_read = sata_fsl_scr_read,
1338 .scr_write = sata_fsl_scr_write,
1339
1340 .freeze = sata_fsl_freeze,
1341 .thaw = sata_fsl_thaw,
1342 .error_handler = sata_fsl_error_handler,
1343 .post_internal_cmd = sata_fsl_post_internal_cmd,
1344
1345 .port_start = sata_fsl_port_start,
1346 .port_stop = sata_fsl_port_stop,
1347};
1348
1349static const struct ata_port_info sata_fsl_port_info[] = {
1350 {
1351 .flags = SATA_FSL_HOST_FLAGS,
1bf617b7 1352 .link_flags = SATA_FSL_HOST_LFLAGS,
faf0b2e5
LY		 1353 .pio_mask = 0x1f, /* pio 0-4 */
1354 .udma_mask = 0x7f, /* udma 0-6 */
1355 .port_ops = &sata_fsl_ops,
1356 },
1357};
1358
1359static int sata_fsl_probe(struct of_device *ofdev,
1360 const struct of_device_id *match)
1361{
1362 int retval = 0;
1363 void __iomem *hcr_base = NULL;
1364 void __iomem *ssr_base = NULL;
1365 void __iomem *csr_base = NULL;
1366 struct sata_fsl_host_priv *host_priv = NULL;
1367 struct resource *r;
1368 int irq;
1369 struct ata_host *host;
1370
1371 struct ata_port_info pi = sata_fsl_port_info[0];
1372 const struct ata_port_info *ppi[] = { &pi, NULL };
1373
1374 dev_printk(KERN_INFO, &ofdev->dev,
1375 "Sata FSL Platform/CSB Driver init\n");
1376
1377 r = kmalloc(sizeof(struct resource), GFP_KERNEL);
1378
1379 hcr_base = of_iomap(ofdev->node, 0);
1380 if (!hcr_base)
1381 goto error_exit_with_cleanup;
1382
1383 ssr_base = hcr_base + 0x100;
1384 csr_base = hcr_base + 0x140;
1385
1386 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1387 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1388 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1389
1390 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1391 if (!host_priv)
1392 goto error_exit_with_cleanup;
1393
1394 host_priv->hcr_base = hcr_base;
1395 host_priv->ssr_base = ssr_base;
1396 host_priv->csr_base = csr_base;
1397
1398 irq = irq_of_parse_and_map(ofdev->node, 0);
1399 if (irq < 0) {
1400 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1401 goto error_exit_with_cleanup;
1402 }
79b3edc9 1403 host_priv->irq = irq;
faf0b2e5
LY		 1404
1405 /* allocate host structure */
1406 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1407
1408 /* host->iomap is not used currently */
1409 host->private_data = host_priv;
1410
1411 /* setup port(s) */
1412
1413 host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base;
1414 host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base;
1415
1416 /* initialize host controller */
1417 sata_fsl_init_controller(host);
1418
1419 /*
1420 * Now, register with libATA core, this will also initiate the
1421 * device discovery process, invoking our port_start() handler &
1422 * error_handler() to execute a dummy Softreset EH session
1423 */
1424 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1425 &sata_fsl_sht);
1426
1427 dev_set_drvdata(&ofdev->dev, host);
1428
1429 return 0;
1430
1431error_exit_with_cleanup:
1432
1433 if (hcr_base)
1434 iounmap(hcr_base);
1435 if (host_priv)
1436 kfree(host_priv);
1437
1438 return retval;
1439}
1440
1441static int sata_fsl_remove(struct of_device *ofdev)
1442{
1443 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1444 struct sata_fsl_host_priv *host_priv = host->private_data;
1445
1446 ata_host_detach(host);
1447
1448 dev_set_drvdata(&ofdev->dev, NULL);
1449
79b3edc9 1450 irq_dispose_mapping(host_priv->irq);
faf0b2e5
LY		 1451 iounmap(host_priv->hcr_base);
1452 kfree(host_priv);
1453
1454 return 0;
1455}
1456
1457static struct of_device_id fsl_sata_match[] = {
1458 {
1459 .compatible = "fsl,mpc8315-sata",
1460 },
1461 {
1462 .compatible = "fsl,mpc8379-sata",
1463 },
1464 {},
1465};
1466
1467MODULE_DEVICE_TABLE(of, fsl_sata_match);
1468
1469static struct of_platform_driver fsl_sata_driver = {
1470 .name = "fsl-sata",
1471 .match_table = fsl_sata_match,
1472 .probe = sata_fsl_probe,
1473 .remove = sata_fsl_remove,
1474};
1475
1476static int __init sata_fsl_init(void)
1477{
1478 of_register_platform_driver(&fsl_sata_driver);
1479 return 0;
1480}
1481
1482static void __exit sata_fsl_exit(void)
1483{
1484 of_unregister_platform_driver(&fsl_sata_driver);
1485}
1486
1487MODULE_LICENSE("GPL");
1488MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1489MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1490MODULE_VERSION("1.10");
1491
1492module_init(sata_fsl_init);
1493module_exit(sata_fsl_exit);
Linux kernel - Deliverables
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