[deliverable/linux.git] / drivers / ata / sata_highbank.c

/*
 * Calxeda Highbank AHCI SATA platform driver
 * Copyright 2012 Calxeda, Inc.
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/ahci_platform.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>

#include "ahci.h"

#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
#define SERDES_CR_CTL			0x80a0
#define SERDES_CR_ADDR			0x80a1
#define SERDES_CR_DATA			0x80a2
#define CR_BUSY				0x0001
#define CR_START			0x0001
#define CR_WR_RDN			0x0002
#define CPHY_RX_INPUT_STS		0x2002
#define CPHY_SATA_OVERRIDE	 	0x4000
#define CPHY_OVERRIDE			0x2005
#define SPHY_LANE			0x100
#define SPHY_HALF_RATE			0x0001
#define CPHY_SATA_DPLL_MODE		0x0700
#define CPHY_SATA_DPLL_SHIFT		8
#define CPHY_SATA_DPLL_RESET		(1 << 11)
#define CPHY_PHY_COUNT			6
#define CPHY_LANE_COUNT			4
#define CPHY_PORT_COUNT			(CPHY_PHY_COUNT * CPHY_LANE_COUNT)

static DEFINE_SPINLOCK(cphy_lock);
/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
 * sata ports to their phys and then to their lanes within the phys
 */
struct phy_lane_info {
	void __iomem *phy_base;
	u8 lane_mapping;
	u8 phy_devs;
};
static struct phy_lane_info port_data[CPHY_PORT_COUNT];

static DEFINE_SPINLOCK(sgpio_lock);
#define SCLOCK				0
#define SLOAD				1
#define SDATA				2
#define SGPIO_PINS			3
#define SGPIO_PORTS			8

/* can be cast as an ahci_host_priv for compatibility with most functions */
struct ecx_plat_data {
	u32		n_ports;
	unsigned	sgpio_gpio[SGPIO_PINS];
	u32		sgpio_pattern;
	u32		port_to_sgpio[SGPIO_PORTS];
};

#define SGPIO_SIGNALS			3
#define ECX_ACTIVITY_BITS		0x300000
#define ECX_ACTIVITY_SHIFT		2
#define ECX_LOCATE_BITS			0x80000
#define ECX_LOCATE_SHIFT		1
#define ECX_FAULT_BITS			0x400000
#define ECX_FAULT_SHIFT			0
static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
				u32 shift)
{
	return 1 << (3 * pdata->port_to_sgpio[port] + shift);
}

static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
{
	if (state & ECX_ACTIVITY_BITS)
		pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
						ECX_ACTIVITY_SHIFT);
	else
		pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
						ECX_ACTIVITY_SHIFT);
	if (state & ECX_LOCATE_BITS)
		pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
						ECX_LOCATE_SHIFT);
	else
		pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
						ECX_LOCATE_SHIFT);
	if (state & ECX_FAULT_BITS)
		pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
						ECX_FAULT_SHIFT);
	else
		pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
						ECX_FAULT_SHIFT);
}

/*
 * Tell the LED controller that the signal has changed by raising the clock
 * line for 50 uS and then lowering it for 50 uS.
 */
static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
{
	gpio_set_value(pdata->sgpio_gpio[SCLOCK], 1);
	udelay(50);
	gpio_set_value(pdata->sgpio_gpio[SCLOCK], 0);
	udelay(50);
}

static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
					ssize_t size)
{
	struct ahci_host_priv *hpriv =  ap->host->private_data;
	struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data;
	struct ahci_port_priv *pp = ap->private_data;
	unsigned long flags;
	int pmp, i;
	struct ahci_em_priv *emp;
	u32 sgpio_out;

	/* get the slot number from the message */
	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
	if (pmp < EM_MAX_SLOTS)
		emp = &pp->em_priv[pmp];
	else
		return -EINVAL;

	if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
		return size;

	spin_lock_irqsave(&sgpio_lock, flags);
	ecx_parse_sgpio(pdata, ap->port_no, state);
	sgpio_out = pdata->sgpio_pattern;
	gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
	ecx_led_cycle_clock(pdata);
	gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
	/*
	 * bit-bang out the SGPIO pattern, by consuming a bit and then
	 * clocking it out.
	 */
	for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
		gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
		sgpio_out >>= 1;
		ecx_led_cycle_clock(pdata);
	}

	/* save off new led state for port/slot */
	emp->led_state = state;

	spin_unlock_irqrestore(&sgpio_lock, flags);
	return size;
}

static void highbank_set_em_messages(struct device *dev,
					struct ahci_host_priv *hpriv,
					struct ata_port_info *pi)
{
	struct device_node *np = dev->of_node;
	struct ecx_plat_data *pdata = hpriv->plat_data;
	int i;
	int err;

	for (i = 0; i < SGPIO_PINS; i++) {
		err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i);
		if (IS_ERR_VALUE(err))
			return;

		pdata->sgpio_gpio[i] = err;
		err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO");
		if (err) {
			pr_err("sata_highbank gpio_request %d failed: %d\n",
					i, err);
			return;
		}
		gpio_direction_output(pdata->sgpio_gpio[i], 1);
	}
	of_property_read_u32_array(np, "calxeda,led-order",
						pdata->port_to_sgpio,
						pdata->n_ports);

	/* store em_loc */
	hpriv->em_loc = 0;
	hpriv->em_buf_sz = 4;
	hpriv->em_msg_type = EM_MSG_TYPE_LED;
	pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY;
}

static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
{
	u32 data;
	u8 dev = port_data[sata_port].phy_devs;
	spin_lock(&cphy_lock);
	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
	spin_unlock(&cphy_lock);
	return data;
}

static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
{
	u8 dev = port_data[sata_port].phy_devs;
	spin_lock(&cphy_lock);
	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
	spin_unlock(&cphy_lock);
}

static void combo_phy_wait_for_ready(u8 sata_port)
{
	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
		udelay(5);
}

static u32 combo_phy_read(u8 sata_port, u32 addr)
{
	combo_phy_wait_for_ready(sata_port);
	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
	combo_phy_wait_for_ready(sata_port);
	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
}

static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
{
	combo_phy_wait_for_ready(sata_port);
	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);
}

static void highbank_cphy_disable_overrides(u8 sata_port)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp;
	if (unlikely(port_data[sata_port].phy_base == NULL))
		return;
	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	tmp &= ~CPHY_SATA_OVERRIDE;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
}

static void cphy_override_rx_mode(u8 sata_port, u32 val)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp;
	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	tmp &= ~CPHY_SATA_OVERRIDE;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= CPHY_SATA_OVERRIDE;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp &= ~CPHY_SATA_DPLL_MODE;
	tmp |= val << CPHY_SATA_DPLL_SHIFT;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= CPHY_SATA_DPLL_RESET;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp &= ~CPHY_SATA_DPLL_RESET;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	msleep(15);
}

static void highbank_cphy_override_lane(u8 sata_port)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp, k = 0;

	if (unlikely(port_data[sata_port].phy_base == NULL))
		return;
	do {
		tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
						lane * SPHY_LANE);
	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
	cphy_override_rx_mode(sata_port, 3);
}

static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
{
	struct device_node *sata_node = dev->of_node;
	int phy_count = 0, phy, port = 0;
	void __iomem *cphy_base[CPHY_PHY_COUNT];
	struct device_node *phy_nodes[CPHY_PHY_COUNT];
	memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
	memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT);

	do {
		u32 tmp;
		struct of_phandle_args phy_data;
		if (of_parse_phandle_with_args(sata_node,
				"calxeda,port-phys", "#phy-cells",
				port, &phy_data))
			break;
		for (phy = 0; phy < phy_count; phy++) {
			if (phy_nodes[phy] == phy_data.np)
				break;
		}
		if (phy_nodes[phy] == NULL) {
			phy_nodes[phy] = phy_data.np;
			cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
			if (cphy_base[phy] == NULL) {
				return 0;
			}
			phy_count += 1;
		}
		port_data[port].lane_mapping = phy_data.args[0];
		of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
		port_data[port].phy_devs = tmp;
		port_data[port].phy_base = cphy_base[phy];
		of_node_put(phy_data.np);
		port += 1;
	} while (port < CPHY_PORT_COUNT);
	return 0;
}

static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	u32 sstatus;
	int rc;
	int retry = 10;

	ahci_stop_engine(ap);

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	do {
		highbank_cphy_disable_overrides(link->ap->port_no);
		rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
		highbank_cphy_override_lane(link->ap->port_no);

		/* If the status is 1, we are connected, but the link did not
		 * come up. So retry resetting the link again.
		 */
		if (sata_scr_read(link, SCR_STATUS, &sstatus))
			break;
		if (!(sstatus & 0x3))
			break;
	} while (!online && retry--);

	ahci_start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	return rc;
}

static struct ata_port_operations ahci_highbank_ops = {
	.inherits		= &ahci_ops,
	.hardreset		= ahci_highbank_hardreset,
	.transmit_led_message   = ecx_transmit_led_message,
};

static const struct ata_port_info ahci_highbank_port_info = {
	.flags          = AHCI_FLAG_COMMON,
	.pio_mask       = ATA_PIO4,
	.udma_mask      = ATA_UDMA6,
	.port_ops       = &ahci_highbank_ops,
};

static struct scsi_host_template ahci_highbank_platform_sht = {
	AHCI_SHT("sata_highbank"),
};

static const struct of_device_id ahci_of_match[] = {
	{ .compatible = "calxeda,hb-ahci" },
	{},
};
MODULE_DEVICE_TABLE(of, ahci_of_match);

static int ahci_highbank_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ecx_plat_data *pdata;
	struct ata_host *host;
	struct resource *mem;
	int irq;
	int i;
	int rc;
	u32 n_ports;
	struct ata_port_info pi = ahci_highbank_port_info;
	const struct ata_port_info *ppi[] = { &pi, NULL };

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(dev, "no mmio space\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq <= 0) {
		dev_err(dev, "no irq\n");
		return -EINVAL;
	}

	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	if (!hpriv) {
		dev_err(dev, "can't alloc ahci_host_priv\n");
		return -ENOMEM;
	}
	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata) {
		dev_err(dev, "can't alloc ecx_plat_data\n");
		return -ENOMEM;
	}

	hpriv->flags |= (unsigned long)pi.private_data;

	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
	if (!hpriv->mmio) {
		dev_err(dev, "can't map %pR\n", mem);
		return -ENOMEM;
	}

	rc = highbank_initialize_phys(dev, hpriv->mmio);
	if (rc)
		return rc;


	ahci_save_initial_config(dev, hpriv, 0, 0);

	/* prepare host */
	if (hpriv->cap & HOST_CAP_NCQ)
		pi.flags |= ATA_FLAG_NCQ;

	if (hpriv->cap & HOST_CAP_PMP)
		pi.flags |= ATA_FLAG_PMP;

	/* CAP.NP sometimes indicate the index of the last enabled
	 * port, at other times, that of the last possible port, so
	 * determining the maximum port number requires looking at
	 * both CAP.NP and port_map.
	 */
	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));

	pdata->n_ports = n_ports;
	hpriv->plat_data = pdata;
	highbank_set_em_messages(dev, hpriv, &pi);

	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
	if (!host) {
		rc = -ENOMEM;
		goto err0;
	}

	host->private_data = hpriv;

	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
		host->flags |= ATA_HOST_PARALLEL_SCAN;

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];

		ata_port_desc(ap, "mmio %pR", mem);
		ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);

		/* set enclosure management message type */
		if (ap->flags & ATA_FLAG_EM)
			ap->em_message_type = hpriv->em_msg_type;

		/* disabled/not-implemented port */
		if (!(hpriv->port_map & (1 << i)))
			ap->ops = &ata_dummy_port_ops;
	}

	rc = ahci_reset_controller(host);
	if (rc)
		goto err0;

	ahci_init_controller(host);
	ahci_print_info(host, "platform");

	rc = ata_host_activate(host, irq, ahci_interrupt, 0,
					&ahci_highbank_platform_sht);
	if (rc)
		goto err0;

	return 0;
err0:
	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_highbank_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	u32 ctl;
	int rc;

	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
		dev_err(dev, "firmware update required for suspend/resume\n");
		return -EIO;
	}

	/*
	 * AHCI spec rev1.1 section 8.3.3:
	 * Software must disable interrupts prior to requesting a
	 * transition of the HBA to D3 state.
	 */
	ctl = readl(mmio + HOST_CTL);
	ctl &= ~HOST_IRQ_EN;
	writel(ctl, mmio + HOST_CTL);
	readl(mmio + HOST_CTL); /* flush */

	rc = ata_host_suspend(host, PMSG_SUSPEND);
	if (rc)
		return rc;

	return 0;
}

static int ahci_highbank_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	int rc;

	if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
		rc = ahci_reset_controller(host);
		if (rc)
			return rc;

		ahci_init_controller(host);
	}

	ata_host_resume(host);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
		  ahci_highbank_suspend, ahci_highbank_resume);

static struct platform_driver ahci_highbank_driver = {
	.remove = ata_platform_remove_one,
        .driver = {
                .name = "highbank-ahci",
                .owner = THIS_MODULE,
                .of_match_table = ahci_of_match,
                .pm = &ahci_highbank_pm_ops,
        },
	.probe = ahci_highbank_probe,
};

module_platform_driver(ahci_highbank_driver);

MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("sata:highbank");
Commit	Line	Data
8996b89d ML	1	/*
	2	* Calxeda Highbank AHCI SATA platform driver
	3	* Copyright 2012 Calxeda, Inc.
	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include <linux/kernel.h>
	20	#include <linux/gfp.h>
	21	#include <linux/module.h>
	22	#include <linux/init.h>
	23	#include <linux/types.h>
	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26	#include <linux/spinlock.h>
	27	#include <linux/device.h>
	28	#include <linux/of_device.h>
	29	#include <linux/of_address.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/libata.h>
	32	#include <linux/ahci_platform.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/delay.h>
	35	#include <linux/export.h>
d50b110f ML	36	#include <linux/gpio.h>
	37	#include <linux/of_gpio.h>
	38
8996b89d ML	39	#include "ahci.h"
	40
	41	#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) \| (((addr) >> 9) & 0x7f))
	42	#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
	43	#define SERDES_CR_CTL 0x80a0
	44	#define SERDES_CR_ADDR 0x80a1
	45	#define SERDES_CR_DATA 0x80a2
	46	#define CR_BUSY 0x0001
	47	#define CR_START 0x0001
	48	#define CR_WR_RDN 0x0002
	49	#define CPHY_RX_INPUT_STS 0x2002
	50	#define CPHY_SATA_OVERRIDE 0x4000
	51	#define CPHY_OVERRIDE 0x2005
	52	#define SPHY_LANE 0x100
	53	#define SPHY_HALF_RATE 0x0001
	54	#define CPHY_SATA_DPLL_MODE 0x0700
	55	#define CPHY_SATA_DPLL_SHIFT 8
	56	#define CPHY_SATA_DPLL_RESET (1 << 11)
	57	#define CPHY_PHY_COUNT 6
	58	#define CPHY_LANE_COUNT 4
	59	#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
	60
	61	static DEFINE_SPINLOCK(cphy_lock);
	62	/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
	63	* sata ports to their phys and then to their lanes within the phys
	64	*/
	65	struct phy_lane_info {
	66	void __iomem *phy_base;
	67	u8 lane_mapping;
	68	u8 phy_devs;
	69	};
	70	static struct phy_lane_info port_data[CPHY_PORT_COUNT];
	71
d50b110f ML	72	static DEFINE_SPINLOCK(sgpio_lock);
	73	#define SCLOCK 0
	74	#define SLOAD 1
	75	#define SDATA 2
	76	#define SGPIO_PINS 3
	77	#define SGPIO_PORTS 8
	78
	79	/* can be cast as an ahci_host_priv for compatibility with most functions */
	80	struct ecx_plat_data {
	81	u32 n_ports;
	82	unsigned sgpio_gpio[SGPIO_PINS];
	83	u32 sgpio_pattern;
	84	u32 port_to_sgpio[SGPIO_PORTS];
	85	};
	86
	87	#define SGPIO_SIGNALS 3
	88	#define ECX_ACTIVITY_BITS 0x300000
	89	#define ECX_ACTIVITY_SHIFT 2
	90	#define ECX_LOCATE_BITS 0x80000
	91	#define ECX_LOCATE_SHIFT 1
	92	#define ECX_FAULT_BITS 0x400000
	93	#define ECX_FAULT_SHIFT 0
	94	static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
	95	u32 shift)
	96	{
	97	return 1 << (3 * pdata->port_to_sgpio[port] + shift);
	98	}
	99
	100	static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
	101	{
	102	if (state & ECX_ACTIVITY_BITS)
	103	pdata->sgpio_pattern \|= sgpio_bit_shift(pdata, port,
	104	ECX_ACTIVITY_SHIFT);
	105	else
	106	pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
	107	ECX_ACTIVITY_SHIFT);
	108	if (state & ECX_LOCATE_BITS)
	109	pdata->sgpio_pattern \|= sgpio_bit_shift(pdata, port,
	110	ECX_LOCATE_SHIFT);
	111	else
	112	pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
	113	ECX_LOCATE_SHIFT);
	114	if (state & ECX_FAULT_BITS)
	115	pdata->sgpio_pattern \|= sgpio_bit_shift(pdata, port,
	116	ECX_FAULT_SHIFT);
	117	else
	118	pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
	119	ECX_FAULT_SHIFT);
	120	}
	121
	122	/*
	123	* Tell the LED controller that the signal has changed by raising the clock
	124	* line for 50 uS and then lowering it for 50 uS.
	125	*/
	126	static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
	127	{
	128	gpio_set_value(pdata->sgpio_gpio[SCLOCK], 1);
	129	udelay(50);
	130	gpio_set_value(pdata->sgpio_gpio[SCLOCK], 0);
	131	udelay(50);
	132	}
	133
	134	static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
	135	ssize_t size)
136	{
137	struct ahci_host_priv *hpriv = ap->host->private_data;
138	struct ecx_plat_data pdata = (struct ecx_plat_data ) hpriv->plat_data;
139	struct ahci_port_priv *pp = ap->private_data;
140	unsigned long flags;
141	int pmp, i;
142	struct ahci_em_priv *emp;
143	u32 sgpio_out;
144
145	/* get the slot number from the message */
146	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
147	if (pmp < EM_MAX_SLOTS)
148	emp = &pp->em_priv[pmp];
149	else
150	return -EINVAL;
151
152	if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
153	return size;
154
155	spin_lock_irqsave(&sgpio_lock, flags);
156	ecx_parse_sgpio(pdata, ap->port_no, state);
157	sgpio_out = pdata->sgpio_pattern;
158	gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
159	ecx_led_cycle_clock(pdata);
160	gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
161	/*
162	* bit-bang out the SGPIO pattern, by consuming a bit and then
163	* clocking it out.
164	*/
165	for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
166	gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
167	sgpio_out >>= 1;
168	ecx_led_cycle_clock(pdata);
169	}
170
171	/* save off new led state for port/slot */
172	emp->led_state = state;
173
174	spin_unlock_irqrestore(&sgpio_lock, flags);
175	return size;
176	}
177
178	static void highbank_set_em_messages(struct device *dev,
179	struct ahci_host_priv *hpriv,
180	struct ata_port_info *pi)
181	{
182	struct device_node *np = dev->of_node;
183	struct ecx_plat_data *pdata = hpriv->plat_data;
184	int i;
185	int err;
186
187	for (i = 0; i < SGPIO_PINS; i++) {
188	err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i);
189	if (IS_ERR_VALUE(err))
190	return;
191
192	pdata->sgpio_gpio[i] = err;
193	err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO");
194	if (err) {
195	pr_err("sata_highbank gpio_request %d failed: %d\n",
196	i, err);
197	return;
198	}
199	gpio_direction_output(pdata->sgpio_gpio[i], 1);
200	}
201	of_property_read_u32_array(np, "calxeda,led-order",
202	pdata->port_to_sgpio,
203	pdata->n_ports);
204
205	/* store em_loc */
206	hpriv->em_loc = 0;
207	hpriv->em_buf_sz = 4;
208	hpriv->em_msg_type = EM_MSG_TYPE_LED;
209	pi->flags \|= ATA_FLAG_EM \| ATA_FLAG_SW_ACTIVITY;
210	}
211
8996b89d ML	212	static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
	213	{
	214	u32 data;
	215	u8 dev = port_data[sata_port].phy_devs;
	216	spin_lock(&cphy_lock);
	217	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	218	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
	219	spin_unlock(&cphy_lock);
	220	return data;
	221	}
	222
	223	static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
	224	{
	225	u8 dev = port_data[sata_port].phy_devs;
	226	spin_lock(&cphy_lock);
	227	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	228	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
	229	spin_unlock(&cphy_lock);
	230	}
	231
	232	static void combo_phy_wait_for_ready(u8 sata_port)
	233	{
	234	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
	235	udelay(5);
	236	}
	237
	238	static u32 combo_phy_read(u8 sata_port, u32 addr)
	239	{
	240	combo_phy_wait_for_ready(sata_port);
	241	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	242	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
	243	combo_phy_wait_for_ready(sata_port);
	244	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
	245	}
	246
	247	static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
	248	{
	249	combo_phy_wait_for_ready(sata_port);
	250	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	251	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
	252	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN \| CR_START);
	253	}
	254
	255	static void highbank_cphy_disable_overrides(u8 sata_port)
	256	{
	257	u8 lane = port_data[sata_port].lane_mapping;
	258	u32 tmp;
	259	if (unlikely(port_data[sata_port].phy_base == NULL))
	260	return;
	261	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	262	tmp &= ~CPHY_SATA_OVERRIDE;
	263	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
	264	}
	265
	266	static void cphy_override_rx_mode(u8 sata_port, u32 val)
	267	{
	268	u8 lane = port_data[sata_port].lane_mapping;
	269	u32 tmp;
	270	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	271	tmp &= ~CPHY_SATA_OVERRIDE;
	272	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
	273
	274	tmp \|= CPHY_SATA_OVERRIDE;
	275	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
276
277	tmp &= ~CPHY_SATA_DPLL_MODE;
278	tmp \|= val << CPHY_SATA_DPLL_SHIFT;
279	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
280
281	tmp \|= CPHY_SATA_DPLL_RESET;
282	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
283
284	tmp &= ~CPHY_SATA_DPLL_RESET;
285	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
286
287	msleep(15);
288	}
289
290	static void highbank_cphy_override_lane(u8 sata_port)
291	{
292	u8 lane = port_data[sata_port].lane_mapping;
293	u32 tmp, k = 0;
294
295	if (unlikely(port_data[sata_port].phy_base == NULL))
296	return;
297	do {
298	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
299	lane * SPHY_LANE);
300	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
301	cphy_override_rx_mode(sata_port, 3);
302	}
303
304	static int highbank_initialize_phys(struct device dev, void __iomem addr)
305	{
306	struct device_node *sata_node = dev->of_node;
307	int phy_count = 0, phy, port = 0;
308	void __iomem *cphy_base[CPHY_PHY_COUNT];
309	struct device_node *phy_nodes[CPHY_PHY_COUNT];
310	memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
311	memset(phy_nodes, 0, sizeof(struct device_node) CPHY_PHY_COUNT);
312
313	do {
314	u32 tmp;
315	struct of_phandle_args phy_data;
316	if (of_parse_phandle_with_args(sata_node,
317	"calxeda,port-phys", "#phy-cells",
318	port, &phy_data))
319	break;
320	for (phy = 0; phy < phy_count; phy++) {
321	if (phy_nodes[phy] == phy_data.np)
322	break;
323	}
324	if (phy_nodes[phy] == NULL) {
325	phy_nodes[phy] = phy_data.np;
326	cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
327	if (cphy_base[phy] == NULL) {
328	return 0;
329	}
330	phy_count += 1;
331	}
332	port_data[port].lane_mapping = phy_data.args[0];
333	of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
334	port_data[port].phy_devs = tmp;
335	port_data[port].phy_base = cphy_base[phy];
336	of_node_put(phy_data.np);
337	port += 1;
338	} while (port < CPHY_PORT_COUNT);
339	return 0;
340	}
341
342	static int ahci_highbank_hardreset(struct ata_link link, unsigned int class,
343	unsigned long deadline)
344	{
345	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
346	struct ata_port *ap = link->ap;
347	struct ahci_port_priv *pp = ap->private_data;
348	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
349	struct ata_taskfile tf;
350	bool online;
351	u32 sstatus;
352	int rc;
353	int retry = 10;
354
355	ahci_stop_engine(ap);
356
357	/* clear D2H reception area to properly wait for D2H FIS */
358	ata_tf_init(link->device, &tf);
121650a5	359	tf.command = ATA_BUSY;
8996b89d ML	360	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	361
	362	do {
	363	highbank_cphy_disable_overrides(link->ap->port_no);
	364	rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
	365	highbank_cphy_override_lane(link->ap->port_no);
	366
	367	/* If the status is 1, we are connected, but the link did not
	368	* come up. So retry resetting the link again.
	369	*/
	370	if (sata_scr_read(link, SCR_STATUS, &sstatus))
	371	break;
	372	if (!(sstatus & 0x3))
	373	break;
	374	} while (!online && retry--);
	375
	376	ahci_start_engine(ap);
	377
	378	if (online)
	379	*class = ahci_dev_classify(ap);
	380
	381	return rc;
	382	}
	383
	384	static struct ata_port_operations ahci_highbank_ops = {
	385	.inherits = &ahci_ops,
	386	.hardreset = ahci_highbank_hardreset,
d50b110f	387	.transmit_led_message = ecx_transmit_led_message,
8996b89d ML	388	};
	389
	390	static const struct ata_port_info ahci_highbank_port_info = {
	391	.flags = AHCI_FLAG_COMMON,
	392	.pio_mask = ATA_PIO4,
	393	.udma_mask = ATA_UDMA6,
	394	.port_ops = &ahci_highbank_ops,
	395	};
	396
	397	static struct scsi_host_template ahci_highbank_platform_sht = {
2cc1144a	398	AHCI_SHT("sata_highbank"),
8996b89d ML	399	};
	400
	401	static const struct of_device_id ahci_of_match[] = {
	402	{ .compatible = "calxeda,hb-ahci" },
	403	{},
	404	};
	405	MODULE_DEVICE_TABLE(of, ahci_of_match);
	406
0ec24914	407	static int ahci_highbank_probe(struct platform_device *pdev)
8996b89d ML	408	{
	409	struct device *dev = &pdev->dev;
	410	struct ahci_host_priv *hpriv;
d50b110f	411	struct ecx_plat_data *pdata;
8996b89d ML	412	struct ata_host *host;
	413	struct resource *mem;
	414	int irq;
8996b89d ML	415	int i;
8996b89d ML	416	int rc;
d50b110f	417	u32 n_ports;
8996b89d ML	418	struct ata_port_info pi = ahci_highbank_port_info;
	419	const struct ata_port_info *ppi[] = { &pi, NULL };
	420
	421	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	422	if (!mem) {
	423	dev_err(dev, "no mmio space\n");
	424	return -EINVAL;
	425	}
	426
	427	irq = platform_get_irq(pdev, 0);
	428	if (irq <= 0) {
	429	dev_err(dev, "no irq\n");
	430	return -EINVAL;
	431	}
	432
	433	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	434	if (!hpriv) {
	435	dev_err(dev, "can't alloc ahci_host_priv\n");
	436	return -ENOMEM;
	437	}
d50b110f ML	438	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	439	if (!pdata) {
	440	dev_err(dev, "can't alloc ecx_plat_data\n");
	441	return -ENOMEM;
	442	}
8996b89d ML	443
	444	hpriv->flags \|= (unsigned long)pi.private_data;
	445
	446	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
	447	if (!hpriv->mmio) {
	448	dev_err(dev, "can't map %pR\n", mem);
	449	return -ENOMEM;
	450	}
	451
	452	rc = highbank_initialize_phys(dev, hpriv->mmio);
	453	if (rc)
	454	return rc;
	455
	456
	457	ahci_save_initial_config(dev, hpriv, 0, 0);
	458
	459	/* prepare host */
	460	if (hpriv->cap & HOST_CAP_NCQ)
	461	pi.flags \|= ATA_FLAG_NCQ;
	462
	463	if (hpriv->cap & HOST_CAP_PMP)
	464	pi.flags \|= ATA_FLAG_PMP;
	465
8996b89d ML	466	/* CAP.NP sometimes indicate the index of the last enabled
	467	* port, at other times, that of the last possible port, so
	468	* determining the maximum port number requires looking at
	469	* both CAP.NP and port_map.
	470	*/
	471	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
	472
d50b110f ML	473	pdata->n_ports = n_ports;
	474	hpriv->plat_data = pdata;
	475	highbank_set_em_messages(dev, hpriv, &pi);
	476
8996b89d ML	477	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
	478	if (!host) {
	479	rc = -ENOMEM;
	480	goto err0;
	481	}
	482
	483	host->private_data = hpriv;
	484
	485	if (!(hpriv->cap & HOST_CAP_SSS) \|\| ahci_ignore_sss)
	486	host->flags \|= ATA_HOST_PARALLEL_SCAN;
	487
8996b89d ML	488	for (i = 0; i < host->n_ports; i++) {
	489	struct ata_port *ap = host->ports[i];
	490
	491	ata_port_desc(ap, "mmio %pR", mem);
	492	ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
	493
	494	/* set enclosure management message type */
	495	if (ap->flags & ATA_FLAG_EM)
	496	ap->em_message_type = hpriv->em_msg_type;
	497
	498	/* disabled/not-implemented port */
	499	if (!(hpriv->port_map & (1 << i)))
	500	ap->ops = &ata_dummy_port_ops;
	501	}
	502
	503	rc = ahci_reset_controller(host);
	504	if (rc)
	505	goto err0;
	506
	507	ahci_init_controller(host);
	508	ahci_print_info(host, "platform");
	509
	510	rc = ata_host_activate(host, irq, ahci_interrupt, 0,
	511	&ahci_highbank_platform_sht);
	512	if (rc)
	513	goto err0;
	514
	515	return 0;
	516	err0:
	517	return rc;
	518	}
	519
29448ec1	520	#ifdef CONFIG_PM_SLEEP
8996b89d ML	521	static int ahci_highbank_suspend(struct device *dev)
	522	{
	523	struct ata_host *host = dev_get_drvdata(dev);
	524	struct ahci_host_priv *hpriv = host->private_data;
	525	void __iomem *mmio = hpriv->mmio;
	526	u32 ctl;
	527	int rc;
	528
	529	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
	530	dev_err(dev, "firmware update required for suspend/resume\n");
	531	return -EIO;
	532	}
	533
	534	/*
	535	* AHCI spec rev1.1 section 8.3.3:
	536	* Software must disable interrupts prior to requesting a
	537	* transition of the HBA to D3 state.
	538	*/
	539	ctl = readl(mmio + HOST_CTL);
	540	ctl &= ~HOST_IRQ_EN;
	541	writel(ctl, mmio + HOST_CTL);
	542	readl(mmio + HOST_CTL); /* flush */
	543
	544	rc = ata_host_suspend(host, PMSG_SUSPEND);
	545	if (rc)
	546	return rc;
	547
	548	return 0;
	549	}
	550
	551	static int ahci_highbank_resume(struct device *dev)
	552	{
	553	struct ata_host *host = dev_get_drvdata(dev);
	554	int rc;
	555
	556	if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
	557	rc = ahci_reset_controller(host);
	558	if (rc)
	559	return rc;
	560
	561	ahci_init_controller(host);
	562	}
	563
	564	ata_host_resume(host);
	565
	566	return 0;
	567	}
	568	#endif
	569
b1a72d60	570	static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
8996b89d ML	571	ahci_highbank_suspend, ahci_highbank_resume);
	572
	573	static struct platform_driver ahci_highbank_driver = {
e2ec1817	574	.remove = ata_platform_remove_one,
8996b89d ML	575	.driver = {
	576	.name = "highbank-ahci",
	577	.owner = THIS_MODULE,
	578	.of_match_table = ahci_of_match,
	579	.pm = &ahci_highbank_pm_ops,
	580	},
	581	.probe = ahci_highbank_probe,
	582	};
	583
	584	module_platform_driver(ahci_highbank_driver);
	585
	586	MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
	587	MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
	588	MODULE_LICENSE("GPL");
	589	MODULE_ALIAS("sata:highbank");