Commit | Line | Data |
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1fd7a697 TH |
1 | /* |
2 | * sata_inic162x.c - Driver for Initio 162x SATA controllers | |
3 | * | |
4 | * Copyright 2006 SUSE Linux Products GmbH | |
5 | * Copyright 2006 Tejun Heo <teheo@novell.com> | |
6 | * | |
7 | * This file is released under GPL v2. | |
8 | * | |
9 | * This controller is eccentric and easily locks up if something isn't | |
10 | * right. Documentation is available at initio's website but it only | |
11 | * documents registers (not programming model). | |
12 | * | |
22bfc6d5 TH |
13 | * This driver has interesting history. The first version was written |
14 | * from the documentation and a 2.4 IDE driver posted on a Taiwan | |
15 | * company, which didn't use any IDMA features and couldn't handle | |
16 | * LBA48. The resulting driver couldn't handle LBA48 devices either | |
17 | * making it pretty useless. | |
18 | * | |
19 | * After a while, initio picked the driver up, renamed it to | |
20 | * sata_initio162x, updated it to use IDMA for ATA DMA commands and | |
21 | * posted it on their website. It only used ATA_PROT_DMA for IDMA and | |
22 | * attaching both devices and issuing IDMA and !IDMA commands | |
23 | * simultaneously broke it due to PIRQ masking interaction but it did | |
24 | * show how to use the IDMA (ADMA + some initio specific twists) | |
25 | * engine. | |
26 | * | |
27 | * Then, I picked up their changes again and here's the usable driver | |
28 | * which uses IDMA for everything. Everything works now including | |
29 | * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some | |
30 | * issues tho. Result Tf is not resported properly, NCQ isn't | |
31 | * supported yet and CD/DVD writing works with DMA assisted PIO | |
32 | * protocol (which, for native SATA devices, shouldn't cause any | |
33 | * noticeable difference). | |
34 | * | |
35 | * Anyways, so, here's finally a working driver for inic162x. Enjoy! | |
36 | * | |
37 | * initio: If you guys wanna improve the driver regarding result TF | |
38 | * access and other stuff, please feel free to contact me. I'll be | |
39 | * happy to assist. | |
1fd7a697 TH |
40 | */ |
41 | ||
5a0e3ad6 | 42 | #include <linux/gfp.h> |
1fd7a697 TH |
43 | #include <linux/kernel.h> |
44 | #include <linux/module.h> | |
45 | #include <linux/pci.h> | |
46 | #include <scsi/scsi_host.h> | |
47 | #include <linux/libata.h> | |
48 | #include <linux/blkdev.h> | |
49 | #include <scsi/scsi_device.h> | |
50 | ||
51 | #define DRV_NAME "sata_inic162x" | |
22bfc6d5 | 52 | #define DRV_VERSION "0.4" |
1fd7a697 TH |
53 | |
54 | enum { | |
ba66b242 TH |
55 | MMIO_BAR_PCI = 5, |
56 | MMIO_BAR_CARDBUS = 1, | |
1fd7a697 TH |
57 | |
58 | NR_PORTS = 2, | |
59 | ||
3ad400a9 TH |
60 | IDMA_CPB_TBL_SIZE = 4 * 32, |
61 | ||
62 | INIC_DMA_BOUNDARY = 0xffffff, | |
63 | ||
b0dd9b8e | 64 | HOST_ACTRL = 0x08, |
1fd7a697 TH |
65 | HOST_CTL = 0x7c, |
66 | HOST_STAT = 0x7e, | |
67 | HOST_IRQ_STAT = 0xbc, | |
68 | HOST_IRQ_MASK = 0xbe, | |
69 | ||
70 | PORT_SIZE = 0x40, | |
71 | ||
72 | /* registers for ATA TF operation */ | |
b0dd9b8e TH |
73 | PORT_TF_DATA = 0x00, |
74 | PORT_TF_FEATURE = 0x01, | |
75 | PORT_TF_NSECT = 0x02, | |
76 | PORT_TF_LBAL = 0x03, | |
77 | PORT_TF_LBAM = 0x04, | |
78 | PORT_TF_LBAH = 0x05, | |
79 | PORT_TF_DEVICE = 0x06, | |
80 | PORT_TF_COMMAND = 0x07, | |
81 | PORT_TF_ALT_STAT = 0x08, | |
1fd7a697 TH |
82 | PORT_IRQ_STAT = 0x09, |
83 | PORT_IRQ_MASK = 0x0a, | |
84 | PORT_PRD_CTL = 0x0b, | |
85 | PORT_PRD_ADDR = 0x0c, | |
86 | PORT_PRD_XFERLEN = 0x10, | |
b0dd9b8e TH |
87 | PORT_CPB_CPBLAR = 0x18, |
88 | PORT_CPB_PTQFIFO = 0x1c, | |
1fd7a697 TH |
89 | |
90 | /* IDMA register */ | |
91 | PORT_IDMA_CTL = 0x14, | |
b0dd9b8e TH |
92 | PORT_IDMA_STAT = 0x16, |
93 | ||
94 | PORT_RPQ_FIFO = 0x1e, | |
95 | PORT_RPQ_CNT = 0x1f, | |
1fd7a697 TH |
96 | |
97 | PORT_SCR = 0x20, | |
98 | ||
99 | /* HOST_CTL bits */ | |
99580664 | 100 | HCTL_LEDEN = (1 << 3), /* enable LED operation */ |
1fd7a697 | 101 | HCTL_IRQOFF = (1 << 8), /* global IRQ off */ |
b0dd9b8e TH |
102 | HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */ |
103 | HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/ | |
104 | HCTL_PWRDWN = (1 << 12), /* power down PHYs */ | |
1fd7a697 TH |
105 | HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ |
106 | HCTL_RPGSEL = (1 << 15), /* register page select */ | |
107 | ||
108 | HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | | |
109 | HCTL_RPGSEL, | |
110 | ||
111 | /* HOST_IRQ_(STAT|MASK) bits */ | |
112 | HIRQ_PORT0 = (1 << 0), | |
113 | HIRQ_PORT1 = (1 << 1), | |
114 | HIRQ_SOFT = (1 << 14), | |
115 | HIRQ_GLOBAL = (1 << 15), /* STAT only */ | |
116 | ||
117 | /* PORT_IRQ_(STAT|MASK) bits */ | |
118 | PIRQ_OFFLINE = (1 << 0), /* device unplugged */ | |
119 | PIRQ_ONLINE = (1 << 1), /* device plugged */ | |
120 | PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ | |
121 | PIRQ_FATAL = (1 << 3), /* fatal error */ | |
122 | PIRQ_ATA = (1 << 4), /* ATA interrupt */ | |
123 | PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ | |
124 | PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ | |
125 | ||
126 | PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, | |
f8b0685a | 127 | PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA, |
1fd7a697 TH |
128 | PIRQ_MASK_FREEZE = 0xff, |
129 | ||
130 | /* PORT_PRD_CTL bits */ | |
131 | PRD_CTL_START = (1 << 0), | |
132 | PRD_CTL_WR = (1 << 3), | |
133 | PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ | |
134 | ||
135 | /* PORT_IDMA_CTL bits */ | |
136 | IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ | |
137 | IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ | |
138 | IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ | |
139 | IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ | |
b0dd9b8e TH |
140 | |
141 | /* PORT_IDMA_STAT bits */ | |
142 | IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */ | |
143 | IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */ | |
144 | IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */ | |
145 | IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */ | |
146 | IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */ | |
147 | IDMA_STAT_PSD = (1 << 6), /* ADMA pause */ | |
148 | IDMA_STAT_DONE = (1 << 7), /* ADMA done */ | |
149 | ||
150 | IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR, | |
151 | ||
152 | /* CPB Control Flags*/ | |
153 | CPB_CTL_VALID = (1 << 0), /* CPB valid */ | |
154 | CPB_CTL_QUEUED = (1 << 1), /* queued command */ | |
155 | CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */ | |
156 | CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */ | |
157 | CPB_CTL_DEVDIR = (1 << 4), /* device direction control */ | |
158 | ||
159 | /* CPB Response Flags */ | |
160 | CPB_RESP_DONE = (1 << 0), /* ATA command complete */ | |
161 | CPB_RESP_REL = (1 << 1), /* ATA release */ | |
162 | CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */ | |
163 | CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */ | |
164 | CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */ | |
165 | CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */ | |
166 | CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */ | |
167 | CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */ | |
168 | ||
169 | /* PRD Control Flags */ | |
170 | PRD_DRAIN = (1 << 1), /* ignore data excess */ | |
171 | PRD_CDB = (1 << 2), /* atapi packet command pointer */ | |
172 | PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */ | |
173 | PRD_DMA = (1 << 4), /* data transfer method */ | |
174 | PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */ | |
175 | PRD_IOM = (1 << 6), /* io/memory transfer */ | |
176 | PRD_END = (1 << 7), /* APRD chain end */ | |
1fd7a697 TH |
177 | }; |
178 | ||
3ad400a9 TH |
179 | /* Comman Parameter Block */ |
180 | struct inic_cpb { | |
181 | u8 resp_flags; /* Response Flags */ | |
182 | u8 error; /* ATA Error */ | |
183 | u8 status; /* ATA Status */ | |
184 | u8 ctl_flags; /* Control Flags */ | |
185 | __le32 len; /* Total Transfer Length */ | |
186 | __le32 prd; /* First PRD pointer */ | |
187 | u8 rsvd[4]; | |
188 | /* 16 bytes */ | |
189 | u8 feature; /* ATA Feature */ | |
190 | u8 hob_feature; /* ATA Ex. Feature */ | |
191 | u8 device; /* ATA Device/Head */ | |
192 | u8 mirctl; /* Mirror Control */ | |
193 | u8 nsect; /* ATA Sector Count */ | |
194 | u8 hob_nsect; /* ATA Ex. Sector Count */ | |
195 | u8 lbal; /* ATA Sector Number */ | |
196 | u8 hob_lbal; /* ATA Ex. Sector Number */ | |
197 | u8 lbam; /* ATA Cylinder Low */ | |
198 | u8 hob_lbam; /* ATA Ex. Cylinder Low */ | |
199 | u8 lbah; /* ATA Cylinder High */ | |
200 | u8 hob_lbah; /* ATA Ex. Cylinder High */ | |
201 | u8 command; /* ATA Command */ | |
202 | u8 ctl; /* ATA Control */ | |
203 | u8 slave_error; /* Slave ATA Error */ | |
204 | u8 slave_status; /* Slave ATA Status */ | |
205 | /* 32 bytes */ | |
206 | } __packed; | |
207 | ||
208 | /* Physical Region Descriptor */ | |
209 | struct inic_prd { | |
210 | __le32 mad; /* Physical Memory Address */ | |
211 | __le16 len; /* Transfer Length */ | |
212 | u8 rsvd; | |
213 | u8 flags; /* Control Flags */ | |
214 | } __packed; | |
215 | ||
216 | struct inic_pkt { | |
217 | struct inic_cpb cpb; | |
b3f677e5 TH |
218 | struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */ |
219 | u8 cdb[ATAPI_CDB_LEN]; | |
3ad400a9 TH |
220 | } __packed; |
221 | ||
1fd7a697 | 222 | struct inic_host_priv { |
ba66b242 | 223 | void __iomem *mmio_base; |
36f674d9 | 224 | u16 cached_hctl; |
1fd7a697 TH |
225 | }; |
226 | ||
227 | struct inic_port_priv { | |
3ad400a9 TH |
228 | struct inic_pkt *pkt; |
229 | dma_addr_t pkt_dma; | |
230 | u32 *cpb_tbl; | |
231 | dma_addr_t cpb_tbl_dma; | |
1fd7a697 TH |
232 | }; |
233 | ||
1fd7a697 | 234 | static struct scsi_host_template inic_sht = { |
ab5b0235 TH |
235 | ATA_BASE_SHT(DRV_NAME), |
236 | .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */ | |
3ad400a9 | 237 | .dma_boundary = INIC_DMA_BOUNDARY, |
1fd7a697 TH |
238 | }; |
239 | ||
240 | static const int scr_map[] = { | |
241 | [SCR_STATUS] = 0, | |
242 | [SCR_ERROR] = 1, | |
243 | [SCR_CONTROL] = 2, | |
244 | }; | |
245 | ||
5796d1c4 | 246 | static void __iomem *inic_port_base(struct ata_port *ap) |
1fd7a697 | 247 | { |
ba66b242 TH |
248 | struct inic_host_priv *hpriv = ap->host->private_data; |
249 | ||
250 | return hpriv->mmio_base + ap->port_no * PORT_SIZE; | |
1fd7a697 TH |
251 | } |
252 | ||
1fd7a697 TH |
253 | static void inic_reset_port(void __iomem *port_base) |
254 | { | |
255 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
1fd7a697 | 256 | |
f8b0685a TH |
257 | /* stop IDMA engine */ |
258 | readw(idma_ctl); /* flush */ | |
259 | msleep(1); | |
1fd7a697 TH |
260 | |
261 | /* mask IRQ and assert reset */ | |
f8b0685a | 262 | writew(IDMA_CTL_RST_IDMA, idma_ctl); |
1fd7a697 | 263 | readw(idma_ctl); /* flush */ |
1fd7a697 TH |
264 | msleep(1); |
265 | ||
266 | /* release reset */ | |
f8b0685a | 267 | writew(0, idma_ctl); |
1fd7a697 TH |
268 | |
269 | /* clear irq */ | |
270 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
1fd7a697 TH |
271 | } |
272 | ||
82ef04fb | 273 | static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) |
1fd7a697 | 274 | { |
82ef04fb | 275 | void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR; |
1fd7a697 TH |
276 | |
277 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 278 | return -EINVAL; |
1fd7a697 | 279 | |
da3dbb17 | 280 | *val = readl(scr_addr + scr_map[sc_reg] * 4); |
1fd7a697 TH |
281 | |
282 | /* this controller has stuck DIAG.N, ignore it */ | |
283 | if (sc_reg == SCR_ERROR) | |
da3dbb17 TH |
284 | *val &= ~SERR_PHYRDY_CHG; |
285 | return 0; | |
1fd7a697 TH |
286 | } |
287 | ||
82ef04fb | 288 | static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) |
1fd7a697 | 289 | { |
82ef04fb | 290 | void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR; |
1fd7a697 TH |
291 | |
292 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 293 | return -EINVAL; |
1fd7a697 | 294 | |
1fd7a697 | 295 | writel(val, scr_addr + scr_map[sc_reg] * 4); |
da3dbb17 | 296 | return 0; |
1fd7a697 TH |
297 | } |
298 | ||
3ad400a9 | 299 | static void inic_stop_idma(struct ata_port *ap) |
1fd7a697 TH |
300 | { |
301 | void __iomem *port_base = inic_port_base(ap); | |
3ad400a9 TH |
302 | |
303 | readb(port_base + PORT_RPQ_FIFO); | |
304 | readb(port_base + PORT_RPQ_CNT); | |
305 | writew(0, port_base + PORT_IDMA_CTL); | |
306 | } | |
307 | ||
308 | static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat) | |
309 | { | |
9af5c9c9 | 310 | struct ata_eh_info *ehi = &ap->link.eh_info; |
3ad400a9 TH |
311 | struct inic_port_priv *pp = ap->private_data; |
312 | struct inic_cpb *cpb = &pp->pkt->cpb; | |
313 | bool freeze = false; | |
314 | ||
315 | ata_ehi_clear_desc(ehi); | |
316 | ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x", | |
317 | irq_stat, idma_stat); | |
318 | ||
319 | inic_stop_idma(ap); | |
320 | ||
321 | if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { | |
322 | ata_ehi_push_desc(ehi, "hotplug"); | |
323 | ata_ehi_hotplugged(ehi); | |
324 | freeze = true; | |
325 | } | |
326 | ||
327 | if (idma_stat & IDMA_STAT_PERR) { | |
328 | ata_ehi_push_desc(ehi, "PCI error"); | |
329 | freeze = true; | |
330 | } | |
331 | ||
332 | if (idma_stat & IDMA_STAT_CPBERR) { | |
333 | ata_ehi_push_desc(ehi, "CPB error"); | |
334 | ||
335 | if (cpb->resp_flags & CPB_RESP_IGNORED) { | |
336 | __ata_ehi_push_desc(ehi, " ignored"); | |
337 | ehi->err_mask |= AC_ERR_INVALID; | |
338 | freeze = true; | |
339 | } | |
340 | ||
341 | if (cpb->resp_flags & CPB_RESP_ATA_ERR) | |
342 | ehi->err_mask |= AC_ERR_DEV; | |
343 | ||
344 | if (cpb->resp_flags & CPB_RESP_SPURIOUS) { | |
345 | __ata_ehi_push_desc(ehi, " spurious-intr"); | |
346 | ehi->err_mask |= AC_ERR_HSM; | |
347 | freeze = true; | |
348 | } | |
349 | ||
350 | if (cpb->resp_flags & | |
351 | (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) { | |
352 | __ata_ehi_push_desc(ehi, " data-over/underflow"); | |
353 | ehi->err_mask |= AC_ERR_HSM; | |
354 | freeze = true; | |
355 | } | |
356 | } | |
357 | ||
358 | if (freeze) | |
359 | ata_port_freeze(ap); | |
360 | else | |
361 | ata_port_abort(ap); | |
362 | } | |
363 | ||
364 | static void inic_host_intr(struct ata_port *ap) | |
365 | { | |
366 | void __iomem *port_base = inic_port_base(ap); | |
367 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1fd7a697 | 368 | u8 irq_stat; |
3ad400a9 | 369 | u16 idma_stat; |
1fd7a697 | 370 | |
3ad400a9 | 371 | /* read and clear IRQ status */ |
1fd7a697 TH |
372 | irq_stat = readb(port_base + PORT_IRQ_STAT); |
373 | writeb(irq_stat, port_base + PORT_IRQ_STAT); | |
3ad400a9 TH |
374 | idma_stat = readw(port_base + PORT_IDMA_STAT); |
375 | ||
376 | if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR))) | |
377 | inic_host_err_intr(ap, irq_stat, idma_stat); | |
378 | ||
f8b0685a | 379 | if (unlikely(!qc)) |
3ad400a9 | 380 | goto spurious; |
3ad400a9 | 381 | |
b3f677e5 TH |
382 | if (likely(idma_stat & IDMA_STAT_DONE)) { |
383 | inic_stop_idma(ap); | |
1fd7a697 | 384 | |
b3f677e5 TH |
385 | /* Depending on circumstances, device error |
386 | * isn't reported by IDMA, check it explicitly. | |
387 | */ | |
388 | if (unlikely(readb(port_base + PORT_TF_COMMAND) & | |
389 | (ATA_DF | ATA_ERR))) | |
390 | qc->err_mask |= AC_ERR_DEV; | |
1fd7a697 | 391 | |
b3f677e5 TH |
392 | ata_qc_complete(qc); |
393 | return; | |
1fd7a697 TH |
394 | } |
395 | ||
3ad400a9 | 396 | spurious: |
a9a79dfe JP |
397 | ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n", |
398 | qc ? qc->tf.command : 0xff, irq_stat, idma_stat); | |
1fd7a697 TH |
399 | } |
400 | ||
401 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) | |
402 | { | |
403 | struct ata_host *host = dev_instance; | |
ba66b242 | 404 | struct inic_host_priv *hpriv = host->private_data; |
1fd7a697 | 405 | u16 host_irq_stat; |
87c8b22b | 406 | int i, handled = 0; |
1fd7a697 | 407 | |
ba66b242 | 408 | host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); |
1fd7a697 TH |
409 | |
410 | if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) | |
411 | goto out; | |
412 | ||
413 | spin_lock(&host->lock); | |
414 | ||
3e4ec344 TH |
415 | for (i = 0; i < NR_PORTS; i++) |
416 | if (host_irq_stat & (HIRQ_PORT0 << i)) { | |
417 | inic_host_intr(host->ports[i]); | |
1fd7a697 | 418 | handled++; |
1fd7a697 | 419 | } |
1fd7a697 TH |
420 | |
421 | spin_unlock(&host->lock); | |
422 | ||
423 | out: | |
424 | return IRQ_RETVAL(handled); | |
425 | } | |
426 | ||
b3f677e5 TH |
427 | static int inic_check_atapi_dma(struct ata_queued_cmd *qc) |
428 | { | |
429 | /* For some reason ATAPI_PROT_DMA doesn't work for some | |
430 | * commands including writes and other misc ops. Use PIO | |
431 | * protocol instead, which BTW is driven by the DMA engine | |
432 | * anyway, so it shouldn't make much difference for native | |
433 | * SATA devices. | |
434 | */ | |
435 | if (atapi_cmd_type(qc->cdb[0]) == READ) | |
436 | return 0; | |
437 | return 1; | |
438 | } | |
439 | ||
3ad400a9 TH |
440 | static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc) |
441 | { | |
442 | struct scatterlist *sg; | |
443 | unsigned int si; | |
049e8e04 | 444 | u8 flags = 0; |
3ad400a9 TH |
445 | |
446 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
447 | flags |= PRD_WRITE; | |
448 | ||
049e8e04 TH |
449 | if (ata_is_dma(qc->tf.protocol)) |
450 | flags |= PRD_DMA; | |
451 | ||
3ad400a9 TH |
452 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
453 | prd->mad = cpu_to_le32(sg_dma_address(sg)); | |
454 | prd->len = cpu_to_le16(sg_dma_len(sg)); | |
455 | prd->flags = flags; | |
456 | prd++; | |
457 | } | |
458 | ||
459 | WARN_ON(!si); | |
460 | prd[-1].flags |= PRD_END; | |
461 | } | |
462 | ||
463 | static void inic_qc_prep(struct ata_queued_cmd *qc) | |
464 | { | |
465 | struct inic_port_priv *pp = qc->ap->private_data; | |
466 | struct inic_pkt *pkt = pp->pkt; | |
467 | struct inic_cpb *cpb = &pkt->cpb; | |
468 | struct inic_prd *prd = pkt->prd; | |
049e8e04 TH |
469 | bool is_atapi = ata_is_atapi(qc->tf.protocol); |
470 | bool is_data = ata_is_data(qc->tf.protocol); | |
b3f677e5 | 471 | unsigned int cdb_len = 0; |
3ad400a9 TH |
472 | |
473 | VPRINTK("ENTER\n"); | |
474 | ||
049e8e04 | 475 | if (is_atapi) |
b3f677e5 | 476 | cdb_len = qc->dev->cdb_len; |
3ad400a9 TH |
477 | |
478 | /* prepare packet, based on initio driver */ | |
479 | memset(pkt, 0, sizeof(struct inic_pkt)); | |
480 | ||
049e8e04 | 481 | cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN; |
b3f677e5 | 482 | if (is_atapi || is_data) |
049e8e04 | 483 | cpb->ctl_flags |= CPB_CTL_DATA; |
3ad400a9 | 484 | |
b3f677e5 | 485 | cpb->len = cpu_to_le32(qc->nbytes + cdb_len); |
3ad400a9 TH |
486 | cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd)); |
487 | ||
488 | cpb->device = qc->tf.device; | |
489 | cpb->feature = qc->tf.feature; | |
490 | cpb->nsect = qc->tf.nsect; | |
491 | cpb->lbal = qc->tf.lbal; | |
492 | cpb->lbam = qc->tf.lbam; | |
493 | cpb->lbah = qc->tf.lbah; | |
494 | ||
495 | if (qc->tf.flags & ATA_TFLAG_LBA48) { | |
496 | cpb->hob_feature = qc->tf.hob_feature; | |
497 | cpb->hob_nsect = qc->tf.hob_nsect; | |
498 | cpb->hob_lbal = qc->tf.hob_lbal; | |
499 | cpb->hob_lbam = qc->tf.hob_lbam; | |
500 | cpb->hob_lbah = qc->tf.hob_lbah; | |
501 | } | |
502 | ||
503 | cpb->command = qc->tf.command; | |
504 | /* don't load ctl - dunno why. it's like that in the initio driver */ | |
505 | ||
b3f677e5 TH |
506 | /* setup PRD for CDB */ |
507 | if (is_atapi) { | |
508 | memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN); | |
509 | prd->mad = cpu_to_le32(pp->pkt_dma + | |
510 | offsetof(struct inic_pkt, cdb)); | |
511 | prd->len = cpu_to_le16(cdb_len); | |
512 | prd->flags = PRD_CDB | PRD_WRITE; | |
513 | if (!is_data) | |
514 | prd->flags |= PRD_END; | |
515 | prd++; | |
516 | } | |
517 | ||
3ad400a9 | 518 | /* setup sg table */ |
049e8e04 TH |
519 | if (is_data) |
520 | inic_fill_sg(prd, qc); | |
3ad400a9 TH |
521 | |
522 | pp->cpb_tbl[0] = pp->pkt_dma; | |
523 | } | |
524 | ||
1fd7a697 TH |
525 | static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) |
526 | { | |
527 | struct ata_port *ap = qc->ap; | |
3ad400a9 | 528 | void __iomem *port_base = inic_port_base(ap); |
1fd7a697 | 529 | |
b3f677e5 | 530 | /* fire up the ADMA engine */ |
99580664 | 531 | writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL); |
b3f677e5 TH |
532 | writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL); |
533 | writeb(0, port_base + PORT_CPB_PTQFIFO); | |
1fd7a697 | 534 | |
b3f677e5 | 535 | return 0; |
1fd7a697 TH |
536 | } |
537 | ||
364fac0e TH |
538 | static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
539 | { | |
540 | void __iomem *port_base = inic_port_base(ap); | |
541 | ||
542 | tf->feature = readb(port_base + PORT_TF_FEATURE); | |
543 | tf->nsect = readb(port_base + PORT_TF_NSECT); | |
544 | tf->lbal = readb(port_base + PORT_TF_LBAL); | |
545 | tf->lbam = readb(port_base + PORT_TF_LBAM); | |
546 | tf->lbah = readb(port_base + PORT_TF_LBAH); | |
547 | tf->device = readb(port_base + PORT_TF_DEVICE); | |
548 | tf->command = readb(port_base + PORT_TF_COMMAND); | |
549 | } | |
550 | ||
551 | static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc) | |
552 | { | |
553 | struct ata_taskfile *rtf = &qc->result_tf; | |
554 | struct ata_taskfile tf; | |
555 | ||
556 | /* FIXME: Except for status and error, result TF access | |
557 | * doesn't work. I tried reading from BAR0/2, CPB and BAR5. | |
558 | * None works regardless of which command interface is used. | |
559 | * For now return true iff status indicates device error. | |
560 | * This means that we're reporting bogus sector for RW | |
561 | * failures. Eeekk.... | |
562 | */ | |
563 | inic_tf_read(qc->ap, &tf); | |
564 | ||
565 | if (!(tf.command & ATA_ERR)) | |
566 | return false; | |
567 | ||
568 | rtf->command = tf.command; | |
569 | rtf->feature = tf.feature; | |
570 | return true; | |
571 | } | |
572 | ||
1fd7a697 TH |
573 | static void inic_freeze(struct ata_port *ap) |
574 | { | |
575 | void __iomem *port_base = inic_port_base(ap); | |
576 | ||
ab5b0235 | 577 | writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK); |
1fd7a697 | 578 | writeb(0xff, port_base + PORT_IRQ_STAT); |
1fd7a697 TH |
579 | } |
580 | ||
581 | static void inic_thaw(struct ata_port *ap) | |
582 | { | |
583 | void __iomem *port_base = inic_port_base(ap); | |
584 | ||
1fd7a697 | 585 | writeb(0xff, port_base + PORT_IRQ_STAT); |
ab5b0235 | 586 | writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK); |
1fd7a697 TH |
587 | } |
588 | ||
364fac0e TH |
589 | static int inic_check_ready(struct ata_link *link) |
590 | { | |
591 | void __iomem *port_base = inic_port_base(link->ap); | |
592 | ||
593 | return ata_check_ready(readb(port_base + PORT_TF_COMMAND)); | |
594 | } | |
595 | ||
1fd7a697 TH |
596 | /* |
597 | * SRST and SControl hardreset don't give valid signature on this | |
598 | * controller. Only controller specific hardreset mechanism works. | |
599 | */ | |
cc0680a5 | 600 | static int inic_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 601 | unsigned long deadline) |
1fd7a697 | 602 | { |
cc0680a5 | 603 | struct ata_port *ap = link->ap; |
1fd7a697 TH |
604 | void __iomem *port_base = inic_port_base(ap); |
605 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
cc0680a5 | 606 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
1fd7a697 TH |
607 | int rc; |
608 | ||
609 | /* hammer it into sane state */ | |
610 | inic_reset_port(port_base); | |
611 | ||
f8b0685a | 612 | writew(IDMA_CTL_RST_ATA, idma_ctl); |
1fd7a697 | 613 | readw(idma_ctl); /* flush */ |
97750ceb | 614 | ata_msleep(ap, 1); |
f8b0685a | 615 | writew(0, idma_ctl); |
1fd7a697 | 616 | |
cc0680a5 | 617 | rc = sata_link_resume(link, timing, deadline); |
1fd7a697 | 618 | if (rc) { |
a9a79dfe JP |
619 | ata_link_warn(link, |
620 | "failed to resume link after reset (errno=%d)\n", | |
621 | rc); | |
1fd7a697 TH |
622 | return rc; |
623 | } | |
624 | ||
1fd7a697 | 625 | *class = ATA_DEV_NONE; |
cc0680a5 | 626 | if (ata_link_online(link)) { |
1fd7a697 TH |
627 | struct ata_taskfile tf; |
628 | ||
705e76be | 629 | /* wait for link to become ready */ |
364fac0e | 630 | rc = ata_wait_after_reset(link, deadline, inic_check_ready); |
9b89391c TH |
631 | /* link occupied, -ENODEV too is an error */ |
632 | if (rc) { | |
a9a79dfe JP |
633 | ata_link_warn(link, |
634 | "device not ready after hardreset (errno=%d)\n", | |
635 | rc); | |
d4b2bab4 | 636 | return rc; |
1fd7a697 TH |
637 | } |
638 | ||
364fac0e | 639 | inic_tf_read(ap, &tf); |
1fd7a697 | 640 | *class = ata_dev_classify(&tf); |
1fd7a697 TH |
641 | } |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | static void inic_error_handler(struct ata_port *ap) | |
647 | { | |
648 | void __iomem *port_base = inic_port_base(ap); | |
1fd7a697 | 649 | |
1fd7a697 | 650 | inic_reset_port(port_base); |
a1efdaba | 651 | ata_std_error_handler(ap); |
1fd7a697 TH |
652 | } |
653 | ||
654 | static void inic_post_internal_cmd(struct ata_queued_cmd *qc) | |
655 | { | |
656 | /* make DMA engine forget about the failed command */ | |
a51d644a | 657 | if (qc->flags & ATA_QCFLAG_FAILED) |
1fd7a697 TH |
658 | inic_reset_port(inic_port_base(qc->ap)); |
659 | } | |
660 | ||
1fd7a697 TH |
661 | static void init_port(struct ata_port *ap) |
662 | { | |
663 | void __iomem *port_base = inic_port_base(ap); | |
3ad400a9 | 664 | struct inic_port_priv *pp = ap->private_data; |
1fd7a697 | 665 | |
3ad400a9 TH |
666 | /* clear packet and CPB table */ |
667 | memset(pp->pkt, 0, sizeof(struct inic_pkt)); | |
668 | memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE); | |
669 | ||
6bc0d390 | 670 | /* setup CPB lookup table addresses */ |
3ad400a9 | 671 | writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR); |
1fd7a697 TH |
672 | } |
673 | ||
674 | static int inic_port_resume(struct ata_port *ap) | |
675 | { | |
676 | init_port(ap); | |
677 | return 0; | |
678 | } | |
679 | ||
680 | static int inic_port_start(struct ata_port *ap) | |
681 | { | |
3ad400a9 | 682 | struct device *dev = ap->host->dev; |
1fd7a697 | 683 | struct inic_port_priv *pp; |
1fd7a697 TH |
684 | |
685 | /* alloc and initialize private data */ | |
3ad400a9 | 686 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
1fd7a697 TH |
687 | if (!pp) |
688 | return -ENOMEM; | |
689 | ap->private_data = pp; | |
690 | ||
1fd7a697 | 691 | /* Alloc resources */ |
3ad400a9 TH |
692 | pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt), |
693 | &pp->pkt_dma, GFP_KERNEL); | |
694 | if (!pp->pkt) | |
695 | return -ENOMEM; | |
696 | ||
697 | pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE, | |
698 | &pp->cpb_tbl_dma, GFP_KERNEL); | |
699 | if (!pp->cpb_tbl) | |
700 | return -ENOMEM; | |
701 | ||
1fd7a697 TH |
702 | init_port(ap); |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
1fd7a697 | 707 | static struct ata_port_operations inic_port_ops = { |
f8b0685a | 708 | .inherits = &sata_port_ops, |
1fd7a697 | 709 | |
b3f677e5 | 710 | .check_atapi_dma = inic_check_atapi_dma, |
3ad400a9 | 711 | .qc_prep = inic_qc_prep, |
1fd7a697 | 712 | .qc_issue = inic_qc_issue, |
364fac0e | 713 | .qc_fill_rtf = inic_qc_fill_rtf, |
1fd7a697 TH |
714 | |
715 | .freeze = inic_freeze, | |
716 | .thaw = inic_thaw, | |
a1efdaba | 717 | .hardreset = inic_hardreset, |
1fd7a697 TH |
718 | .error_handler = inic_error_handler, |
719 | .post_internal_cmd = inic_post_internal_cmd, | |
1fd7a697 | 720 | |
029cfd6b TH |
721 | .scr_read = inic_scr_read, |
722 | .scr_write = inic_scr_write, | |
1fd7a697 | 723 | |
029cfd6b | 724 | .port_resume = inic_port_resume, |
1fd7a697 | 725 | .port_start = inic_port_start, |
1fd7a697 TH |
726 | }; |
727 | ||
728 | static struct ata_port_info inic_port_info = { | |
1fd7a697 | 729 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
14bdef98 EIB |
730 | .pio_mask = ATA_PIO4, |
731 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 732 | .udma_mask = ATA_UDMA6, |
1fd7a697 TH |
733 | .port_ops = &inic_port_ops |
734 | }; | |
735 | ||
736 | static int init_controller(void __iomem *mmio_base, u16 hctl) | |
737 | { | |
738 | int i; | |
739 | u16 val; | |
740 | ||
741 | hctl &= ~HCTL_KNOWN_BITS; | |
742 | ||
743 | /* Soft reset whole controller. Spec says reset duration is 3 | |
744 | * PCI clocks, be generous and give it 10ms. | |
745 | */ | |
746 | writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); | |
747 | readw(mmio_base + HOST_CTL); /* flush */ | |
748 | ||
749 | for (i = 0; i < 10; i++) { | |
750 | msleep(1); | |
751 | val = readw(mmio_base + HOST_CTL); | |
752 | if (!(val & HCTL_SOFTRST)) | |
753 | break; | |
754 | } | |
755 | ||
756 | if (val & HCTL_SOFTRST) | |
757 | return -EIO; | |
758 | ||
759 | /* mask all interrupts and reset ports */ | |
760 | for (i = 0; i < NR_PORTS; i++) { | |
761 | void __iomem *port_base = mmio_base + i * PORT_SIZE; | |
762 | ||
763 | writeb(0xff, port_base + PORT_IRQ_MASK); | |
764 | inic_reset_port(port_base); | |
765 | } | |
766 | ||
767 | /* port IRQ is masked now, unmask global IRQ */ | |
768 | writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); | |
769 | val = readw(mmio_base + HOST_IRQ_MASK); | |
770 | val &= ~(HIRQ_PORT0 | HIRQ_PORT1); | |
771 | writew(val, mmio_base + HOST_IRQ_MASK); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
438ac6d5 | 776 | #ifdef CONFIG_PM |
1fd7a697 TH |
777 | static int inic_pci_device_resume(struct pci_dev *pdev) |
778 | { | |
779 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
780 | struct inic_host_priv *hpriv = host->private_data; | |
1fd7a697 TH |
781 | int rc; |
782 | ||
5aea408d DM |
783 | rc = ata_pci_device_do_resume(pdev); |
784 | if (rc) | |
785 | return rc; | |
1fd7a697 TH |
786 | |
787 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
ba66b242 | 788 | rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); |
1fd7a697 TH |
789 | if (rc) |
790 | return rc; | |
791 | } | |
792 | ||
793 | ata_host_resume(host); | |
794 | ||
795 | return 0; | |
796 | } | |
438ac6d5 | 797 | #endif |
1fd7a697 TH |
798 | |
799 | static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
800 | { | |
4447d351 TH |
801 | const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; |
802 | struct ata_host *host; | |
1fd7a697 | 803 | struct inic_host_priv *hpriv; |
0d5ff566 | 804 | void __iomem * const *iomap; |
ba66b242 | 805 | int mmio_bar; |
1fd7a697 TH |
806 | int i, rc; |
807 | ||
06296a1e | 808 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1fd7a697 | 809 | |
4447d351 TH |
810 | /* alloc host */ |
811 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS); | |
812 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
813 | if (!host || !hpriv) | |
814 | return -ENOMEM; | |
815 | ||
816 | host->private_data = hpriv; | |
817 | ||
ba66b242 TH |
818 | /* Acquire resources and fill host. Note that PCI and cardbus |
819 | * use different BARs. | |
820 | */ | |
24dc5f33 | 821 | rc = pcim_enable_device(pdev); |
1fd7a697 TH |
822 | if (rc) |
823 | return rc; | |
824 | ||
ba66b242 TH |
825 | if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM) |
826 | mmio_bar = MMIO_BAR_PCI; | |
827 | else | |
828 | mmio_bar = MMIO_BAR_CARDBUS; | |
829 | ||
830 | rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME); | |
0d5ff566 TH |
831 | if (rc) |
832 | return rc; | |
4447d351 | 833 | host->iomap = iomap = pcim_iomap_table(pdev); |
ba66b242 TH |
834 | hpriv->mmio_base = iomap[mmio_bar]; |
835 | hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL); | |
4447d351 TH |
836 | |
837 | for (i = 0; i < NR_PORTS; i++) { | |
cbcdd875 | 838 | struct ata_port *ap = host->ports[i]; |
cbcdd875 | 839 | |
ba66b242 TH |
840 | ata_port_pbar_desc(ap, mmio_bar, -1, "mmio"); |
841 | ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port"); | |
4447d351 TH |
842 | } |
843 | ||
1fd7a697 | 844 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ |
284901a9 | 845 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1fd7a697 | 846 | if (rc) { |
a44fec1f | 847 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
24dc5f33 | 848 | return rc; |
1fd7a697 TH |
849 | } |
850 | ||
284901a9 | 851 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1fd7a697 | 852 | if (rc) { |
a44fec1f | 853 | dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n"); |
24dc5f33 | 854 | return rc; |
1fd7a697 TH |
855 | } |
856 | ||
b7d8629f FT |
857 | /* |
858 | * This controller is braindamaged. dma_boundary is 0xffff | |
859 | * like others but it will lock up the whole machine HARD if | |
860 | * 65536 byte PRD entry is fed. Reduce maximum segment size. | |
861 | */ | |
862 | rc = pci_set_dma_max_seg_size(pdev, 65536 - 512); | |
863 | if (rc) { | |
a44fec1f | 864 | dev_err(&pdev->dev, "failed to set the maximum segment size\n"); |
b7d8629f FT |
865 | return rc; |
866 | } | |
867 | ||
ba66b242 | 868 | rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); |
1fd7a697 | 869 | if (rc) { |
a44fec1f | 870 | dev_err(&pdev->dev, "failed to initialize controller\n"); |
24dc5f33 | 871 | return rc; |
1fd7a697 TH |
872 | } |
873 | ||
874 | pci_set_master(pdev); | |
4447d351 TH |
875 | return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED, |
876 | &inic_sht); | |
1fd7a697 TH |
877 | } |
878 | ||
879 | static const struct pci_device_id inic_pci_tbl[] = { | |
880 | { PCI_VDEVICE(INIT, 0x1622), }, | |
881 | { }, | |
882 | }; | |
883 | ||
884 | static struct pci_driver inic_pci_driver = { | |
885 | .name = DRV_NAME, | |
886 | .id_table = inic_pci_tbl, | |
438ac6d5 | 887 | #ifdef CONFIG_PM |
1fd7a697 TH |
888 | .suspend = ata_pci_device_suspend, |
889 | .resume = inic_pci_device_resume, | |
438ac6d5 | 890 | #endif |
1fd7a697 TH |
891 | .probe = inic_init_one, |
892 | .remove = ata_pci_remove_one, | |
893 | }; | |
894 | ||
2fc75da0 | 895 | module_pci_driver(inic_pci_driver); |
1fd7a697 TH |
896 | |
897 | MODULE_AUTHOR("Tejun Heo"); | |
898 | MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); | |
899 | MODULE_LICENSE("GPL v2"); | |
900 | MODULE_DEVICE_TABLE(pci, inic_pci_tbl); | |
901 | MODULE_VERSION(DRV_VERSION); |