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1fd7a697 TH |
1 | /* |
2 | * sata_inic162x.c - Driver for Initio 162x SATA controllers | |
3 | * | |
4 | * Copyright 2006 SUSE Linux Products GmbH | |
5 | * Copyright 2006 Tejun Heo <teheo@novell.com> | |
6 | * | |
7 | * This file is released under GPL v2. | |
8 | * | |
9 | * This controller is eccentric and easily locks up if something isn't | |
10 | * right. Documentation is available at initio's website but it only | |
11 | * documents registers (not programming model). | |
12 | * | |
22bfc6d5 TH |
13 | * This driver has interesting history. The first version was written |
14 | * from the documentation and a 2.4 IDE driver posted on a Taiwan | |
15 | * company, which didn't use any IDMA features and couldn't handle | |
16 | * LBA48. The resulting driver couldn't handle LBA48 devices either | |
17 | * making it pretty useless. | |
18 | * | |
19 | * After a while, initio picked the driver up, renamed it to | |
20 | * sata_initio162x, updated it to use IDMA for ATA DMA commands and | |
21 | * posted it on their website. It only used ATA_PROT_DMA for IDMA and | |
22 | * attaching both devices and issuing IDMA and !IDMA commands | |
23 | * simultaneously broke it due to PIRQ masking interaction but it did | |
24 | * show how to use the IDMA (ADMA + some initio specific twists) | |
25 | * engine. | |
26 | * | |
27 | * Then, I picked up their changes again and here's the usable driver | |
28 | * which uses IDMA for everything. Everything works now including | |
29 | * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some | |
30 | * issues tho. Result Tf is not resported properly, NCQ isn't | |
31 | * supported yet and CD/DVD writing works with DMA assisted PIO | |
32 | * protocol (which, for native SATA devices, shouldn't cause any | |
33 | * noticeable difference). | |
34 | * | |
35 | * Anyways, so, here's finally a working driver for inic162x. Enjoy! | |
36 | * | |
37 | * initio: If you guys wanna improve the driver regarding result TF | |
38 | * access and other stuff, please feel free to contact me. I'll be | |
39 | * happy to assist. | |
1fd7a697 TH |
40 | */ |
41 | ||
42 | #include <linux/kernel.h> | |
43 | #include <linux/module.h> | |
44 | #include <linux/pci.h> | |
45 | #include <scsi/scsi_host.h> | |
46 | #include <linux/libata.h> | |
47 | #include <linux/blkdev.h> | |
48 | #include <scsi/scsi_device.h> | |
49 | ||
50 | #define DRV_NAME "sata_inic162x" | |
22bfc6d5 | 51 | #define DRV_VERSION "0.4" |
1fd7a697 TH |
52 | |
53 | enum { | |
ba66b242 TH |
54 | MMIO_BAR_PCI = 5, |
55 | MMIO_BAR_CARDBUS = 1, | |
1fd7a697 TH |
56 | |
57 | NR_PORTS = 2, | |
58 | ||
3ad400a9 TH |
59 | IDMA_CPB_TBL_SIZE = 4 * 32, |
60 | ||
61 | INIC_DMA_BOUNDARY = 0xffffff, | |
62 | ||
b0dd9b8e | 63 | HOST_ACTRL = 0x08, |
1fd7a697 TH |
64 | HOST_CTL = 0x7c, |
65 | HOST_STAT = 0x7e, | |
66 | HOST_IRQ_STAT = 0xbc, | |
67 | HOST_IRQ_MASK = 0xbe, | |
68 | ||
69 | PORT_SIZE = 0x40, | |
70 | ||
71 | /* registers for ATA TF operation */ | |
b0dd9b8e TH |
72 | PORT_TF_DATA = 0x00, |
73 | PORT_TF_FEATURE = 0x01, | |
74 | PORT_TF_NSECT = 0x02, | |
75 | PORT_TF_LBAL = 0x03, | |
76 | PORT_TF_LBAM = 0x04, | |
77 | PORT_TF_LBAH = 0x05, | |
78 | PORT_TF_DEVICE = 0x06, | |
79 | PORT_TF_COMMAND = 0x07, | |
80 | PORT_TF_ALT_STAT = 0x08, | |
1fd7a697 TH |
81 | PORT_IRQ_STAT = 0x09, |
82 | PORT_IRQ_MASK = 0x0a, | |
83 | PORT_PRD_CTL = 0x0b, | |
84 | PORT_PRD_ADDR = 0x0c, | |
85 | PORT_PRD_XFERLEN = 0x10, | |
b0dd9b8e TH |
86 | PORT_CPB_CPBLAR = 0x18, |
87 | PORT_CPB_PTQFIFO = 0x1c, | |
1fd7a697 TH |
88 | |
89 | /* IDMA register */ | |
90 | PORT_IDMA_CTL = 0x14, | |
b0dd9b8e TH |
91 | PORT_IDMA_STAT = 0x16, |
92 | ||
93 | PORT_RPQ_FIFO = 0x1e, | |
94 | PORT_RPQ_CNT = 0x1f, | |
1fd7a697 TH |
95 | |
96 | PORT_SCR = 0x20, | |
97 | ||
98 | /* HOST_CTL bits */ | |
99 | HCTL_IRQOFF = (1 << 8), /* global IRQ off */ | |
b0dd9b8e TH |
100 | HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */ |
101 | HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/ | |
102 | HCTL_PWRDWN = (1 << 12), /* power down PHYs */ | |
1fd7a697 TH |
103 | HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ |
104 | HCTL_RPGSEL = (1 << 15), /* register page select */ | |
105 | ||
106 | HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | | |
107 | HCTL_RPGSEL, | |
108 | ||
109 | /* HOST_IRQ_(STAT|MASK) bits */ | |
110 | HIRQ_PORT0 = (1 << 0), | |
111 | HIRQ_PORT1 = (1 << 1), | |
112 | HIRQ_SOFT = (1 << 14), | |
113 | HIRQ_GLOBAL = (1 << 15), /* STAT only */ | |
114 | ||
115 | /* PORT_IRQ_(STAT|MASK) bits */ | |
116 | PIRQ_OFFLINE = (1 << 0), /* device unplugged */ | |
117 | PIRQ_ONLINE = (1 << 1), /* device plugged */ | |
118 | PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ | |
119 | PIRQ_FATAL = (1 << 3), /* fatal error */ | |
120 | PIRQ_ATA = (1 << 4), /* ATA interrupt */ | |
121 | PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ | |
122 | PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ | |
123 | ||
124 | PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, | |
f8b0685a | 125 | PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA, |
1fd7a697 TH |
126 | PIRQ_MASK_FREEZE = 0xff, |
127 | ||
128 | /* PORT_PRD_CTL bits */ | |
129 | PRD_CTL_START = (1 << 0), | |
130 | PRD_CTL_WR = (1 << 3), | |
131 | PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ | |
132 | ||
133 | /* PORT_IDMA_CTL bits */ | |
134 | IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ | |
135 | IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ | |
136 | IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ | |
137 | IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ | |
b0dd9b8e TH |
138 | |
139 | /* PORT_IDMA_STAT bits */ | |
140 | IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */ | |
141 | IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */ | |
142 | IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */ | |
143 | IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */ | |
144 | IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */ | |
145 | IDMA_STAT_PSD = (1 << 6), /* ADMA pause */ | |
146 | IDMA_STAT_DONE = (1 << 7), /* ADMA done */ | |
147 | ||
148 | IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR, | |
149 | ||
150 | /* CPB Control Flags*/ | |
151 | CPB_CTL_VALID = (1 << 0), /* CPB valid */ | |
152 | CPB_CTL_QUEUED = (1 << 1), /* queued command */ | |
153 | CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */ | |
154 | CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */ | |
155 | CPB_CTL_DEVDIR = (1 << 4), /* device direction control */ | |
156 | ||
157 | /* CPB Response Flags */ | |
158 | CPB_RESP_DONE = (1 << 0), /* ATA command complete */ | |
159 | CPB_RESP_REL = (1 << 1), /* ATA release */ | |
160 | CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */ | |
161 | CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */ | |
162 | CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */ | |
163 | CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */ | |
164 | CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */ | |
165 | CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */ | |
166 | ||
167 | /* PRD Control Flags */ | |
168 | PRD_DRAIN = (1 << 1), /* ignore data excess */ | |
169 | PRD_CDB = (1 << 2), /* atapi packet command pointer */ | |
170 | PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */ | |
171 | PRD_DMA = (1 << 4), /* data transfer method */ | |
172 | PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */ | |
173 | PRD_IOM = (1 << 6), /* io/memory transfer */ | |
174 | PRD_END = (1 << 7), /* APRD chain end */ | |
1fd7a697 TH |
175 | }; |
176 | ||
3ad400a9 TH |
177 | /* Comman Parameter Block */ |
178 | struct inic_cpb { | |
179 | u8 resp_flags; /* Response Flags */ | |
180 | u8 error; /* ATA Error */ | |
181 | u8 status; /* ATA Status */ | |
182 | u8 ctl_flags; /* Control Flags */ | |
183 | __le32 len; /* Total Transfer Length */ | |
184 | __le32 prd; /* First PRD pointer */ | |
185 | u8 rsvd[4]; | |
186 | /* 16 bytes */ | |
187 | u8 feature; /* ATA Feature */ | |
188 | u8 hob_feature; /* ATA Ex. Feature */ | |
189 | u8 device; /* ATA Device/Head */ | |
190 | u8 mirctl; /* Mirror Control */ | |
191 | u8 nsect; /* ATA Sector Count */ | |
192 | u8 hob_nsect; /* ATA Ex. Sector Count */ | |
193 | u8 lbal; /* ATA Sector Number */ | |
194 | u8 hob_lbal; /* ATA Ex. Sector Number */ | |
195 | u8 lbam; /* ATA Cylinder Low */ | |
196 | u8 hob_lbam; /* ATA Ex. Cylinder Low */ | |
197 | u8 lbah; /* ATA Cylinder High */ | |
198 | u8 hob_lbah; /* ATA Ex. Cylinder High */ | |
199 | u8 command; /* ATA Command */ | |
200 | u8 ctl; /* ATA Control */ | |
201 | u8 slave_error; /* Slave ATA Error */ | |
202 | u8 slave_status; /* Slave ATA Status */ | |
203 | /* 32 bytes */ | |
204 | } __packed; | |
205 | ||
206 | /* Physical Region Descriptor */ | |
207 | struct inic_prd { | |
208 | __le32 mad; /* Physical Memory Address */ | |
209 | __le16 len; /* Transfer Length */ | |
210 | u8 rsvd; | |
211 | u8 flags; /* Control Flags */ | |
212 | } __packed; | |
213 | ||
214 | struct inic_pkt { | |
215 | struct inic_cpb cpb; | |
b3f677e5 TH |
216 | struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */ |
217 | u8 cdb[ATAPI_CDB_LEN]; | |
3ad400a9 TH |
218 | } __packed; |
219 | ||
1fd7a697 | 220 | struct inic_host_priv { |
ba66b242 | 221 | void __iomem *mmio_base; |
36f674d9 | 222 | u16 cached_hctl; |
1fd7a697 TH |
223 | }; |
224 | ||
225 | struct inic_port_priv { | |
3ad400a9 TH |
226 | struct inic_pkt *pkt; |
227 | dma_addr_t pkt_dma; | |
228 | u32 *cpb_tbl; | |
229 | dma_addr_t cpb_tbl_dma; | |
1fd7a697 TH |
230 | }; |
231 | ||
1fd7a697 | 232 | static struct scsi_host_template inic_sht = { |
ab5b0235 TH |
233 | ATA_BASE_SHT(DRV_NAME), |
234 | .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */ | |
3ad400a9 | 235 | .dma_boundary = INIC_DMA_BOUNDARY, |
1fd7a697 TH |
236 | }; |
237 | ||
238 | static const int scr_map[] = { | |
239 | [SCR_STATUS] = 0, | |
240 | [SCR_ERROR] = 1, | |
241 | [SCR_CONTROL] = 2, | |
242 | }; | |
243 | ||
5796d1c4 | 244 | static void __iomem *inic_port_base(struct ata_port *ap) |
1fd7a697 | 245 | { |
ba66b242 TH |
246 | struct inic_host_priv *hpriv = ap->host->private_data; |
247 | ||
248 | return hpriv->mmio_base + ap->port_no * PORT_SIZE; | |
1fd7a697 TH |
249 | } |
250 | ||
1fd7a697 TH |
251 | static void inic_reset_port(void __iomem *port_base) |
252 | { | |
253 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
1fd7a697 | 254 | |
f8b0685a TH |
255 | /* stop IDMA engine */ |
256 | readw(idma_ctl); /* flush */ | |
257 | msleep(1); | |
1fd7a697 TH |
258 | |
259 | /* mask IRQ and assert reset */ | |
f8b0685a | 260 | writew(IDMA_CTL_RST_IDMA, idma_ctl); |
1fd7a697 | 261 | readw(idma_ctl); /* flush */ |
1fd7a697 TH |
262 | msleep(1); |
263 | ||
264 | /* release reset */ | |
f8b0685a | 265 | writew(0, idma_ctl); |
1fd7a697 TH |
266 | |
267 | /* clear irq */ | |
268 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
1fd7a697 TH |
269 | } |
270 | ||
da3dbb17 | 271 | static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val) |
1fd7a697 | 272 | { |
f8b0685a | 273 | void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR; |
1fd7a697 | 274 | void __iomem *addr; |
1fd7a697 TH |
275 | |
276 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 277 | return -EINVAL; |
1fd7a697 TH |
278 | |
279 | addr = scr_addr + scr_map[sc_reg] * 4; | |
da3dbb17 | 280 | *val = readl(scr_addr + scr_map[sc_reg] * 4); |
1fd7a697 TH |
281 | |
282 | /* this controller has stuck DIAG.N, ignore it */ | |
283 | if (sc_reg == SCR_ERROR) | |
da3dbb17 TH |
284 | *val &= ~SERR_PHYRDY_CHG; |
285 | return 0; | |
1fd7a697 TH |
286 | } |
287 | ||
da3dbb17 | 288 | static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
1fd7a697 | 289 | { |
f8b0685a | 290 | void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR; |
1fd7a697 TH |
291 | |
292 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 293 | return -EINVAL; |
1fd7a697 | 294 | |
1fd7a697 | 295 | writel(val, scr_addr + scr_map[sc_reg] * 4); |
da3dbb17 | 296 | return 0; |
1fd7a697 TH |
297 | } |
298 | ||
3ad400a9 | 299 | static void inic_stop_idma(struct ata_port *ap) |
1fd7a697 TH |
300 | { |
301 | void __iomem *port_base = inic_port_base(ap); | |
3ad400a9 TH |
302 | |
303 | readb(port_base + PORT_RPQ_FIFO); | |
304 | readb(port_base + PORT_RPQ_CNT); | |
305 | writew(0, port_base + PORT_IDMA_CTL); | |
306 | } | |
307 | ||
308 | static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat) | |
309 | { | |
9af5c9c9 | 310 | struct ata_eh_info *ehi = &ap->link.eh_info; |
3ad400a9 TH |
311 | struct inic_port_priv *pp = ap->private_data; |
312 | struct inic_cpb *cpb = &pp->pkt->cpb; | |
313 | bool freeze = false; | |
314 | ||
315 | ata_ehi_clear_desc(ehi); | |
316 | ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x", | |
317 | irq_stat, idma_stat); | |
318 | ||
319 | inic_stop_idma(ap); | |
320 | ||
321 | if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { | |
322 | ata_ehi_push_desc(ehi, "hotplug"); | |
323 | ata_ehi_hotplugged(ehi); | |
324 | freeze = true; | |
325 | } | |
326 | ||
327 | if (idma_stat & IDMA_STAT_PERR) { | |
328 | ata_ehi_push_desc(ehi, "PCI error"); | |
329 | freeze = true; | |
330 | } | |
331 | ||
332 | if (idma_stat & IDMA_STAT_CPBERR) { | |
333 | ata_ehi_push_desc(ehi, "CPB error"); | |
334 | ||
335 | if (cpb->resp_flags & CPB_RESP_IGNORED) { | |
336 | __ata_ehi_push_desc(ehi, " ignored"); | |
337 | ehi->err_mask |= AC_ERR_INVALID; | |
338 | freeze = true; | |
339 | } | |
340 | ||
341 | if (cpb->resp_flags & CPB_RESP_ATA_ERR) | |
342 | ehi->err_mask |= AC_ERR_DEV; | |
343 | ||
344 | if (cpb->resp_flags & CPB_RESP_SPURIOUS) { | |
345 | __ata_ehi_push_desc(ehi, " spurious-intr"); | |
346 | ehi->err_mask |= AC_ERR_HSM; | |
347 | freeze = true; | |
348 | } | |
349 | ||
350 | if (cpb->resp_flags & | |
351 | (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) { | |
352 | __ata_ehi_push_desc(ehi, " data-over/underflow"); | |
353 | ehi->err_mask |= AC_ERR_HSM; | |
354 | freeze = true; | |
355 | } | |
356 | } | |
357 | ||
358 | if (freeze) | |
359 | ata_port_freeze(ap); | |
360 | else | |
361 | ata_port_abort(ap); | |
362 | } | |
363 | ||
364 | static void inic_host_intr(struct ata_port *ap) | |
365 | { | |
366 | void __iomem *port_base = inic_port_base(ap); | |
367 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1fd7a697 | 368 | u8 irq_stat; |
3ad400a9 | 369 | u16 idma_stat; |
1fd7a697 | 370 | |
3ad400a9 | 371 | /* read and clear IRQ status */ |
1fd7a697 TH |
372 | irq_stat = readb(port_base + PORT_IRQ_STAT); |
373 | writeb(irq_stat, port_base + PORT_IRQ_STAT); | |
3ad400a9 TH |
374 | idma_stat = readw(port_base + PORT_IDMA_STAT); |
375 | ||
376 | if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR))) | |
377 | inic_host_err_intr(ap, irq_stat, idma_stat); | |
378 | ||
f8b0685a | 379 | if (unlikely(!qc)) |
3ad400a9 | 380 | goto spurious; |
3ad400a9 | 381 | |
b3f677e5 TH |
382 | if (likely(idma_stat & IDMA_STAT_DONE)) { |
383 | inic_stop_idma(ap); | |
1fd7a697 | 384 | |
b3f677e5 TH |
385 | /* Depending on circumstances, device error |
386 | * isn't reported by IDMA, check it explicitly. | |
387 | */ | |
388 | if (unlikely(readb(port_base + PORT_TF_COMMAND) & | |
389 | (ATA_DF | ATA_ERR))) | |
390 | qc->err_mask |= AC_ERR_DEV; | |
1fd7a697 | 391 | |
b3f677e5 TH |
392 | ata_qc_complete(qc); |
393 | return; | |
1fd7a697 TH |
394 | } |
395 | ||
3ad400a9 | 396 | spurious: |
f8b0685a TH |
397 | ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: " |
398 | "cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n", | |
399 | qc ? qc->tf.command : 0xff, irq_stat, idma_stat); | |
1fd7a697 TH |
400 | } |
401 | ||
402 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) | |
403 | { | |
404 | struct ata_host *host = dev_instance; | |
ba66b242 | 405 | struct inic_host_priv *hpriv = host->private_data; |
1fd7a697 TH |
406 | u16 host_irq_stat; |
407 | int i, handled = 0;; | |
408 | ||
ba66b242 | 409 | host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); |
1fd7a697 TH |
410 | |
411 | if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) | |
412 | goto out; | |
413 | ||
414 | spin_lock(&host->lock); | |
415 | ||
416 | for (i = 0; i < NR_PORTS; i++) { | |
417 | struct ata_port *ap = host->ports[i]; | |
418 | ||
419 | if (!(host_irq_stat & (HIRQ_PORT0 << i))) | |
420 | continue; | |
421 | ||
422 | if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) { | |
423 | inic_host_intr(ap); | |
424 | handled++; | |
425 | } else { | |
426 | if (ata_ratelimit()) | |
427 | dev_printk(KERN_ERR, host->dev, "interrupt " | |
428 | "from disabled port %d (0x%x)\n", | |
429 | i, host_irq_stat); | |
430 | } | |
431 | } | |
432 | ||
433 | spin_unlock(&host->lock); | |
434 | ||
435 | out: | |
436 | return IRQ_RETVAL(handled); | |
437 | } | |
438 | ||
b3f677e5 TH |
439 | static int inic_check_atapi_dma(struct ata_queued_cmd *qc) |
440 | { | |
441 | /* For some reason ATAPI_PROT_DMA doesn't work for some | |
442 | * commands including writes and other misc ops. Use PIO | |
443 | * protocol instead, which BTW is driven by the DMA engine | |
444 | * anyway, so it shouldn't make much difference for native | |
445 | * SATA devices. | |
446 | */ | |
447 | if (atapi_cmd_type(qc->cdb[0]) == READ) | |
448 | return 0; | |
449 | return 1; | |
450 | } | |
451 | ||
3ad400a9 TH |
452 | static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc) |
453 | { | |
454 | struct scatterlist *sg; | |
455 | unsigned int si; | |
049e8e04 | 456 | u8 flags = 0; |
3ad400a9 TH |
457 | |
458 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
459 | flags |= PRD_WRITE; | |
460 | ||
049e8e04 TH |
461 | if (ata_is_dma(qc->tf.protocol)) |
462 | flags |= PRD_DMA; | |
463 | ||
3ad400a9 TH |
464 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
465 | prd->mad = cpu_to_le32(sg_dma_address(sg)); | |
466 | prd->len = cpu_to_le16(sg_dma_len(sg)); | |
467 | prd->flags = flags; | |
468 | prd++; | |
469 | } | |
470 | ||
471 | WARN_ON(!si); | |
472 | prd[-1].flags |= PRD_END; | |
473 | } | |
474 | ||
475 | static void inic_qc_prep(struct ata_queued_cmd *qc) | |
476 | { | |
477 | struct inic_port_priv *pp = qc->ap->private_data; | |
478 | struct inic_pkt *pkt = pp->pkt; | |
479 | struct inic_cpb *cpb = &pkt->cpb; | |
480 | struct inic_prd *prd = pkt->prd; | |
049e8e04 TH |
481 | bool is_atapi = ata_is_atapi(qc->tf.protocol); |
482 | bool is_data = ata_is_data(qc->tf.protocol); | |
b3f677e5 | 483 | unsigned int cdb_len = 0; |
3ad400a9 TH |
484 | |
485 | VPRINTK("ENTER\n"); | |
486 | ||
049e8e04 | 487 | if (is_atapi) |
b3f677e5 | 488 | cdb_len = qc->dev->cdb_len; |
3ad400a9 TH |
489 | |
490 | /* prepare packet, based on initio driver */ | |
491 | memset(pkt, 0, sizeof(struct inic_pkt)); | |
492 | ||
049e8e04 | 493 | cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN; |
b3f677e5 | 494 | if (is_atapi || is_data) |
049e8e04 | 495 | cpb->ctl_flags |= CPB_CTL_DATA; |
3ad400a9 | 496 | |
b3f677e5 | 497 | cpb->len = cpu_to_le32(qc->nbytes + cdb_len); |
3ad400a9 TH |
498 | cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd)); |
499 | ||
500 | cpb->device = qc->tf.device; | |
501 | cpb->feature = qc->tf.feature; | |
502 | cpb->nsect = qc->tf.nsect; | |
503 | cpb->lbal = qc->tf.lbal; | |
504 | cpb->lbam = qc->tf.lbam; | |
505 | cpb->lbah = qc->tf.lbah; | |
506 | ||
507 | if (qc->tf.flags & ATA_TFLAG_LBA48) { | |
508 | cpb->hob_feature = qc->tf.hob_feature; | |
509 | cpb->hob_nsect = qc->tf.hob_nsect; | |
510 | cpb->hob_lbal = qc->tf.hob_lbal; | |
511 | cpb->hob_lbam = qc->tf.hob_lbam; | |
512 | cpb->hob_lbah = qc->tf.hob_lbah; | |
513 | } | |
514 | ||
515 | cpb->command = qc->tf.command; | |
516 | /* don't load ctl - dunno why. it's like that in the initio driver */ | |
517 | ||
b3f677e5 TH |
518 | /* setup PRD for CDB */ |
519 | if (is_atapi) { | |
520 | memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN); | |
521 | prd->mad = cpu_to_le32(pp->pkt_dma + | |
522 | offsetof(struct inic_pkt, cdb)); | |
523 | prd->len = cpu_to_le16(cdb_len); | |
524 | prd->flags = PRD_CDB | PRD_WRITE; | |
525 | if (!is_data) | |
526 | prd->flags |= PRD_END; | |
527 | prd++; | |
528 | } | |
529 | ||
3ad400a9 | 530 | /* setup sg table */ |
049e8e04 TH |
531 | if (is_data) |
532 | inic_fill_sg(prd, qc); | |
3ad400a9 TH |
533 | |
534 | pp->cpb_tbl[0] = pp->pkt_dma; | |
535 | } | |
536 | ||
1fd7a697 TH |
537 | static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) |
538 | { | |
539 | struct ata_port *ap = qc->ap; | |
3ad400a9 | 540 | void __iomem *port_base = inic_port_base(ap); |
1fd7a697 | 541 | |
b3f677e5 TH |
542 | /* fire up the ADMA engine */ |
543 | writew(HCTL_FTHD0, port_base + HOST_CTL); | |
544 | writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL); | |
545 | writeb(0, port_base + PORT_CPB_PTQFIFO); | |
1fd7a697 | 546 | |
b3f677e5 | 547 | return 0; |
1fd7a697 TH |
548 | } |
549 | ||
364fac0e TH |
550 | static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
551 | { | |
552 | void __iomem *port_base = inic_port_base(ap); | |
553 | ||
554 | tf->feature = readb(port_base + PORT_TF_FEATURE); | |
555 | tf->nsect = readb(port_base + PORT_TF_NSECT); | |
556 | tf->lbal = readb(port_base + PORT_TF_LBAL); | |
557 | tf->lbam = readb(port_base + PORT_TF_LBAM); | |
558 | tf->lbah = readb(port_base + PORT_TF_LBAH); | |
559 | tf->device = readb(port_base + PORT_TF_DEVICE); | |
560 | tf->command = readb(port_base + PORT_TF_COMMAND); | |
561 | } | |
562 | ||
563 | static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc) | |
564 | { | |
565 | struct ata_taskfile *rtf = &qc->result_tf; | |
566 | struct ata_taskfile tf; | |
567 | ||
568 | /* FIXME: Except for status and error, result TF access | |
569 | * doesn't work. I tried reading from BAR0/2, CPB and BAR5. | |
570 | * None works regardless of which command interface is used. | |
571 | * For now return true iff status indicates device error. | |
572 | * This means that we're reporting bogus sector for RW | |
573 | * failures. Eeekk.... | |
574 | */ | |
575 | inic_tf_read(qc->ap, &tf); | |
576 | ||
577 | if (!(tf.command & ATA_ERR)) | |
578 | return false; | |
579 | ||
580 | rtf->command = tf.command; | |
581 | rtf->feature = tf.feature; | |
582 | return true; | |
583 | } | |
584 | ||
1fd7a697 TH |
585 | static void inic_freeze(struct ata_port *ap) |
586 | { | |
587 | void __iomem *port_base = inic_port_base(ap); | |
588 | ||
ab5b0235 | 589 | writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK); |
1fd7a697 | 590 | writeb(0xff, port_base + PORT_IRQ_STAT); |
1fd7a697 TH |
591 | } |
592 | ||
593 | static void inic_thaw(struct ata_port *ap) | |
594 | { | |
595 | void __iomem *port_base = inic_port_base(ap); | |
596 | ||
1fd7a697 | 597 | writeb(0xff, port_base + PORT_IRQ_STAT); |
ab5b0235 | 598 | writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK); |
1fd7a697 TH |
599 | } |
600 | ||
364fac0e TH |
601 | static int inic_check_ready(struct ata_link *link) |
602 | { | |
603 | void __iomem *port_base = inic_port_base(link->ap); | |
604 | ||
605 | return ata_check_ready(readb(port_base + PORT_TF_COMMAND)); | |
606 | } | |
607 | ||
1fd7a697 TH |
608 | /* |
609 | * SRST and SControl hardreset don't give valid signature on this | |
610 | * controller. Only controller specific hardreset mechanism works. | |
611 | */ | |
cc0680a5 | 612 | static int inic_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 613 | unsigned long deadline) |
1fd7a697 | 614 | { |
cc0680a5 | 615 | struct ata_port *ap = link->ap; |
1fd7a697 TH |
616 | void __iomem *port_base = inic_port_base(ap); |
617 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
cc0680a5 | 618 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
1fd7a697 TH |
619 | int rc; |
620 | ||
621 | /* hammer it into sane state */ | |
622 | inic_reset_port(port_base); | |
623 | ||
f8b0685a | 624 | writew(IDMA_CTL_RST_ATA, idma_ctl); |
1fd7a697 TH |
625 | readw(idma_ctl); /* flush */ |
626 | msleep(1); | |
f8b0685a | 627 | writew(0, idma_ctl); |
1fd7a697 | 628 | |
cc0680a5 | 629 | rc = sata_link_resume(link, timing, deadline); |
1fd7a697 | 630 | if (rc) { |
cc0680a5 | 631 | ata_link_printk(link, KERN_WARNING, "failed to resume " |
fe334602 | 632 | "link after reset (errno=%d)\n", rc); |
1fd7a697 TH |
633 | return rc; |
634 | } | |
635 | ||
1fd7a697 | 636 | *class = ATA_DEV_NONE; |
cc0680a5 | 637 | if (ata_link_online(link)) { |
1fd7a697 TH |
638 | struct ata_taskfile tf; |
639 | ||
705e76be | 640 | /* wait for link to become ready */ |
364fac0e | 641 | rc = ata_wait_after_reset(link, deadline, inic_check_ready); |
9b89391c TH |
642 | /* link occupied, -ENODEV too is an error */ |
643 | if (rc) { | |
cc0680a5 | 644 | ata_link_printk(link, KERN_WARNING, "device not ready " |
d4b2bab4 TH |
645 | "after hardreset (errno=%d)\n", rc); |
646 | return rc; | |
1fd7a697 TH |
647 | } |
648 | ||
364fac0e | 649 | inic_tf_read(ap, &tf); |
1fd7a697 | 650 | *class = ata_dev_classify(&tf); |
1fd7a697 TH |
651 | } |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | static void inic_error_handler(struct ata_port *ap) | |
657 | { | |
658 | void __iomem *port_base = inic_port_base(ap); | |
1fd7a697 | 659 | |
1fd7a697 | 660 | inic_reset_port(port_base); |
a1efdaba | 661 | ata_std_error_handler(ap); |
1fd7a697 TH |
662 | } |
663 | ||
664 | static void inic_post_internal_cmd(struct ata_queued_cmd *qc) | |
665 | { | |
666 | /* make DMA engine forget about the failed command */ | |
a51d644a | 667 | if (qc->flags & ATA_QCFLAG_FAILED) |
1fd7a697 TH |
668 | inic_reset_port(inic_port_base(qc->ap)); |
669 | } | |
670 | ||
1fd7a697 TH |
671 | static void init_port(struct ata_port *ap) |
672 | { | |
673 | void __iomem *port_base = inic_port_base(ap); | |
3ad400a9 | 674 | struct inic_port_priv *pp = ap->private_data; |
1fd7a697 | 675 | |
3ad400a9 TH |
676 | /* clear packet and CPB table */ |
677 | memset(pp->pkt, 0, sizeof(struct inic_pkt)); | |
678 | memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE); | |
679 | ||
680 | /* setup PRD and CPB lookup table addresses */ | |
1fd7a697 | 681 | writel(ap->prd_dma, port_base + PORT_PRD_ADDR); |
3ad400a9 | 682 | writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR); |
1fd7a697 TH |
683 | } |
684 | ||
685 | static int inic_port_resume(struct ata_port *ap) | |
686 | { | |
687 | init_port(ap); | |
688 | return 0; | |
689 | } | |
690 | ||
691 | static int inic_port_start(struct ata_port *ap) | |
692 | { | |
3ad400a9 | 693 | struct device *dev = ap->host->dev; |
1fd7a697 | 694 | struct inic_port_priv *pp; |
1fd7a697 TH |
695 | int rc; |
696 | ||
697 | /* alloc and initialize private data */ | |
3ad400a9 | 698 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
1fd7a697 TH |
699 | if (!pp) |
700 | return -ENOMEM; | |
701 | ap->private_data = pp; | |
702 | ||
1fd7a697 TH |
703 | /* Alloc resources */ |
704 | rc = ata_port_start(ap); | |
36f674d9 | 705 | if (rc) |
1fd7a697 | 706 | return rc; |
1fd7a697 | 707 | |
3ad400a9 TH |
708 | pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt), |
709 | &pp->pkt_dma, GFP_KERNEL); | |
710 | if (!pp->pkt) | |
711 | return -ENOMEM; | |
712 | ||
713 | pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE, | |
714 | &pp->cpb_tbl_dma, GFP_KERNEL); | |
715 | if (!pp->cpb_tbl) | |
716 | return -ENOMEM; | |
717 | ||
1fd7a697 TH |
718 | init_port(ap); |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
1fd7a697 | 723 | static struct ata_port_operations inic_port_ops = { |
f8b0685a | 724 | .inherits = &sata_port_ops, |
1fd7a697 | 725 | |
b3f677e5 | 726 | .check_atapi_dma = inic_check_atapi_dma, |
3ad400a9 | 727 | .qc_prep = inic_qc_prep, |
1fd7a697 | 728 | .qc_issue = inic_qc_issue, |
364fac0e | 729 | .qc_fill_rtf = inic_qc_fill_rtf, |
1fd7a697 TH |
730 | |
731 | .freeze = inic_freeze, | |
732 | .thaw = inic_thaw, | |
a1efdaba | 733 | .hardreset = inic_hardreset, |
1fd7a697 TH |
734 | .error_handler = inic_error_handler, |
735 | .post_internal_cmd = inic_post_internal_cmd, | |
1fd7a697 | 736 | |
029cfd6b TH |
737 | .scr_read = inic_scr_read, |
738 | .scr_write = inic_scr_write, | |
1fd7a697 | 739 | |
029cfd6b | 740 | .port_resume = inic_port_resume, |
1fd7a697 | 741 | .port_start = inic_port_start, |
1fd7a697 TH |
742 | }; |
743 | ||
744 | static struct ata_port_info inic_port_info = { | |
1fd7a697 TH |
745 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
746 | .pio_mask = 0x1f, /* pio0-4 */ | |
747 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 748 | .udma_mask = ATA_UDMA6, |
1fd7a697 TH |
749 | .port_ops = &inic_port_ops |
750 | }; | |
751 | ||
752 | static int init_controller(void __iomem *mmio_base, u16 hctl) | |
753 | { | |
754 | int i; | |
755 | u16 val; | |
756 | ||
757 | hctl &= ~HCTL_KNOWN_BITS; | |
758 | ||
759 | /* Soft reset whole controller. Spec says reset duration is 3 | |
760 | * PCI clocks, be generous and give it 10ms. | |
761 | */ | |
762 | writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); | |
763 | readw(mmio_base + HOST_CTL); /* flush */ | |
764 | ||
765 | for (i = 0; i < 10; i++) { | |
766 | msleep(1); | |
767 | val = readw(mmio_base + HOST_CTL); | |
768 | if (!(val & HCTL_SOFTRST)) | |
769 | break; | |
770 | } | |
771 | ||
772 | if (val & HCTL_SOFTRST) | |
773 | return -EIO; | |
774 | ||
775 | /* mask all interrupts and reset ports */ | |
776 | for (i = 0; i < NR_PORTS; i++) { | |
777 | void __iomem *port_base = mmio_base + i * PORT_SIZE; | |
778 | ||
779 | writeb(0xff, port_base + PORT_IRQ_MASK); | |
780 | inic_reset_port(port_base); | |
781 | } | |
782 | ||
783 | /* port IRQ is masked now, unmask global IRQ */ | |
784 | writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); | |
785 | val = readw(mmio_base + HOST_IRQ_MASK); | |
786 | val &= ~(HIRQ_PORT0 | HIRQ_PORT1); | |
787 | writew(val, mmio_base + HOST_IRQ_MASK); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
438ac6d5 | 792 | #ifdef CONFIG_PM |
1fd7a697 TH |
793 | static int inic_pci_device_resume(struct pci_dev *pdev) |
794 | { | |
795 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
796 | struct inic_host_priv *hpriv = host->private_data; | |
1fd7a697 TH |
797 | int rc; |
798 | ||
5aea408d DM |
799 | rc = ata_pci_device_do_resume(pdev); |
800 | if (rc) | |
801 | return rc; | |
1fd7a697 TH |
802 | |
803 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
ba66b242 | 804 | rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); |
1fd7a697 TH |
805 | if (rc) |
806 | return rc; | |
807 | } | |
808 | ||
809 | ata_host_resume(host); | |
810 | ||
811 | return 0; | |
812 | } | |
438ac6d5 | 813 | #endif |
1fd7a697 TH |
814 | |
815 | static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
816 | { | |
817 | static int printed_version; | |
4447d351 TH |
818 | const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; |
819 | struct ata_host *host; | |
1fd7a697 | 820 | struct inic_host_priv *hpriv; |
0d5ff566 | 821 | void __iomem * const *iomap; |
ba66b242 | 822 | int mmio_bar; |
1fd7a697 TH |
823 | int i, rc; |
824 | ||
825 | if (!printed_version++) | |
826 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
827 | ||
4447d351 TH |
828 | /* alloc host */ |
829 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS); | |
830 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
831 | if (!host || !hpriv) | |
832 | return -ENOMEM; | |
833 | ||
834 | host->private_data = hpriv; | |
835 | ||
ba66b242 TH |
836 | /* Acquire resources and fill host. Note that PCI and cardbus |
837 | * use different BARs. | |
838 | */ | |
24dc5f33 | 839 | rc = pcim_enable_device(pdev); |
1fd7a697 TH |
840 | if (rc) |
841 | return rc; | |
842 | ||
ba66b242 TH |
843 | if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM) |
844 | mmio_bar = MMIO_BAR_PCI; | |
845 | else | |
846 | mmio_bar = MMIO_BAR_CARDBUS; | |
847 | ||
848 | rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME); | |
0d5ff566 TH |
849 | if (rc) |
850 | return rc; | |
4447d351 | 851 | host->iomap = iomap = pcim_iomap_table(pdev); |
ba66b242 TH |
852 | hpriv->mmio_base = iomap[mmio_bar]; |
853 | hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL); | |
4447d351 TH |
854 | |
855 | for (i = 0; i < NR_PORTS; i++) { | |
cbcdd875 | 856 | struct ata_port *ap = host->ports[i]; |
cbcdd875 | 857 | |
ba66b242 TH |
858 | ata_port_pbar_desc(ap, mmio_bar, -1, "mmio"); |
859 | ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port"); | |
4447d351 TH |
860 | } |
861 | ||
1fd7a697 TH |
862 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ |
863 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
864 | if (rc) { | |
865 | dev_printk(KERN_ERR, &pdev->dev, | |
866 | "32-bit DMA enable failed\n"); | |
24dc5f33 | 867 | return rc; |
1fd7a697 TH |
868 | } |
869 | ||
870 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
871 | if (rc) { | |
872 | dev_printk(KERN_ERR, &pdev->dev, | |
873 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 874 | return rc; |
1fd7a697 TH |
875 | } |
876 | ||
b7d8629f FT |
877 | /* |
878 | * This controller is braindamaged. dma_boundary is 0xffff | |
879 | * like others but it will lock up the whole machine HARD if | |
880 | * 65536 byte PRD entry is fed. Reduce maximum segment size. | |
881 | */ | |
882 | rc = pci_set_dma_max_seg_size(pdev, 65536 - 512); | |
883 | if (rc) { | |
884 | dev_printk(KERN_ERR, &pdev->dev, | |
885 | "failed to set the maximum segment size.\n"); | |
886 | return rc; | |
887 | } | |
888 | ||
ba66b242 | 889 | rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); |
1fd7a697 TH |
890 | if (rc) { |
891 | dev_printk(KERN_ERR, &pdev->dev, | |
892 | "failed to initialize controller\n"); | |
24dc5f33 | 893 | return rc; |
1fd7a697 TH |
894 | } |
895 | ||
896 | pci_set_master(pdev); | |
4447d351 TH |
897 | return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED, |
898 | &inic_sht); | |
1fd7a697 TH |
899 | } |
900 | ||
901 | static const struct pci_device_id inic_pci_tbl[] = { | |
902 | { PCI_VDEVICE(INIT, 0x1622), }, | |
903 | { }, | |
904 | }; | |
905 | ||
906 | static struct pci_driver inic_pci_driver = { | |
907 | .name = DRV_NAME, | |
908 | .id_table = inic_pci_tbl, | |
438ac6d5 | 909 | #ifdef CONFIG_PM |
1fd7a697 TH |
910 | .suspend = ata_pci_device_suspend, |
911 | .resume = inic_pci_device_resume, | |
438ac6d5 | 912 | #endif |
1fd7a697 TH |
913 | .probe = inic_init_one, |
914 | .remove = ata_pci_remove_one, | |
915 | }; | |
916 | ||
917 | static int __init inic_init(void) | |
918 | { | |
919 | return pci_register_driver(&inic_pci_driver); | |
920 | } | |
921 | ||
922 | static void __exit inic_exit(void) | |
923 | { | |
924 | pci_unregister_driver(&inic_pci_driver); | |
925 | } | |
926 | ||
927 | MODULE_AUTHOR("Tejun Heo"); | |
928 | MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); | |
929 | MODULE_LICENSE("GPL v2"); | |
930 | MODULE_DEVICE_TABLE(pci, inic_pci_tbl); | |
931 | MODULE_VERSION(DRV_VERSION); | |
932 | ||
933 | module_init(inic_init); | |
934 | module_exit(inic_exit); |