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1fd7a697 TH |
1 | /* |
2 | * sata_inic162x.c - Driver for Initio 162x SATA controllers | |
3 | * | |
4 | * Copyright 2006 SUSE Linux Products GmbH | |
5 | * Copyright 2006 Tejun Heo <teheo@novell.com> | |
6 | * | |
7 | * This file is released under GPL v2. | |
8 | * | |
9 | * This controller is eccentric and easily locks up if something isn't | |
10 | * right. Documentation is available at initio's website but it only | |
11 | * documents registers (not programming model). | |
12 | * | |
13 | * - ATA disks work. | |
14 | * - Hotplug works. | |
15 | * - ATAPI read works but burning doesn't. This thing is really | |
16 | * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and | |
17 | * ATAPI DMA WRITE should be programmed. If you've got a clue, be | |
18 | * my guest. | |
19 | * - Both STR and STD work. | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/pci.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | #include <linux/blkdev.h> | |
28 | #include <scsi/scsi_device.h> | |
29 | ||
30 | #define DRV_NAME "sata_inic162x" | |
2a3103ce | 31 | #define DRV_VERSION "0.3" |
1fd7a697 TH |
32 | |
33 | enum { | |
ba66b242 TH |
34 | MMIO_BAR_PCI = 5, |
35 | MMIO_BAR_CARDBUS = 1, | |
1fd7a697 TH |
36 | |
37 | NR_PORTS = 2, | |
38 | ||
3ad400a9 TH |
39 | IDMA_CPB_TBL_SIZE = 4 * 32, |
40 | ||
41 | INIC_DMA_BOUNDARY = 0xffffff, | |
42 | ||
b0dd9b8e | 43 | HOST_ACTRL = 0x08, |
1fd7a697 TH |
44 | HOST_CTL = 0x7c, |
45 | HOST_STAT = 0x7e, | |
46 | HOST_IRQ_STAT = 0xbc, | |
47 | HOST_IRQ_MASK = 0xbe, | |
48 | ||
49 | PORT_SIZE = 0x40, | |
50 | ||
51 | /* registers for ATA TF operation */ | |
b0dd9b8e TH |
52 | PORT_TF_DATA = 0x00, |
53 | PORT_TF_FEATURE = 0x01, | |
54 | PORT_TF_NSECT = 0x02, | |
55 | PORT_TF_LBAL = 0x03, | |
56 | PORT_TF_LBAM = 0x04, | |
57 | PORT_TF_LBAH = 0x05, | |
58 | PORT_TF_DEVICE = 0x06, | |
59 | PORT_TF_COMMAND = 0x07, | |
60 | PORT_TF_ALT_STAT = 0x08, | |
1fd7a697 TH |
61 | PORT_IRQ_STAT = 0x09, |
62 | PORT_IRQ_MASK = 0x0a, | |
63 | PORT_PRD_CTL = 0x0b, | |
64 | PORT_PRD_ADDR = 0x0c, | |
65 | PORT_PRD_XFERLEN = 0x10, | |
b0dd9b8e TH |
66 | PORT_CPB_CPBLAR = 0x18, |
67 | PORT_CPB_PTQFIFO = 0x1c, | |
1fd7a697 TH |
68 | |
69 | /* IDMA register */ | |
70 | PORT_IDMA_CTL = 0x14, | |
b0dd9b8e TH |
71 | PORT_IDMA_STAT = 0x16, |
72 | ||
73 | PORT_RPQ_FIFO = 0x1e, | |
74 | PORT_RPQ_CNT = 0x1f, | |
1fd7a697 TH |
75 | |
76 | PORT_SCR = 0x20, | |
77 | ||
78 | /* HOST_CTL bits */ | |
79 | HCTL_IRQOFF = (1 << 8), /* global IRQ off */ | |
b0dd9b8e TH |
80 | HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */ |
81 | HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/ | |
82 | HCTL_PWRDWN = (1 << 12), /* power down PHYs */ | |
1fd7a697 TH |
83 | HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ |
84 | HCTL_RPGSEL = (1 << 15), /* register page select */ | |
85 | ||
86 | HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | | |
87 | HCTL_RPGSEL, | |
88 | ||
89 | /* HOST_IRQ_(STAT|MASK) bits */ | |
90 | HIRQ_PORT0 = (1 << 0), | |
91 | HIRQ_PORT1 = (1 << 1), | |
92 | HIRQ_SOFT = (1 << 14), | |
93 | HIRQ_GLOBAL = (1 << 15), /* STAT only */ | |
94 | ||
95 | /* PORT_IRQ_(STAT|MASK) bits */ | |
96 | PIRQ_OFFLINE = (1 << 0), /* device unplugged */ | |
97 | PIRQ_ONLINE = (1 << 1), /* device plugged */ | |
98 | PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ | |
99 | PIRQ_FATAL = (1 << 3), /* fatal error */ | |
100 | PIRQ_ATA = (1 << 4), /* ATA interrupt */ | |
101 | PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ | |
102 | PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ | |
103 | ||
104 | PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, | |
f8b0685a | 105 | PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA, |
1fd7a697 TH |
106 | PIRQ_MASK_FREEZE = 0xff, |
107 | ||
108 | /* PORT_PRD_CTL bits */ | |
109 | PRD_CTL_START = (1 << 0), | |
110 | PRD_CTL_WR = (1 << 3), | |
111 | PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ | |
112 | ||
113 | /* PORT_IDMA_CTL bits */ | |
114 | IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ | |
115 | IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ | |
116 | IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ | |
117 | IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ | |
b0dd9b8e TH |
118 | |
119 | /* PORT_IDMA_STAT bits */ | |
120 | IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */ | |
121 | IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */ | |
122 | IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */ | |
123 | IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */ | |
124 | IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */ | |
125 | IDMA_STAT_PSD = (1 << 6), /* ADMA pause */ | |
126 | IDMA_STAT_DONE = (1 << 7), /* ADMA done */ | |
127 | ||
128 | IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR, | |
129 | ||
130 | /* CPB Control Flags*/ | |
131 | CPB_CTL_VALID = (1 << 0), /* CPB valid */ | |
132 | CPB_CTL_QUEUED = (1 << 1), /* queued command */ | |
133 | CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */ | |
134 | CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */ | |
135 | CPB_CTL_DEVDIR = (1 << 4), /* device direction control */ | |
136 | ||
137 | /* CPB Response Flags */ | |
138 | CPB_RESP_DONE = (1 << 0), /* ATA command complete */ | |
139 | CPB_RESP_REL = (1 << 1), /* ATA release */ | |
140 | CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */ | |
141 | CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */ | |
142 | CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */ | |
143 | CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */ | |
144 | CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */ | |
145 | CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */ | |
146 | ||
147 | /* PRD Control Flags */ | |
148 | PRD_DRAIN = (1 << 1), /* ignore data excess */ | |
149 | PRD_CDB = (1 << 2), /* atapi packet command pointer */ | |
150 | PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */ | |
151 | PRD_DMA = (1 << 4), /* data transfer method */ | |
152 | PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */ | |
153 | PRD_IOM = (1 << 6), /* io/memory transfer */ | |
154 | PRD_END = (1 << 7), /* APRD chain end */ | |
1fd7a697 TH |
155 | }; |
156 | ||
3ad400a9 TH |
157 | /* Comman Parameter Block */ |
158 | struct inic_cpb { | |
159 | u8 resp_flags; /* Response Flags */ | |
160 | u8 error; /* ATA Error */ | |
161 | u8 status; /* ATA Status */ | |
162 | u8 ctl_flags; /* Control Flags */ | |
163 | __le32 len; /* Total Transfer Length */ | |
164 | __le32 prd; /* First PRD pointer */ | |
165 | u8 rsvd[4]; | |
166 | /* 16 bytes */ | |
167 | u8 feature; /* ATA Feature */ | |
168 | u8 hob_feature; /* ATA Ex. Feature */ | |
169 | u8 device; /* ATA Device/Head */ | |
170 | u8 mirctl; /* Mirror Control */ | |
171 | u8 nsect; /* ATA Sector Count */ | |
172 | u8 hob_nsect; /* ATA Ex. Sector Count */ | |
173 | u8 lbal; /* ATA Sector Number */ | |
174 | u8 hob_lbal; /* ATA Ex. Sector Number */ | |
175 | u8 lbam; /* ATA Cylinder Low */ | |
176 | u8 hob_lbam; /* ATA Ex. Cylinder Low */ | |
177 | u8 lbah; /* ATA Cylinder High */ | |
178 | u8 hob_lbah; /* ATA Ex. Cylinder High */ | |
179 | u8 command; /* ATA Command */ | |
180 | u8 ctl; /* ATA Control */ | |
181 | u8 slave_error; /* Slave ATA Error */ | |
182 | u8 slave_status; /* Slave ATA Status */ | |
183 | /* 32 bytes */ | |
184 | } __packed; | |
185 | ||
186 | /* Physical Region Descriptor */ | |
187 | struct inic_prd { | |
188 | __le32 mad; /* Physical Memory Address */ | |
189 | __le16 len; /* Transfer Length */ | |
190 | u8 rsvd; | |
191 | u8 flags; /* Control Flags */ | |
192 | } __packed; | |
193 | ||
194 | struct inic_pkt { | |
195 | struct inic_cpb cpb; | |
b3f677e5 TH |
196 | struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */ |
197 | u8 cdb[ATAPI_CDB_LEN]; | |
3ad400a9 TH |
198 | } __packed; |
199 | ||
1fd7a697 | 200 | struct inic_host_priv { |
ba66b242 | 201 | void __iomem *mmio_base; |
36f674d9 | 202 | u16 cached_hctl; |
1fd7a697 TH |
203 | }; |
204 | ||
205 | struct inic_port_priv { | |
3ad400a9 TH |
206 | struct inic_pkt *pkt; |
207 | dma_addr_t pkt_dma; | |
208 | u32 *cpb_tbl; | |
209 | dma_addr_t cpb_tbl_dma; | |
1fd7a697 TH |
210 | }; |
211 | ||
1fd7a697 | 212 | static struct scsi_host_template inic_sht = { |
ab5b0235 TH |
213 | ATA_BASE_SHT(DRV_NAME), |
214 | .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */ | |
3ad400a9 | 215 | .dma_boundary = INIC_DMA_BOUNDARY, |
1fd7a697 TH |
216 | }; |
217 | ||
218 | static const int scr_map[] = { | |
219 | [SCR_STATUS] = 0, | |
220 | [SCR_ERROR] = 1, | |
221 | [SCR_CONTROL] = 2, | |
222 | }; | |
223 | ||
5796d1c4 | 224 | static void __iomem *inic_port_base(struct ata_port *ap) |
1fd7a697 | 225 | { |
ba66b242 TH |
226 | struct inic_host_priv *hpriv = ap->host->private_data; |
227 | ||
228 | return hpriv->mmio_base + ap->port_no * PORT_SIZE; | |
1fd7a697 TH |
229 | } |
230 | ||
1fd7a697 TH |
231 | static void inic_reset_port(void __iomem *port_base) |
232 | { | |
233 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
1fd7a697 | 234 | |
f8b0685a TH |
235 | /* stop IDMA engine */ |
236 | readw(idma_ctl); /* flush */ | |
237 | msleep(1); | |
1fd7a697 TH |
238 | |
239 | /* mask IRQ and assert reset */ | |
f8b0685a | 240 | writew(IDMA_CTL_RST_IDMA, idma_ctl); |
1fd7a697 | 241 | readw(idma_ctl); /* flush */ |
1fd7a697 TH |
242 | msleep(1); |
243 | ||
244 | /* release reset */ | |
f8b0685a | 245 | writew(0, idma_ctl); |
1fd7a697 TH |
246 | |
247 | /* clear irq */ | |
248 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
1fd7a697 TH |
249 | } |
250 | ||
da3dbb17 | 251 | static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val) |
1fd7a697 | 252 | { |
f8b0685a | 253 | void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR; |
1fd7a697 | 254 | void __iomem *addr; |
1fd7a697 TH |
255 | |
256 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 257 | return -EINVAL; |
1fd7a697 TH |
258 | |
259 | addr = scr_addr + scr_map[sc_reg] * 4; | |
da3dbb17 | 260 | *val = readl(scr_addr + scr_map[sc_reg] * 4); |
1fd7a697 TH |
261 | |
262 | /* this controller has stuck DIAG.N, ignore it */ | |
263 | if (sc_reg == SCR_ERROR) | |
da3dbb17 TH |
264 | *val &= ~SERR_PHYRDY_CHG; |
265 | return 0; | |
1fd7a697 TH |
266 | } |
267 | ||
da3dbb17 | 268 | static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
1fd7a697 | 269 | { |
f8b0685a | 270 | void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR; |
1fd7a697 TH |
271 | |
272 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 273 | return -EINVAL; |
1fd7a697 | 274 | |
1fd7a697 | 275 | writel(val, scr_addr + scr_map[sc_reg] * 4); |
da3dbb17 | 276 | return 0; |
1fd7a697 TH |
277 | } |
278 | ||
3ad400a9 | 279 | static void inic_stop_idma(struct ata_port *ap) |
1fd7a697 TH |
280 | { |
281 | void __iomem *port_base = inic_port_base(ap); | |
3ad400a9 TH |
282 | |
283 | readb(port_base + PORT_RPQ_FIFO); | |
284 | readb(port_base + PORT_RPQ_CNT); | |
285 | writew(0, port_base + PORT_IDMA_CTL); | |
286 | } | |
287 | ||
288 | static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat) | |
289 | { | |
9af5c9c9 | 290 | struct ata_eh_info *ehi = &ap->link.eh_info; |
3ad400a9 TH |
291 | struct inic_port_priv *pp = ap->private_data; |
292 | struct inic_cpb *cpb = &pp->pkt->cpb; | |
293 | bool freeze = false; | |
294 | ||
295 | ata_ehi_clear_desc(ehi); | |
296 | ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x", | |
297 | irq_stat, idma_stat); | |
298 | ||
299 | inic_stop_idma(ap); | |
300 | ||
301 | if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { | |
302 | ata_ehi_push_desc(ehi, "hotplug"); | |
303 | ata_ehi_hotplugged(ehi); | |
304 | freeze = true; | |
305 | } | |
306 | ||
307 | if (idma_stat & IDMA_STAT_PERR) { | |
308 | ata_ehi_push_desc(ehi, "PCI error"); | |
309 | freeze = true; | |
310 | } | |
311 | ||
312 | if (idma_stat & IDMA_STAT_CPBERR) { | |
313 | ata_ehi_push_desc(ehi, "CPB error"); | |
314 | ||
315 | if (cpb->resp_flags & CPB_RESP_IGNORED) { | |
316 | __ata_ehi_push_desc(ehi, " ignored"); | |
317 | ehi->err_mask |= AC_ERR_INVALID; | |
318 | freeze = true; | |
319 | } | |
320 | ||
321 | if (cpb->resp_flags & CPB_RESP_ATA_ERR) | |
322 | ehi->err_mask |= AC_ERR_DEV; | |
323 | ||
324 | if (cpb->resp_flags & CPB_RESP_SPURIOUS) { | |
325 | __ata_ehi_push_desc(ehi, " spurious-intr"); | |
326 | ehi->err_mask |= AC_ERR_HSM; | |
327 | freeze = true; | |
328 | } | |
329 | ||
330 | if (cpb->resp_flags & | |
331 | (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) { | |
332 | __ata_ehi_push_desc(ehi, " data-over/underflow"); | |
333 | ehi->err_mask |= AC_ERR_HSM; | |
334 | freeze = true; | |
335 | } | |
336 | } | |
337 | ||
338 | if (freeze) | |
339 | ata_port_freeze(ap); | |
340 | else | |
341 | ata_port_abort(ap); | |
342 | } | |
343 | ||
344 | static void inic_host_intr(struct ata_port *ap) | |
345 | { | |
346 | void __iomem *port_base = inic_port_base(ap); | |
347 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1fd7a697 | 348 | u8 irq_stat; |
3ad400a9 | 349 | u16 idma_stat; |
1fd7a697 | 350 | |
3ad400a9 | 351 | /* read and clear IRQ status */ |
1fd7a697 TH |
352 | irq_stat = readb(port_base + PORT_IRQ_STAT); |
353 | writeb(irq_stat, port_base + PORT_IRQ_STAT); | |
3ad400a9 TH |
354 | idma_stat = readw(port_base + PORT_IDMA_STAT); |
355 | ||
356 | if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR))) | |
357 | inic_host_err_intr(ap, irq_stat, idma_stat); | |
358 | ||
f8b0685a | 359 | if (unlikely(!qc)) |
3ad400a9 | 360 | goto spurious; |
3ad400a9 | 361 | |
b3f677e5 TH |
362 | if (likely(idma_stat & IDMA_STAT_DONE)) { |
363 | inic_stop_idma(ap); | |
1fd7a697 | 364 | |
b3f677e5 TH |
365 | /* Depending on circumstances, device error |
366 | * isn't reported by IDMA, check it explicitly. | |
367 | */ | |
368 | if (unlikely(readb(port_base + PORT_TF_COMMAND) & | |
369 | (ATA_DF | ATA_ERR))) | |
370 | qc->err_mask |= AC_ERR_DEV; | |
1fd7a697 | 371 | |
b3f677e5 TH |
372 | ata_qc_complete(qc); |
373 | return; | |
1fd7a697 TH |
374 | } |
375 | ||
3ad400a9 | 376 | spurious: |
f8b0685a TH |
377 | ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: " |
378 | "cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n", | |
379 | qc ? qc->tf.command : 0xff, irq_stat, idma_stat); | |
1fd7a697 TH |
380 | } |
381 | ||
382 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) | |
383 | { | |
384 | struct ata_host *host = dev_instance; | |
ba66b242 | 385 | struct inic_host_priv *hpriv = host->private_data; |
1fd7a697 TH |
386 | u16 host_irq_stat; |
387 | int i, handled = 0;; | |
388 | ||
ba66b242 | 389 | host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); |
1fd7a697 TH |
390 | |
391 | if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) | |
392 | goto out; | |
393 | ||
394 | spin_lock(&host->lock); | |
395 | ||
396 | for (i = 0; i < NR_PORTS; i++) { | |
397 | struct ata_port *ap = host->ports[i]; | |
398 | ||
399 | if (!(host_irq_stat & (HIRQ_PORT0 << i))) | |
400 | continue; | |
401 | ||
402 | if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) { | |
403 | inic_host_intr(ap); | |
404 | handled++; | |
405 | } else { | |
406 | if (ata_ratelimit()) | |
407 | dev_printk(KERN_ERR, host->dev, "interrupt " | |
408 | "from disabled port %d (0x%x)\n", | |
409 | i, host_irq_stat); | |
410 | } | |
411 | } | |
412 | ||
413 | spin_unlock(&host->lock); | |
414 | ||
415 | out: | |
416 | return IRQ_RETVAL(handled); | |
417 | } | |
418 | ||
b3f677e5 TH |
419 | static int inic_check_atapi_dma(struct ata_queued_cmd *qc) |
420 | { | |
421 | /* For some reason ATAPI_PROT_DMA doesn't work for some | |
422 | * commands including writes and other misc ops. Use PIO | |
423 | * protocol instead, which BTW is driven by the DMA engine | |
424 | * anyway, so it shouldn't make much difference for native | |
425 | * SATA devices. | |
426 | */ | |
427 | if (atapi_cmd_type(qc->cdb[0]) == READ) | |
428 | return 0; | |
429 | return 1; | |
430 | } | |
431 | ||
3ad400a9 TH |
432 | static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc) |
433 | { | |
434 | struct scatterlist *sg; | |
435 | unsigned int si; | |
049e8e04 | 436 | u8 flags = 0; |
3ad400a9 TH |
437 | |
438 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
439 | flags |= PRD_WRITE; | |
440 | ||
049e8e04 TH |
441 | if (ata_is_dma(qc->tf.protocol)) |
442 | flags |= PRD_DMA; | |
443 | ||
3ad400a9 TH |
444 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
445 | prd->mad = cpu_to_le32(sg_dma_address(sg)); | |
446 | prd->len = cpu_to_le16(sg_dma_len(sg)); | |
447 | prd->flags = flags; | |
448 | prd++; | |
449 | } | |
450 | ||
451 | WARN_ON(!si); | |
452 | prd[-1].flags |= PRD_END; | |
453 | } | |
454 | ||
455 | static void inic_qc_prep(struct ata_queued_cmd *qc) | |
456 | { | |
457 | struct inic_port_priv *pp = qc->ap->private_data; | |
458 | struct inic_pkt *pkt = pp->pkt; | |
459 | struct inic_cpb *cpb = &pkt->cpb; | |
460 | struct inic_prd *prd = pkt->prd; | |
049e8e04 TH |
461 | bool is_atapi = ata_is_atapi(qc->tf.protocol); |
462 | bool is_data = ata_is_data(qc->tf.protocol); | |
b3f677e5 | 463 | unsigned int cdb_len = 0; |
3ad400a9 TH |
464 | |
465 | VPRINTK("ENTER\n"); | |
466 | ||
049e8e04 | 467 | if (is_atapi) |
b3f677e5 | 468 | cdb_len = qc->dev->cdb_len; |
3ad400a9 TH |
469 | |
470 | /* prepare packet, based on initio driver */ | |
471 | memset(pkt, 0, sizeof(struct inic_pkt)); | |
472 | ||
049e8e04 | 473 | cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN; |
b3f677e5 | 474 | if (is_atapi || is_data) |
049e8e04 | 475 | cpb->ctl_flags |= CPB_CTL_DATA; |
3ad400a9 | 476 | |
b3f677e5 | 477 | cpb->len = cpu_to_le32(qc->nbytes + cdb_len); |
3ad400a9 TH |
478 | cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd)); |
479 | ||
480 | cpb->device = qc->tf.device; | |
481 | cpb->feature = qc->tf.feature; | |
482 | cpb->nsect = qc->tf.nsect; | |
483 | cpb->lbal = qc->tf.lbal; | |
484 | cpb->lbam = qc->tf.lbam; | |
485 | cpb->lbah = qc->tf.lbah; | |
486 | ||
487 | if (qc->tf.flags & ATA_TFLAG_LBA48) { | |
488 | cpb->hob_feature = qc->tf.hob_feature; | |
489 | cpb->hob_nsect = qc->tf.hob_nsect; | |
490 | cpb->hob_lbal = qc->tf.hob_lbal; | |
491 | cpb->hob_lbam = qc->tf.hob_lbam; | |
492 | cpb->hob_lbah = qc->tf.hob_lbah; | |
493 | } | |
494 | ||
495 | cpb->command = qc->tf.command; | |
496 | /* don't load ctl - dunno why. it's like that in the initio driver */ | |
497 | ||
b3f677e5 TH |
498 | /* setup PRD for CDB */ |
499 | if (is_atapi) { | |
500 | memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN); | |
501 | prd->mad = cpu_to_le32(pp->pkt_dma + | |
502 | offsetof(struct inic_pkt, cdb)); | |
503 | prd->len = cpu_to_le16(cdb_len); | |
504 | prd->flags = PRD_CDB | PRD_WRITE; | |
505 | if (!is_data) | |
506 | prd->flags |= PRD_END; | |
507 | prd++; | |
508 | } | |
509 | ||
3ad400a9 | 510 | /* setup sg table */ |
049e8e04 TH |
511 | if (is_data) |
512 | inic_fill_sg(prd, qc); | |
3ad400a9 TH |
513 | |
514 | pp->cpb_tbl[0] = pp->pkt_dma; | |
515 | } | |
516 | ||
1fd7a697 TH |
517 | static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) |
518 | { | |
519 | struct ata_port *ap = qc->ap; | |
3ad400a9 | 520 | void __iomem *port_base = inic_port_base(ap); |
1fd7a697 | 521 | |
b3f677e5 TH |
522 | /* fire up the ADMA engine */ |
523 | writew(HCTL_FTHD0, port_base + HOST_CTL); | |
524 | writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL); | |
525 | writeb(0, port_base + PORT_CPB_PTQFIFO); | |
1fd7a697 | 526 | |
b3f677e5 | 527 | return 0; |
1fd7a697 TH |
528 | } |
529 | ||
364fac0e TH |
530 | static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
531 | { | |
532 | void __iomem *port_base = inic_port_base(ap); | |
533 | ||
534 | tf->feature = readb(port_base + PORT_TF_FEATURE); | |
535 | tf->nsect = readb(port_base + PORT_TF_NSECT); | |
536 | tf->lbal = readb(port_base + PORT_TF_LBAL); | |
537 | tf->lbam = readb(port_base + PORT_TF_LBAM); | |
538 | tf->lbah = readb(port_base + PORT_TF_LBAH); | |
539 | tf->device = readb(port_base + PORT_TF_DEVICE); | |
540 | tf->command = readb(port_base + PORT_TF_COMMAND); | |
541 | } | |
542 | ||
543 | static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc) | |
544 | { | |
545 | struct ata_taskfile *rtf = &qc->result_tf; | |
546 | struct ata_taskfile tf; | |
547 | ||
548 | /* FIXME: Except for status and error, result TF access | |
549 | * doesn't work. I tried reading from BAR0/2, CPB and BAR5. | |
550 | * None works regardless of which command interface is used. | |
551 | * For now return true iff status indicates device error. | |
552 | * This means that we're reporting bogus sector for RW | |
553 | * failures. Eeekk.... | |
554 | */ | |
555 | inic_tf_read(qc->ap, &tf); | |
556 | ||
557 | if (!(tf.command & ATA_ERR)) | |
558 | return false; | |
559 | ||
560 | rtf->command = tf.command; | |
561 | rtf->feature = tf.feature; | |
562 | return true; | |
563 | } | |
564 | ||
1fd7a697 TH |
565 | static void inic_freeze(struct ata_port *ap) |
566 | { | |
567 | void __iomem *port_base = inic_port_base(ap); | |
568 | ||
ab5b0235 | 569 | writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK); |
1fd7a697 | 570 | writeb(0xff, port_base + PORT_IRQ_STAT); |
1fd7a697 TH |
571 | } |
572 | ||
573 | static void inic_thaw(struct ata_port *ap) | |
574 | { | |
575 | void __iomem *port_base = inic_port_base(ap); | |
576 | ||
1fd7a697 | 577 | writeb(0xff, port_base + PORT_IRQ_STAT); |
ab5b0235 | 578 | writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK); |
1fd7a697 TH |
579 | } |
580 | ||
364fac0e TH |
581 | static int inic_check_ready(struct ata_link *link) |
582 | { | |
583 | void __iomem *port_base = inic_port_base(link->ap); | |
584 | ||
585 | return ata_check_ready(readb(port_base + PORT_TF_COMMAND)); | |
586 | } | |
587 | ||
1fd7a697 TH |
588 | /* |
589 | * SRST and SControl hardreset don't give valid signature on this | |
590 | * controller. Only controller specific hardreset mechanism works. | |
591 | */ | |
cc0680a5 | 592 | static int inic_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 593 | unsigned long deadline) |
1fd7a697 | 594 | { |
cc0680a5 | 595 | struct ata_port *ap = link->ap; |
1fd7a697 TH |
596 | void __iomem *port_base = inic_port_base(ap); |
597 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
cc0680a5 | 598 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
1fd7a697 TH |
599 | int rc; |
600 | ||
601 | /* hammer it into sane state */ | |
602 | inic_reset_port(port_base); | |
603 | ||
f8b0685a | 604 | writew(IDMA_CTL_RST_ATA, idma_ctl); |
1fd7a697 TH |
605 | readw(idma_ctl); /* flush */ |
606 | msleep(1); | |
f8b0685a | 607 | writew(0, idma_ctl); |
1fd7a697 | 608 | |
cc0680a5 | 609 | rc = sata_link_resume(link, timing, deadline); |
1fd7a697 | 610 | if (rc) { |
cc0680a5 | 611 | ata_link_printk(link, KERN_WARNING, "failed to resume " |
fe334602 | 612 | "link after reset (errno=%d)\n", rc); |
1fd7a697 TH |
613 | return rc; |
614 | } | |
615 | ||
1fd7a697 | 616 | *class = ATA_DEV_NONE; |
cc0680a5 | 617 | if (ata_link_online(link)) { |
1fd7a697 TH |
618 | struct ata_taskfile tf; |
619 | ||
705e76be | 620 | /* wait for link to become ready */ |
364fac0e | 621 | rc = ata_wait_after_reset(link, deadline, inic_check_ready); |
9b89391c TH |
622 | /* link occupied, -ENODEV too is an error */ |
623 | if (rc) { | |
cc0680a5 | 624 | ata_link_printk(link, KERN_WARNING, "device not ready " |
d4b2bab4 TH |
625 | "after hardreset (errno=%d)\n", rc); |
626 | return rc; | |
1fd7a697 TH |
627 | } |
628 | ||
364fac0e | 629 | inic_tf_read(ap, &tf); |
1fd7a697 | 630 | *class = ata_dev_classify(&tf); |
1fd7a697 TH |
631 | } |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static void inic_error_handler(struct ata_port *ap) | |
637 | { | |
638 | void __iomem *port_base = inic_port_base(ap); | |
1fd7a697 | 639 | |
1fd7a697 | 640 | inic_reset_port(port_base); |
a1efdaba | 641 | ata_std_error_handler(ap); |
1fd7a697 TH |
642 | } |
643 | ||
644 | static void inic_post_internal_cmd(struct ata_queued_cmd *qc) | |
645 | { | |
646 | /* make DMA engine forget about the failed command */ | |
a51d644a | 647 | if (qc->flags & ATA_QCFLAG_FAILED) |
1fd7a697 TH |
648 | inic_reset_port(inic_port_base(qc->ap)); |
649 | } | |
650 | ||
1fd7a697 TH |
651 | static void init_port(struct ata_port *ap) |
652 | { | |
653 | void __iomem *port_base = inic_port_base(ap); | |
3ad400a9 | 654 | struct inic_port_priv *pp = ap->private_data; |
1fd7a697 | 655 | |
3ad400a9 TH |
656 | /* clear packet and CPB table */ |
657 | memset(pp->pkt, 0, sizeof(struct inic_pkt)); | |
658 | memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE); | |
659 | ||
660 | /* setup PRD and CPB lookup table addresses */ | |
1fd7a697 | 661 | writel(ap->prd_dma, port_base + PORT_PRD_ADDR); |
3ad400a9 | 662 | writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR); |
1fd7a697 TH |
663 | } |
664 | ||
665 | static int inic_port_resume(struct ata_port *ap) | |
666 | { | |
667 | init_port(ap); | |
668 | return 0; | |
669 | } | |
670 | ||
671 | static int inic_port_start(struct ata_port *ap) | |
672 | { | |
3ad400a9 | 673 | struct device *dev = ap->host->dev; |
1fd7a697 | 674 | struct inic_port_priv *pp; |
1fd7a697 TH |
675 | int rc; |
676 | ||
677 | /* alloc and initialize private data */ | |
3ad400a9 | 678 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
1fd7a697 TH |
679 | if (!pp) |
680 | return -ENOMEM; | |
681 | ap->private_data = pp; | |
682 | ||
1fd7a697 TH |
683 | /* Alloc resources */ |
684 | rc = ata_port_start(ap); | |
36f674d9 | 685 | if (rc) |
1fd7a697 | 686 | return rc; |
1fd7a697 | 687 | |
3ad400a9 TH |
688 | pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt), |
689 | &pp->pkt_dma, GFP_KERNEL); | |
690 | if (!pp->pkt) | |
691 | return -ENOMEM; | |
692 | ||
693 | pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE, | |
694 | &pp->cpb_tbl_dma, GFP_KERNEL); | |
695 | if (!pp->cpb_tbl) | |
696 | return -ENOMEM; | |
697 | ||
1fd7a697 TH |
698 | init_port(ap); |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
1fd7a697 | 703 | static struct ata_port_operations inic_port_ops = { |
f8b0685a | 704 | .inherits = &sata_port_ops, |
1fd7a697 | 705 | |
b3f677e5 | 706 | .check_atapi_dma = inic_check_atapi_dma, |
3ad400a9 | 707 | .qc_prep = inic_qc_prep, |
1fd7a697 | 708 | .qc_issue = inic_qc_issue, |
364fac0e | 709 | .qc_fill_rtf = inic_qc_fill_rtf, |
1fd7a697 TH |
710 | |
711 | .freeze = inic_freeze, | |
712 | .thaw = inic_thaw, | |
a1efdaba | 713 | .hardreset = inic_hardreset, |
1fd7a697 TH |
714 | .error_handler = inic_error_handler, |
715 | .post_internal_cmd = inic_post_internal_cmd, | |
1fd7a697 | 716 | |
029cfd6b TH |
717 | .scr_read = inic_scr_read, |
718 | .scr_write = inic_scr_write, | |
1fd7a697 | 719 | |
029cfd6b | 720 | .port_resume = inic_port_resume, |
1fd7a697 | 721 | .port_start = inic_port_start, |
1fd7a697 TH |
722 | }; |
723 | ||
724 | static struct ata_port_info inic_port_info = { | |
1fd7a697 TH |
725 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
726 | .pio_mask = 0x1f, /* pio0-4 */ | |
727 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 728 | .udma_mask = ATA_UDMA6, |
1fd7a697 TH |
729 | .port_ops = &inic_port_ops |
730 | }; | |
731 | ||
732 | static int init_controller(void __iomem *mmio_base, u16 hctl) | |
733 | { | |
734 | int i; | |
735 | u16 val; | |
736 | ||
737 | hctl &= ~HCTL_KNOWN_BITS; | |
738 | ||
739 | /* Soft reset whole controller. Spec says reset duration is 3 | |
740 | * PCI clocks, be generous and give it 10ms. | |
741 | */ | |
742 | writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); | |
743 | readw(mmio_base + HOST_CTL); /* flush */ | |
744 | ||
745 | for (i = 0; i < 10; i++) { | |
746 | msleep(1); | |
747 | val = readw(mmio_base + HOST_CTL); | |
748 | if (!(val & HCTL_SOFTRST)) | |
749 | break; | |
750 | } | |
751 | ||
752 | if (val & HCTL_SOFTRST) | |
753 | return -EIO; | |
754 | ||
755 | /* mask all interrupts and reset ports */ | |
756 | for (i = 0; i < NR_PORTS; i++) { | |
757 | void __iomem *port_base = mmio_base + i * PORT_SIZE; | |
758 | ||
759 | writeb(0xff, port_base + PORT_IRQ_MASK); | |
760 | inic_reset_port(port_base); | |
761 | } | |
762 | ||
763 | /* port IRQ is masked now, unmask global IRQ */ | |
764 | writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); | |
765 | val = readw(mmio_base + HOST_IRQ_MASK); | |
766 | val &= ~(HIRQ_PORT0 | HIRQ_PORT1); | |
767 | writew(val, mmio_base + HOST_IRQ_MASK); | |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
438ac6d5 | 772 | #ifdef CONFIG_PM |
1fd7a697 TH |
773 | static int inic_pci_device_resume(struct pci_dev *pdev) |
774 | { | |
775 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
776 | struct inic_host_priv *hpriv = host->private_data; | |
1fd7a697 TH |
777 | int rc; |
778 | ||
5aea408d DM |
779 | rc = ata_pci_device_do_resume(pdev); |
780 | if (rc) | |
781 | return rc; | |
1fd7a697 TH |
782 | |
783 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
ba66b242 | 784 | rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); |
1fd7a697 TH |
785 | if (rc) |
786 | return rc; | |
787 | } | |
788 | ||
789 | ata_host_resume(host); | |
790 | ||
791 | return 0; | |
792 | } | |
438ac6d5 | 793 | #endif |
1fd7a697 TH |
794 | |
795 | static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
796 | { | |
797 | static int printed_version; | |
4447d351 TH |
798 | const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; |
799 | struct ata_host *host; | |
1fd7a697 | 800 | struct inic_host_priv *hpriv; |
0d5ff566 | 801 | void __iomem * const *iomap; |
ba66b242 | 802 | int mmio_bar; |
1fd7a697 TH |
803 | int i, rc; |
804 | ||
805 | if (!printed_version++) | |
806 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
807 | ||
4447d351 TH |
808 | /* alloc host */ |
809 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS); | |
810 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
811 | if (!host || !hpriv) | |
812 | return -ENOMEM; | |
813 | ||
814 | host->private_data = hpriv; | |
815 | ||
ba66b242 TH |
816 | /* Acquire resources and fill host. Note that PCI and cardbus |
817 | * use different BARs. | |
818 | */ | |
24dc5f33 | 819 | rc = pcim_enable_device(pdev); |
1fd7a697 TH |
820 | if (rc) |
821 | return rc; | |
822 | ||
ba66b242 TH |
823 | if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM) |
824 | mmio_bar = MMIO_BAR_PCI; | |
825 | else | |
826 | mmio_bar = MMIO_BAR_CARDBUS; | |
827 | ||
828 | rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME); | |
0d5ff566 TH |
829 | if (rc) |
830 | return rc; | |
4447d351 | 831 | host->iomap = iomap = pcim_iomap_table(pdev); |
ba66b242 TH |
832 | hpriv->mmio_base = iomap[mmio_bar]; |
833 | hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL); | |
4447d351 TH |
834 | |
835 | for (i = 0; i < NR_PORTS; i++) { | |
cbcdd875 | 836 | struct ata_port *ap = host->ports[i]; |
cbcdd875 | 837 | |
ba66b242 TH |
838 | ata_port_pbar_desc(ap, mmio_bar, -1, "mmio"); |
839 | ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port"); | |
4447d351 TH |
840 | } |
841 | ||
1fd7a697 TH |
842 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ |
843 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
844 | if (rc) { | |
845 | dev_printk(KERN_ERR, &pdev->dev, | |
846 | "32-bit DMA enable failed\n"); | |
24dc5f33 | 847 | return rc; |
1fd7a697 TH |
848 | } |
849 | ||
850 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
851 | if (rc) { | |
852 | dev_printk(KERN_ERR, &pdev->dev, | |
853 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 854 | return rc; |
1fd7a697 TH |
855 | } |
856 | ||
b7d8629f FT |
857 | /* |
858 | * This controller is braindamaged. dma_boundary is 0xffff | |
859 | * like others but it will lock up the whole machine HARD if | |
860 | * 65536 byte PRD entry is fed. Reduce maximum segment size. | |
861 | */ | |
862 | rc = pci_set_dma_max_seg_size(pdev, 65536 - 512); | |
863 | if (rc) { | |
864 | dev_printk(KERN_ERR, &pdev->dev, | |
865 | "failed to set the maximum segment size.\n"); | |
866 | return rc; | |
867 | } | |
868 | ||
ba66b242 | 869 | rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); |
1fd7a697 TH |
870 | if (rc) { |
871 | dev_printk(KERN_ERR, &pdev->dev, | |
872 | "failed to initialize controller\n"); | |
24dc5f33 | 873 | return rc; |
1fd7a697 TH |
874 | } |
875 | ||
876 | pci_set_master(pdev); | |
4447d351 TH |
877 | return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED, |
878 | &inic_sht); | |
1fd7a697 TH |
879 | } |
880 | ||
881 | static const struct pci_device_id inic_pci_tbl[] = { | |
882 | { PCI_VDEVICE(INIT, 0x1622), }, | |
883 | { }, | |
884 | }; | |
885 | ||
886 | static struct pci_driver inic_pci_driver = { | |
887 | .name = DRV_NAME, | |
888 | .id_table = inic_pci_tbl, | |
438ac6d5 | 889 | #ifdef CONFIG_PM |
1fd7a697 TH |
890 | .suspend = ata_pci_device_suspend, |
891 | .resume = inic_pci_device_resume, | |
438ac6d5 | 892 | #endif |
1fd7a697 TH |
893 | .probe = inic_init_one, |
894 | .remove = ata_pci_remove_one, | |
895 | }; | |
896 | ||
897 | static int __init inic_init(void) | |
898 | { | |
899 | return pci_register_driver(&inic_pci_driver); | |
900 | } | |
901 | ||
902 | static void __exit inic_exit(void) | |
903 | { | |
904 | pci_unregister_driver(&inic_pci_driver); | |
905 | } | |
906 | ||
907 | MODULE_AUTHOR("Tejun Heo"); | |
908 | MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); | |
909 | MODULE_LICENSE("GPL v2"); | |
910 | MODULE_DEVICE_TABLE(pci, inic_pci_tbl); | |
911 | MODULE_VERSION(DRV_VERSION); | |
912 | ||
913 | module_init(inic_init); | |
914 | module_exit(inic_exit); |