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libata: More TSSTcorp pain, keep in sync with legacy IDE
[deliverable/linux.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
1fd2e1c2 74#define DRV_VERSION "1.20"
20f733e7
BR		 75
76enum {
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
84
85 MV_PCI_REG_BASE = 0,
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92
20f733e7 93 MV_SATAHC0_REG_BASE = 0x20000,
522479fb 94 MV_FLASH_CTL = 0x1046c,
bca1c4eb
JG		 95 MV_GPIO_PORT_CTL = 0x104f0,
96 MV_RESET_CFG = 0x180d8,
20f733e7
BR		 97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
31961943
BR		 103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 112 MV_MAX_SG_CT = 256,
31961943 113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 114
352fab70 115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 116 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 124 /* SoC integrated controllers, no PCI interface */
e12bef50 125 MV_FLAG_SOC = (1 << 28),
7bb3c529 126
c5d3e45a 127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
47c2b677 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 131
31961943
BR		 132 CRQB_FLAG_READ = (1 << 0),
133 CRQB_TAG_SHIFT = 1,
c5d3e45a 134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
20f733e7
BR		 147 /* PCI interface registers */
148
31961943
BR		 149 PCI_COMMAND_OFS = 0xc00,
150
20f733e7
BR		 151 PCI_MAIN_CMD_STS_OFS = 0xd30,
152 STOP_PCI_MASTER = (1 << 2),
153 PCI_MASTER_EMPTY = (1 << 3),
154 GLOB_SFT_RST = (1 << 4),
155
522479fb
JG		 156 MV_PCI_MODE = 0xd00,
157 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
158 MV_PCI_DISC_TIMER = 0xd04,
159 MV_PCI_MSI_TRIGGER = 0xc38,
160 MV_PCI_SERR_MASK = 0xc28,
161 MV_PCI_XBAR_TMOUT = 0x1d04,
162 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
163 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
164 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
165 MV_PCI_ERR_COMMAND = 0x1d50,
166
02a121da
ML		 167 PCI_IRQ_CAUSE_OFS = 0x1d58,
168 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 169 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
170
02a121da
ML		 171 PCIE_IRQ_CAUSE_OFS = 0x1900,
172 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 173 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 174
7368f919
ML		 175 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
176 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
177 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
178 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
179 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 180 ERR_IRQ = (1 << 0), /* shift by port # */
181 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 182 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
183 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
184 PCI_ERR = (1 << 18),
185 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
186 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 187 PORTS_0_3_COAL_DONE = (1 << 8),
188 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 189 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
190 GPIO_INT = (1 << 22),
191 SELF_INT = (1 << 23),
192 TWSI_INT = (1 << 24),
193 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 194 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 195 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
8b260248 196 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
f9f7fe01 197 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
20f733e7
BR		 198 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
199 HC_MAIN_RSVD),
fb621e2f
JG		 200 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
201 HC_MAIN_RSVD_5),
f351b2d6 202 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
20f733e7
BR		 203
204 /* SATAHC registers */
205 HC_CFG_OFS = 0,
206
207 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 208 DMA_IRQ = (1 << 0), /* shift by port # */
209 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 210 DEV_IRQ = (1 << 8), /* shift by port # */
211
212 /* Shadow block registers */
31961943
BR		 213 SHD_BLK_OFS = 0x100,
214 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 215
216 /* SATA registers */
217 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
218 SATA_ACTIVE_OFS = 0x350,
0c58912e 219 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
17c5aab5 220
e12bef50 221 LTMODE_OFS = 0x30c,
17c5aab5
ML		 222 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
223
47c2b677 224 PHY_MODE3 = 0x310,
bca1c4eb
JG		 225 PHY_MODE4 = 0x314,
226 PHY_MODE2 = 0x330,
e12bef50
ML		 227 SATA_IFCTL_OFS = 0x344,
228 SATA_IFSTAT_OFS = 0x34c,
229 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 230
e12bef50 231 FIS_CFG_OFS = 0x360,
17c5aab5
ML		 232 FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
233
c9d39130
JG		 234 MV5_PHY_MODE = 0x74,
235 MV5_LT_MODE = 0x30,
236 MV5_PHY_CTL = 0x0C,
e12bef50 237 SATA_INTERFACE_CFG = 0x050,
bca1c4eb
JG		 238
239 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 240
241 /* Port registers */
242 EDMA_CFG_OFS = 0,
0c58912e
ML		 243 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
244 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
245 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
246 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
247 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 248 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
249 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 250
251 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
252 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 253 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
254 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
255 EDMA_ERR_DEV = (1 << 2), /* device error */
256 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
257 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
258 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 259 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
260 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 261 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 262 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 263 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
264 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
265 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
266 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 267
6c1153e0 268 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 269 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
270 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
271 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
272 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
273
6c1153e0 274 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 275
6c1153e0 276 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 277 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
278 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
279 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
280 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
281 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
282
6c1153e0 283 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 284
6c1153e0 285 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 286 EDMA_ERR_OVERRUN_5 = (1 << 5),
287 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 288
289 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
290 EDMA_ERR_LNK_CTRL_RX_1 |
291 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 292 EDMA_ERR_LNK_CTRL_TX,
646a4da5 293
bdd4ddde
JG		 294 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
295 EDMA_ERR_PRD_PAR |
296 EDMA_ERR_DEV_DCON |
297 EDMA_ERR_DEV_CON |
298 EDMA_ERR_SERR |
299 EDMA_ERR_SELF_DIS |
6c1153e0 300 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 301 EDMA_ERR_CRPB_PAR |
302 EDMA_ERR_INTRL_PAR |
303 EDMA_ERR_IORDY |
304 EDMA_ERR_LNK_CTRL_RX_2 |
305 EDMA_ERR_LNK_DATA_RX |
306 EDMA_ERR_LNK_DATA_TX |
307 EDMA_ERR_TRANS_PROTO,
e12bef50 308
bdd4ddde
JG		 309 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
310 EDMA_ERR_PRD_PAR |
311 EDMA_ERR_DEV_DCON |
312 EDMA_ERR_DEV_CON |
313 EDMA_ERR_OVERRUN_5 |
314 EDMA_ERR_UNDERRUN_5 |
315 EDMA_ERR_SELF_DIS_5 |
6c1153e0 316 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 317 EDMA_ERR_CRPB_PAR |
318 EDMA_ERR_INTRL_PAR |
319 EDMA_ERR_IORDY,
20f733e7 320
31961943
BR		 321 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
322 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 323
324 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
325 EDMA_REQ_Q_PTR_SHIFT = 5,
326
327 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
328 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
329 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 330 EDMA_RSP_Q_PTR_SHIFT = 3,
331
0ea9e179
JG		 332 EDMA_CMD_OFS = 0x28, /* EDMA command register */
333 EDMA_EN = (1 << 0), /* enable EDMA */
334 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
335 ATA_RST = (1 << 2), /* reset trans/link/phy */
20f733e7 336
c9d39130 337 EDMA_IORDY_TMOUT = 0x34,
bca1c4eb 338 EDMA_ARB_CFG = 0x38,
bca1c4eb 339
352fab70
ML		 340 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
341
31961943
BR		 342 /* Host private flags (hp_flags) */
343 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 344 MV_HP_ERRATA_50XXB0 = (1 << 1),
345 MV_HP_ERRATA_50XXB2 = (1 << 2),
346 MV_HP_ERRATA_60X1B2 = (1 << 3),
347 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 348 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 349 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
350 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
351 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 352 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
20f733e7 353
31961943 354 /* Port private flags (pp_flags) */
0ea9e179 355 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 356 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
20f733e7
BR		 357};
358
ee9ccdf7
JG		 359#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
360#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 361#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
7bb3c529 362#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 363
15a32632
LB		 364#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
365#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
366
095fec88 367enum {
baf14aa1
JG		 368 /* DMA boundary 0xffff is required by the s/g splitting
369 * we need on /length/ in mv_fill-sg().
370 */
371 MV_DMA_BOUNDARY = 0xffffU,
095fec88 372
0ea9e179
JG		 373 /* mask of register bits containing lower 32 bits
374 * of EDMA request queue DMA address
375 */
095fec88
JG		 376 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
377
0ea9e179 378 /* ditto, for response queue */
095fec88
JG		 379 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
380};
381
522479fb
JG		 382enum chip_type {
383 chip_504x,
384 chip_508x,
385 chip_5080,
386 chip_604x,
387 chip_608x,
e4e7b892
JG		 388 chip_6042,
389 chip_7042,
f351b2d6 390 chip_soc,
522479fb
JG		 391};
392
31961943
BR		 393/* Command ReQuest Block: 32B */
394struct mv_crqb {
e1469874
ML		 395 __le32 sg_addr;
396 __le32 sg_addr_hi;
397 __le16 ctrl_flags;
398 __le16 ata_cmd[11];
31961943 399};
20f733e7 400
e4e7b892 401struct mv_crqb_iie {
e1469874
ML		 402 __le32 addr;
403 __le32 addr_hi;
404 __le32 flags;
405 __le32 len;
406 __le32 ata_cmd[4];
e4e7b892
JG		 407};
408
31961943
BR		 409/* Command ResPonse Block: 8B */
410struct mv_crpb {
e1469874
ML		 411 __le16 id;
412 __le16 flags;
413 __le32 tmstmp;
20f733e7
BR		 414};
415
31961943
BR		 416/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
417struct mv_sg {
e1469874
ML		 418 __le32 addr;
419 __le32 flags_size;
420 __le32 addr_hi;
421 __le32 reserved;
31961943 422};
20f733e7 423
31961943
BR		 424struct mv_port_priv {
425 struct mv_crqb *crqb;
426 dma_addr_t crqb_dma;
427 struct mv_crpb *crpb;
428 dma_addr_t crpb_dma;
eb73d558
ML		 429 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
430 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 431
432 unsigned int req_idx;
433 unsigned int resp_idx;
434
31961943
BR		 435 u32 pp_flags;
436};
437
bca1c4eb
JG		 438struct mv_port_signal {
439 u32 amps;
440 u32 pre;
441};
442
02a121da
ML		 443struct mv_host_priv {
444 u32 hp_flags;
445 struct mv_port_signal signal[8];
446 const struct mv_hw_ops *ops;
f351b2d6
SB		 447 int n_ports;
448 void __iomem *base;
7368f919
ML		 449 void __iomem *main_irq_cause_addr;
450 void __iomem *main_irq_mask_addr;
02a121da
ML		 451 u32 irq_cause_ofs;
452 u32 irq_mask_ofs;
453 u32 unmask_all_irqs;
da2fa9ba
ML		 454 /*
455 * These consistent DMA memory pools give us guaranteed
456 * alignment for hardware-accessed data structures,
457 * and less memory waste in accomplishing the alignment.
458 */
459 struct dma_pool *crqb_pool;
460 struct dma_pool *crpb_pool;
461 struct dma_pool *sg_tbl_pool;
02a121da
ML		 462};
463
47c2b677 464struct mv_hw_ops {
2a47ce06
JG		 465 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
466 unsigned int port);
47c2b677
JG		 467 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
468 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
469 void __iomem *mmio);
c9d39130
JG		 470 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
471 unsigned int n_hc);
522479fb 472 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 473 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 474};
475
da3dbb17
TH		 476static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
477static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
478static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
479static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 480static int mv_port_start(struct ata_port *ap);
481static void mv_port_stop(struct ata_port *ap);
482static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 483static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 484static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 485static int mv_hardreset(struct ata_link *link, unsigned int *class,
486 unsigned long deadline);
bdd4ddde
JG		 487static void mv_eh_freeze(struct ata_port *ap);
488static void mv_eh_thaw(struct ata_port *ap);
f273827e 489static void mv6_dev_config(struct ata_device *dev);
20f733e7 490
2a47ce06
JG		 491static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
492 unsigned int port);
47c2b677
JG		 493static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
494static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
495 void __iomem *mmio);
c9d39130
JG		 496static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
497 unsigned int n_hc);
522479fb 498static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 499static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 500
2a47ce06
JG		 501static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
502 unsigned int port);
47c2b677
JG		 503static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
504static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
505 void __iomem *mmio);
c9d39130
JG		 506static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
507 unsigned int n_hc);
522479fb 508static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 509static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
510 void __iomem *mmio);
511static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
512 void __iomem *mmio);
513static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
514 void __iomem *mmio, unsigned int n_hc);
515static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
516 void __iomem *mmio);
517static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 518static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 519static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 520 unsigned int port_no);
e12bef50 521static int mv_stop_edma(struct ata_port *ap);
b562468c 522static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 523static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 524
e49856d8
ML		 525static void mv_pmp_select(struct ata_port *ap, int pmp);
526static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
527 unsigned long deadline);
528static int mv_softreset(struct ata_link *link, unsigned int *class,
529 unsigned long deadline);
47c2b677 530
eb73d558
ML		 531/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
532 * because we have to allow room for worst case splitting of
533 * PRDs for 64K boundaries in mv_fill_sg().
534 */
c5d3e45a 535static struct scsi_host_template mv5_sht = {
68d1d07b 536 ATA_BASE_SHT(DRV_NAME),
baf14aa1 537 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 538 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 539};
540
541static struct scsi_host_template mv6_sht = {
68d1d07b 542 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 543 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 544 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 545 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 546};
547
029cfd6b
TH		 548static struct ata_port_operations mv5_ops = {
549 .inherits = &ata_sff_port_ops,
c9d39130
JG		 550
551 .qc_prep = mv_qc_prep,
552 .qc_issue = mv_qc_issue,
c9d39130 553
bdd4ddde
JG		 554 .freeze = mv_eh_freeze,
555 .thaw = mv_eh_thaw,
a1efdaba 556 .hardreset = mv_hardreset,
a1efdaba 557 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 558 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 559
c9d39130
JG		 560 .scr_read = mv5_scr_read,
561 .scr_write = mv5_scr_write,
562
563 .port_start = mv_port_start,
564 .port_stop = mv_port_stop,
c9d39130
JG		 565};
566
029cfd6b
TH		 567static struct ata_port_operations mv6_ops = {
568 .inherits = &mv5_ops,
e49856d8 569 .qc_defer = sata_pmp_qc_defer_cmd_switch,
f273827e 570 .dev_config = mv6_dev_config,
20f733e7
BR		 571 .scr_read = mv_scr_read,
572 .scr_write = mv_scr_write,
573
e49856d8
ML		 574 .pmp_hardreset = mv_pmp_hardreset,
575 .pmp_softreset = mv_softreset,
576 .softreset = mv_softreset,
577 .error_handler = sata_pmp_error_handler,
20f733e7
BR		 578};
579
029cfd6b
TH		 580static struct ata_port_operations mv_iie_ops = {
581 .inherits = &mv6_ops,
e49856d8 582 .qc_defer = ata_std_qc_defer, /* FIS-based switching */
029cfd6b 583 .dev_config = ATA_OP_NULL,
e4e7b892 584 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 585};
586
98ac62de 587static const struct ata_port_info mv_port_info[] = {
20f733e7 588 { /* chip_504x */
cca3974e 589 .flags = MV_COMMON_FLAGS,
31961943 590 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 591 .udma_mask = ATA_UDMA6,
c9d39130 592 .port_ops = &mv5_ops,
20f733e7
BR		 593 },
594 { /* chip_508x */
c5d3e45a 595 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 596 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 597 .udma_mask = ATA_UDMA6,
c9d39130 598 .port_ops = &mv5_ops,
20f733e7 599 },
47c2b677 600 { /* chip_5080 */
c5d3e45a 601 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 602 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 603 .udma_mask = ATA_UDMA6,
c9d39130 604 .port_ops = &mv5_ops,
47c2b677 605 },
20f733e7 606 { /* chip_604x */
138bfdd0 607 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 608 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 609 ATA_FLAG_NCQ,
31961943 610 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 611 .udma_mask = ATA_UDMA6,
c9d39130 612 .port_ops = &mv6_ops,
20f733e7
BR		 613 },
614 { /* chip_608x */
c5d3e45a 615 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 616 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 617 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 618 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 619 .udma_mask = ATA_UDMA6,
c9d39130 620 .port_ops = &mv6_ops,
20f733e7 621 },
e4e7b892 622 { /* chip_6042 */
138bfdd0 623 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 624 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 625 ATA_FLAG_NCQ,
e4e7b892 626 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 627 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 628 .port_ops = &mv_iie_ops,
629 },
630 { /* chip_7042 */
138bfdd0 631 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 632 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 633 ATA_FLAG_NCQ,
e4e7b892 634 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 635 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 636 .port_ops = &mv_iie_ops,
637 },
f351b2d6 638 { /* chip_soc */
02c1f32f 639 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 640 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
02c1f32f 641 ATA_FLAG_NCQ | MV_FLAG_SOC,
17c5aab5
ML		 642 .pio_mask = 0x1f, /* pio0-4 */
643 .udma_mask = ATA_UDMA6,
644 .port_ops = &mv_iie_ops,
f351b2d6 645 },
20f733e7
BR		 646};
647
3b7d697d 648static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 649 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
650 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
651 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
652 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 653 /* RocketRAID 1740/174x have different identifiers */
654 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
655 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 656
657 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
658 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
659 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
660 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
661 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
662
663 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
664
d9f9c6bc
FA		 665 /* Adaptec 1430SA */
666 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
667
02a121da 668 /* Marvell 7042 support */
6a3d586d
MT		 669 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
670
02a121da
ML		 671 /* Highpoint RocketRAID PCIe series */
672 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
673 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
674
2d2744fc 675 { } /* terminate list */
20f733e7
BR		 676};
677
47c2b677
JG		 678static const struct mv_hw_ops mv5xxx_ops = {
679 .phy_errata = mv5_phy_errata,
680 .enable_leds = mv5_enable_leds,
681 .read_preamp = mv5_read_preamp,
682 .reset_hc = mv5_reset_hc,
522479fb
JG		 683 .reset_flash = mv5_reset_flash,
684 .reset_bus = mv5_reset_bus,
47c2b677
JG		 685};
686
687static const struct mv_hw_ops mv6xxx_ops = {
688 .phy_errata = mv6_phy_errata,
689 .enable_leds = mv6_enable_leds,
690 .read_preamp = mv6_read_preamp,
691 .reset_hc = mv6_reset_hc,
522479fb
JG		 692 .reset_flash = mv6_reset_flash,
693 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 694};
695
f351b2d6
SB		 696static const struct mv_hw_ops mv_soc_ops = {
697 .phy_errata = mv6_phy_errata,
698 .enable_leds = mv_soc_enable_leds,
699 .read_preamp = mv_soc_read_preamp,
700 .reset_hc = mv_soc_reset_hc,
701 .reset_flash = mv_soc_reset_flash,
702 .reset_bus = mv_soc_reset_bus,
703};
704
20f733e7
BR		 705/*
706 * Functions
707 */
708
709static inline void writelfl(unsigned long data, void __iomem *addr)
710{
711 writel(data, addr);
712 (void) readl(addr); /* flush to avoid PCI posted write */
713}
714
c9d39130
JG		 715static inline unsigned int mv_hc_from_port(unsigned int port)
716{
717 return port >> MV_PORT_HC_SHIFT;
718}
719
720static inline unsigned int mv_hardport_from_port(unsigned int port)
721{
722 return port & MV_PORT_MASK;
723}
724
1cfd19ae
ML		 725/*
726 * Consolidate some rather tricky bit shift calculations.
727 * This is hot-path stuff, so not a function.
728 * Simple code, with two return values, so macro rather than inline.
729 *
730 * port is the sole input, in range 0..7.
7368f919
ML		 731 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
732 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 733 *
734 * Note that port and hardport may be the same variable in some cases.
735 */
736#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
737{ \
738 shift = mv_hc_from_port(port) * HC_SHIFT; \
739 hardport = mv_hardport_from_port(port); \
740 shift += hardport * 2; \
741}
742
352fab70
ML		 743static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
744{
745 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
746}
747
c9d39130
JG		 748static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
749 unsigned int port)
750{
751 return mv_hc_base(base, mv_hc_from_port(port));
752}
753
20f733e7
BR		 754static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
755{
c9d39130 756 return mv_hc_base_from_port(base, port) +
8b260248 757 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 758 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 759}
760
e12bef50
ML		 761static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
762{
763 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
764 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
765
766 return hc_mmio + ofs;
767}
768
f351b2d6
SB		 769static inline void __iomem *mv_host_base(struct ata_host *host)
770{
771 struct mv_host_priv *hpriv = host->private_data;
772 return hpriv->base;
773}
774
20f733e7
BR		 775static inline void __iomem *mv_ap_base(struct ata_port *ap)
776{
f351b2d6 777 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 778}
779
cca3974e 780static inline int mv_get_hc_count(unsigned long port_flags)
31961943 781{
cca3974e 782 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 783}
784
c5d3e45a
JG		 785static void mv_set_edma_ptrs(void __iomem *port_mmio,
786 struct mv_host_priv *hpriv,
787 struct mv_port_priv *pp)
788{
bdd4ddde
JG		 789 u32 index;
790
c5d3e45a
JG		 791 /*
792 * initialize request queue
793 */
fcfb1f77
ML		 794 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
795 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 796
c5d3e45a
JG		 797 WARN_ON(pp->crqb_dma & 0x3ff);
798 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 799 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 800 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
801
802 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 803 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 804 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
805 else
bdd4ddde 806 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 807
808 /*
809 * initialize response queue
810 */
fcfb1f77
ML		 811 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
812 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 813
c5d3e45a
JG		 814 WARN_ON(pp->crpb_dma & 0xff);
815 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
816
817 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 818 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 819 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
820 else
bdd4ddde 821 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 822
bdd4ddde 823 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 824 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 825}
826
05b308e1
BR		 827/**
828 * mv_start_dma - Enable eDMA engine
829 * @base: port base address
830 * @pp: port private data
831 *
beec7dbc
TH		 832 * Verify the local cache of the eDMA state is accurate with a
833 * WARN_ON.
05b308e1
BR		 834 *
835 * LOCKING:
836 * Inherited from caller.
837 */
0c58912e 838static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 839 struct mv_port_priv *pp, u8 protocol)
20f733e7 840{
72109168
ML		 841 int want_ncq = (protocol == ATA_PROT_NCQ);
842
843 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
844 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
845 if (want_ncq != using_ncq)
b562468c 846 mv_stop_edma(ap);
72109168 847 }
c5d3e45a 848 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 849 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 850 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 851 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 852 mv_host_base(ap->host), hardport);
0c58912e
ML		 853 u32 hc_irq_cause, ipending;
854
bdd4ddde 855 /* clear EDMA event indicators, if any */
f630d562 856 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 857
0c58912e
ML		 858 /* clear EDMA interrupt indicator, if any */
859 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 860 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 861 if (hc_irq_cause & ipending) {
862 writelfl(hc_irq_cause & ~ipending,
863 hc_mmio + HC_IRQ_CAUSE_OFS);
864 }
865
e12bef50 866 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 867
868 /* clear FIS IRQ Cause */
869 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
870
f630d562 871 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 872
f630d562 873 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 874 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
875 }
20f733e7
BR		 876}
877
05b308e1 878/**
e12bef50 879 * mv_stop_edma_engine - Disable eDMA engine
b562468c 880 * @port_mmio: io base address
05b308e1
BR		 881 *
882 * LOCKING:
883 * Inherited from caller.
884 */
b562468c 885static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 886{
b562468c 887 int i;
31961943 888
b562468c
ML		 889 /* Disable eDMA. The disable bit auto clears. */
890 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 891
b562468c
ML		 892 /* Wait for the chip to confirm eDMA is off. */
893 for (i = 10000; i > 0; i--) {
894 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 895 if (!(reg & EDMA_EN))
b562468c
ML		 896 return 0;
897 udelay(10);
31961943 898 }
b562468c 899 return -EIO;
20f733e7
BR		 900}
901
e12bef50 902static int mv_stop_edma(struct ata_port *ap)
0ea9e179 903{
b562468c
ML		 904 void __iomem *port_mmio = mv_ap_base(ap);
905 struct mv_port_priv *pp = ap->private_data;
0ea9e179 906
b562468c
ML		 907 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
908 return 0;
909 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
910 if (mv_stop_edma_engine(port_mmio)) {
911 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
912 return -EIO;
913 }
914 return 0;
0ea9e179
JG		 915}
916
8a70f8dc 917#ifdef ATA_DEBUG
31961943 918static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 919{
31961943
BR		 920 int b, w;
921 for (b = 0; b < bytes; ) {
922 DPRINTK("%p: ", start + b);
923 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 924 printk("%08x ", readl(start + b));
31961943
BR		 925 b += sizeof(u32);
926 }
927 printk("\n");
928 }
31961943 929}
8a70f8dc
JG		 930#endif
931
31961943
BR		 932static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
933{
934#ifdef ATA_DEBUG
935 int b, w;
936 u32 dw;
937 for (b = 0; b < bytes; ) {
938 DPRINTK("%02x: ", b);
939 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 940 (void) pci_read_config_dword(pdev, b, &dw);
941 printk("%08x ", dw);
31961943
BR		 942 b += sizeof(u32);
943 }
944 printk("\n");
945 }
946#endif
947}
948static void mv_dump_all_regs(void __iomem *mmio_base, int port,
949 struct pci_dev *pdev)
950{
951#ifdef ATA_DEBUG
8b260248 952 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 953 port >> MV_PORT_HC_SHIFT);
954 void __iomem *port_base;
955 int start_port, num_ports, p, start_hc, num_hcs, hc;
956
957 if (0 > port) {
958 start_hc = start_port = 0;
959 num_ports = 8; /* shld be benign for 4 port devs */
960 num_hcs = 2;
961 } else {
962 start_hc = port >> MV_PORT_HC_SHIFT;
963 start_port = port;
964 num_ports = num_hcs = 1;
965 }
8b260248 966 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 967 num_ports > 1 ? num_ports - 1 : start_port);
968
969 if (NULL != pdev) {
970 DPRINTK("PCI config space regs:\n");
971 mv_dump_pci_cfg(pdev, 0x68);
972 }
973 DPRINTK("PCI regs:\n");
974 mv_dump_mem(mmio_base+0xc00, 0x3c);
975 mv_dump_mem(mmio_base+0xd00, 0x34);
976 mv_dump_mem(mmio_base+0xf00, 0x4);
977 mv_dump_mem(mmio_base+0x1d00, 0x6c);
978 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 979 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 980 DPRINTK("HC regs (HC %i):\n", hc);
981 mv_dump_mem(hc_base, 0x1c);
982 }
983 for (p = start_port; p < start_port + num_ports; p++) {
984 port_base = mv_port_base(mmio_base, p);
2dcb407e 985 DPRINTK("EDMA regs (port %i):\n", p);
31961943 986 mv_dump_mem(port_base, 0x54);
2dcb407e 987 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 988 mv_dump_mem(port_base+0x300, 0x60);
989 }
990#endif
20f733e7
BR		 991}
992
993static unsigned int mv_scr_offset(unsigned int sc_reg_in)
994{
995 unsigned int ofs;
996
997 switch (sc_reg_in) {
998 case SCR_STATUS:
999 case SCR_CONTROL:
1000 case SCR_ERROR:
1001 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1002 break;
1003 case SCR_ACTIVE:
1004 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1005 break;
1006 default:
1007 ofs = 0xffffffffU;
1008 break;
1009 }
1010 return ofs;
1011}
1012
da3dbb17 1013static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1014{
1015 unsigned int ofs = mv_scr_offset(sc_reg_in);
1016
da3dbb17
TH		 1017 if (ofs != 0xffffffffU) {
1018 *val = readl(mv_ap_base(ap) + ofs);
1019 return 0;
1020 } else
1021 return -EINVAL;
20f733e7
BR		 1022}
1023
da3dbb17 1024static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1025{
1026 unsigned int ofs = mv_scr_offset(sc_reg_in);
1027
da3dbb17 1028 if (ofs != 0xffffffffU) {
20f733e7 1029 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1030 return 0;
1031 } else
1032 return -EINVAL;
20f733e7
BR		 1033}
1034
f273827e
ML		 1035static void mv6_dev_config(struct ata_device *adev)
1036{
1037 /*
e49856d8
ML		 1038 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1039 *
1040 * Gen-II does not support NCQ over a port multiplier
1041 * (no FIS-based switching).
1042 *
f273827e
ML		 1043 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1044 * See mv_qc_prep() for more info.
1045 */
e49856d8 1046 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1047 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1048 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1049 ata_dev_printk(adev, KERN_INFO,
1050 "NCQ disabled for command-based switching\n");
1051 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1052 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1053 ata_dev_printk(adev, KERN_INFO,
1054 "max_sectors limited to %u for NCQ\n",
1055 adev->max_sectors);
1056 }
e49856d8 1057 }
f273827e
ML		 1058}
1059
e49856d8
ML		 1060static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
1061{
1062 u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode;
1063 /*
1064 * Various bit settings required for operation
1065 * in FIS-based switching (fbs) mode on GenIIe:
1066 */
1067 old_fcfg = readl(port_mmio + FIS_CFG_OFS);
1068 old_ltmode = readl(port_mmio + LTMODE_OFS);
1069 if (enable_fbs) {
1070 new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC;
1071 new_ltmode = old_ltmode | LTMODE_BIT8;
1072 } else { /* disable fbs */
1073 new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC;
1074 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1075 }
1076 if (new_fcfg != old_fcfg)
1077 writelfl(new_fcfg, port_mmio + FIS_CFG_OFS);
1078 if (new_ltmode != old_ltmode)
1079 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
f273827e
ML		 1080}
1081
e12bef50 1082static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1083{
0c58912e 1084 u32 cfg;
e12bef50
ML		 1085 struct mv_port_priv *pp = ap->private_data;
1086 struct mv_host_priv *hpriv = ap->host->private_data;
1087 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1088
1089 /* set up non-NCQ EDMA configuration */
0c58912e 1090 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
e4e7b892 1091
0c58912e 1092 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1093 cfg |= (1 << 8); /* enab config burst size mask */
1094
0c58912e 1095 else if (IS_GEN_II(hpriv))
e4e7b892
JG		 1096 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1097
1098 else if (IS_GEN_IIE(hpriv)) {
e728eabe
JG		 1099 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1100 cfg |= (1 << 22); /* enab 4-entry host queue cache */
e4e7b892 1101 cfg |= (1 << 18); /* enab early completion */
e728eabe 1102 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
e49856d8
ML		 1103
1104 if (want_ncq && sata_pmp_attached(ap)) {
1105 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1106 mv_config_fbs(port_mmio, 1);
1107 } else {
1108 mv_config_fbs(port_mmio, 0);
1109 }
e4e7b892
JG		 1110 }
1111
72109168
ML		 1112 if (want_ncq) {
1113 cfg |= EDMA_CFG_NCQ;
1114 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1115 } else
1116 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1117
e4e7b892
JG		 1118 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1119}
1120
da2fa9ba
ML		 1121static void mv_port_free_dma_mem(struct ata_port *ap)
1122{
1123 struct mv_host_priv *hpriv = ap->host->private_data;
1124 struct mv_port_priv *pp = ap->private_data;
eb73d558 1125 int tag;
da2fa9ba
ML		 1126
1127 if (pp->crqb) {
1128 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1129 pp->crqb = NULL;
1130 }
1131 if (pp->crpb) {
1132 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1133 pp->crpb = NULL;
1134 }
eb73d558
ML		 1135 /*
1136 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1137 * For later hardware, we have one unique sg_tbl per NCQ tag.
1138 */
1139 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1140 if (pp->sg_tbl[tag]) {
1141 if (tag == 0 || !IS_GEN_I(hpriv))
1142 dma_pool_free(hpriv->sg_tbl_pool,
1143 pp->sg_tbl[tag],
1144 pp->sg_tbl_dma[tag]);
1145 pp->sg_tbl[tag] = NULL;
1146 }
da2fa9ba
ML		 1147 }
1148}
1149
05b308e1
BR		 1150/**
1151 * mv_port_start - Port specific init/start routine.
1152 * @ap: ATA channel to manipulate
1153 *
1154 * Allocate and point to DMA memory, init port private memory,
1155 * zero indices.
1156 *
1157 * LOCKING:
1158 * Inherited from caller.
1159 */
31961943
BR		 1160static int mv_port_start(struct ata_port *ap)
1161{
cca3974e
JG		 1162 struct device *dev = ap->host->dev;
1163 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1164 struct mv_port_priv *pp;
dde20207 1165 int tag;
31961943 1166
24dc5f33 1167 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1168 if (!pp)
24dc5f33 1169 return -ENOMEM;
da2fa9ba 1170 ap->private_data = pp;
31961943 1171
da2fa9ba
ML		 1172 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1173 if (!pp->crqb)
1174 return -ENOMEM;
1175 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1176
da2fa9ba
ML		 1177 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1178 if (!pp->crpb)
1179 goto out_port_free_dma_mem;
1180 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1181
eb73d558
ML		 1182 /*
1183 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1184 * For later hardware, we need one unique sg_tbl per NCQ tag.
1185 */
1186 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1187 if (tag == 0 || !IS_GEN_I(hpriv)) {
1188 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1189 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1190 if (!pp->sg_tbl[tag])
1191 goto out_port_free_dma_mem;
1192 } else {
1193 pp->sg_tbl[tag] = pp->sg_tbl[0];
1194 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1195 }
1196 }
31961943 1197 return 0;
da2fa9ba
ML		 1198
1199out_port_free_dma_mem:
1200 mv_port_free_dma_mem(ap);
1201 return -ENOMEM;
31961943
BR		 1202}
1203
05b308e1
BR		 1204/**
1205 * mv_port_stop - Port specific cleanup/stop routine.
1206 * @ap: ATA channel to manipulate
1207 *
1208 * Stop DMA, cleanup port memory.
1209 *
1210 * LOCKING:
cca3974e 1211 * This routine uses the host lock to protect the DMA stop.
05b308e1 1212 */
31961943
BR		 1213static void mv_port_stop(struct ata_port *ap)
1214{
e12bef50 1215 mv_stop_edma(ap);
da2fa9ba 1216 mv_port_free_dma_mem(ap);
31961943
BR		 1217}
1218
05b308e1
BR		 1219/**
1220 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1221 * @qc: queued command whose SG list to source from
1222 *
1223 * Populate the SG list and mark the last entry.
1224 *
1225 * LOCKING:
1226 * Inherited from caller.
1227 */
6c08772e 1228static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1229{
1230 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1231 struct scatterlist *sg;
3be6cbd7 1232 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1233 unsigned int si;
31961943 1234
eb73d558 1235 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1236 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1237 dma_addr_t addr = sg_dma_address(sg);
1238 u32 sg_len = sg_dma_len(sg);
22374677 1239
4007b493
OJ		 1240 while (sg_len) {
1241 u32 offset = addr & 0xffff;
1242 u32 len = sg_len;
22374677 1243
4007b493
OJ		 1244 if ((offset + sg_len > 0x10000))
1245 len = 0x10000 - offset;
1246
1247 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1248 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1249 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1250
1251 sg_len -= len;
1252 addr += len;
1253
3be6cbd7 1254 last_sg = mv_sg;
4007b493 1255 mv_sg++;
4007b493 1256 }
31961943 1257 }
3be6cbd7
JG		 1258
1259 if (likely(last_sg))
1260 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1261}
1262
5796d1c4 1263static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1264{
559eedad 1265 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1266 (last ? CRQB_CMD_LAST : 0);
559eedad 1267 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1268}
1269
05b308e1
BR		 1270/**
1271 * mv_qc_prep - Host specific command preparation.
1272 * @qc: queued command to prepare
1273 *
1274 * This routine simply redirects to the general purpose routine
1275 * if command is not DMA. Else, it handles prep of the CRQB
1276 * (command request block), does some sanity checking, and calls
1277 * the SG load routine.
1278 *
1279 * LOCKING:
1280 * Inherited from caller.
1281 */
31961943
BR		 1282static void mv_qc_prep(struct ata_queued_cmd *qc)
1283{
1284 struct ata_port *ap = qc->ap;
1285 struct mv_port_priv *pp = ap->private_data;
e1469874 1286 __le16 *cw;
31961943
BR		 1287 struct ata_taskfile *tf;
1288 u16 flags = 0;
a6432436 1289 unsigned in_index;
31961943 1290
138bfdd0
ML		 1291 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1292 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1293 return;
20f733e7 1294
31961943
BR		 1295 /* Fill in command request block
1296 */
e4e7b892 1297 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1298 flags |= CRQB_FLAG_READ;
beec7dbc 1299 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1300 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1301 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1302
bdd4ddde 1303 /* get current queue index from software */
fcfb1f77 1304 in_index = pp->req_idx;
a6432436
ML		 1305
1306 pp->crqb[in_index].sg_addr =
eb73d558 1307 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1308 pp->crqb[in_index].sg_addr_hi =
eb73d558 1309 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1310 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1311
a6432436 1312 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1313 tf = &qc->tf;
1314
1315 /* Sadly, the CRQB cannot accomodate all registers--there are
1316 * only 11 bytes...so we must pick and choose required
1317 * registers based on the command. So, we drop feature and
1318 * hob_feature for [RW] DMA commands, but they are needed for
1319 * NCQ. NCQ will drop hob_nsect.
20f733e7 1320 */
31961943
BR		 1321 switch (tf->command) {
1322 case ATA_CMD_READ:
1323 case ATA_CMD_READ_EXT:
1324 case ATA_CMD_WRITE:
1325 case ATA_CMD_WRITE_EXT:
c15d85c8 1326 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1327 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1328 break;
31961943
BR		 1329 case ATA_CMD_FPDMA_READ:
1330 case ATA_CMD_FPDMA_WRITE:
8b260248 1331 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1332 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1333 break;
31961943
BR		 1334 default:
1335 /* The only other commands EDMA supports in non-queued and
1336 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1337 * of which are defined/used by Linux. If we get here, this
1338 * driver needs work.
1339 *
1340 * FIXME: modify libata to give qc_prep a return value and
1341 * return error here.
1342 */
1343 BUG_ON(tf->command);
1344 break;
1345 }
1346 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1347 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1348 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1349 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1350 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1351 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1352 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1353 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1354 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1355
e4e7b892
JG		 1356 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1357 return;
1358 mv_fill_sg(qc);
1359}
1360
1361/**
1362 * mv_qc_prep_iie - Host specific command preparation.
1363 * @qc: queued command to prepare
1364 *
1365 * This routine simply redirects to the general purpose routine
1366 * if command is not DMA. Else, it handles prep of the CRQB
1367 * (command request block), does some sanity checking, and calls
1368 * the SG load routine.
1369 *
1370 * LOCKING:
1371 * Inherited from caller.
1372 */
1373static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1374{
1375 struct ata_port *ap = qc->ap;
1376 struct mv_port_priv *pp = ap->private_data;
1377 struct mv_crqb_iie *crqb;
1378 struct ata_taskfile *tf;
a6432436 1379 unsigned in_index;
e4e7b892
JG		 1380 u32 flags = 0;
1381
138bfdd0
ML		 1382 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1383 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1384 return;
1385
e12bef50 1386 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1387 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1388 flags |= CRQB_FLAG_READ;
1389
beec7dbc 1390 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1391 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1392 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1393 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1394
bdd4ddde 1395 /* get current queue index from software */
fcfb1f77 1396 in_index = pp->req_idx;
a6432436
ML		 1397
1398 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1399 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1400 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1401 crqb->flags = cpu_to_le32(flags);
1402
1403 tf = &qc->tf;
1404 crqb->ata_cmd[0] = cpu_to_le32(
1405 (tf->command << 16) |
1406 (tf->feature << 24)
1407 );
1408 crqb->ata_cmd[1] = cpu_to_le32(
1409 (tf->lbal << 0) |
1410 (tf->lbam << 8) |
1411 (tf->lbah << 16) |
1412 (tf->device << 24)
1413 );
1414 crqb->ata_cmd[2] = cpu_to_le32(
1415 (tf->hob_lbal << 0) |
1416 (tf->hob_lbam << 8) |
1417 (tf->hob_lbah << 16) |
1418 (tf->hob_feature << 24)
1419 );
1420 crqb->ata_cmd[3] = cpu_to_le32(
1421 (tf->nsect << 0) |
1422 (tf->hob_nsect << 8)
1423 );
1424
1425 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1426 return;
31961943
BR		 1427 mv_fill_sg(qc);
1428}
1429
05b308e1
BR		 1430/**
1431 * mv_qc_issue - Initiate a command to the host
1432 * @qc: queued command to start
1433 *
1434 * This routine simply redirects to the general purpose routine
1435 * if command is not DMA. Else, it sanity checks our local
1436 * caches of the request producer/consumer indices then enables
1437 * DMA and bumps the request producer index.
1438 *
1439 * LOCKING:
1440 * Inherited from caller.
1441 */
9a3d9eb0 1442static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1443{
c5d3e45a
JG		 1444 struct ata_port *ap = qc->ap;
1445 void __iomem *port_mmio = mv_ap_base(ap);
1446 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1447 u32 in_index;
31961943 1448
138bfdd0
ML		 1449 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1450 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1451 /*
1452 * We're about to send a non-EDMA capable command to the
31961943
BR		 1453 * port. Turn off EDMA so there won't be problems accessing
1454 * shadow block, etc registers.
1455 */
b562468c 1456 mv_stop_edma(ap);
e49856d8 1457 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1458 return ata_sff_qc_issue(qc);
31961943
BR		 1459 }
1460
72109168 1461 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1462
fcfb1f77
ML		 1463 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1464 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1465
1466 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1467 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1468 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1469
1470 return 0;
1471}
1472
8f767f8a
ML		 1473static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1474{
1475 struct mv_port_priv *pp = ap->private_data;
1476 struct ata_queued_cmd *qc;
1477
1478 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1479 return NULL;
1480 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1481 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1482 qc = NULL;
1483 return qc;
1484}
1485
1486static void mv_unexpected_intr(struct ata_port *ap)
1487{
1488 struct mv_port_priv *pp = ap->private_data;
1489 struct ata_eh_info *ehi = &ap->link.eh_info;
1490 char *when = "";
1491
1492 /*
1493 * We got a device interrupt from something that
1494 * was supposed to be using EDMA or polling.
1495 */
1496 ata_ehi_clear_desc(ehi);
1497 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1498 when = " while EDMA enabled";
1499 } else {
1500 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1501 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1502 when = " while polling";
1503 }
1504 ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when);
1505 ehi->err_mask |= AC_ERR_OTHER;
1506 ehi->action |= ATA_EH_RESET;
1507 ata_port_freeze(ap);
1508}
1509
05b308e1
BR		 1510/**
1511 * mv_err_intr - Handle error interrupts on the port
1512 * @ap: ATA channel to manipulate
8d07379d 1513 * @qc: affected command (non-NCQ), or NULL
05b308e1 1514 *
8d07379d
ML		 1515 * Most cases require a full reset of the chip's state machine,
1516 * which also performs a COMRESET.
1517 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1518 *
1519 * LOCKING:
1520 * Inherited from caller.
1521 */
bdd4ddde 1522static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
31961943
BR		 1523{
1524 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde
JG		 1525 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1526 struct mv_port_priv *pp = ap->private_data;
1527 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1528 unsigned int action = 0, err_mask = 0;
9af5c9c9 1529 struct ata_eh_info *ehi = &ap->link.eh_info;
20f733e7 1530
bdd4ddde 1531 ata_ehi_clear_desc(ehi);
20f733e7 1532
8d07379d
ML		 1533 /*
1534 * Read and clear the err_cause bits. This won't actually
1535 * clear for some errors (eg. SError), but we will be doing
1536 * a hard reset in those cases regardless, which *will* clear it.
1537 */
bdd4ddde 1538 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
8d07379d 1539 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1540
352fab70 1541 ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause);
bdd4ddde
JG		 1542
1543 /*
352fab70 1544 * All generations share these EDMA error cause bits:
bdd4ddde 1545 */
bdd4ddde
JG		 1546 if (edma_err_cause & EDMA_ERR_DEV)
1547 err_mask |= AC_ERR_DEV;
1548 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1549 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1550 EDMA_ERR_INTRL_PAR)) {
1551 err_mask |= AC_ERR_ATA_BUS;
cf480626 1552 action |= ATA_EH_RESET;
b64bbc39 1553 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1554 }
1555 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1556 ata_ehi_hotplugged(ehi);
1557 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1558 "dev disconnect" : "dev connect");
cf480626 1559 action |= ATA_EH_RESET;
bdd4ddde
JG		 1560 }
1561
352fab70
ML		 1562 /*
1563 * Gen-I has a different SELF_DIS bit,
1564 * different FREEZE bits, and no SERR bit:
1565 */
ee9ccdf7 1566 if (IS_GEN_I(hpriv)) {
bdd4ddde 1567 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1568 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1569 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1570 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1571 }
1572 } else {
1573 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1574 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1575 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1576 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1577 }
bdd4ddde 1578 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1579 /*
1580 * Ensure that we read our own SCR, not a pmp link SCR:
1581 */
1582 ap->ops->scr_read(ap, SCR_ERROR, &serr);
1583 /*
1584 * Don't clear SError here; leave it for libata-eh:
1585 */
1586 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1587 err_mask |= AC_ERR_ATA_BUS;
cf480626 1588 action |= ATA_EH_RESET;
bdd4ddde 1589 }
afb0edd9 1590 }
20f733e7 1591
bdd4ddde
JG		 1592 if (!err_mask) {
1593 err_mask = AC_ERR_OTHER;
cf480626 1594 action |= ATA_EH_RESET;
bdd4ddde
JG		 1595 }
1596
1597 ehi->serror |= serr;
1598 ehi->action |= action;
1599
1600 if (qc)
1601 qc->err_mask |= err_mask;
1602 else
1603 ehi->err_mask |= err_mask;
1604
1605 if (edma_err_cause & eh_freeze_mask)
1606 ata_port_freeze(ap);
1607 else
1608 ata_port_abort(ap);
1609}
1610
fcfb1f77
ML		 1611static void mv_process_crpb_response(struct ata_port *ap,
1612 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1613{
1614 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1615
1616 if (qc) {
1617 u8 ata_status;
1618 u16 edma_status = le16_to_cpu(response->flags);
1619 /*
1620 * edma_status from a response queue entry:
1621 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1622 * MSB is saved ATA status from command completion.
1623 */
1624 if (!ncq_enabled) {
1625 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1626 if (err_cause) {
1627 /*
1628 * Error will be seen/handled by mv_err_intr().
1629 * So do nothing at all here.
1630 */
1631 return;
1632 }
1633 }
1634 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1635 qc->err_mask |= ac_err_mask(ata_status);
1636 ata_qc_complete(qc);
1637 } else {
1638 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1639 __func__, tag);
1640 }
1641}
1642
1643static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1644{
1645 void __iomem *port_mmio = mv_ap_base(ap);
1646 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1647 u32 in_index;
bdd4ddde 1648 bool work_done = false;
fcfb1f77 1649 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1650
fcfb1f77 1651 /* Get the hardware queue position index */
bdd4ddde
JG		 1652 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1653 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1654
fcfb1f77
ML		 1655 /* Process new responses from since the last time we looked */
1656 while (in_index != pp->resp_idx) {
6c1153e0 1657 unsigned int tag;
fcfb1f77 1658 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1659
fcfb1f77 1660 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1661
fcfb1f77
ML		 1662 if (IS_GEN_I(hpriv)) {
1663 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1664 tag = ap->link.active_tag;
fcfb1f77
ML		 1665 } else {
1666 /* Gen II/IIE: get command tag from CRPB entry */
1667 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1668 }
fcfb1f77 1669 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 1670 work_done = true;
bdd4ddde
JG		 1671 }
1672
352fab70 1673 /* Update the software queue position index in hardware */
bdd4ddde
JG		 1674 if (work_done)
1675 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 1676 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 1677 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 1678}
1679
05b308e1
BR		 1680/**
1681 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1682 * @host: host specific structure
7368f919 1683 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 1684 *
1685 * LOCKING:
1686 * Inherited from caller.
1687 */
7368f919 1688static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 1689{
f351b2d6 1690 struct mv_host_priv *hpriv = host->private_data;
a3718c1f
ML		 1691 void __iomem *mmio = hpriv->base, *hc_mmio = NULL;
1692 u32 hc_irq_cause = 0;
1693 unsigned int handled = 0, port;
20f733e7 1694
a3718c1f 1695 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 1696 struct ata_port *ap = host->ports[port];
8f71efe2 1697 struct mv_port_priv *pp;
a3718c1f
ML		 1698 unsigned int shift, hardport, port_cause;
1699 /*
1700 * When we move to the second hc, flag our cached
1701 * copies of hc_mmio (and hc_irq_cause) as invalid again.
1702 */
1703 if (port == MV_PORTS_PER_HC)
1704 hc_mmio = NULL;
1705 /*
1706 * Do nothing if port is not interrupting or is disabled:
1707 */
1708 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
7368f919 1709 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
a3718c1f 1710 if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED))
a2c91a88 1711 continue;
a3718c1f
ML		 1712 /*
1713 * Each hc within the host has its own hc_irq_cause register.
1714 * We defer reading it until we know we need it, right now:
1715 *
1716 * FIXME later: we don't really need to read this register
1717 * (some logic changes required below if we go that way),
1718 * because it doesn't tell us anything new. But we do need
1719 * to write to it, outside the top of this loop,
1720 * to reset the interrupt triggers for next time.
1721 */
1722 if (!hc_mmio) {
1723 hc_mmio = mv_hc_base_from_port(mmio, port);
1724 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1725 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1726 handled = 1;
1727 }
8f767f8a
ML		 1728 /*
1729 * Process completed CRPB response(s) before other events.
1730 */
a3718c1f 1731 pp = ap->private_data;
8f767f8a
ML		 1732 if (hc_irq_cause & (DMA_IRQ << hardport)) {
1733 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN)
fcfb1f77 1734 mv_process_crpb_entries(ap, pp);
8f767f8a
ML		 1735 }
1736 /*
1737 * Handle chip-reported errors, or continue on to handle PIO.
1738 */
1739 if (unlikely(port_cause & ERR_IRQ)) {
1740 mv_err_intr(ap, mv_get_active_qc(ap));
1741 } else if (hc_irq_cause & (DEV_IRQ << hardport)) {
1742 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1743 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
1744 if (qc) {
1745 ata_sff_host_intr(ap, qc);
1746 continue;
1747 }
1748 }
1749 mv_unexpected_intr(ap);
20f733e7
BR		 1750 }
1751 }
a3718c1f 1752 return handled;
20f733e7
BR		 1753}
1754
a3718c1f 1755static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 1756{
02a121da 1757 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 1758 struct ata_port *ap;
1759 struct ata_queued_cmd *qc;
1760 struct ata_eh_info *ehi;
1761 unsigned int i, err_mask, printed = 0;
1762 u32 err_cause;
1763
02a121da 1764 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1765
1766 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1767 err_cause);
1768
1769 DPRINTK("All regs @ PCI error\n");
1770 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1771
02a121da 1772 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1773
1774 for (i = 0; i < host->n_ports; i++) {
1775 ap = host->ports[i];
936fd732 1776 if (!ata_link_offline(&ap->link)) {
9af5c9c9 1777 ehi = &ap->link.eh_info;
bdd4ddde
JG		 1778 ata_ehi_clear_desc(ehi);
1779 if (!printed++)
1780 ata_ehi_push_desc(ehi,
1781 "PCI err cause 0x%08x", err_cause);
1782 err_mask = AC_ERR_HOST_BUS;
cf480626 1783 ehi->action = ATA_EH_RESET;
9af5c9c9 1784 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 1785 if (qc)
1786 qc->err_mask |= err_mask;
1787 else
1788 ehi->err_mask |= err_mask;
1789
1790 ata_port_freeze(ap);
1791 }
1792 }
a3718c1f 1793 return 1; /* handled */
bdd4ddde
JG		 1794}
1795
05b308e1 1796/**
c5d3e45a 1797 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 1798 * @irq: unused
1799 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 1800 *
1801 * Read the read only register to determine if any host
1802 * controllers have pending interrupts. If so, call lower level
1803 * routine to handle. Also check for PCI errors which are only
1804 * reported here.
1805 *
8b260248 1806 * LOCKING:
cca3974e 1807 * This routine holds the host lock while processing pending
05b308e1
BR		 1808 * interrupts.
1809 */
7d12e780 1810static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1811{
cca3974e 1812 struct ata_host *host = dev_instance;
f351b2d6 1813 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 1814 unsigned int handled = 0;
7368f919 1815 u32 main_irq_cause, main_irq_mask;
20f733e7 1816
646a4da5 1817 spin_lock(&host->lock);
7368f919
ML		 1818 main_irq_cause = readl(hpriv->main_irq_cause_addr);
1819 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 1820 /*
1821 * Deal with cases where we either have nothing pending, or have read
1822 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 1823 */
7368f919
ML		 1824 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
1825 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 1826 handled = mv_pci_error(host, hpriv->base);
1827 else
7368f919 1828 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 1829 }
cca3974e 1830 spin_unlock(&host->lock);
20f733e7
BR		 1831 return IRQ_RETVAL(handled);
1832}
1833
c9d39130
JG		 1834static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1835{
1836 unsigned int ofs;
1837
1838 switch (sc_reg_in) {
1839 case SCR_STATUS:
1840 case SCR_ERROR:
1841 case SCR_CONTROL:
1842 ofs = sc_reg_in * sizeof(u32);
1843 break;
1844 default:
1845 ofs = 0xffffffffU;
1846 break;
1847 }
1848 return ofs;
1849}
1850
da3dbb17 1851static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 1852{
f351b2d6
SB		 1853 struct mv_host_priv *hpriv = ap->host->private_data;
1854 void __iomem *mmio = hpriv->base;
0d5ff566 1855 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1856 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1857
da3dbb17
TH		 1858 if (ofs != 0xffffffffU) {
1859 *val = readl(addr + ofs);
1860 return 0;
1861 } else
1862 return -EINVAL;
c9d39130
JG		 1863}
1864
da3dbb17 1865static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 1866{
f351b2d6
SB		 1867 struct mv_host_priv *hpriv = ap->host->private_data;
1868 void __iomem *mmio = hpriv->base;
0d5ff566 1869 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1870 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1871
da3dbb17 1872 if (ofs != 0xffffffffU) {
0d5ff566 1873 writelfl(val, addr + ofs);
da3dbb17
TH		 1874 return 0;
1875 } else
1876 return -EINVAL;
c9d39130
JG		 1877}
1878
7bb3c529 1879static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 1880{
7bb3c529 1881 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 1882 int early_5080;
1883
44c10138 1884 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 1885
1886 if (!early_5080) {
1887 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1888 tmp |= (1 << 0);
1889 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1890 }
1891
7bb3c529 1892 mv_reset_pci_bus(host, mmio);
522479fb
JG		 1893}
1894
1895static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1896{
1897 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1898}
1899
47c2b677 1900static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1901 void __iomem *mmio)
1902{
c9d39130
JG		 1903 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1904 u32 tmp;
1905
1906 tmp = readl(phy_mmio + MV5_PHY_MODE);
1907
1908 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1909 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1910}
1911
47c2b677 1912static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1913{
522479fb
JG		 1914 u32 tmp;
1915
1916 writel(0, mmio + MV_GPIO_PORT_CTL);
1917
1918 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1919
1920 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1921 tmp |= ~(1 << 0);
1922 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1923}
1924
2a47ce06
JG		 1925static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1926 unsigned int port)
bca1c4eb 1927{
c9d39130
JG		 1928 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1929 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1930 u32 tmp;
1931 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1932
1933 if (fix_apm_sq) {
1934 tmp = readl(phy_mmio + MV5_LT_MODE);
1935 tmp |= (1 << 19);
1936 writel(tmp, phy_mmio + MV5_LT_MODE);
1937
1938 tmp = readl(phy_mmio + MV5_PHY_CTL);
1939 tmp &= ~0x3;
1940 tmp |= 0x1;
1941 writel(tmp, phy_mmio + MV5_PHY_CTL);
1942 }
1943
1944 tmp = readl(phy_mmio + MV5_PHY_MODE);
1945 tmp &= ~mask;
1946 tmp |= hpriv->signal[port].pre;
1947 tmp |= hpriv->signal[port].amps;
1948 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1949}
1950
c9d39130
JG		 1951
1952#undef ZERO
1953#define ZERO(reg) writel(0, port_mmio + (reg))
1954static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1955 unsigned int port)
1956{
1957 void __iomem *port_mmio = mv_port_base(mmio, port);
1958
b562468c
ML		 1959 /*
1960 * The datasheet warns against setting ATA_RST when EDMA is active
1961 * (but doesn't say what the problem might be). So we first try
1962 * to disable the EDMA engine before doing the ATA_RST operation.
1963 */
e12bef50 1964 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 1965
1966 ZERO(0x028); /* command */
1967 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1968 ZERO(0x004); /* timer */
1969 ZERO(0x008); /* irq err cause */
1970 ZERO(0x00c); /* irq err mask */
1971 ZERO(0x010); /* rq bah */
1972 ZERO(0x014); /* rq inp */
1973 ZERO(0x018); /* rq outp */
1974 ZERO(0x01c); /* respq bah */
1975 ZERO(0x024); /* respq outp */
1976 ZERO(0x020); /* respq inp */
1977 ZERO(0x02c); /* test control */
1978 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1979}
1980#undef ZERO
1981
1982#define ZERO(reg) writel(0, hc_mmio + (reg))
1983static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1984 unsigned int hc)
47c2b677 1985{
c9d39130
JG		 1986 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1987 u32 tmp;
1988
1989 ZERO(0x00c);
1990 ZERO(0x010);
1991 ZERO(0x014);
1992 ZERO(0x018);
1993
1994 tmp = readl(hc_mmio + 0x20);
1995 tmp &= 0x1c1c1c1c;
1996 tmp |= 0x03030303;
1997 writel(tmp, hc_mmio + 0x20);
1998}
1999#undef ZERO
2000
2001static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2002 unsigned int n_hc)
2003{
2004 unsigned int hc, port;
2005
2006 for (hc = 0; hc < n_hc; hc++) {
2007 for (port = 0; port < MV_PORTS_PER_HC; port++)
2008 mv5_reset_hc_port(hpriv, mmio,
2009 (hc * MV_PORTS_PER_HC) + port);
2010
2011 mv5_reset_one_hc(hpriv, mmio, hc);
2012 }
2013
2014 return 0;
47c2b677
JG		 2015}
2016
101ffae2
JG		 2017#undef ZERO
2018#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2019static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2020{
02a121da 2021 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2022 u32 tmp;
2023
2024 tmp = readl(mmio + MV_PCI_MODE);
2025 tmp &= 0xff00ffff;
2026 writel(tmp, mmio + MV_PCI_MODE);
2027
2028 ZERO(MV_PCI_DISC_TIMER);
2029 ZERO(MV_PCI_MSI_TRIGGER);
2030 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
7368f919 2031 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2032 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2033 ZERO(hpriv->irq_cause_ofs);
2034 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2035 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2036 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2037 ZERO(MV_PCI_ERR_ATTRIBUTE);
2038 ZERO(MV_PCI_ERR_COMMAND);
2039}
2040#undef ZERO
2041
2042static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2043{
2044 u32 tmp;
2045
2046 mv5_reset_flash(hpriv, mmio);
2047
2048 tmp = readl(mmio + MV_GPIO_PORT_CTL);
2049 tmp &= 0x3;
2050 tmp |= (1 << 5) | (1 << 6);
2051 writel(tmp, mmio + MV_GPIO_PORT_CTL);
2052}
2053
2054/**
2055 * mv6_reset_hc - Perform the 6xxx global soft reset
2056 * @mmio: base address of the HBA
2057 *
2058 * This routine only applies to 6xxx parts.
2059 *
2060 * LOCKING:
2061 * Inherited from caller.
2062 */
c9d39130
JG		 2063static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2064 unsigned int n_hc)
101ffae2
JG		 2065{
2066 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2067 int i, rc = 0;
2068 u32 t;
2069
2070 /* Following procedure defined in PCI "main command and status
2071 * register" table.
2072 */
2073 t = readl(reg);
2074 writel(t | STOP_PCI_MASTER, reg);
2075
2076 for (i = 0; i < 1000; i++) {
2077 udelay(1);
2078 t = readl(reg);
2dcb407e 2079 if (PCI_MASTER_EMPTY & t)
101ffae2 2080 break;
101ffae2
JG		 2081 }
2082 if (!(PCI_MASTER_EMPTY & t)) {
2083 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2084 rc = 1;
2085 goto done;
2086 }
2087
2088 /* set reset */
2089 i = 5;
2090 do {
2091 writel(t | GLOB_SFT_RST, reg);
2092 t = readl(reg);
2093 udelay(1);
2094 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2095
2096 if (!(GLOB_SFT_RST & t)) {
2097 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2098 rc = 1;
2099 goto done;
2100 }
2101
2102 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2103 i = 5;
2104 do {
2105 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2106 t = readl(reg);
2107 udelay(1);
2108 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2109
2110 if (GLOB_SFT_RST & t) {
2111 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2112 rc = 1;
2113 }
2114done:
2115 return rc;
2116}
2117
47c2b677 2118static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2119 void __iomem *mmio)
2120{
2121 void __iomem *port_mmio;
2122 u32 tmp;
2123
ba3fe8fb
JG		 2124 tmp = readl(mmio + MV_RESET_CFG);
2125 if ((tmp & (1 << 0)) == 0) {
47c2b677 2126 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2127 hpriv->signal[idx].pre = 0x1 << 5;
2128 return;
2129 }
2130
2131 port_mmio = mv_port_base(mmio, idx);
2132 tmp = readl(port_mmio + PHY_MODE2);
2133
2134 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2135 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2136}
2137
47c2b677 2138static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2139{
47c2b677 2140 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
ba3fe8fb
JG		 2141}
2142
c9d39130 2143static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2144 unsigned int port)
bca1c4eb 2145{
c9d39130
JG		 2146 void __iomem *port_mmio = mv_port_base(mmio, port);
2147
bca1c4eb 2148 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2149 int fix_phy_mode2 =
2150 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2151 int fix_phy_mode4 =
47c2b677
JG		 2152 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2153 u32 m2, tmp;
2154
2155 if (fix_phy_mode2) {
2156 m2 = readl(port_mmio + PHY_MODE2);
2157 m2 &= ~(1 << 16);
2158 m2 |= (1 << 31);
2159 writel(m2, port_mmio + PHY_MODE2);
2160
2161 udelay(200);
2162
2163 m2 = readl(port_mmio + PHY_MODE2);
2164 m2 &= ~((1 << 16) | (1 << 31));
2165 writel(m2, port_mmio + PHY_MODE2);
2166
2167 udelay(200);
2168 }
2169
2170 /* who knows what this magic does */
2171 tmp = readl(port_mmio + PHY_MODE3);
2172 tmp &= ~0x7F800000;
2173 tmp |= 0x2A800000;
2174 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2175
2176 if (fix_phy_mode4) {
47c2b677 2177 u32 m4;
bca1c4eb
JG		 2178
2179 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2180
2181 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2182 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2183
e12bef50 2184 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2185 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2186
2187 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2188
2189 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2190 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2191 }
2192
2193 /* Revert values of pre-emphasis and signal amps to the saved ones */
2194 m2 = readl(port_mmio + PHY_MODE2);
2195
2196 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2197 m2 |= hpriv->signal[port].amps;
2198 m2 |= hpriv->signal[port].pre;
47c2b677 2199 m2 &= ~(1 << 16);
bca1c4eb 2200
e4e7b892
JG		 2201 /* according to mvSata 3.6.1, some IIE values are fixed */
2202 if (IS_GEN_IIE(hpriv)) {
2203 m2 &= ~0xC30FF01F;
2204 m2 |= 0x0000900F;
2205 }
2206
bca1c4eb
JG		 2207 writel(m2, port_mmio + PHY_MODE2);
2208}
2209
f351b2d6
SB		 2210/* TODO: use the generic LED interface to configure the SATA Presence */
2211/* & Acitivy LEDs on the board */
2212static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2213 void __iomem *mmio)
2214{
2215 return;
2216}
2217
2218static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2219 void __iomem *mmio)
2220{
2221 void __iomem *port_mmio;
2222 u32 tmp;
2223
2224 port_mmio = mv_port_base(mmio, idx);
2225 tmp = readl(port_mmio + PHY_MODE2);
2226
2227 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2228 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2229}
2230
2231#undef ZERO
2232#define ZERO(reg) writel(0, port_mmio + (reg))
2233static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2234 void __iomem *mmio, unsigned int port)
2235{
2236 void __iomem *port_mmio = mv_port_base(mmio, port);
2237
b562468c
ML		 2238 /*
2239 * The datasheet warns against setting ATA_RST when EDMA is active
2240 * (but doesn't say what the problem might be). So we first try
2241 * to disable the EDMA engine before doing the ATA_RST operation.
2242 */
e12bef50 2243 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2244
2245 ZERO(0x028); /* command */
2246 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2247 ZERO(0x004); /* timer */
2248 ZERO(0x008); /* irq err cause */
2249 ZERO(0x00c); /* irq err mask */
2250 ZERO(0x010); /* rq bah */
2251 ZERO(0x014); /* rq inp */
2252 ZERO(0x018); /* rq outp */
2253 ZERO(0x01c); /* respq bah */
2254 ZERO(0x024); /* respq outp */
2255 ZERO(0x020); /* respq inp */
2256 ZERO(0x02c); /* test control */
2257 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
2258}
2259
2260#undef ZERO
2261
2262#define ZERO(reg) writel(0, hc_mmio + (reg))
2263static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2264 void __iomem *mmio)
2265{
2266 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2267
2268 ZERO(0x00c);
2269 ZERO(0x010);
2270 ZERO(0x014);
2271
2272}
2273
2274#undef ZERO
2275
2276static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2277 void __iomem *mmio, unsigned int n_hc)
2278{
2279 unsigned int port;
2280
2281 for (port = 0; port < hpriv->n_ports; port++)
2282 mv_soc_reset_hc_port(hpriv, mmio, port);
2283
2284 mv_soc_reset_one_hc(hpriv, mmio);
2285
2286 return 0;
2287}
2288
2289static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2290 void __iomem *mmio)
2291{
2292 return;
2293}
2294
2295static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2296{
2297 return;
2298}
2299
b67a1064
ML		 2300static void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i)
2301{
2302 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG);
2303
2304 ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */
2305 if (want_gen2i)
2306 ifctl |= (1 << 7); /* enable gen2i speed */
2307 writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG);
2308}
2309
b562468c
ML		 2310/*
2311 * Caller must ensure that EDMA is not active,
2312 * by first doing mv_stop_edma() where needed.
2313 */
e12bef50 2314static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2315 unsigned int port_no)
2316{
2317 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2318
0d8be5cb 2319 mv_stop_edma_engine(port_mmio);
c9d39130
JG		 2320 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
2321
b67a1064
ML		 2322 if (!IS_GEN_I(hpriv)) {
2323 /* Enable 3.0gb/s link speed */
2324 mv_setup_ifctl(port_mmio, 1);
c9d39130 2325 }
b67a1064
ML		 2326 /*
2327 * Strobing ATA_RST here causes a hard reset of the SATA transport,
2328 * link, and physical layers. It resets all SATA interface registers
2329 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2330 */
b67a1064
ML		 2331 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
2332 udelay(25); /* allow reset propagation */
c9d39130
JG		 2333 writelfl(0, port_mmio + EDMA_CMD_OFS);
2334
2335 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2336
ee9ccdf7 2337 if (IS_GEN_I(hpriv))
c9d39130
JG		 2338 mdelay(1);
2339}
2340
e49856d8 2341static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2342{
e49856d8
ML		 2343 if (sata_pmp_supported(ap)) {
2344 void __iomem *port_mmio = mv_ap_base(ap);
2345 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2346 int old = reg & 0xf;
22374677 2347
e49856d8
ML		 2348 if (old != pmp) {
2349 reg = (reg & ~0xf) | pmp;
2350 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2351 }
22374677 2352 }
20f733e7
BR		 2353}
2354
e49856d8
ML		 2355static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2356 unsigned long deadline)
22374677 2357{
e49856d8
ML		 2358 mv_pmp_select(link->ap, sata_srst_pmp(link));
2359 return sata_std_hardreset(link, class, deadline);
2360}
bdd4ddde 2361
e49856d8
ML		 2362static int mv_softreset(struct ata_link *link, unsigned int *class,
2363 unsigned long deadline)
2364{
2365 mv_pmp_select(link->ap, sata_srst_pmp(link));
2366 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2367}
2368
cc0680a5 2369static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2370 unsigned long deadline)
31961943 2371{
cc0680a5 2372 struct ata_port *ap = link->ap;
bdd4ddde 2373 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2374 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2375 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2376 int rc, attempts = 0, extra = 0;
2377 u32 sstatus;
2378 bool online;
31961943 2379
e12bef50 2380 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2381 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2382
0d8be5cb
ML		 2383 /* Workaround for errata FEr SATA#10 (part 2) */
2384 do {
17c5aab5
ML		 2385 const unsigned long *timing =
2386 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2387
17c5aab5
ML		 2388 rc = sata_link_hardreset(link, timing, deadline + extra,
2389 &online, NULL);
2390 if (rc)
0d8be5cb 2391 return rc;
0d8be5cb
ML		 2392 sata_scr_read(link, SCR_STATUS, &sstatus);
2393 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2394 /* Force 1.5gb/s link speed and try again */
2395 mv_setup_ifctl(mv_ap_base(ap), 0);
2396 if (time_after(jiffies + HZ, deadline))
2397 extra = HZ; /* only extend it once, max */
2398 }
2399 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2400
17c5aab5 2401 return rc;
bdd4ddde
JG		 2402}
2403
bdd4ddde
JG		 2404static void mv_eh_freeze(struct ata_port *ap)
2405{
f351b2d6 2406 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2407 unsigned int shift, hardport, port = ap->port_no;
7368f919 2408 u32 main_irq_mask;
bdd4ddde
JG		 2409
2410 /* FIXME: handle coalescing completion events properly */
2411
1cfd19ae
ML		 2412 mv_stop_edma(ap);
2413 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2414
bdd4ddde 2415 /* disable assertion of portN err, done events */
7368f919
ML		 2416 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2417 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2418 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2419}
2420
2421static void mv_eh_thaw(struct ata_port *ap)
2422{
f351b2d6 2423 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2424 unsigned int shift, hardport, port = ap->port_no;
2425 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2426 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2427 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2428
2429 /* FIXME: handle coalescing completion events properly */
2430
1cfd19ae 2431 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2432
bdd4ddde
JG		 2433 /* clear EDMA errors on this port */
2434 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2435
2436 /* clear pending irq events */
2437 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2438 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2439 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2440
2441 /* enable assertion of portN err, done events */
7368f919
ML		 2442 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2443 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2444 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2445}
2446
05b308e1
BR		 2447/**
2448 * mv_port_init - Perform some early initialization on a single port.
2449 * @port: libata data structure storing shadow register addresses
2450 * @port_mmio: base address of the port
2451 *
2452 * Initialize shadow register mmio addresses, clear outstanding
2453 * interrupts on the port, and unmask interrupts for the future
2454 * start of the port.
2455 *
2456 * LOCKING:
2457 * Inherited from caller.
2458 */
31961943 2459static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2460{
0d5ff566 2461 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2462 unsigned serr_ofs;
2463
8b260248 2464 /* PIO related setup
31961943
BR		 2465 */
2466 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2467 port->error_addr =
31961943
BR		 2468 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2469 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2470 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2471 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2472 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2473 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2474 port->status_addr =
31961943
BR		 2475 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2476 /* special case: control/altstatus doesn't have ATA_REG_ address */
2477 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2478
2479 /* unused: */
8d9db2d2 2480 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2481
31961943
BR		 2482 /* Clear any currently outstanding port interrupt conditions */
2483 serr_ofs = mv_scr_offset(SCR_ERROR);
2484 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2485 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2486
646a4da5
ML		 2487 /* unmask all non-transient EDMA error interrupts */
2488 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2489
8b260248 2490 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2491 readl(port_mmio + EDMA_CFG_OFS),
2492 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2493 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2494}
2495
4447d351 2496static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2497{
4447d351
TH		 2498 struct pci_dev *pdev = to_pci_dev(host->dev);
2499 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2500 u32 hp_flags = hpriv->hp_flags;
2501
5796d1c4 2502 switch (board_idx) {
47c2b677
JG		 2503 case chip_5080:
2504 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2505 hp_flags |= MV_HP_GEN_I;
47c2b677 2506
44c10138 2507 switch (pdev->revision) {
47c2b677
JG		 2508 case 0x1:
2509 hp_flags |= MV_HP_ERRATA_50XXB0;
2510 break;
2511 case 0x3:
2512 hp_flags |= MV_HP_ERRATA_50XXB2;
2513 break;
2514 default:
2515 dev_printk(KERN_WARNING, &pdev->dev,
2516 "Applying 50XXB2 workarounds to unknown rev\n");
2517 hp_flags |= MV_HP_ERRATA_50XXB2;
2518 break;
2519 }
2520 break;
2521
bca1c4eb
JG		 2522 case chip_504x:
2523 case chip_508x:
47c2b677 2524 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2525 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2526
44c10138 2527 switch (pdev->revision) {
47c2b677
JG		 2528 case 0x0:
2529 hp_flags |= MV_HP_ERRATA_50XXB0;
2530 break;
2531 case 0x3:
2532 hp_flags |= MV_HP_ERRATA_50XXB2;
2533 break;
2534 default:
2535 dev_printk(KERN_WARNING, &pdev->dev,
2536 "Applying B2 workarounds to unknown rev\n");
2537 hp_flags |= MV_HP_ERRATA_50XXB2;
2538 break;
bca1c4eb
JG		 2539 }
2540 break;
2541
2542 case chip_604x:
2543 case chip_608x:
47c2b677 2544 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2545 hp_flags |= MV_HP_GEN_II;
47c2b677 2546
44c10138 2547 switch (pdev->revision) {
47c2b677
JG		 2548 case 0x7:
2549 hp_flags |= MV_HP_ERRATA_60X1B2;
2550 break;
2551 case 0x9:
2552 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2553 break;
2554 default:
2555 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2556 "Applying B2 workarounds to unknown rev\n");
2557 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2558 break;
2559 }
2560 break;
2561
e4e7b892 2562 case chip_7042:
02a121da 2563 hp_flags |= MV_HP_PCIE;
306b30f7
ML		 2564 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2565 (pdev->device == 0x2300 || pdev->device == 0x2310))
2566 {
4e520033
ML		 2567 /*
2568 * Highpoint RocketRAID PCIe 23xx series cards:
2569 *
2570 * Unconfigured drives are treated as "Legacy"
2571 * by the BIOS, and it overwrites sector 8 with
2572 * a "Lgcy" metadata block prior to Linux boot.
2573 *
2574 * Configured drives (RAID or JBOD) leave sector 8
2575 * alone, but instead overwrite a high numbered
2576 * sector for the RAID metadata. This sector can
2577 * be determined exactly, by truncating the physical
2578 * drive capacity to a nice even GB value.
2579 *
2580 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2581 *
2582 * Warn the user, lest they think we're just buggy.
2583 */
2584 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2585 " BIOS CORRUPTS DATA on all attached drives,"
2586 " regardless of if/how they are configured."
2587 " BEWARE!\n");
2588 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2589 " use sectors 8-9 on \"Legacy\" drives,"
2590 " and avoid the final two gigabytes on"
2591 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2592 }
e4e7b892
JG		 2593 case chip_6042:
2594 hpriv->ops = &mv6xxx_ops;
e4e7b892
JG		 2595 hp_flags |= MV_HP_GEN_IIE;
2596
44c10138 2597 switch (pdev->revision) {
e4e7b892
JG		 2598 case 0x0:
2599 hp_flags |= MV_HP_ERRATA_XX42A0;
2600 break;
2601 case 0x1:
2602 hp_flags |= MV_HP_ERRATA_60X1C0;
2603 break;
2604 default:
2605 dev_printk(KERN_WARNING, &pdev->dev,
2606 "Applying 60X1C0 workarounds to unknown rev\n");
2607 hp_flags |= MV_HP_ERRATA_60X1C0;
2608 break;
2609 }
2610 break;
f351b2d6
SB		 2611 case chip_soc:
2612 hpriv->ops = &mv_soc_ops;
2613 hp_flags |= MV_HP_ERRATA_60X1C0;
2614 break;
e4e7b892 2615
bca1c4eb 2616 default:
f351b2d6 2617 dev_printk(KERN_ERR, host->dev,
5796d1c4 2618 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2619 return 1;
2620 }
2621
2622 hpriv->hp_flags = hp_flags;
02a121da
ML		 2623 if (hp_flags & MV_HP_PCIE) {
2624 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2625 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2626 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2627 } else {
2628 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2629 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2630 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2631 }
bca1c4eb
JG		 2632
2633 return 0;
2634}
2635
05b308e1 2636/**
47c2b677 2637 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 2638 * @host: ATA host to initialize
2639 * @board_idx: controller index
05b308e1
BR		 2640 *
2641 * If possible, do an early global reset of the host. Then do
2642 * our port init and clear/unmask all/relevant host interrupts.
2643 *
2644 * LOCKING:
2645 * Inherited from caller.
2646 */
4447d351 2647static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 2648{
2649 int rc = 0, n_hc, port, hc;
4447d351 2650 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 2651 void __iomem *mmio = hpriv->base;
47c2b677 2652
4447d351 2653 rc = mv_chip_id(host, board_idx);
bca1c4eb 2654 if (rc)
352fab70 2655 goto done;
f351b2d6
SB		 2656
2657 if (HAS_PCI(host)) {
7368f919
ML		 2658 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
2659 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2660 } else {
7368f919
ML		 2661 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
2662 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2663 }
352fab70
ML		 2664
2665 /* global interrupt mask: 0 == mask everything */
7368f919 2666 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 2667
4447d351 2668 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 2669
4447d351 2670 for (port = 0; port < host->n_ports; port++)
47c2b677 2671 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2672
c9d39130 2673 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2674 if (rc)
20f733e7 2675 goto done;
20f733e7 2676
522479fb 2677 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 2678 hpriv->ops->reset_bus(host, mmio);
47c2b677 2679 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 2680
4447d351 2681 for (port = 0; port < host->n_ports; port++) {
cbcdd875 2682 struct ata_port *ap = host->ports[port];
2a47ce06 2683 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 2684
2685 mv_port_init(&ap->ioaddr, port_mmio);
2686
7bb3c529 2687#ifdef CONFIG_PCI
f351b2d6
SB		 2688 if (HAS_PCI(host)) {
2689 unsigned int offset = port_mmio - mmio;
2690 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2691 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2692 }
7bb3c529 2693#endif
20f733e7
BR		 2694 }
2695
2696 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2697 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2698
2699 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2700 "(before clear)=0x%08x\n", hc,
2701 readl(hc_mmio + HC_CFG_OFS),
2702 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2703
2704 /* Clear any currently outstanding hc interrupt conditions */
2705 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2706 }
2707
f351b2d6
SB		 2708 if (HAS_PCI(host)) {
2709 /* Clear any currently outstanding host interrupt conditions */
2710 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 2711
f351b2d6
SB		 2712 /* and unmask interrupt generation for host regs */
2713 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2714 if (IS_GEN_I(hpriv))
2715 writelfl(~HC_MAIN_MASKED_IRQS_5,
7368f919 2716 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2717 else
2718 writelfl(~HC_MAIN_MASKED_IRQS,
7368f919 2719 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2720
2721 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2722 "PCI int cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2723 readl(hpriv->main_irq_cause_addr),
2724 readl(hpriv->main_irq_mask_addr),
f351b2d6
SB		 2725 readl(mmio + hpriv->irq_cause_ofs),
2726 readl(mmio + hpriv->irq_mask_ofs));
2727 } else {
2728 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
7368f919 2729 hpriv->main_irq_mask_addr);
f351b2d6 2730 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2731 readl(hpriv->main_irq_cause_addr),
2732 readl(hpriv->main_irq_mask_addr));
f351b2d6
SB		 2733 }
2734done:
2735 return rc;
2736}
fb621e2f 2737
fbf14e2f
BB		 2738static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2739{
2740 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
2741 MV_CRQB_Q_SZ, 0);
2742 if (!hpriv->crqb_pool)
2743 return -ENOMEM;
2744
2745 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
2746 MV_CRPB_Q_SZ, 0);
2747 if (!hpriv->crpb_pool)
2748 return -ENOMEM;
2749
2750 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
2751 MV_SG_TBL_SZ, 0);
2752 if (!hpriv->sg_tbl_pool)
2753 return -ENOMEM;
2754
2755 return 0;
2756}
2757
15a32632
LB		 2758static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
2759 struct mbus_dram_target_info *dram)
2760{
2761 int i;
2762
2763 for (i = 0; i < 4; i++) {
2764 writel(0, hpriv->base + WINDOW_CTRL(i));
2765 writel(0, hpriv->base + WINDOW_BASE(i));
2766 }
2767
2768 for (i = 0; i < dram->num_cs; i++) {
2769 struct mbus_dram_window *cs = dram->cs + i;
2770
2771 writel(((cs->size - 1) & 0xffff0000) |
2772 (cs->mbus_attr << 8) |
2773 (dram->mbus_dram_target_id << 4) | 1,
2774 hpriv->base + WINDOW_CTRL(i));
2775 writel(cs->base, hpriv->base + WINDOW_BASE(i));
2776 }
2777}
2778
f351b2d6
SB		 2779/**
2780 * mv_platform_probe - handle a positive probe of an soc Marvell
2781 * host
2782 * @pdev: platform device found
2783 *
2784 * LOCKING:
2785 * Inherited from caller.
2786 */
2787static int mv_platform_probe(struct platform_device *pdev)
2788{
2789 static int printed_version;
2790 const struct mv_sata_platform_data *mv_platform_data;
2791 const struct ata_port_info *ppi[] =
2792 { &mv_port_info[chip_soc], NULL };
2793 struct ata_host *host;
2794 struct mv_host_priv *hpriv;
2795 struct resource *res;
2796 int n_ports, rc;
20f733e7 2797
f351b2d6
SB		 2798 if (!printed_version++)
2799 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 2800
f351b2d6
SB		 2801 /*
2802 * Simple resource validation ..
2803 */
2804 if (unlikely(pdev->num_resources != 2)) {
2805 dev_err(&pdev->dev, "invalid number of resources\n");
2806 return -EINVAL;
2807 }
2808
2809 /*
2810 * Get the register base first
2811 */
2812 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2813 if (res == NULL)
2814 return -EINVAL;
2815
2816 /* allocate host */
2817 mv_platform_data = pdev->dev.platform_data;
2818 n_ports = mv_platform_data->n_ports;
2819
2820 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2821 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2822
2823 if (!host || !hpriv)
2824 return -ENOMEM;
2825 host->private_data = hpriv;
2826 hpriv->n_ports = n_ports;
2827
2828 host->iomap = NULL;
f1cb0ea1
SB		 2829 hpriv->base = devm_ioremap(&pdev->dev, res->start,
2830 res->end - res->start + 1);
f351b2d6
SB		 2831 hpriv->base -= MV_SATAHC0_REG_BASE;
2832
15a32632
LB		 2833 /*
2834 * (Re-)program MBUS remapping windows if we are asked to.
2835 */
2836 if (mv_platform_data->dram != NULL)
2837 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
2838
fbf14e2f
BB		 2839 rc = mv_create_dma_pools(hpriv, &pdev->dev);
2840 if (rc)
2841 return rc;
2842
f351b2d6
SB		 2843 /* initialize adapter */
2844 rc = mv_init_host(host, chip_soc);
2845 if (rc)
2846 return rc;
2847
2848 dev_printk(KERN_INFO, &pdev->dev,
2849 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
2850 host->n_ports);
2851
2852 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
2853 IRQF_SHARED, &mv6_sht);
2854}
2855
2856/*
2857 *
2858 * mv_platform_remove - unplug a platform interface
2859 * @pdev: platform device
2860 *
2861 * A platform bus SATA device has been unplugged. Perform the needed
2862 * cleanup. Also called on module unload for any active devices.
2863 */
2864static int __devexit mv_platform_remove(struct platform_device *pdev)
2865{
2866 struct device *dev = &pdev->dev;
2867 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 2868
2869 ata_host_detach(host);
f351b2d6 2870 return 0;
20f733e7
BR		 2871}
2872
f351b2d6
SB		 2873static struct platform_driver mv_platform_driver = {
2874 .probe = mv_platform_probe,
2875 .remove = __devexit_p(mv_platform_remove),
2876 .driver = {
2877 .name = DRV_NAME,
2878 .owner = THIS_MODULE,
2879 },
2880};
2881
2882
7bb3c529 2883#ifdef CONFIG_PCI
f351b2d6
SB		 2884static int mv_pci_init_one(struct pci_dev *pdev,
2885 const struct pci_device_id *ent);
2886
7bb3c529
SB		 2887
2888static struct pci_driver mv_pci_driver = {
2889 .name = DRV_NAME,
2890 .id_table = mv_pci_tbl,
f351b2d6 2891 .probe = mv_pci_init_one,
7bb3c529
SB		 2892 .remove = ata_pci_remove_one,
2893};
2894
2895/*
2896 * module options
2897 */
2898static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
2899
2900
2901/* move to PCI layer or libata core? */
2902static int pci_go_64(struct pci_dev *pdev)
2903{
2904 int rc;
2905
2906 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2907 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2908 if (rc) {
2909 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2910 if (rc) {
2911 dev_printk(KERN_ERR, &pdev->dev,
2912 "64-bit DMA enable failed\n");
2913 return rc;
2914 }
2915 }
2916 } else {
2917 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2918 if (rc) {
2919 dev_printk(KERN_ERR, &pdev->dev,
2920 "32-bit DMA enable failed\n");
2921 return rc;
2922 }
2923 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2924 if (rc) {
2925 dev_printk(KERN_ERR, &pdev->dev,
2926 "32-bit consistent DMA enable failed\n");
2927 return rc;
2928 }
2929 }
2930
2931 return rc;
2932}
2933
05b308e1
BR		 2934/**
2935 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 2936 * @host: ATA host to print info about
05b308e1
BR		 2937 *
2938 * FIXME: complete this.
2939 *
2940 * LOCKING:
2941 * Inherited from caller.
2942 */
4447d351 2943static void mv_print_info(struct ata_host *host)
31961943 2944{
4447d351
TH		 2945 struct pci_dev *pdev = to_pci_dev(host->dev);
2946 struct mv_host_priv *hpriv = host->private_data;
44c10138 2947 u8 scc;
c1e4fe71 2948 const char *scc_s, *gen;
31961943
BR		 2949
2950 /* Use this to determine the HW stepping of the chip so we know
2951 * what errata to workaround
2952 */
31961943
BR		 2953 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2954 if (scc == 0)
2955 scc_s = "SCSI";
2956 else if (scc == 0x01)
2957 scc_s = "RAID";
2958 else
c1e4fe71
JG		 2959 scc_s = "?";
2960
2961 if (IS_GEN_I(hpriv))
2962 gen = "I";
2963 else if (IS_GEN_II(hpriv))
2964 gen = "II";
2965 else if (IS_GEN_IIE(hpriv))
2966 gen = "IIE";
2967 else
2968 gen = "?";
31961943 2969
a9524a76 2970 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 2971 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
2972 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 2973 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2974}
2975
05b308e1 2976/**
f351b2d6 2977 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 2978 * @pdev: PCI device found
2979 * @ent: PCI device ID entry for the matched host
2980 *
2981 * LOCKING:
2982 * Inherited from caller.
2983 */
f351b2d6
SB		 2984static int mv_pci_init_one(struct pci_dev *pdev,
2985 const struct pci_device_id *ent)
20f733e7 2986{
2dcb407e 2987 static int printed_version;
20f733e7 2988 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 2989 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
2990 struct ata_host *host;
2991 struct mv_host_priv *hpriv;
2992 int n_ports, rc;
20f733e7 2993
a9524a76
JG		 2994 if (!printed_version++)
2995 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 2996
4447d351
TH		 2997 /* allocate host */
2998 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
2999
3000 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3001 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3002 if (!host || !hpriv)
3003 return -ENOMEM;
3004 host->private_data = hpriv;
f351b2d6 3005 hpriv->n_ports = n_ports;
4447d351
TH		 3006
3007 /* acquire resources */
24dc5f33
TH		 3008 rc = pcim_enable_device(pdev);
3009 if (rc)
20f733e7 3010 return rc;
20f733e7 3011
0d5ff566
TH		 3012 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3013 if (rc == -EBUSY)
24dc5f33 3014 pcim_pin_device(pdev);
0d5ff566 3015 if (rc)
24dc5f33 3016 return rc;
4447d351 3017 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3018 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3019
d88184fb
JG		 3020 rc = pci_go_64(pdev);
3021 if (rc)
3022 return rc;
3023
da2fa9ba
ML		 3024 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3025 if (rc)
3026 return rc;
3027
20f733e7 3028 /* initialize adapter */
4447d351 3029 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3030 if (rc)
3031 return rc;
20f733e7 3032
31961943 3033 /* Enable interrupts */
6a59dcf8 3034 if (msi && pci_enable_msi(pdev))
31961943 3035 pci_intx(pdev, 1);
20f733e7 3036
31961943 3037 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3038 mv_print_info(host);
20f733e7 3039
4447d351 3040 pci_set_master(pdev);
ea8b4db9 3041 pci_try_set_mwi(pdev);
4447d351 3042 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3043 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3044}
7bb3c529 3045#endif
20f733e7 3046
f351b2d6
SB		 3047static int mv_platform_probe(struct platform_device *pdev);
3048static int __devexit mv_platform_remove(struct platform_device *pdev);
3049
20f733e7
BR		 3050static int __init mv_init(void)
3051{
7bb3c529
SB		 3052 int rc = -ENODEV;
3053#ifdef CONFIG_PCI
3054 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3055 if (rc < 0)
3056 return rc;
3057#endif
3058 rc = platform_driver_register(&mv_platform_driver);
3059
3060#ifdef CONFIG_PCI
3061 if (rc < 0)
3062 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3063#endif
3064 return rc;
20f733e7
BR		 3065}
3066
3067static void __exit mv_exit(void)
3068{
7bb3c529 3069#ifdef CONFIG_PCI
20f733e7 3070 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3071#endif
f351b2d6 3072 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3073}
3074
3075MODULE_AUTHOR("Brett Russ");
3076MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3077MODULE_LICENSE("GPL");
3078MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3079MODULE_VERSION(DRV_VERSION);
17c5aab5 3080MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3081
7bb3c529 3082#ifdef CONFIG_PCI
ddef9bb3
JG		 3083module_param(msi, int, 0444);
3084MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3085#endif
ddef9bb3 3086
20f733e7
BR		 3087module_init(mv_init);
3088module_exit(mv_exit);
Linux kernel - Deliverables
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