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[libata] export sata_print_link_status()
[deliverable/linux.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
8b260248 4 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 5 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
20f733e7 31#include <linux/dma-mapping.h>
a9524a76 32#include <linux/device.h>
20f733e7 33#include <scsi/scsi_host.h>
193515d5 34#include <scsi/scsi_cmnd.h>
20f733e7 35#include <linux/libata.h>
20f733e7
BR		 36
37#define DRV_NAME "sata_mv"
cb48cab7 38#define DRV_VERSION "0.8"
20f733e7
BR		 39
40enum {
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
45
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
48
49 MV_PCI_REG_BASE = 0,
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 51 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
52 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
53 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
54 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
55 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
56
20f733e7 57 MV_SATAHC0_REG_BASE = 0x20000,
522479fb 58 MV_FLASH_CTL = 0x1046c,
bca1c4eb
JG		 59 MV_GPIO_PORT_CTL = 0x104f0,
60 MV_RESET_CFG = 0x180d8,
20f733e7
BR		 61
62 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
63 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
65 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
66
31961943 67 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
20f733e7 68
31961943
BR		 69 MV_MAX_Q_DEPTH = 32,
70 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
71
72 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
73 * CRPB needs alignment on a 256B boundary. Size == 256B
74 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
75 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
76 */
77 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
78 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
79 MV_MAX_SG_CT = 176,
80 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
81 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
82
20f733e7
BR		 83 MV_PORTS_PER_HC = 4,
84 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
85 MV_PORT_HC_SHIFT = 2,
31961943 86 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
20f733e7
BR		 87 MV_PORT_MASK = 3,
88
89 /* Host Flags */
90 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
91 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
31961943 92 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
50630195 93 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
1f3461a7 94 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
47c2b677 95 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 96
31961943
BR		 97 CRQB_FLAG_READ = (1 << 0),
98 CRQB_TAG_SHIFT = 1,
99 CRQB_CMD_ADDR_SHIFT = 8,
100 CRQB_CMD_CS = (0x2 << 11),
101 CRQB_CMD_LAST = (1 << 15),
102
103 CRPB_FLAG_STATUS_SHIFT = 8,
104
105 EPRD_FLAG_END_OF_TBL = (1 << 31),
106
20f733e7
BR		 107 /* PCI interface registers */
108
31961943
BR		 109 PCI_COMMAND_OFS = 0xc00,
110
20f733e7
BR		 111 PCI_MAIN_CMD_STS_OFS = 0xd30,
112 STOP_PCI_MASTER = (1 << 2),
113 PCI_MASTER_EMPTY = (1 << 3),
114 GLOB_SFT_RST = (1 << 4),
115
522479fb
JG		 116 MV_PCI_MODE = 0xd00,
117 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
118 MV_PCI_DISC_TIMER = 0xd04,
119 MV_PCI_MSI_TRIGGER = 0xc38,
120 MV_PCI_SERR_MASK = 0xc28,
121 MV_PCI_XBAR_TMOUT = 0x1d04,
122 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
123 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
124 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
125 MV_PCI_ERR_COMMAND = 0x1d50,
126
127 PCI_IRQ_CAUSE_OFS = 0x1d58,
128 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 129 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
130
131 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
132 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
133 PORT0_ERR = (1 << 0), /* shift by port # */
134 PORT0_DONE = (1 << 1), /* shift by port # */
135 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
136 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
137 PCI_ERR = (1 << 18),
138 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
139 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 140 PORTS_0_3_COAL_DONE = (1 << 8),
141 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 147 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
8b260248 148 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
20f733e7
BR		 149 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
150 HC_MAIN_RSVD),
fb621e2f
JG		 151 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
152 HC_MAIN_RSVD_5),
20f733e7
BR		 153
154 /* SATAHC registers */
155 HC_CFG_OFS = 0,
156
157 HC_IRQ_CAUSE_OFS = 0x14,
31961943 158 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
20f733e7
BR		 159 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
160 DEV_IRQ = (1 << 8), /* shift by port # */
161
162 /* Shadow block registers */
31961943
BR		 163 SHD_BLK_OFS = 0x100,
164 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 165
166 /* SATA registers */
167 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
168 SATA_ACTIVE_OFS = 0x350,
47c2b677 169 PHY_MODE3 = 0x310,
bca1c4eb
JG		 170 PHY_MODE4 = 0x314,
171 PHY_MODE2 = 0x330,
c9d39130
JG		 172 MV5_PHY_MODE = 0x74,
173 MV5_LT_MODE = 0x30,
174 MV5_PHY_CTL = 0x0C,
bca1c4eb
JG		 175 SATA_INTERFACE_CTL = 0x050,
176
177 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 178
179 /* Port registers */
180 EDMA_CFG_OFS = 0,
31961943
BR		 181 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
182 EDMA_CFG_NCQ = (1 << 5),
183 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
184 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
185 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
20f733e7
BR		 186
187 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
188 EDMA_ERR_IRQ_MASK_OFS = 0xc,
189 EDMA_ERR_D_PAR = (1 << 0),
190 EDMA_ERR_PRD_PAR = (1 << 1),
191 EDMA_ERR_DEV = (1 << 2),
192 EDMA_ERR_DEV_DCON = (1 << 3),
193 EDMA_ERR_DEV_CON = (1 << 4),
194 EDMA_ERR_SERR = (1 << 5),
195 EDMA_ERR_SELF_DIS = (1 << 7),
196 EDMA_ERR_BIST_ASYNC = (1 << 8),
197 EDMA_ERR_CRBQ_PAR = (1 << 9),
198 EDMA_ERR_CRPB_PAR = (1 << 10),
199 EDMA_ERR_INTRL_PAR = (1 << 11),
200 EDMA_ERR_IORDY = (1 << 12),
201 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
202 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
203 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
204 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
205 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
206 EDMA_ERR_TRANS_PROTO = (1 << 31),
8b260248 207 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
20f733e7
BR		 208 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
209 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
8b260248 210 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
20f733e7 211 EDMA_ERR_LNK_DATA_RX |
8b260248 212 EDMA_ERR_LNK_DATA_TX |
20f733e7
BR		 213 EDMA_ERR_TRANS_PROTO),
214
31961943
BR		 215 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
216 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 217
218 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
219 EDMA_REQ_Q_PTR_SHIFT = 5,
220
221 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
222 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
223 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 224 EDMA_RSP_Q_PTR_SHIFT = 3,
225
20f733e7
BR		 226 EDMA_CMD_OFS = 0x28,
227 EDMA_EN = (1 << 0),
228 EDMA_DS = (1 << 1),
229 ATA_RST = (1 << 2),
230
c9d39130 231 EDMA_IORDY_TMOUT = 0x34,
bca1c4eb 232 EDMA_ARB_CFG = 0x38,
bca1c4eb 233
31961943
BR		 234 /* Host private flags (hp_flags) */
235 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 236 MV_HP_ERRATA_50XXB0 = (1 << 1),
237 MV_HP_ERRATA_50XXB2 = (1 << 2),
238 MV_HP_ERRATA_60X1B2 = (1 << 3),
239 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892
JG		 240 MV_HP_ERRATA_XX42A0 = (1 << 5),
241 MV_HP_50XX = (1 << 6),
242 MV_HP_GEN_IIE = (1 << 7),
20f733e7 243
31961943
BR		 244 /* Port private flags (pp_flags) */
245 MV_PP_FLAG_EDMA_EN = (1 << 0),
246 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
20f733e7
BR		 247};
248
c9d39130 249#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
bca1c4eb 250#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
e4e7b892
JG		 251#define IS_GEN_I(hpriv) IS_50XX(hpriv)
252#define IS_GEN_II(hpriv) IS_60XX(hpriv)
253#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
bca1c4eb 254
095fec88
JG		 255enum {
256 /* Our DMA boundary is determined by an ePRD being unable to handle
257 * anything larger than 64KB
258 */
259 MV_DMA_BOUNDARY = 0xffffU,
260
261 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
262
263 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
264};
265
522479fb
JG		 266enum chip_type {
267 chip_504x,
268 chip_508x,
269 chip_5080,
270 chip_604x,
271 chip_608x,
e4e7b892
JG		 272 chip_6042,
273 chip_7042,
522479fb
JG		 274};
275
31961943
BR		 276/* Command ReQuest Block: 32B */
277struct mv_crqb {
e1469874
ML		 278 __le32 sg_addr;
279 __le32 sg_addr_hi;
280 __le16 ctrl_flags;
281 __le16 ata_cmd[11];
31961943 282};
20f733e7 283
e4e7b892 284struct mv_crqb_iie {
e1469874
ML		 285 __le32 addr;
286 __le32 addr_hi;
287 __le32 flags;
288 __le32 len;
289 __le32 ata_cmd[4];
e4e7b892
JG		 290};
291
31961943
BR		 292/* Command ResPonse Block: 8B */
293struct mv_crpb {
e1469874
ML		 294 __le16 id;
295 __le16 flags;
296 __le32 tmstmp;
20f733e7
BR		 297};
298
31961943
BR		 299/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
300struct mv_sg {
e1469874
ML		 301 __le32 addr;
302 __le32 flags_size;
303 __le32 addr_hi;
304 __le32 reserved;
31961943 305};
20f733e7 306
31961943
BR		 307struct mv_port_priv {
308 struct mv_crqb *crqb;
309 dma_addr_t crqb_dma;
310 struct mv_crpb *crpb;
311 dma_addr_t crpb_dma;
312 struct mv_sg *sg_tbl;
313 dma_addr_t sg_tbl_dma;
31961943
BR		 314 u32 pp_flags;
315};
316
bca1c4eb
JG		 317struct mv_port_signal {
318 u32 amps;
319 u32 pre;
320};
321
47c2b677
JG		 322struct mv_host_priv;
323struct mv_hw_ops {
2a47ce06
JG		 324 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
325 unsigned int port);
47c2b677
JG		 326 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
327 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
328 void __iomem *mmio);
c9d39130
JG		 329 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
330 unsigned int n_hc);
522479fb
JG		 331 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
332 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
47c2b677
JG		 333};
334
31961943
BR		 335struct mv_host_priv {
336 u32 hp_flags;
bca1c4eb 337 struct mv_port_signal signal[8];
47c2b677 338 const struct mv_hw_ops *ops;
20f733e7
BR		 339};
340
341static void mv_irq_clear(struct ata_port *ap);
342static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
343static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
c9d39130
JG		 344static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
345static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
20f733e7 346static void mv_phy_reset(struct ata_port *ap);
22374677 347static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
31961943
BR		 348static int mv_port_start(struct ata_port *ap);
349static void mv_port_stop(struct ata_port *ap);
350static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 351static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 352static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
7d12e780 353static irqreturn_t mv_interrupt(int irq, void *dev_instance);
31961943 354static void mv_eng_timeout(struct ata_port *ap);
20f733e7
BR		 355static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
356
2a47ce06
JG		 357static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
358 unsigned int port);
47c2b677
JG		 359static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
360static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
361 void __iomem *mmio);
c9d39130
JG		 362static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
363 unsigned int n_hc);
522479fb
JG		 364static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
365static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
47c2b677 366
2a47ce06
JG		 367static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
368 unsigned int port);
47c2b677
JG		 369static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
370static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
371 void __iomem *mmio);
c9d39130
JG		 372static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
373 unsigned int n_hc);
522479fb
JG		 374static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
375static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
c9d39130
JG		 376static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
377 unsigned int port_no);
378static void mv_stop_and_reset(struct ata_port *ap);
47c2b677 379
193515d5 380static struct scsi_host_template mv_sht = {
20f733e7
BR		 381 .module = THIS_MODULE,
382 .name = DRV_NAME,
383 .ioctl = ata_scsi_ioctl,
384 .queuecommand = ata_scsi_queuecmd,
31961943 385 .can_queue = MV_USE_Q_DEPTH,
20f733e7 386 .this_id = ATA_SHT_THIS_ID,
22374677 387 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7
BR		 388 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
389 .emulated = ATA_SHT_EMULATED,
31961943 390 .use_clustering = ATA_SHT_USE_CLUSTERING,
20f733e7
BR		 391 .proc_name = DRV_NAME,
392 .dma_boundary = MV_DMA_BOUNDARY,
393 .slave_configure = ata_scsi_slave_config,
ccf68c34 394 .slave_destroy = ata_scsi_slave_destroy,
20f733e7 395 .bios_param = ata_std_bios_param,
20f733e7
BR		 396};
397
c9d39130
JG		 398static const struct ata_port_operations mv5_ops = {
399 .port_disable = ata_port_disable,
400
401 .tf_load = ata_tf_load,
402 .tf_read = ata_tf_read,
403 .check_status = ata_check_status,
404 .exec_command = ata_exec_command,
405 .dev_select = ata_std_dev_select,
406
407 .phy_reset = mv_phy_reset,
408
409 .qc_prep = mv_qc_prep,
410 .qc_issue = mv_qc_issue,
0d5ff566 411 .data_xfer = ata_data_xfer,
c9d39130
JG		 412
413 .eng_timeout = mv_eng_timeout,
414
415 .irq_handler = mv_interrupt,
416 .irq_clear = mv_irq_clear,
246ce3b6
AI		 417 .irq_on = ata_irq_on,
418 .irq_ack = ata_irq_ack,
c9d39130
JG		 419
420 .scr_read = mv5_scr_read,
421 .scr_write = mv5_scr_write,
422
423 .port_start = mv_port_start,
424 .port_stop = mv_port_stop,
c9d39130
JG		 425};
426
427static const struct ata_port_operations mv6_ops = {
20f733e7
BR		 428 .port_disable = ata_port_disable,
429
430 .tf_load = ata_tf_load,
431 .tf_read = ata_tf_read,
432 .check_status = ata_check_status,
433 .exec_command = ata_exec_command,
434 .dev_select = ata_std_dev_select,
435
436 .phy_reset = mv_phy_reset,
437
31961943
BR		 438 .qc_prep = mv_qc_prep,
439 .qc_issue = mv_qc_issue,
0d5ff566 440 .data_xfer = ata_data_xfer,
20f733e7 441
31961943 442 .eng_timeout = mv_eng_timeout,
20f733e7
BR		 443
444 .irq_handler = mv_interrupt,
445 .irq_clear = mv_irq_clear,
246ce3b6
AI		 446 .irq_on = ata_irq_on,
447 .irq_ack = ata_irq_ack,
20f733e7
BR		 448
449 .scr_read = mv_scr_read,
450 .scr_write = mv_scr_write,
451
31961943
BR		 452 .port_start = mv_port_start,
453 .port_stop = mv_port_stop,
20f733e7
BR		 454};
455
e4e7b892
JG		 456static const struct ata_port_operations mv_iie_ops = {
457 .port_disable = ata_port_disable,
458
459 .tf_load = ata_tf_load,
460 .tf_read = ata_tf_read,
461 .check_status = ata_check_status,
462 .exec_command = ata_exec_command,
463 .dev_select = ata_std_dev_select,
464
465 .phy_reset = mv_phy_reset,
466
467 .qc_prep = mv_qc_prep_iie,
468 .qc_issue = mv_qc_issue,
0d5ff566 469 .data_xfer = ata_data_xfer,
e4e7b892
JG		 470
471 .eng_timeout = mv_eng_timeout,
472
473 .irq_handler = mv_interrupt,
474 .irq_clear = mv_irq_clear,
246ce3b6
AI		 475 .irq_on = ata_irq_on,
476 .irq_ack = ata_irq_ack,
e4e7b892
JG		 477
478 .scr_read = mv_scr_read,
479 .scr_write = mv_scr_write,
480
481 .port_start = mv_port_start,
482 .port_stop = mv_port_stop,
e4e7b892
JG		 483};
484
98ac62de 485static const struct ata_port_info mv_port_info[] = {
20f733e7
BR		 486 { /* chip_504x */
487 .sht = &mv_sht,
cca3974e 488 .flags = MV_COMMON_FLAGS,
31961943 489 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 490 .udma_mask = 0x7f, /* udma0-6 */
491 .port_ops = &mv5_ops,
20f733e7
BR		 492 },
493 { /* chip_508x */
494 .sht = &mv_sht,
cca3974e 495 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
31961943 496 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 497 .udma_mask = 0x7f, /* udma0-6 */
498 .port_ops = &mv5_ops,
20f733e7 499 },
47c2b677
JG		 500 { /* chip_5080 */
501 .sht = &mv_sht,
cca3974e 502 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
47c2b677 503 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 504 .udma_mask = 0x7f, /* udma0-6 */
505 .port_ops = &mv5_ops,
47c2b677 506 },
20f733e7
BR		 507 { /* chip_604x */
508 .sht = &mv_sht,
cca3974e 509 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
31961943
BR		 510 .pio_mask = 0x1f, /* pio0-4 */
511 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 512 .port_ops = &mv6_ops,
20f733e7
BR		 513 },
514 { /* chip_608x */
515 .sht = &mv_sht,
cca3974e 516 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
31961943
BR		 517 MV_FLAG_DUAL_HC),
518 .pio_mask = 0x1f, /* pio0-4 */
519 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 520 .port_ops = &mv6_ops,
20f733e7 521 },
e4e7b892
JG		 522 { /* chip_6042 */
523 .sht = &mv_sht,
cca3974e 524 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
e4e7b892
JG		 525 .pio_mask = 0x1f, /* pio0-4 */
526 .udma_mask = 0x7f, /* udma0-6 */
527 .port_ops = &mv_iie_ops,
528 },
529 { /* chip_7042 */
530 .sht = &mv_sht,
e93f09dc 531 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
e4e7b892
JG		 532 .pio_mask = 0x1f, /* pio0-4 */
533 .udma_mask = 0x7f, /* udma0-6 */
534 .port_ops = &mv_iie_ops,
535 },
20f733e7
BR		 536};
537
3b7d697d 538static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 539 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
540 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
541 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
542 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
543
544 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
545 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
546 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
547 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
548 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
549
550 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
551
e93f09dc
OJ		 552 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
553
2d2744fc 554 { } /* terminate list */
20f733e7
BR		 555};
556
557static struct pci_driver mv_pci_driver = {
558 .name = DRV_NAME,
559 .id_table = mv_pci_tbl,
560 .probe = mv_init_one,
561 .remove = ata_pci_remove_one,
562};
563
47c2b677
JG		 564static const struct mv_hw_ops mv5xxx_ops = {
565 .phy_errata = mv5_phy_errata,
566 .enable_leds = mv5_enable_leds,
567 .read_preamp = mv5_read_preamp,
568 .reset_hc = mv5_reset_hc,
522479fb
JG		 569 .reset_flash = mv5_reset_flash,
570 .reset_bus = mv5_reset_bus,
47c2b677
JG		 571};
572
573static const struct mv_hw_ops mv6xxx_ops = {
574 .phy_errata = mv6_phy_errata,
575 .enable_leds = mv6_enable_leds,
576 .read_preamp = mv6_read_preamp,
577 .reset_hc = mv6_reset_hc,
522479fb
JG		 578 .reset_flash = mv6_reset_flash,
579 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 580};
581
ddef9bb3
JG		 582/*
583 * module options
584 */
585static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
586
587
20f733e7
BR		 588/*
589 * Functions
590 */
591
592static inline void writelfl(unsigned long data, void __iomem *addr)
593{
594 writel(data, addr);
595 (void) readl(addr); /* flush to avoid PCI posted write */
596}
597
20f733e7
BR		 598static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
599{
600 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
601}
602
c9d39130
JG		 603static inline unsigned int mv_hc_from_port(unsigned int port)
604{
605 return port >> MV_PORT_HC_SHIFT;
606}
607
608static inline unsigned int mv_hardport_from_port(unsigned int port)
609{
610 return port & MV_PORT_MASK;
611}
612
613static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
614 unsigned int port)
615{
616 return mv_hc_base(base, mv_hc_from_port(port));
617}
618
20f733e7
BR		 619static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
620{
c9d39130 621 return mv_hc_base_from_port(base, port) +
8b260248 622 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 623 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 624}
625
626static inline void __iomem *mv_ap_base(struct ata_port *ap)
627{
0d5ff566 628 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
20f733e7
BR		 629}
630
cca3974e 631static inline int mv_get_hc_count(unsigned long port_flags)
31961943 632{
cca3974e 633 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 634}
635
636static void mv_irq_clear(struct ata_port *ap)
20f733e7 637{
20f733e7
BR		 638}
639
05b308e1
BR		 640/**
641 * mv_start_dma - Enable eDMA engine
642 * @base: port base address
643 * @pp: port private data
644 *
beec7dbc
TH		 645 * Verify the local cache of the eDMA state is accurate with a
646 * WARN_ON.
05b308e1
BR		 647 *
648 * LOCKING:
649 * Inherited from caller.
650 */
afb0edd9 651static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
20f733e7 652{
afb0edd9
BR		 653 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
654 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
655 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
656 }
beec7dbc 657 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
20f733e7
BR		 658}
659
05b308e1
BR		 660/**
661 * mv_stop_dma - Disable eDMA engine
662 * @ap: ATA channel to manipulate
663 *
beec7dbc
TH		 664 * Verify the local cache of the eDMA state is accurate with a
665 * WARN_ON.
05b308e1
BR		 666 *
667 * LOCKING:
668 * Inherited from caller.
669 */
31961943 670static void mv_stop_dma(struct ata_port *ap)
20f733e7 671{
31961943
BR		 672 void __iomem *port_mmio = mv_ap_base(ap);
673 struct mv_port_priv *pp = ap->private_data;
31961943
BR		 674 u32 reg;
675 int i;
676
afb0edd9
BR		 677 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
678 /* Disable EDMA if active. The disable bit auto clears.
31961943 679 */
31961943
BR		 680 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
681 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
afb0edd9 682 } else {
beec7dbc 683 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
afb0edd9 684 }
8b260248 685
31961943
BR		 686 /* now properly wait for the eDMA to stop */
687 for (i = 1000; i > 0; i--) {
688 reg = readl(port_mmio + EDMA_CMD_OFS);
689 if (!(EDMA_EN & reg)) {
690 break;
691 }
692 udelay(100);
693 }
694
31961943 695 if (EDMA_EN & reg) {
f15a1daf 696 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
afb0edd9 697 /* FIXME: Consider doing a reset here to recover */
31961943 698 }
20f733e7
BR		 699}
700
8a70f8dc 701#ifdef ATA_DEBUG
31961943 702static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 703{
31961943
BR		 704 int b, w;
705 for (b = 0; b < bytes; ) {
706 DPRINTK("%p: ", start + b);
707 for (w = 0; b < bytes && w < 4; w++) {
708 printk("%08x ",readl(start + b));
709 b += sizeof(u32);
710 }
711 printk("\n");
712 }
31961943 713}
8a70f8dc
JG		 714#endif
715
31961943
BR		 716static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
717{
718#ifdef ATA_DEBUG
719 int b, w;
720 u32 dw;
721 for (b = 0; b < bytes; ) {
722 DPRINTK("%02x: ", b);
723 for (w = 0; b < bytes && w < 4; w++) {
724 (void) pci_read_config_dword(pdev,b,&dw);
725 printk("%08x ",dw);
726 b += sizeof(u32);
727 }
728 printk("\n");
729 }
730#endif
731}
732static void mv_dump_all_regs(void __iomem *mmio_base, int port,
733 struct pci_dev *pdev)
734{
735#ifdef ATA_DEBUG
8b260248 736 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 737 port >> MV_PORT_HC_SHIFT);
738 void __iomem *port_base;
739 int start_port, num_ports, p, start_hc, num_hcs, hc;
740
741 if (0 > port) {
742 start_hc = start_port = 0;
743 num_ports = 8; /* shld be benign for 4 port devs */
744 num_hcs = 2;
745 } else {
746 start_hc = port >> MV_PORT_HC_SHIFT;
747 start_port = port;
748 num_ports = num_hcs = 1;
749 }
8b260248 750 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 751 num_ports > 1 ? num_ports - 1 : start_port);
752
753 if (NULL != pdev) {
754 DPRINTK("PCI config space regs:\n");
755 mv_dump_pci_cfg(pdev, 0x68);
756 }
757 DPRINTK("PCI regs:\n");
758 mv_dump_mem(mmio_base+0xc00, 0x3c);
759 mv_dump_mem(mmio_base+0xd00, 0x34);
760 mv_dump_mem(mmio_base+0xf00, 0x4);
761 mv_dump_mem(mmio_base+0x1d00, 0x6c);
762 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 763 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 764 DPRINTK("HC regs (HC %i):\n", hc);
765 mv_dump_mem(hc_base, 0x1c);
766 }
767 for (p = start_port; p < start_port + num_ports; p++) {
768 port_base = mv_port_base(mmio_base, p);
769 DPRINTK("EDMA regs (port %i):\n",p);
770 mv_dump_mem(port_base, 0x54);
771 DPRINTK("SATA regs (port %i):\n",p);
772 mv_dump_mem(port_base+0x300, 0x60);
773 }
774#endif
20f733e7
BR		 775}
776
777static unsigned int mv_scr_offset(unsigned int sc_reg_in)
778{
779 unsigned int ofs;
780
781 switch (sc_reg_in) {
782 case SCR_STATUS:
783 case SCR_CONTROL:
784 case SCR_ERROR:
785 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
786 break;
787 case SCR_ACTIVE:
788 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
789 break;
790 default:
791 ofs = 0xffffffffU;
792 break;
793 }
794 return ofs;
795}
796
797static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
798{
799 unsigned int ofs = mv_scr_offset(sc_reg_in);
800
35177265 801 if (0xffffffffU != ofs)
20f733e7 802 return readl(mv_ap_base(ap) + ofs);
35177265 803 else
20f733e7 804 return (u32) ofs;
20f733e7
BR		 805}
806
807static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
808{
809 unsigned int ofs = mv_scr_offset(sc_reg_in);
810
35177265 811 if (0xffffffffU != ofs)
20f733e7 812 writelfl(val, mv_ap_base(ap) + ofs);
20f733e7
BR		 813}
814
e4e7b892
JG		 815static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
816{
817 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
818
819 /* set up non-NCQ EDMA configuration */
e4e7b892
JG		 820 cfg &= ~(1 << 9); /* disable equeue */
821
e728eabe
JG		 822 if (IS_GEN_I(hpriv)) {
823 cfg &= ~0x1f; /* clear queue depth */
e4e7b892 824 cfg |= (1 << 8); /* enab config burst size mask */
e728eabe 825 }
e4e7b892 826
e728eabe
JG		 827 else if (IS_GEN_II(hpriv)) {
828 cfg &= ~0x1f; /* clear queue depth */
e4e7b892 829 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
e728eabe
JG		 830 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
831 }
e4e7b892
JG		 832
833 else if (IS_GEN_IIE(hpriv)) {
e728eabe
JG		 834 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
835 cfg |= (1 << 22); /* enab 4-entry host queue cache */
e4e7b892
JG		 836 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
837 cfg |= (1 << 18); /* enab early completion */
e728eabe
JG		 838 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
839 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
840 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
e4e7b892
JG		 841 }
842
843 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
844}
845
05b308e1
BR		 846/**
847 * mv_port_start - Port specific init/start routine.
848 * @ap: ATA channel to manipulate
849 *
850 * Allocate and point to DMA memory, init port private memory,
851 * zero indices.
852 *
853 * LOCKING:
854 * Inherited from caller.
855 */
31961943
BR		 856static int mv_port_start(struct ata_port *ap)
857{
cca3974e
JG		 858 struct device *dev = ap->host->dev;
859 struct mv_host_priv *hpriv = ap->host->private_data;
31961943
BR		 860 struct mv_port_priv *pp;
861 void __iomem *port_mmio = mv_ap_base(ap);
862 void *mem;
863 dma_addr_t mem_dma;
24dc5f33 864 int rc;
31961943 865
24dc5f33 866 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 867 if (!pp)
24dc5f33 868 return -ENOMEM;
31961943 869
24dc5f33
TH		 870 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
871 GFP_KERNEL);
6037d6bb 872 if (!mem)
24dc5f33 873 return -ENOMEM;
31961943
BR		 874 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
875
6037d6bb
JG		 876 rc = ata_pad_alloc(ap, dev);
877 if (rc)
24dc5f33 878 return rc;
6037d6bb 879
8b260248 880 /* First item in chunk of DMA memory:
31961943
BR		 881 * 32-slot command request table (CRQB), 32 bytes each in size
882 */
883 pp->crqb = mem;
884 pp->crqb_dma = mem_dma;
885 mem += MV_CRQB_Q_SZ;
886 mem_dma += MV_CRQB_Q_SZ;
887
8b260248 888 /* Second item:
31961943
BR		 889 * 32-slot command response table (CRPB), 8 bytes each in size
890 */
891 pp->crpb = mem;
892 pp->crpb_dma = mem_dma;
893 mem += MV_CRPB_Q_SZ;
894 mem_dma += MV_CRPB_Q_SZ;
895
896 /* Third item:
897 * Table of scatter-gather descriptors (ePRD), 16 bytes each
898 */
899 pp->sg_tbl = mem;
900 pp->sg_tbl_dma = mem_dma;
901
e4e7b892 902 mv_edma_cfg(hpriv, port_mmio);
31961943
BR		 903
904 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
8b260248 905 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
31961943
BR		 906 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
907
e4e7b892
JG		 908 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
909 writelfl(pp->crqb_dma & 0xffffffff,
910 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
911 else
912 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
31961943
BR		 913
914 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
e4e7b892
JG		 915
916 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
917 writelfl(pp->crpb_dma & 0xffffffff,
918 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
919 else
920 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
921
8b260248 922 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
31961943
BR		 923 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
924
31961943
BR		 925 /* Don't turn on EDMA here...do it before DMA commands only. Else
926 * we'll be unable to send non-data, PIO, etc due to restricted access
927 * to shadow regs.
928 */
929 ap->private_data = pp;
930 return 0;
931}
932
05b308e1
BR		 933/**
934 * mv_port_stop - Port specific cleanup/stop routine.
935 * @ap: ATA channel to manipulate
936 *
937 * Stop DMA, cleanup port memory.
938 *
939 * LOCKING:
cca3974e 940 * This routine uses the host lock to protect the DMA stop.
05b308e1 941 */
31961943
BR		 942static void mv_port_stop(struct ata_port *ap)
943{
afb0edd9 944 unsigned long flags;
31961943 945
cca3974e 946 spin_lock_irqsave(&ap->host->lock, flags);
31961943 947 mv_stop_dma(ap);
cca3974e 948 spin_unlock_irqrestore(&ap->host->lock, flags);
31961943
BR		 949}
950
05b308e1
BR		 951/**
952 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
953 * @qc: queued command whose SG list to source from
954 *
955 * Populate the SG list and mark the last entry.
956 *
957 * LOCKING:
958 * Inherited from caller.
959 */
31961943
BR		 960static void mv_fill_sg(struct ata_queued_cmd *qc)
961{
962 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd
JG		 963 unsigned int i = 0;
964 struct scatterlist *sg;
31961943 965
972c26bd 966 ata_for_each_sg(sg, qc) {
31961943 967 dma_addr_t addr;
22374677 968 u32 sg_len, len, offset;
31961943 969
972c26bd
JG		 970 addr = sg_dma_address(sg);
971 sg_len = sg_dma_len(sg);
31961943 972
22374677
JG		 973 while (sg_len) {
974 offset = addr & MV_DMA_BOUNDARY;
975 len = sg_len;
976 if ((offset + sg_len) > 0x10000)
977 len = 0x10000 - offset;
972c26bd 978
22374677
JG		 979 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
980 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
63af2a5c 981 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
22374677
JG		 982
983 sg_len -= len;
984 addr += len;
985
986 if (!sg_len && ata_sg_is_last(sg, qc))
987 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
988
989 i++;
990 }
31961943
BR		 991 }
992}
993
a6432436 994static inline unsigned mv_inc_q_index(unsigned index)
31961943 995{
a6432436 996 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
31961943
BR		 997}
998
e1469874 999static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1000{
559eedad 1001 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1002 (last ? CRQB_CMD_LAST : 0);
559eedad 1003 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1004}
1005
05b308e1
BR		 1006/**
1007 * mv_qc_prep - Host specific command preparation.
1008 * @qc: queued command to prepare
1009 *
1010 * This routine simply redirects to the general purpose routine
1011 * if command is not DMA. Else, it handles prep of the CRQB
1012 * (command request block), does some sanity checking, and calls
1013 * the SG load routine.
1014 *
1015 * LOCKING:
1016 * Inherited from caller.
1017 */
31961943
BR		 1018static void mv_qc_prep(struct ata_queued_cmd *qc)
1019{
1020 struct ata_port *ap = qc->ap;
1021 struct mv_port_priv *pp = ap->private_data;
e1469874 1022 __le16 *cw;
31961943
BR		 1023 struct ata_taskfile *tf;
1024 u16 flags = 0;
a6432436 1025 unsigned in_index;
31961943 1026
e4e7b892 1027 if (ATA_PROT_DMA != qc->tf.protocol)
31961943 1028 return;
20f733e7 1029
31961943
BR		 1030 /* Fill in command request block
1031 */
e4e7b892 1032 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1033 flags |= CRQB_FLAG_READ;
beec7dbc 1034 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943
BR		 1035 flags |= qc->tag << CRQB_TAG_SHIFT;
1036
a6432436
ML		 1037 /* get current queue index from hardware */
1038 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1039 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1040
1041 pp->crqb[in_index].sg_addr =
31961943 1042 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
a6432436 1043 pp->crqb[in_index].sg_addr_hi =
31961943 1044 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
a6432436 1045 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1046
a6432436 1047 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1048 tf = &qc->tf;
1049
1050 /* Sadly, the CRQB cannot accomodate all registers--there are
1051 * only 11 bytes...so we must pick and choose required
1052 * registers based on the command. So, we drop feature and
1053 * hob_feature for [RW] DMA commands, but they are needed for
1054 * NCQ. NCQ will drop hob_nsect.
20f733e7 1055 */
31961943
BR		 1056 switch (tf->command) {
1057 case ATA_CMD_READ:
1058 case ATA_CMD_READ_EXT:
1059 case ATA_CMD_WRITE:
1060 case ATA_CMD_WRITE_EXT:
c15d85c8 1061 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1062 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1063 break;
1064#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1065 case ATA_CMD_FPDMA_READ:
1066 case ATA_CMD_FPDMA_WRITE:
8b260248 1067 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1068 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1069 break;
1070#endif /* FIXME: remove this line when NCQ added */
1071 default:
1072 /* The only other commands EDMA supports in non-queued and
1073 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1074 * of which are defined/used by Linux. If we get here, this
1075 * driver needs work.
1076 *
1077 * FIXME: modify libata to give qc_prep a return value and
1078 * return error here.
1079 */
1080 BUG_ON(tf->command);
1081 break;
1082 }
1083 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1084 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1085 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1086 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1087 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1088 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1089 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1090 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1091 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1092
e4e7b892
JG		 1093 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1094 return;
1095 mv_fill_sg(qc);
1096}
1097
1098/**
1099 * mv_qc_prep_iie - Host specific command preparation.
1100 * @qc: queued command to prepare
1101 *
1102 * This routine simply redirects to the general purpose routine
1103 * if command is not DMA. Else, it handles prep of the CRQB
1104 * (command request block), does some sanity checking, and calls
1105 * the SG load routine.
1106 *
1107 * LOCKING:
1108 * Inherited from caller.
1109 */
1110static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1111{
1112 struct ata_port *ap = qc->ap;
1113 struct mv_port_priv *pp = ap->private_data;
1114 struct mv_crqb_iie *crqb;
1115 struct ata_taskfile *tf;
a6432436 1116 unsigned in_index;
e4e7b892
JG		 1117 u32 flags = 0;
1118
1119 if (ATA_PROT_DMA != qc->tf.protocol)
1120 return;
1121
e4e7b892
JG		 1122 /* Fill in Gen IIE command request block
1123 */
1124 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1125 flags |= CRQB_FLAG_READ;
1126
beec7dbc 1127 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892
JG		 1128 flags |= qc->tag << CRQB_TAG_SHIFT;
1129
a6432436
ML		 1130 /* get current queue index from hardware */
1131 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1132 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1133
1134 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
e4e7b892
JG		 1135 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1136 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1137 crqb->flags = cpu_to_le32(flags);
1138
1139 tf = &qc->tf;
1140 crqb->ata_cmd[0] = cpu_to_le32(
1141 (tf->command << 16) |
1142 (tf->feature << 24)
1143 );
1144 crqb->ata_cmd[1] = cpu_to_le32(
1145 (tf->lbal << 0) |
1146 (tf->lbam << 8) |
1147 (tf->lbah << 16) |
1148 (tf->device << 24)
1149 );
1150 crqb->ata_cmd[2] = cpu_to_le32(
1151 (tf->hob_lbal << 0) |
1152 (tf->hob_lbam << 8) |
1153 (tf->hob_lbah << 16) |
1154 (tf->hob_feature << 24)
1155 );
1156 crqb->ata_cmd[3] = cpu_to_le32(
1157 (tf->nsect << 0) |
1158 (tf->hob_nsect << 8)
1159 );
1160
1161 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1162 return;
31961943
BR		 1163 mv_fill_sg(qc);
1164}
1165
05b308e1
BR		 1166/**
1167 * mv_qc_issue - Initiate a command to the host
1168 * @qc: queued command to start
1169 *
1170 * This routine simply redirects to the general purpose routine
1171 * if command is not DMA. Else, it sanity checks our local
1172 * caches of the request producer/consumer indices then enables
1173 * DMA and bumps the request producer index.
1174 *
1175 * LOCKING:
1176 * Inherited from caller.
1177 */
9a3d9eb0 1178static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943
BR		 1179{
1180 void __iomem *port_mmio = mv_ap_base(qc->ap);
1181 struct mv_port_priv *pp = qc->ap->private_data;
a6432436 1182 unsigned in_index;
31961943
BR		 1183 u32 in_ptr;
1184
1185 if (ATA_PROT_DMA != qc->tf.protocol) {
1186 /* We're about to send a non-EDMA capable command to the
1187 * port. Turn off EDMA so there won't be problems accessing
1188 * shadow block, etc registers.
1189 */
1190 mv_stop_dma(qc->ap);
1191 return ata_qc_issue_prot(qc);
1192 }
1193
a6432436
ML		 1194 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1195 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1196
31961943 1197 /* until we do queuing, the queue should be empty at this point */
a6432436
ML		 1198 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1199 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943 1200
a6432436 1201 in_index = mv_inc_q_index(in_index); /* now incr producer index */
31961943 1202
afb0edd9 1203 mv_start_dma(port_mmio, pp);
31961943
BR		 1204
1205 /* and write the request in pointer to kick the EDMA to life */
1206 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
a6432436 1207 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1208 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1209
1210 return 0;
1211}
1212
05b308e1
BR		 1213/**
1214 * mv_get_crpb_status - get status from most recently completed cmd
1215 * @ap: ATA channel to manipulate
1216 *
1217 * This routine is for use when the port is in DMA mode, when it
1218 * will be using the CRPB (command response block) method of
beec7dbc 1219 * returning command completion information. We check indices
05b308e1
BR		 1220 * are good, grab status, and bump the response consumer index to
1221 * prove that we're up to date.
1222 *
1223 * LOCKING:
1224 * Inherited from caller.
1225 */
31961943
BR		 1226static u8 mv_get_crpb_status(struct ata_port *ap)
1227{
1228 void __iomem *port_mmio = mv_ap_base(ap);
1229 struct mv_port_priv *pp = ap->private_data;
a6432436 1230 unsigned out_index;
31961943 1231 u32 out_ptr;
806a6e7a 1232 u8 ata_status;
31961943 1233
a6432436
ML		 1234 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1235 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1236
a6432436
ML		 1237 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1238 >> CRPB_FLAG_STATUS_SHIFT;
806a6e7a 1239
31961943 1240 /* increment our consumer index... */
a6432436 1241 out_index = mv_inc_q_index(out_index);
8b260248 1242
31961943 1243 /* and, until we do NCQ, there should only be 1 CRPB waiting */
a6432436
ML		 1244 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1245 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943
BR		 1246
1247 /* write out our inc'd consumer index so EDMA knows we're caught up */
1248 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
a6432436 1249 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
31961943
BR		 1250 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1251
1252 /* Return ATA status register for completed CRPB */
806a6e7a 1253 return ata_status;
31961943
BR		 1254}
1255
05b308e1
BR		 1256/**
1257 * mv_err_intr - Handle error interrupts on the port
1258 * @ap: ATA channel to manipulate
9b358e30 1259 * @reset_allowed: bool: 0 == don't trigger from reset here
05b308e1
BR		 1260 *
1261 * In most cases, just clear the interrupt and move on. However,
1262 * some cases require an eDMA reset, which is done right before
1263 * the COMRESET in mv_phy_reset(). The SERR case requires a
1264 * clear of pending errors in the SATA SERROR register. Finally,
1265 * if the port disabled DMA, update our cached copy to match.
1266 *
1267 * LOCKING:
1268 * Inherited from caller.
1269 */
9b358e30 1270static void mv_err_intr(struct ata_port *ap, int reset_allowed)
31961943
BR		 1271{
1272 void __iomem *port_mmio = mv_ap_base(ap);
1273 u32 edma_err_cause, serr = 0;
20f733e7
BR		 1274
1275 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1276
1277 if (EDMA_ERR_SERR & edma_err_cause) {
81952c54
TH		 1278 sata_scr_read(ap, SCR_ERROR, &serr);
1279 sata_scr_write_flush(ap, SCR_ERROR, serr);
20f733e7 1280 }
afb0edd9
BR		 1281 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1282 struct mv_port_priv *pp = ap->private_data;
1283 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1284 }
1285 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
44877b4e 1286 "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
20f733e7
BR		 1287
1288 /* Clear EDMA now that SERR cleanup done */
1289 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1290
1291 /* check for fatal here and recover if needed */
9b358e30 1292 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
c9d39130 1293 mv_stop_and_reset(ap);
20f733e7
BR		 1294}
1295
05b308e1
BR		 1296/**
1297 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1298 * @host: host specific structure
05b308e1
BR		 1299 * @relevant: port error bits relevant to this host controller
1300 * @hc: which host controller we're to look at
1301 *
1302 * Read then write clear the HC interrupt status then walk each
1303 * port connected to the HC and see if it needs servicing. Port
1304 * success ints are reported in the HC interrupt status reg, the
1305 * port error ints are reported in the higher level main
1306 * interrupt status register and thus are passed in via the
1307 * 'relevant' argument.
1308 *
1309 * LOCKING:
1310 * Inherited from caller.
1311 */
cca3974e 1312static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
20f733e7 1313{
0d5ff566 1314 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
20f733e7 1315 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
20f733e7
BR		 1316 struct ata_queued_cmd *qc;
1317 u32 hc_irq_cause;
31961943 1318 int shift, port, port0, hard_port, handled;
a7dac447 1319 unsigned int err_mask;
20f733e7 1320
35177265 1321 if (hc == 0)
20f733e7 1322 port0 = 0;
35177265 1323 else
20f733e7 1324 port0 = MV_PORTS_PER_HC;
20f733e7
BR		 1325
1326 /* we'll need the HC success int register in most cases */
1327 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
35177265 1328 if (hc_irq_cause)
31961943 1329 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 1330
1331 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1332 hc,relevant,hc_irq_cause);
1333
1334 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
cd85f6e2 1335 u8 ata_status = 0;
cca3974e 1336 struct ata_port *ap = host->ports[port];
63af2a5c 1337 struct mv_port_priv *pp = ap->private_data;
55d8ca4f 1338
e857f141 1339 hard_port = mv_hardport_from_port(port); /* range 0..3 */
31961943 1340 handled = 0; /* ensure ata_status is set if handled++ */
20f733e7 1341
63af2a5c 1342 /* Note that DEV_IRQ might happen spuriously during EDMA,
e857f141
ML		 1343 * and should be ignored in such cases.
1344 * The cause of this is still under investigation.
8190bdb9 1345 */
63af2a5c
ML		 1346 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1347 /* EDMA: check for response queue interrupt */
1348 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1349 ata_status = mv_get_crpb_status(ap);
1350 handled = 1;
1351 }
1352 } else {
1353 /* PIO: check for device (drive) interrupt */
1354 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
0d5ff566 1355 ata_status = readb(ap->ioaddr.status_addr);
63af2a5c 1356 handled = 1;
e857f141
ML		 1357 /* ignore spurious intr if drive still BUSY */
1358 if (ata_status & ATA_BUSY) {
1359 ata_status = 0;
1360 handled = 0;
1361 }
63af2a5c 1362 }
20f733e7
BR		 1363 }
1364
029f5468 1365 if (ap && (ap->flags & ATA_FLAG_DISABLED))
a2c91a88
JG		 1366 continue;
1367
a7dac447
JG		 1368 err_mask = ac_err_mask(ata_status);
1369
31961943 1370 shift = port << 1; /* (port * 2) */
20f733e7
BR		 1371 if (port >= MV_PORTS_PER_HC) {
1372 shift++; /* skip bit 8 in the HC Main IRQ reg */
1373 }
1374 if ((PORT0_ERR << shift) & relevant) {
9b358e30 1375 mv_err_intr(ap, 1);
a7dac447 1376 err_mask |= AC_ERR_OTHER;
63af2a5c 1377 handled = 1;
20f733e7 1378 }
8b260248 1379
63af2a5c 1380 if (handled) {
20f733e7 1381 qc = ata_qc_from_tag(ap, ap->active_tag);
63af2a5c 1382 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
20f733e7
BR		 1383 VPRINTK("port %u IRQ found for qc, "
1384 "ata_status 0x%x\n", port,ata_status);
20f733e7 1385 /* mark qc status appropriately */
701db69d 1386 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
a22e2eb0
AL		 1387 qc->err_mask |= err_mask;
1388 ata_qc_complete(qc);
1389 }
20f733e7
BR		 1390 }
1391 }
1392 }
1393 VPRINTK("EXIT\n");
1394}
1395
05b308e1 1396/**
8b260248 1397 * mv_interrupt -
05b308e1
BR		 1398 * @irq: unused
1399 * @dev_instance: private data; in this case the host structure
1400 * @regs: unused
1401 *
1402 * Read the read only register to determine if any host
1403 * controllers have pending interrupts. If so, call lower level
1404 * routine to handle. Also check for PCI errors which are only
1405 * reported here.
1406 *
8b260248 1407 * LOCKING:
cca3974e 1408 * This routine holds the host lock while processing pending
05b308e1
BR		 1409 * interrupts.
1410 */
7d12e780 1411static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1412{
cca3974e 1413 struct ata_host *host = dev_instance;
20f733e7 1414 unsigned int hc, handled = 0, n_hcs;
0d5ff566 1415 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
615ab953 1416 struct mv_host_priv *hpriv;
20f733e7
BR		 1417 u32 irq_stat;
1418
20f733e7 1419 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
20f733e7
BR		 1420
1421 /* check the cases where we either have nothing pending or have read
1422 * a bogus register value which can indicate HW removal or PCI fault
1423 */
35177265 1424 if (!irq_stat || (0xffffffffU == irq_stat))
20f733e7 1425 return IRQ_NONE;
20f733e7 1426
cca3974e
JG		 1427 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1428 spin_lock(&host->lock);
20f733e7
BR		 1429
1430 for (hc = 0; hc < n_hcs; hc++) {
1431 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1432 if (relevant) {
cca3974e 1433 mv_host_intr(host, relevant, hc);
31961943 1434 handled++;
20f733e7
BR		 1435 }
1436 }
615ab953 1437
cca3974e 1438 hpriv = host->private_data;
615ab953
ML		 1439 if (IS_60XX(hpriv)) {
1440 /* deal with the interrupt coalescing bits */
1441 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1442 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1443 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1444 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1445 }
1446 }
1447
20f733e7 1448 if (PCI_ERR & irq_stat) {
31961943
BR		 1449 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1450 readl(mmio + PCI_IRQ_CAUSE_OFS));
1451
afb0edd9 1452 DPRINTK("All regs @ PCI error\n");
cca3974e 1453 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
20f733e7 1454
31961943
BR		 1455 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1456 handled++;
1457 }
cca3974e 1458 spin_unlock(&host->lock);
20f733e7
BR		 1459
1460 return IRQ_RETVAL(handled);
1461}
1462
c9d39130
JG		 1463static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1464{
1465 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1466 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1467
1468 return hc_mmio + ofs;
1469}
1470
1471static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1472{
1473 unsigned int ofs;
1474
1475 switch (sc_reg_in) {
1476 case SCR_STATUS:
1477 case SCR_ERROR:
1478 case SCR_CONTROL:
1479 ofs = sc_reg_in * sizeof(u32);
1480 break;
1481 default:
1482 ofs = 0xffffffffU;
1483 break;
1484 }
1485 return ofs;
1486}
1487
1488static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1489{
0d5ff566
TH		 1490 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1491 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1492 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1493
1494 if (ofs != 0xffffffffU)
0d5ff566 1495 return readl(addr + ofs);
c9d39130
JG		 1496 else
1497 return (u32) ofs;
1498}
1499
1500static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1501{
0d5ff566
TH		 1502 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1503 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1504 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1505
1506 if (ofs != 0xffffffffU)
0d5ff566 1507 writelfl(val, addr + ofs);
c9d39130
JG		 1508}
1509
522479fb
JG		 1510static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1511{
1512 u8 rev_id;
1513 int early_5080;
1514
1515 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1516
1517 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1518
1519 if (!early_5080) {
1520 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1521 tmp |= (1 << 0);
1522 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1523 }
1524
1525 mv_reset_pci_bus(pdev, mmio);
1526}
1527
1528static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1529{
1530 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1531}
1532
47c2b677 1533static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1534 void __iomem *mmio)
1535{
c9d39130
JG		 1536 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1537 u32 tmp;
1538
1539 tmp = readl(phy_mmio + MV5_PHY_MODE);
1540
1541 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1542 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1543}
1544
47c2b677 1545static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1546{
522479fb
JG		 1547 u32 tmp;
1548
1549 writel(0, mmio + MV_GPIO_PORT_CTL);
1550
1551 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1552
1553 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1554 tmp |= ~(1 << 0);
1555 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1556}
1557
2a47ce06
JG		 1558static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1559 unsigned int port)
bca1c4eb 1560{
c9d39130
JG		 1561 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1562 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1563 u32 tmp;
1564 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1565
1566 if (fix_apm_sq) {
1567 tmp = readl(phy_mmio + MV5_LT_MODE);
1568 tmp |= (1 << 19);
1569 writel(tmp, phy_mmio + MV5_LT_MODE);
1570
1571 tmp = readl(phy_mmio + MV5_PHY_CTL);
1572 tmp &= ~0x3;
1573 tmp |= 0x1;
1574 writel(tmp, phy_mmio + MV5_PHY_CTL);
1575 }
1576
1577 tmp = readl(phy_mmio + MV5_PHY_MODE);
1578 tmp &= ~mask;
1579 tmp |= hpriv->signal[port].pre;
1580 tmp |= hpriv->signal[port].amps;
1581 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1582}
1583
c9d39130
JG		 1584
1585#undef ZERO
1586#define ZERO(reg) writel(0, port_mmio + (reg))
1587static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1588 unsigned int port)
1589{
1590 void __iomem *port_mmio = mv_port_base(mmio, port);
1591
1592 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1593
1594 mv_channel_reset(hpriv, mmio, port);
1595
1596 ZERO(0x028); /* command */
1597 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1598 ZERO(0x004); /* timer */
1599 ZERO(0x008); /* irq err cause */
1600 ZERO(0x00c); /* irq err mask */
1601 ZERO(0x010); /* rq bah */
1602 ZERO(0x014); /* rq inp */
1603 ZERO(0x018); /* rq outp */
1604 ZERO(0x01c); /* respq bah */
1605 ZERO(0x024); /* respq outp */
1606 ZERO(0x020); /* respq inp */
1607 ZERO(0x02c); /* test control */
1608 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1609}
1610#undef ZERO
1611
1612#define ZERO(reg) writel(0, hc_mmio + (reg))
1613static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1614 unsigned int hc)
47c2b677 1615{
c9d39130
JG		 1616 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1617 u32 tmp;
1618
1619 ZERO(0x00c);
1620 ZERO(0x010);
1621 ZERO(0x014);
1622 ZERO(0x018);
1623
1624 tmp = readl(hc_mmio + 0x20);
1625 tmp &= 0x1c1c1c1c;
1626 tmp |= 0x03030303;
1627 writel(tmp, hc_mmio + 0x20);
1628}
1629#undef ZERO
1630
1631static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1632 unsigned int n_hc)
1633{
1634 unsigned int hc, port;
1635
1636 for (hc = 0; hc < n_hc; hc++) {
1637 for (port = 0; port < MV_PORTS_PER_HC; port++)
1638 mv5_reset_hc_port(hpriv, mmio,
1639 (hc * MV_PORTS_PER_HC) + port);
1640
1641 mv5_reset_one_hc(hpriv, mmio, hc);
1642 }
1643
1644 return 0;
47c2b677
JG		 1645}
1646
101ffae2
JG		 1647#undef ZERO
1648#define ZERO(reg) writel(0, mmio + (reg))
1649static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1650{
1651 u32 tmp;
1652
1653 tmp = readl(mmio + MV_PCI_MODE);
1654 tmp &= 0xff00ffff;
1655 writel(tmp, mmio + MV_PCI_MODE);
1656
1657 ZERO(MV_PCI_DISC_TIMER);
1658 ZERO(MV_PCI_MSI_TRIGGER);
1659 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1660 ZERO(HC_MAIN_IRQ_MASK_OFS);
1661 ZERO(MV_PCI_SERR_MASK);
1662 ZERO(PCI_IRQ_CAUSE_OFS);
1663 ZERO(PCI_IRQ_MASK_OFS);
1664 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1665 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1666 ZERO(MV_PCI_ERR_ATTRIBUTE);
1667 ZERO(MV_PCI_ERR_COMMAND);
1668}
1669#undef ZERO
1670
1671static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1672{
1673 u32 tmp;
1674
1675 mv5_reset_flash(hpriv, mmio);
1676
1677 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1678 tmp &= 0x3;
1679 tmp |= (1 << 5) | (1 << 6);
1680 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1681}
1682
1683/**
1684 * mv6_reset_hc - Perform the 6xxx global soft reset
1685 * @mmio: base address of the HBA
1686 *
1687 * This routine only applies to 6xxx parts.
1688 *
1689 * LOCKING:
1690 * Inherited from caller.
1691 */
c9d39130
JG		 1692static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1693 unsigned int n_hc)
101ffae2
JG		 1694{
1695 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1696 int i, rc = 0;
1697 u32 t;
1698
1699 /* Following procedure defined in PCI "main command and status
1700 * register" table.
1701 */
1702 t = readl(reg);
1703 writel(t | STOP_PCI_MASTER, reg);
1704
1705 for (i = 0; i < 1000; i++) {
1706 udelay(1);
1707 t = readl(reg);
1708 if (PCI_MASTER_EMPTY & t) {
1709 break;
1710 }
1711 }
1712 if (!(PCI_MASTER_EMPTY & t)) {
1713 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1714 rc = 1;
1715 goto done;
1716 }
1717
1718 /* set reset */
1719 i = 5;
1720 do {
1721 writel(t | GLOB_SFT_RST, reg);
1722 t = readl(reg);
1723 udelay(1);
1724 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1725
1726 if (!(GLOB_SFT_RST & t)) {
1727 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1728 rc = 1;
1729 goto done;
1730 }
1731
1732 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1733 i = 5;
1734 do {
1735 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1736 t = readl(reg);
1737 udelay(1);
1738 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1739
1740 if (GLOB_SFT_RST & t) {
1741 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1742 rc = 1;
1743 }
1744done:
1745 return rc;
1746}
1747
47c2b677 1748static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1749 void __iomem *mmio)
1750{
1751 void __iomem *port_mmio;
1752 u32 tmp;
1753
ba3fe8fb
JG		 1754 tmp = readl(mmio + MV_RESET_CFG);
1755 if ((tmp & (1 << 0)) == 0) {
47c2b677 1756 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 1757 hpriv->signal[idx].pre = 0x1 << 5;
1758 return;
1759 }
1760
1761 port_mmio = mv_port_base(mmio, idx);
1762 tmp = readl(port_mmio + PHY_MODE2);
1763
1764 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1765 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1766}
1767
47c2b677 1768static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1769{
47c2b677 1770 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
ba3fe8fb
JG		 1771}
1772
c9d39130 1773static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 1774 unsigned int port)
bca1c4eb 1775{
c9d39130
JG		 1776 void __iomem *port_mmio = mv_port_base(mmio, port);
1777
bca1c4eb 1778 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 1779 int fix_phy_mode2 =
1780 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 1781 int fix_phy_mode4 =
47c2b677
JG		 1782 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1783 u32 m2, tmp;
1784
1785 if (fix_phy_mode2) {
1786 m2 = readl(port_mmio + PHY_MODE2);
1787 m2 &= ~(1 << 16);
1788 m2 |= (1 << 31);
1789 writel(m2, port_mmio + PHY_MODE2);
1790
1791 udelay(200);
1792
1793 m2 = readl(port_mmio + PHY_MODE2);
1794 m2 &= ~((1 << 16) | (1 << 31));
1795 writel(m2, port_mmio + PHY_MODE2);
1796
1797 udelay(200);
1798 }
1799
1800 /* who knows what this magic does */
1801 tmp = readl(port_mmio + PHY_MODE3);
1802 tmp &= ~0x7F800000;
1803 tmp |= 0x2A800000;
1804 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 1805
1806 if (fix_phy_mode4) {
47c2b677 1807 u32 m4;
bca1c4eb
JG		 1808
1809 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 1810
1811 if (hp_flags & MV_HP_ERRATA_60X1B2)
1812 tmp = readl(port_mmio + 0x310);
bca1c4eb
JG		 1813
1814 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1815
1816 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 1817
1818 if (hp_flags & MV_HP_ERRATA_60X1B2)
1819 writel(tmp, port_mmio + 0x310);
bca1c4eb
JG		 1820 }
1821
1822 /* Revert values of pre-emphasis and signal amps to the saved ones */
1823 m2 = readl(port_mmio + PHY_MODE2);
1824
1825 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 1826 m2 |= hpriv->signal[port].amps;
1827 m2 |= hpriv->signal[port].pre;
47c2b677 1828 m2 &= ~(1 << 16);
bca1c4eb 1829
e4e7b892
JG		 1830 /* according to mvSata 3.6.1, some IIE values are fixed */
1831 if (IS_GEN_IIE(hpriv)) {
1832 m2 &= ~0xC30FF01F;
1833 m2 |= 0x0000900F;
1834 }
1835
bca1c4eb
JG		 1836 writel(m2, port_mmio + PHY_MODE2);
1837}
1838
c9d39130
JG		 1839static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1840 unsigned int port_no)
1841{
1842 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1843
1844 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1845
1846 if (IS_60XX(hpriv)) {
1847 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 1848 ifctl |= (1 << 7); /* enable gen2i speed */
1849 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
c9d39130
JG		 1850 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1851 }
1852
1853 udelay(25); /* allow reset propagation */
1854
1855 /* Spec never mentions clearing the bit. Marvell's driver does
1856 * clear the bit, however.
1857 */
1858 writelfl(0, port_mmio + EDMA_CMD_OFS);
1859
1860 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1861
1862 if (IS_50XX(hpriv))
1863 mdelay(1);
1864}
1865
1866static void mv_stop_and_reset(struct ata_port *ap)
1867{
cca3974e 1868 struct mv_host_priv *hpriv = ap->host->private_data;
0d5ff566 1869 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
c9d39130
JG		 1870
1871 mv_stop_dma(ap);
1872
1873 mv_channel_reset(hpriv, mmio, ap->port_no);
1874
22374677
JG		 1875 __mv_phy_reset(ap, 0);
1876}
1877
1878static inline void __msleep(unsigned int msec, int can_sleep)
1879{
1880 if (can_sleep)
1881 msleep(msec);
1882 else
1883 mdelay(msec);
c9d39130
JG		 1884}
1885
05b308e1 1886/**
22374677 1887 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
05b308e1
BR		 1888 * @ap: ATA channel to manipulate
1889 *
1890 * Part of this is taken from __sata_phy_reset and modified to
1891 * not sleep since this routine gets called from interrupt level.
1892 *
1893 * LOCKING:
1894 * Inherited from caller. This is coded to safe to call at
1895 * interrupt level, i.e. it does not sleep.
31961943 1896 */
22374677 1897static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
20f733e7 1898{
095fec88 1899 struct mv_port_priv *pp = ap->private_data;
cca3974e 1900 struct mv_host_priv *hpriv = ap->host->private_data;
20f733e7
BR		 1901 void __iomem *port_mmio = mv_ap_base(ap);
1902 struct ata_taskfile tf;
1903 struct ata_device *dev = &ap->device[0];
31961943 1904 unsigned long timeout;
22374677
JG		 1905 int retry = 5;
1906 u32 sstatus;
20f733e7
BR		 1907
1908 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1909
095fec88 1910 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1911 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1912 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
20f733e7 1913
22374677
JG		 1914 /* Issue COMRESET via SControl */
1915comreset_retry:
81952c54 1916 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
22374677
JG		 1917 __msleep(1, can_sleep);
1918
81952c54 1919 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
22374677
JG		 1920 __msleep(20, can_sleep);
1921
1922 timeout = jiffies + msecs_to_jiffies(200);
31961943 1923 do {
81952c54 1924 sata_scr_read(ap, SCR_STATUS, &sstatus);
62f1d0e6 1925 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
31961943 1926 break;
22374677
JG		 1927
1928 __msleep(1, can_sleep);
31961943 1929 } while (time_before(jiffies, timeout));
20f733e7 1930
22374677
JG		 1931 /* work around errata */
1932 if (IS_60XX(hpriv) &&
1933 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1934 (retry-- > 0))
1935 goto comreset_retry;
095fec88
JG		 1936
1937 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1938 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1939 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1940
81952c54 1941 if (ata_port_online(ap)) {
31961943
BR		 1942 ata_port_probe(ap);
1943 } else {
81952c54 1944 sata_scr_read(ap, SCR_STATUS, &sstatus);
f15a1daf
TH		 1945 ata_port_printk(ap, KERN_INFO,
1946 "no device found (phy stat %08x)\n", sstatus);
31961943 1947 ata_port_disable(ap);
20f733e7
BR		 1948 return;
1949 }
31961943 1950 ap->cbl = ATA_CBL_SATA;
20f733e7 1951
22374677
JG		 1952 /* even after SStatus reflects that device is ready,
1953 * it seems to take a while for link to be fully
1954 * established (and thus Status no longer 0x80/0x7F),
1955 * so we poll a bit for that, here.
1956 */
1957 retry = 20;
1958 while (1) {
1959 u8 drv_stat = ata_check_status(ap);
1960 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1961 break;
1962 __msleep(500, can_sleep);
1963 if (retry-- <= 0)
1964 break;
1965 }
1966
0d5ff566
TH		 1967 tf.lbah = readb(ap->ioaddr.lbah_addr);
1968 tf.lbam = readb(ap->ioaddr.lbam_addr);
1969 tf.lbal = readb(ap->ioaddr.lbal_addr);
1970 tf.nsect = readb(ap->ioaddr.nsect_addr);
20f733e7
BR		 1971
1972 dev->class = ata_dev_classify(&tf);
e1211e3f 1973 if (!ata_dev_enabled(dev)) {
20f733e7
BR		 1974 VPRINTK("Port disabled post-sig: No device present.\n");
1975 ata_port_disable(ap);
1976 }
095fec88
JG		 1977
1978 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1979
1980 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1981
bca1c4eb 1982 VPRINTK("EXIT\n");
20f733e7
BR		 1983}
1984
22374677
JG		 1985static void mv_phy_reset(struct ata_port *ap)
1986{
1987 __mv_phy_reset(ap, 1);
1988}
1989
05b308e1
BR		 1990/**
1991 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1992 * @ap: ATA channel to manipulate
1993 *
1994 * Intent is to clear all pending error conditions, reset the
1995 * chip/bus, fail the command, and move on.
1996 *
1997 * LOCKING:
cca3974e 1998 * This routine holds the host lock while failing the command.
05b308e1 1999 */
31961943
BR		 2000static void mv_eng_timeout(struct ata_port *ap)
2001{
0d5ff566 2002 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
31961943 2003 struct ata_queued_cmd *qc;
2f9719b6 2004 unsigned long flags;
31961943 2005
f15a1daf 2006 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
31961943 2007 DPRINTK("All regs @ start of eng_timeout\n");
0d5ff566 2008 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
31961943
BR		 2009
2010 qc = ata_qc_from_tag(ap, ap->active_tag);
2011 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
0d5ff566 2012 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
31961943 2013
cca3974e 2014 spin_lock_irqsave(&ap->host->lock, flags);
9b358e30 2015 mv_err_intr(ap, 0);
c9d39130 2016 mv_stop_and_reset(ap);
cca3974e 2017 spin_unlock_irqrestore(&ap->host->lock, flags);
31961943 2018
9b358e30
ML		 2019 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2020 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2021 qc->err_mask |= AC_ERR_TIMEOUT;
2022 ata_eh_qc_complete(qc);
2023 }
31961943
BR		 2024}
2025
05b308e1
BR		 2026/**
2027 * mv_port_init - Perform some early initialization on a single port.
2028 * @port: libata data structure storing shadow register addresses
2029 * @port_mmio: base address of the port
2030 *
2031 * Initialize shadow register mmio addresses, clear outstanding
2032 * interrupts on the port, and unmask interrupts for the future
2033 * start of the port.
2034 *
2035 * LOCKING:
2036 * Inherited from caller.
2037 */
31961943 2038static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2039{
0d5ff566 2040 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2041 unsigned serr_ofs;
2042
8b260248 2043 /* PIO related setup
31961943
BR		 2044 */
2045 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2046 port->error_addr =
31961943
BR		 2047 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2048 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2049 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2050 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2051 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2052 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2053 port->status_addr =
31961943
BR		 2054 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2055 /* special case: control/altstatus doesn't have ATA_REG_ address */
2056 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2057
2058 /* unused: */
8d9db2d2 2059 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2060
31961943
BR		 2061 /* Clear any currently outstanding port interrupt conditions */
2062 serr_ofs = mv_scr_offset(SCR_ERROR);
2063 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2064 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2065
20f733e7 2066 /* unmask all EDMA error interrupts */
31961943 2067 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2068
8b260248 2069 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2070 readl(port_mmio + EDMA_CFG_OFS),
2071 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2072 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2073}
2074
47c2b677 2075static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
522479fb 2076 unsigned int board_idx)
bca1c4eb
JG		 2077{
2078 u8 rev_id;
2079 u32 hp_flags = hpriv->hp_flags;
2080
2081 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2082
2083 switch(board_idx) {
47c2b677
JG		 2084 case chip_5080:
2085 hpriv->ops = &mv5xxx_ops;
2086 hp_flags |= MV_HP_50XX;
2087
2088 switch (rev_id) {
2089 case 0x1:
2090 hp_flags |= MV_HP_ERRATA_50XXB0;
2091 break;
2092 case 0x3:
2093 hp_flags |= MV_HP_ERRATA_50XXB2;
2094 break;
2095 default:
2096 dev_printk(KERN_WARNING, &pdev->dev,
2097 "Applying 50XXB2 workarounds to unknown rev\n");
2098 hp_flags |= MV_HP_ERRATA_50XXB2;
2099 break;
2100 }
2101 break;
2102
bca1c4eb
JG		 2103 case chip_504x:
2104 case chip_508x:
47c2b677 2105 hpriv->ops = &mv5xxx_ops;
bca1c4eb
JG		 2106 hp_flags |= MV_HP_50XX;
2107
47c2b677
JG		 2108 switch (rev_id) {
2109 case 0x0:
2110 hp_flags |= MV_HP_ERRATA_50XXB0;
2111 break;
2112 case 0x3:
2113 hp_flags |= MV_HP_ERRATA_50XXB2;
2114 break;
2115 default:
2116 dev_printk(KERN_WARNING, &pdev->dev,
2117 "Applying B2 workarounds to unknown rev\n");
2118 hp_flags |= MV_HP_ERRATA_50XXB2;
2119 break;
bca1c4eb
JG		 2120 }
2121 break;
2122
2123 case chip_604x:
2124 case chip_608x:
47c2b677
JG		 2125 hpriv->ops = &mv6xxx_ops;
2126
bca1c4eb 2127 switch (rev_id) {
47c2b677
JG		 2128 case 0x7:
2129 hp_flags |= MV_HP_ERRATA_60X1B2;
2130 break;
2131 case 0x9:
2132 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2133 break;
2134 default:
2135 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2136 "Applying B2 workarounds to unknown rev\n");
2137 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2138 break;
2139 }
2140 break;
2141
e4e7b892
JG		 2142 case chip_7042:
2143 case chip_6042:
2144 hpriv->ops = &mv6xxx_ops;
2145
2146 hp_flags |= MV_HP_GEN_IIE;
2147
2148 switch (rev_id) {
2149 case 0x0:
2150 hp_flags |= MV_HP_ERRATA_XX42A0;
2151 break;
2152 case 0x1:
2153 hp_flags |= MV_HP_ERRATA_60X1C0;
2154 break;
2155 default:
2156 dev_printk(KERN_WARNING, &pdev->dev,
2157 "Applying 60X1C0 workarounds to unknown rev\n");
2158 hp_flags |= MV_HP_ERRATA_60X1C0;
2159 break;
2160 }
2161 break;
2162
bca1c4eb
JG		 2163 default:
2164 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2165 return 1;
2166 }
2167
2168 hpriv->hp_flags = hp_flags;
2169
2170 return 0;
2171}
2172
05b308e1 2173/**
47c2b677 2174 * mv_init_host - Perform some early initialization of the host.
bca1c4eb 2175 * @pdev: host PCI device
05b308e1
BR		 2176 * @probe_ent: early data struct representing the host
2177 *
2178 * If possible, do an early global reset of the host. Then do
2179 * our port init and clear/unmask all/relevant host interrupts.
2180 *
2181 * LOCKING:
2182 * Inherited from caller.
2183 */
47c2b677 2184static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
bca1c4eb 2185 unsigned int board_idx)
20f733e7
BR		 2186{
2187 int rc = 0, n_hc, port, hc;
0d5ff566 2188 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
bca1c4eb
JG		 2189 struct mv_host_priv *hpriv = probe_ent->private_data;
2190
47c2b677
JG		 2191 /* global interrupt mask */
2192 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2193
2194 rc = mv_chip_id(pdev, hpriv, board_idx);
bca1c4eb
JG		 2195 if (rc)
2196 goto done;
2197
cca3974e 2198 n_hc = mv_get_hc_count(probe_ent->port_flags);
bca1c4eb
JG		 2199 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2200
47c2b677
JG		 2201 for (port = 0; port < probe_ent->n_ports; port++)
2202 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2203
c9d39130 2204 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2205 if (rc)
20f733e7 2206 goto done;
20f733e7 2207
522479fb
JG		 2208 hpriv->ops->reset_flash(hpriv, mmio);
2209 hpriv->ops->reset_bus(pdev, mmio);
47c2b677 2210 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7
BR		 2211
2212 for (port = 0; port < probe_ent->n_ports; port++) {
2a47ce06 2213 if (IS_60XX(hpriv)) {
c9d39130
JG		 2214 void __iomem *port_mmio = mv_port_base(mmio, port);
2215
2a47ce06 2216 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 2217 ifctl |= (1 << 7); /* enable gen2i speed */
2218 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2a47ce06
JG		 2219 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2220 }
2221
c9d39130 2222 hpriv->ops->phy_errata(hpriv, mmio, port);
2a47ce06
JG		 2223 }
2224
2225 for (port = 0; port < probe_ent->n_ports; port++) {
2226 void __iomem *port_mmio = mv_port_base(mmio, port);
31961943 2227 mv_port_init(&probe_ent->port[port], port_mmio);
20f733e7
BR		 2228 }
2229
2230 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2231 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2232
2233 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2234 "(before clear)=0x%08x\n", hc,
2235 readl(hc_mmio + HC_CFG_OFS),
2236 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2237
2238 /* Clear any currently outstanding hc interrupt conditions */
2239 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2240 }
2241
31961943
BR		 2242 /* Clear any currently outstanding host interrupt conditions */
2243 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2244
2245 /* and unmask interrupt generation for host regs */
2246 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
fb621e2f
JG		 2247
2248 if (IS_50XX(hpriv))
2249 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2250 else
2251 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
20f733e7
BR		 2252
2253 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
8b260248 2254 "PCI int cause/mask=0x%08x/0x%08x\n",
20f733e7
BR		 2255 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2256 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2257 readl(mmio + PCI_IRQ_CAUSE_OFS),
2258 readl(mmio + PCI_IRQ_MASK_OFS));
bca1c4eb 2259
31961943 2260done:
20f733e7
BR		 2261 return rc;
2262}
2263
05b308e1
BR		 2264/**
2265 * mv_print_info - Dump key info to kernel log for perusal.
2266 * @probe_ent: early data struct representing the host
2267 *
2268 * FIXME: complete this.
2269 *
2270 * LOCKING:
2271 * Inherited from caller.
2272 */
31961943
BR		 2273static void mv_print_info(struct ata_probe_ent *probe_ent)
2274{
2275 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2276 struct mv_host_priv *hpriv = probe_ent->private_data;
2277 u8 rev_id, scc;
2278 const char *scc_s;
2279
2280 /* Use this to determine the HW stepping of the chip so we know
2281 * what errata to workaround
2282 */
2283 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2284
2285 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2286 if (scc == 0)
2287 scc_s = "SCSI";
2288 else if (scc == 0x01)
2289 scc_s = "RAID";
2290 else
2291 scc_s = "unknown";
2292
a9524a76
JG		 2293 dev_printk(KERN_INFO, &pdev->dev,
2294 "%u slots %u ports %s mode IRQ via %s\n",
8b260248 2295 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
31961943
BR		 2296 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2297}
2298
05b308e1
BR		 2299/**
2300 * mv_init_one - handle a positive probe of a Marvell host
2301 * @pdev: PCI device found
2302 * @ent: PCI device ID entry for the matched host
2303 *
2304 * LOCKING:
2305 * Inherited from caller.
2306 */
20f733e7
BR		 2307static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2308{
2309 static int printed_version = 0;
24dc5f33
TH		 2310 struct device *dev = &pdev->dev;
2311 struct ata_probe_ent *probe_ent;
20f733e7
BR		 2312 struct mv_host_priv *hpriv;
2313 unsigned int board_idx = (unsigned int)ent->driver_data;
24dc5f33 2314 int rc;
20f733e7 2315
a9524a76
JG		 2316 if (!printed_version++)
2317 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 2318
24dc5f33
TH		 2319 rc = pcim_enable_device(pdev);
2320 if (rc)
20f733e7 2321 return rc;
eb46d684 2322 pci_set_master(pdev);
20f733e7 2323
0d5ff566
TH		 2324 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2325 if (rc == -EBUSY)
24dc5f33 2326 pcim_pin_device(pdev);
0d5ff566 2327 if (rc)
24dc5f33 2328 return rc;
20f733e7 2329
24dc5f33
TH		 2330 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2331 if (probe_ent == NULL)
2332 return -ENOMEM;
20f733e7 2333
20f733e7
BR		 2334 probe_ent->dev = pci_dev_to_dev(pdev);
2335 INIT_LIST_HEAD(&probe_ent->node);
2336
24dc5f33
TH		 2337 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2338 if (!hpriv)
2339 return -ENOMEM;
20f733e7
BR		 2340
2341 probe_ent->sht = mv_port_info[board_idx].sht;
cca3974e 2342 probe_ent->port_flags = mv_port_info[board_idx].flags;
20f733e7
BR		 2343 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2344 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2345 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2346
2347 probe_ent->irq = pdev->irq;
1d6f359a 2348 probe_ent->irq_flags = IRQF_SHARED;
0d5ff566 2349 probe_ent->iomap = pcim_iomap_table(pdev);
20f733e7
BR		 2350 probe_ent->private_data = hpriv;
2351
2352 /* initialize adapter */
47c2b677 2353 rc = mv_init_host(pdev, probe_ent, board_idx);
24dc5f33
TH		 2354 if (rc)
2355 return rc;
20f733e7 2356
31961943 2357 /* Enable interrupts */
6a59dcf8 2358 if (msi && pci_enable_msi(pdev))
31961943 2359 pci_intx(pdev, 1);
20f733e7 2360
31961943
BR		 2361 mv_dump_pci_cfg(pdev, 0x68);
2362 mv_print_info(probe_ent);
2363
24dc5f33
TH		 2364 if (ata_device_add(probe_ent) == 0)
2365 return -ENODEV;
20f733e7 2366
24dc5f33 2367 devm_kfree(dev, probe_ent);
20f733e7 2368 return 0;
20f733e7
BR		 2369}
2370
2371static int __init mv_init(void)
2372{
b7887196 2373 return pci_register_driver(&mv_pci_driver);
20f733e7
BR		 2374}
2375
2376static void __exit mv_exit(void)
2377{
2378 pci_unregister_driver(&mv_pci_driver);
2379}
2380
2381MODULE_AUTHOR("Brett Russ");
2382MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2383MODULE_LICENSE("GPL");
2384MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2385MODULE_VERSION(DRV_VERSION);
2386
ddef9bb3
JG		 2387module_param(msi, int, 0444);
2388MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2389
20f733e7
BR		 2390module_init(mv_init);
2391module_exit(mv_exit);
Linux kernel - Deliverables
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