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sata_mv: don't blindly enable IRQs
[deliverable/linux.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
c46938cc 68#include <linux/bitops.h>
20f733e7 69#include <scsi/scsi_host.h>
193515d5 70#include <scsi/scsi_cmnd.h>
6c08772e 71#include <scsi/scsi_device.h>
20f733e7 72#include <linux/libata.h>
20f733e7
BR		 73
74#define DRV_NAME "sata_mv"
1fd2e1c2 75#define DRV_VERSION "1.20"
20f733e7
BR		 76
77enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85
86 MV_PCI_REG_BASE = 0,
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93
20f733e7 94 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 98
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103
31961943
BR		 104 MV_MAX_Q_DEPTH = 32,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 */
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 113 MV_MAX_SG_CT = 256,
31961943 114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 115
352fab70 116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 117 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 121
122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 125 /* SoC integrated controllers, no PCI interface */
e12bef50 126 MV_FLAG_SOC = (1 << 28),
7bb3c529 127
c5d3e45a 128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
ad3aef51 131
47c2b677 132 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 133
ad3aef51
ML		 134 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
135 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
c443c500 136 ATA_FLAG_NCQ | ATA_FLAG_AN,
ad3aef51 137
31961943
BR		 138 CRQB_FLAG_READ = (1 << 0),
139 CRQB_TAG_SHIFT = 1,
c5d3e45a 140 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 141 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 142 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 143 CRQB_CMD_ADDR_SHIFT = 8,
144 CRQB_CMD_CS = (0x2 << 11),
145 CRQB_CMD_LAST = (1 << 15),
146
147 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 148 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
149 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 150
151 EPRD_FLAG_END_OF_TBL = (1 << 31),
152
20f733e7
BR		 153 /* PCI interface registers */
154
31961943 155 PCI_COMMAND_OFS = 0xc00,
8e7decdb 156 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 157
20f733e7
BR		 158 PCI_MAIN_CMD_STS_OFS = 0xd30,
159 STOP_PCI_MASTER = (1 << 2),
160 PCI_MASTER_EMPTY = (1 << 3),
161 GLOB_SFT_RST = (1 << 4),
162
8e7decdb
ML		 163 MV_PCI_MODE_OFS = 0xd00,
164 MV_PCI_MODE_MASK = 0x30,
165
522479fb
JG		 166 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
167 MV_PCI_DISC_TIMER = 0xd04,
168 MV_PCI_MSI_TRIGGER = 0xc38,
169 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 170 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 171 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
172 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
173 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
174 MV_PCI_ERR_COMMAND = 0x1d50,
175
02a121da
ML		 176 PCI_IRQ_CAUSE_OFS = 0x1d58,
177 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 178 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
179
02a121da
ML		 180 PCIE_IRQ_CAUSE_OFS = 0x1900,
181 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 182 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 183
7368f919
ML		 184 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
185 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
186 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
187 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
188 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 189 ERR_IRQ = (1 << 0), /* shift by port # */
190 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 191 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
192 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
193 PCI_ERR = (1 << 18),
194 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
195 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 196 PORTS_0_3_COAL_DONE = (1 << 8),
197 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 198 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
199 GPIO_INT = (1 << 22),
200 SELF_INT = (1 << 23),
201 TWSI_INT = (1 << 24),
202 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 203 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 204 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 205
206 /* SATAHC registers */
207 HC_CFG_OFS = 0,
208
209 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 210 DMA_IRQ = (1 << 0), /* shift by port # */
211 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 212 DEV_IRQ = (1 << 8), /* shift by port # */
213
214 /* Shadow block registers */
31961943
BR		 215 SHD_BLK_OFS = 0x100,
216 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 217
218 /* SATA registers */
219 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
220 SATA_ACTIVE_OFS = 0x350,
0c58912e 221 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 222 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 223
e12bef50 224 LTMODE_OFS = 0x30c,
17c5aab5
ML		 225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
47c2b677 227 PHY_MODE3 = 0x310,
bca1c4eb
JG		 228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
e12bef50 230 SATA_IFCTL_OFS = 0x344,
8e7decdb 231 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 234
8e7decdb
ML		 235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 238
c9d39130 239 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 243
244 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
0c58912e
ML		 248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 272
6c1153e0 273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
6c1153e0 279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 280
6c1153e0 281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
6c1153e0 288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 289
6c1153e0 290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 297 EDMA_ERR_LNK_CTRL_TX,
646a4da5 298
bdd4ddde
JG		 299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
6c1153e0 305 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
e12bef50 313
bdd4ddde
JG		 314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
6c1153e0 321 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
20f733e7 325
31961943
BR		 326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
0ea9e179
JG		 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 345
8e7decdb
ML		 346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 350
352fab70
ML		 351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
31961943
BR		 353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 359 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 365
31961943 366 /* Port private flags (pp_flags) */
0ea9e179 367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 369 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 370 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 371};
372
ee9ccdf7
JG		 373#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
374#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 375#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 376#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 377#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 378
15a32632
LB		 379#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
380#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
381
095fec88 382enum {
baf14aa1
JG		 383 /* DMA boundary 0xffff is required by the s/g splitting
384 * we need on /length/ in mv_fill-sg().
385 */
386 MV_DMA_BOUNDARY = 0xffffU,
095fec88 387
0ea9e179
JG		 388 /* mask of register bits containing lower 32 bits
389 * of EDMA request queue DMA address
390 */
095fec88
JG		 391 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
392
0ea9e179 393 /* ditto, for response queue */
095fec88
JG		 394 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
395};
396
522479fb
JG		 397enum chip_type {
398 chip_504x,
399 chip_508x,
400 chip_5080,
401 chip_604x,
402 chip_608x,
e4e7b892
JG		 403 chip_6042,
404 chip_7042,
f351b2d6 405 chip_soc,
522479fb
JG		 406};
407
31961943
BR		 408/* Command ReQuest Block: 32B */
409struct mv_crqb {
e1469874
ML		 410 __le32 sg_addr;
411 __le32 sg_addr_hi;
412 __le16 ctrl_flags;
413 __le16 ata_cmd[11];
31961943 414};
20f733e7 415
e4e7b892 416struct mv_crqb_iie {
e1469874
ML		 417 __le32 addr;
418 __le32 addr_hi;
419 __le32 flags;
420 __le32 len;
421 __le32 ata_cmd[4];
e4e7b892
JG		 422};
423
31961943
BR		 424/* Command ResPonse Block: 8B */
425struct mv_crpb {
e1469874
ML		 426 __le16 id;
427 __le16 flags;
428 __le32 tmstmp;
20f733e7
BR		 429};
430
31961943
BR		 431/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
432struct mv_sg {
e1469874
ML		 433 __le32 addr;
434 __le32 flags_size;
435 __le32 addr_hi;
436 __le32 reserved;
31961943 437};
20f733e7 438
31961943
BR		 439struct mv_port_priv {
440 struct mv_crqb *crqb;
441 dma_addr_t crqb_dma;
442 struct mv_crpb *crpb;
443 dma_addr_t crpb_dma;
eb73d558
ML		 444 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
445 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 446
447 unsigned int req_idx;
448 unsigned int resp_idx;
449
31961943 450 u32 pp_flags;
29d187bb 451 unsigned int delayed_eh_pmp_map;
31961943
BR		 452};
453
bca1c4eb
JG		 454struct mv_port_signal {
455 u32 amps;
456 u32 pre;
457};
458
02a121da
ML		 459struct mv_host_priv {
460 u32 hp_flags;
461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
f351b2d6
SB		 463 int n_ports;
464 void __iomem *base;
7368f919
ML		 465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
02a121da
ML		 467 u32 irq_cause_ofs;
468 u32 irq_mask_ofs;
469 u32 unmask_all_irqs;
da2fa9ba
ML		 470 /*
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
474 */
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
02a121da
ML		 478};
479
47c2b677 480struct mv_hw_ops {
2a47ce06
JG		 481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
482 unsigned int port);
47c2b677
JG		 483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
485 void __iomem *mmio);
c9d39130
JG		 486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
487 unsigned int n_hc);
522479fb 488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 490};
491
da3dbb17
TH		 492static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
493static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
494static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
495static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 496static int mv_port_start(struct ata_port *ap);
497static void mv_port_stop(struct ata_port *ap);
3e4a1391 498static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 499static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 500static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 501static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 502static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
bdd4ddde
JG		 504static void mv_eh_freeze(struct ata_port *ap);
505static void mv_eh_thaw(struct ata_port *ap);
f273827e 506static void mv6_dev_config(struct ata_device *dev);
20f733e7 507
2a47ce06
JG		 508static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
509 unsigned int port);
47c2b677
JG		 510static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
512 void __iomem *mmio);
c9d39130
JG		 513static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
514 unsigned int n_hc);
522479fb 515static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 516static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 517
2a47ce06
JG		 518static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
519 unsigned int port);
47c2b677
JG		 520static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
522 void __iomem *mmio);
c9d39130
JG		 523static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
524 unsigned int n_hc);
522479fb 525static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 526static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
527 void __iomem *mmio);
528static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
529 void __iomem *mmio);
530static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
533 void __iomem *mmio);
534static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 535static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 536static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 537 unsigned int port_no);
e12bef50 538static int mv_stop_edma(struct ata_port *ap);
b562468c 539static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 540static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 541
e49856d8
ML		 542static void mv_pmp_select(struct ata_port *ap, int pmp);
543static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
29d187bb 547static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 548static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
47c2b677 550
eb73d558
ML		 551/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
554 */
c5d3e45a 555static struct scsi_host_template mv5_sht = {
68d1d07b 556 ATA_BASE_SHT(DRV_NAME),
baf14aa1 557 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 558 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 559};
560
561static struct scsi_host_template mv6_sht = {
68d1d07b 562 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 563 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 564 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 565 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 566};
567
029cfd6b
TH		 568static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
c9d39130 570
3e4a1391 571 .qc_defer = mv_qc_defer,
c9d39130
JG		 572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
c9d39130 574
bdd4ddde
JG		 575 .freeze = mv_eh_freeze,
576 .thaw = mv_eh_thaw,
a1efdaba 577 .hardreset = mv_hardreset,
a1efdaba 578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 579 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 580
c9d39130
JG		 581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
583
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
c9d39130
JG		 586};
587
029cfd6b
TH		 588static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
f273827e 590 .dev_config = mv6_dev_config,
20f733e7
BR		 591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
593
e49856d8
ML		 594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
29d187bb 597 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 598};
599
029cfd6b
TH		 600static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
e4e7b892 603 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 604};
605
98ac62de 606static const struct ata_port_info mv_port_info[] = {
20f733e7 607 { /* chip_504x */
cca3974e 608 .flags = MV_COMMON_FLAGS,
31961943 609 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 610 .udma_mask = ATA_UDMA6,
c9d39130 611 .port_ops = &mv5_ops,
20f733e7
BR		 612 },
613 { /* chip_508x */
c5d3e45a 614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 615 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
c9d39130 617 .port_ops = &mv5_ops,
20f733e7 618 },
47c2b677 619 { /* chip_5080 */
c5d3e45a 620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 621 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 622 .udma_mask = ATA_UDMA6,
c9d39130 623 .port_ops = &mv5_ops,
47c2b677 624 },
20f733e7 625 { /* chip_604x */
138bfdd0 626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 628 ATA_FLAG_NCQ,
31961943 629 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 630 .udma_mask = ATA_UDMA6,
c9d39130 631 .port_ops = &mv6_ops,
20f733e7
BR		 632 },
633 { /* chip_608x */
c5d3e45a 634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 637 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 638 .udma_mask = ATA_UDMA6,
c9d39130 639 .port_ops = &mv6_ops,
20f733e7 640 },
e4e7b892 641 { /* chip_6042 */
ad3aef51 642 .flags = MV_GENIIE_FLAGS,
e4e7b892 643 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 644 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 645 .port_ops = &mv_iie_ops,
646 },
647 { /* chip_7042 */
ad3aef51 648 .flags = MV_GENIIE_FLAGS,
e4e7b892 649 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 650 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 651 .port_ops = &mv_iie_ops,
652 },
f351b2d6 653 { /* chip_soc */
ad3aef51 654 .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC,
17c5aab5
ML		 655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
f351b2d6 658 },
20f733e7
BR		 659};
660
3b7d697d 661static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 666 /* RocketRAID 1740/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
668 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 669
670 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
673 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
674 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
675
676 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
677
d9f9c6bc
FA		 678 /* Adaptec 1430SA */
679 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
680
02a121da 681 /* Marvell 7042 support */
6a3d586d
MT		 682 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
683
02a121da
ML		 684 /* Highpoint RocketRAID PCIe series */
685 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
686 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
687
2d2744fc 688 { } /* terminate list */
20f733e7
BR		 689};
690
47c2b677
JG		 691static const struct mv_hw_ops mv5xxx_ops = {
692 .phy_errata = mv5_phy_errata,
693 .enable_leds = mv5_enable_leds,
694 .read_preamp = mv5_read_preamp,
695 .reset_hc = mv5_reset_hc,
522479fb
JG		 696 .reset_flash = mv5_reset_flash,
697 .reset_bus = mv5_reset_bus,
47c2b677
JG		 698};
699
700static const struct mv_hw_ops mv6xxx_ops = {
701 .phy_errata = mv6_phy_errata,
702 .enable_leds = mv6_enable_leds,
703 .read_preamp = mv6_read_preamp,
704 .reset_hc = mv6_reset_hc,
522479fb
JG		 705 .reset_flash = mv6_reset_flash,
706 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 707};
708
f351b2d6
SB		 709static const struct mv_hw_ops mv_soc_ops = {
710 .phy_errata = mv6_phy_errata,
711 .enable_leds = mv_soc_enable_leds,
712 .read_preamp = mv_soc_read_preamp,
713 .reset_hc = mv_soc_reset_hc,
714 .reset_flash = mv_soc_reset_flash,
715 .reset_bus = mv_soc_reset_bus,
716};
717
20f733e7
BR		 718/*
719 * Functions
720 */
721
722static inline void writelfl(unsigned long data, void __iomem *addr)
723{
724 writel(data, addr);
725 (void) readl(addr); /* flush to avoid PCI posted write */
726}
727
c9d39130
JG		 728static inline unsigned int mv_hc_from_port(unsigned int port)
729{
730 return port >> MV_PORT_HC_SHIFT;
731}
732
733static inline unsigned int mv_hardport_from_port(unsigned int port)
734{
735 return port & MV_PORT_MASK;
736}
737
1cfd19ae
ML		 738/*
739 * Consolidate some rather tricky bit shift calculations.
740 * This is hot-path stuff, so not a function.
741 * Simple code, with two return values, so macro rather than inline.
742 *
743 * port is the sole input, in range 0..7.
7368f919
ML		 744 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
745 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 746 *
747 * Note that port and hardport may be the same variable in some cases.
748 */
749#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
750{ \
751 shift = mv_hc_from_port(port) * HC_SHIFT; \
752 hardport = mv_hardport_from_port(port); \
753 shift += hardport * 2; \
754}
755
352fab70
ML		 756static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
757{
758 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
759}
760
c9d39130
JG		 761static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
762 unsigned int port)
763{
764 return mv_hc_base(base, mv_hc_from_port(port));
765}
766
20f733e7
BR		 767static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
768{
c9d39130 769 return mv_hc_base_from_port(base, port) +
8b260248 770 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 771 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 772}
773
e12bef50
ML		 774static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
775{
776 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
777 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
778
779 return hc_mmio + ofs;
780}
781
f351b2d6
SB		 782static inline void __iomem *mv_host_base(struct ata_host *host)
783{
784 struct mv_host_priv *hpriv = host->private_data;
785 return hpriv->base;
786}
787
20f733e7
BR		 788static inline void __iomem *mv_ap_base(struct ata_port *ap)
789{
f351b2d6 790 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 791}
792
cca3974e 793static inline int mv_get_hc_count(unsigned long port_flags)
31961943 794{
cca3974e 795 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 796}
797
c5d3e45a
JG		 798static void mv_set_edma_ptrs(void __iomem *port_mmio,
799 struct mv_host_priv *hpriv,
800 struct mv_port_priv *pp)
801{
bdd4ddde
JG		 802 u32 index;
803
c5d3e45a
JG		 804 /*
805 * initialize request queue
806 */
fcfb1f77
ML		 807 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
808 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 809
c5d3e45a
JG		 810 WARN_ON(pp->crqb_dma & 0x3ff);
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
814
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 816 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
818 else
bdd4ddde 819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 820
821 /*
822 * initialize response queue
823 */
fcfb1f77
ML		 824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 826
c5d3e45a
JG		 827 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
829
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 831 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
833 else
bdd4ddde 834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 835
bdd4ddde 836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 838}
839
05b308e1
BR		 840/**
841 * mv_start_dma - Enable eDMA engine
842 * @base: port base address
843 * @pp: port private data
844 *
beec7dbc
TH		 845 * Verify the local cache of the eDMA state is accurate with a
846 * WARN_ON.
05b308e1
BR		 847 *
848 * LOCKING:
849 * Inherited from caller.
850 */
0c58912e 851static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 852 struct mv_port_priv *pp, u8 protocol)
20f733e7 853{
72109168
ML		 854 int want_ncq = (protocol == ATA_PROT_NCQ);
855
856 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
857 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
858 if (want_ncq != using_ncq)
b562468c 859 mv_stop_edma(ap);
72109168 860 }
c5d3e45a 861 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 862 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 863 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 864 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 865 mv_host_base(ap->host), hardport);
0c58912e
ML		 866 u32 hc_irq_cause, ipending;
867
bdd4ddde 868 /* clear EDMA event indicators, if any */
f630d562 869 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 870
0c58912e
ML		 871 /* clear EDMA interrupt indicator, if any */
872 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 873 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 874 if (hc_irq_cause & ipending) {
875 writelfl(hc_irq_cause & ~ipending,
876 hc_mmio + HC_IRQ_CAUSE_OFS);
877 }
878
e12bef50 879 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 880
881 /* clear FIS IRQ Cause */
e4006077
ML		 882 if (IS_GEN_IIE(hpriv))
883 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
0c58912e 884
f630d562 885 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 886
f630d562 887 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 888 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
889 }
20f733e7
BR		 890}
891
9b2c4e0b
ML		 892static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
893{
894 void __iomem *port_mmio = mv_ap_base(ap);
895 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
896 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
897 int i;
898
899 /*
900 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 901 * No idea what a good "timeout" value might be, but measurements
902 * indicate that it often requires hundreds of microseconds
903 * with two drives in-use. So we use the 15msec value above
904 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 905 */
906 for (i = 0; i < timeout; ++i) {
907 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
908 if ((edma_stat & empty_idle) == empty_idle)
909 break;
910 udelay(per_loop);
911 }
912 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
913}
914
05b308e1 915/**
e12bef50 916 * mv_stop_edma_engine - Disable eDMA engine
b562468c 917 * @port_mmio: io base address
05b308e1
BR		 918 *
919 * LOCKING:
920 * Inherited from caller.
921 */
b562468c 922static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 923{
b562468c 924 int i;
31961943 925
b562468c
ML		 926 /* Disable eDMA. The disable bit auto clears. */
927 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 928
b562468c
ML		 929 /* Wait for the chip to confirm eDMA is off. */
930 for (i = 10000; i > 0; i--) {
931 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 932 if (!(reg & EDMA_EN))
b562468c
ML		 933 return 0;
934 udelay(10);
31961943 935 }
b562468c 936 return -EIO;
20f733e7
BR		 937}
938
e12bef50 939static int mv_stop_edma(struct ata_port *ap)
0ea9e179 940{
b562468c
ML		 941 void __iomem *port_mmio = mv_ap_base(ap);
942 struct mv_port_priv *pp = ap->private_data;
0ea9e179 943
b562468c
ML		 944 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
945 return 0;
946 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 947 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 948 if (mv_stop_edma_engine(port_mmio)) {
949 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
950 return -EIO;
951 }
952 return 0;
0ea9e179
JG		 953}
954
8a70f8dc 955#ifdef ATA_DEBUG
31961943 956static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 957{
31961943
BR		 958 int b, w;
959 for (b = 0; b < bytes; ) {
960 DPRINTK("%p: ", start + b);
961 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 962 printk("%08x ", readl(start + b));
31961943
BR		 963 b += sizeof(u32);
964 }
965 printk("\n");
966 }
31961943 967}
8a70f8dc
JG		 968#endif
969
31961943
BR		 970static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
971{
972#ifdef ATA_DEBUG
973 int b, w;
974 u32 dw;
975 for (b = 0; b < bytes; ) {
976 DPRINTK("%02x: ", b);
977 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 978 (void) pci_read_config_dword(pdev, b, &dw);
979 printk("%08x ", dw);
31961943
BR		 980 b += sizeof(u32);
981 }
982 printk("\n");
983 }
984#endif
985}
986static void mv_dump_all_regs(void __iomem *mmio_base, int port,
987 struct pci_dev *pdev)
988{
989#ifdef ATA_DEBUG
8b260248 990 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 991 port >> MV_PORT_HC_SHIFT);
992 void __iomem *port_base;
993 int start_port, num_ports, p, start_hc, num_hcs, hc;
994
995 if (0 > port) {
996 start_hc = start_port = 0;
997 num_ports = 8; /* shld be benign for 4 port devs */
998 num_hcs = 2;
999 } else {
1000 start_hc = port >> MV_PORT_HC_SHIFT;
1001 start_port = port;
1002 num_ports = num_hcs = 1;
1003 }
8b260248 1004 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1005 num_ports > 1 ? num_ports - 1 : start_port);
1006
1007 if (NULL != pdev) {
1008 DPRINTK("PCI config space regs:\n");
1009 mv_dump_pci_cfg(pdev, 0x68);
1010 }
1011 DPRINTK("PCI regs:\n");
1012 mv_dump_mem(mmio_base+0xc00, 0x3c);
1013 mv_dump_mem(mmio_base+0xd00, 0x34);
1014 mv_dump_mem(mmio_base+0xf00, 0x4);
1015 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1016 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1017 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1018 DPRINTK("HC regs (HC %i):\n", hc);
1019 mv_dump_mem(hc_base, 0x1c);
1020 }
1021 for (p = start_port; p < start_port + num_ports; p++) {
1022 port_base = mv_port_base(mmio_base, p);
2dcb407e 1023 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1024 mv_dump_mem(port_base, 0x54);
2dcb407e 1025 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1026 mv_dump_mem(port_base+0x300, 0x60);
1027 }
1028#endif
20f733e7
BR		 1029}
1030
1031static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1032{
1033 unsigned int ofs;
1034
1035 switch (sc_reg_in) {
1036 case SCR_STATUS:
1037 case SCR_CONTROL:
1038 case SCR_ERROR:
1039 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1040 break;
1041 case SCR_ACTIVE:
1042 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1043 break;
1044 default:
1045 ofs = 0xffffffffU;
1046 break;
1047 }
1048 return ofs;
1049}
1050
da3dbb17 1051static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1052{
1053 unsigned int ofs = mv_scr_offset(sc_reg_in);
1054
da3dbb17
TH		 1055 if (ofs != 0xffffffffU) {
1056 *val = readl(mv_ap_base(ap) + ofs);
1057 return 0;
1058 } else
1059 return -EINVAL;
20f733e7
BR		 1060}
1061
da3dbb17 1062static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1063{
1064 unsigned int ofs = mv_scr_offset(sc_reg_in);
1065
da3dbb17 1066 if (ofs != 0xffffffffU) {
20f733e7 1067 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1068 return 0;
1069 } else
1070 return -EINVAL;
20f733e7
BR		 1071}
1072
f273827e
ML		 1073static void mv6_dev_config(struct ata_device *adev)
1074{
1075 /*
e49856d8
ML		 1076 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1077 *
1078 * Gen-II does not support NCQ over a port multiplier
1079 * (no FIS-based switching).
1080 *
f273827e
ML		 1081 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1082 * See mv_qc_prep() for more info.
1083 */
e49856d8 1084 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1085 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1086 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1087 ata_dev_printk(adev, KERN_INFO,
1088 "NCQ disabled for command-based switching\n");
1089 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1090 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1091 ata_dev_printk(adev, KERN_INFO,
1092 "max_sectors limited to %u for NCQ\n",
1093 adev->max_sectors);
1094 }
e49856d8 1095 }
f273827e
ML		 1096}
1097
3e4a1391
ML		 1098static int mv_qc_defer(struct ata_queued_cmd *qc)
1099{
1100 struct ata_link *link = qc->dev->link;
1101 struct ata_port *ap = link->ap;
1102 struct mv_port_priv *pp = ap->private_data;
1103
29d187bb
ML		 1104 /*
1105 * Don't allow new commands if we're in a delayed EH state
1106 * for NCQ and/or FIS-based switching.
1107 */
1108 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1109 return ATA_DEFER_PORT;
3e4a1391
ML		 1110 /*
1111 * If the port is completely idle, then allow the new qc.
1112 */
1113 if (ap->nr_active_links == 0)
1114 return 0;
1115
1116 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1117 /*
1118 * The port is operating in host queuing mode (EDMA).
1119 * It can accomodate a new qc if the qc protocol
1120 * is compatible with the current host queue mode.
1121 */
1122 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1123 /*
1124 * The host queue (EDMA) is in NCQ mode.
1125 * If the new qc is also an NCQ command,
1126 * then allow the new qc.
1127 */
1128 if (qc->tf.protocol == ATA_PROT_NCQ)
1129 return 0;
1130 } else {
1131 /*
1132 * The host queue (EDMA) is in non-NCQ, DMA mode.
1133 * If the new qc is also a non-NCQ, DMA command,
1134 * then allow the new qc.
1135 */
1136 if (qc->tf.protocol == ATA_PROT_DMA)
1137 return 0;
1138 }
1139 }
1140 return ATA_DEFER_PORT;
1141}
1142
00f42eab 1143static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1144{
00f42eab
ML		 1145 u32 new_fiscfg, old_fiscfg;
1146 u32 new_ltmode, old_ltmode;
1147 u32 new_haltcond, old_haltcond;
1148
1149 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1150 old_ltmode = readl(port_mmio + LTMODE_OFS);
1151 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1152
1153 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1154 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1155 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1156
1157 if (want_fbs) {
1158 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1159 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1160 if (want_ncq)
1161 new_haltcond &= ~EDMA_ERR_DEV;
1162 else
1163 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1164 }
00f42eab 1165
8e7decdb
ML		 1166 if (new_fiscfg != old_fiscfg)
1167 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1168 if (new_ltmode != old_ltmode)
1169 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1170 if (new_haltcond != old_haltcond)
1171 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1172}
1173
dd2890f6
ML		 1174static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1175{
1176 struct mv_host_priv *hpriv = ap->host->private_data;
1177 u32 old, new;
1178
1179 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1180 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1181 if (want_ncq)
1182 new = old | (1 << 22);
1183 else
1184 new = old & ~(1 << 22);
1185 if (new != old)
1186 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1187}
1188
e12bef50 1189static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1190{
0c58912e 1191 u32 cfg;
e12bef50
ML		 1192 struct mv_port_priv *pp = ap->private_data;
1193 struct mv_host_priv *hpriv = ap->host->private_data;
1194 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1195
1196 /* set up non-NCQ EDMA configuration */
0c58912e 1197 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00f42eab 1198 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
e4e7b892 1199
0c58912e 1200 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1201 cfg |= (1 << 8); /* enab config burst size mask */
1202
dd2890f6 1203 else if (IS_GEN_II(hpriv)) {
e4e7b892 1204 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1205 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1206
dd2890f6 1207 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1208 int want_fbs = sata_pmp_attached(ap);
1209 /*
1210 * Possible future enhancement:
1211 *
1212 * The chip can use FBS with non-NCQ, if we allow it,
1213 * But first we need to have the error handling in place
1214 * for this mode (datasheet section 7.3.15.4.2.3).
1215 * So disallow non-NCQ FBS for now.
1216 */
1217 want_fbs &= want_ncq;
1218
1219 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1220
1221 if (want_fbs) {
1222 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1223 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1224 }
1225
e728eabe
JG		 1226 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1227 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1228 if (HAS_PCI(ap->host))
1229 cfg |= (1 << 18); /* enab early completion */
1230 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1231 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1232 }
1233
72109168
ML		 1234 if (want_ncq) {
1235 cfg |= EDMA_CFG_NCQ;
1236 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1237 } else
1238 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1239
e4e7b892
JG		 1240 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1241}
1242
da2fa9ba
ML		 1243static void mv_port_free_dma_mem(struct ata_port *ap)
1244{
1245 struct mv_host_priv *hpriv = ap->host->private_data;
1246 struct mv_port_priv *pp = ap->private_data;
eb73d558 1247 int tag;
da2fa9ba
ML		 1248
1249 if (pp->crqb) {
1250 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1251 pp->crqb = NULL;
1252 }
1253 if (pp->crpb) {
1254 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1255 pp->crpb = NULL;
1256 }
eb73d558
ML		 1257 /*
1258 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1259 * For later hardware, we have one unique sg_tbl per NCQ tag.
1260 */
1261 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1262 if (pp->sg_tbl[tag]) {
1263 if (tag == 0 || !IS_GEN_I(hpriv))
1264 dma_pool_free(hpriv->sg_tbl_pool,
1265 pp->sg_tbl[tag],
1266 pp->sg_tbl_dma[tag]);
1267 pp->sg_tbl[tag] = NULL;
1268 }
da2fa9ba
ML		 1269 }
1270}
1271
05b308e1
BR		 1272/**
1273 * mv_port_start - Port specific init/start routine.
1274 * @ap: ATA channel to manipulate
1275 *
1276 * Allocate and point to DMA memory, init port private memory,
1277 * zero indices.
1278 *
1279 * LOCKING:
1280 * Inherited from caller.
1281 */
31961943
BR		 1282static int mv_port_start(struct ata_port *ap)
1283{
cca3974e
JG		 1284 struct device *dev = ap->host->dev;
1285 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1286 struct mv_port_priv *pp;
dde20207 1287 int tag;
31961943 1288
24dc5f33 1289 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1290 if (!pp)
24dc5f33 1291 return -ENOMEM;
da2fa9ba 1292 ap->private_data = pp;
31961943 1293
da2fa9ba
ML		 1294 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1295 if (!pp->crqb)
1296 return -ENOMEM;
1297 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1298
da2fa9ba
ML		 1299 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1300 if (!pp->crpb)
1301 goto out_port_free_dma_mem;
1302 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1303
eb73d558
ML		 1304 /*
1305 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1306 * For later hardware, we need one unique sg_tbl per NCQ tag.
1307 */
1308 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1309 if (tag == 0 || !IS_GEN_I(hpriv)) {
1310 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1311 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1312 if (!pp->sg_tbl[tag])
1313 goto out_port_free_dma_mem;
1314 } else {
1315 pp->sg_tbl[tag] = pp->sg_tbl[0];
1316 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1317 }
1318 }
31961943 1319 return 0;
da2fa9ba
ML		 1320
1321out_port_free_dma_mem:
1322 mv_port_free_dma_mem(ap);
1323 return -ENOMEM;
31961943
BR		 1324}
1325
05b308e1
BR		 1326/**
1327 * mv_port_stop - Port specific cleanup/stop routine.
1328 * @ap: ATA channel to manipulate
1329 *
1330 * Stop DMA, cleanup port memory.
1331 *
1332 * LOCKING:
cca3974e 1333 * This routine uses the host lock to protect the DMA stop.
05b308e1 1334 */
31961943
BR		 1335static void mv_port_stop(struct ata_port *ap)
1336{
e12bef50 1337 mv_stop_edma(ap);
da2fa9ba 1338 mv_port_free_dma_mem(ap);
31961943
BR		 1339}
1340
05b308e1
BR		 1341/**
1342 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1343 * @qc: queued command whose SG list to source from
1344 *
1345 * Populate the SG list and mark the last entry.
1346 *
1347 * LOCKING:
1348 * Inherited from caller.
1349 */
6c08772e 1350static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1351{
1352 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1353 struct scatterlist *sg;
3be6cbd7 1354 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1355 unsigned int si;
31961943 1356
eb73d558 1357 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1358 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1359 dma_addr_t addr = sg_dma_address(sg);
1360 u32 sg_len = sg_dma_len(sg);
22374677 1361
4007b493
OJ		 1362 while (sg_len) {
1363 u32 offset = addr & 0xffff;
1364 u32 len = sg_len;
22374677 1365
4007b493
OJ		 1366 if ((offset + sg_len > 0x10000))
1367 len = 0x10000 - offset;
1368
1369 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1370 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1371 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1372
1373 sg_len -= len;
1374 addr += len;
1375
3be6cbd7 1376 last_sg = mv_sg;
4007b493 1377 mv_sg++;
4007b493 1378 }
31961943 1379 }
3be6cbd7
JG		 1380
1381 if (likely(last_sg))
1382 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1383}
1384
5796d1c4 1385static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1386{
559eedad 1387 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1388 (last ? CRQB_CMD_LAST : 0);
559eedad 1389 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1390}
1391
05b308e1
BR		 1392/**
1393 * mv_qc_prep - Host specific command preparation.
1394 * @qc: queued command to prepare
1395 *
1396 * This routine simply redirects to the general purpose routine
1397 * if command is not DMA. Else, it handles prep of the CRQB
1398 * (command request block), does some sanity checking, and calls
1399 * the SG load routine.
1400 *
1401 * LOCKING:
1402 * Inherited from caller.
1403 */
31961943
BR		 1404static void mv_qc_prep(struct ata_queued_cmd *qc)
1405{
1406 struct ata_port *ap = qc->ap;
1407 struct mv_port_priv *pp = ap->private_data;
e1469874 1408 __le16 *cw;
31961943
BR		 1409 struct ata_taskfile *tf;
1410 u16 flags = 0;
a6432436 1411 unsigned in_index;
31961943 1412
138bfdd0
ML		 1413 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1414 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1415 return;
20f733e7 1416
31961943
BR		 1417 /* Fill in command request block
1418 */
e4e7b892 1419 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1420 flags |= CRQB_FLAG_READ;
beec7dbc 1421 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1422 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1423 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1424
bdd4ddde 1425 /* get current queue index from software */
fcfb1f77 1426 in_index = pp->req_idx;
a6432436
ML		 1427
1428 pp->crqb[in_index].sg_addr =
eb73d558 1429 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1430 pp->crqb[in_index].sg_addr_hi =
eb73d558 1431 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1432 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1433
a6432436 1434 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1435 tf = &qc->tf;
1436
1437 /* Sadly, the CRQB cannot accomodate all registers--there are
1438 * only 11 bytes...so we must pick and choose required
1439 * registers based on the command. So, we drop feature and
1440 * hob_feature for [RW] DMA commands, but they are needed for
1441 * NCQ. NCQ will drop hob_nsect.
20f733e7 1442 */
31961943
BR		 1443 switch (tf->command) {
1444 case ATA_CMD_READ:
1445 case ATA_CMD_READ_EXT:
1446 case ATA_CMD_WRITE:
1447 case ATA_CMD_WRITE_EXT:
c15d85c8 1448 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1449 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1450 break;
31961943
BR		 1451 case ATA_CMD_FPDMA_READ:
1452 case ATA_CMD_FPDMA_WRITE:
8b260248 1453 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1454 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1455 break;
31961943
BR		 1456 default:
1457 /* The only other commands EDMA supports in non-queued and
1458 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1459 * of which are defined/used by Linux. If we get here, this
1460 * driver needs work.
1461 *
1462 * FIXME: modify libata to give qc_prep a return value and
1463 * return error here.
1464 */
1465 BUG_ON(tf->command);
1466 break;
1467 }
1468 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1469 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1470 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1471 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1472 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1473 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1474 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1475 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1476 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1477
e4e7b892
JG		 1478 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1479 return;
1480 mv_fill_sg(qc);
1481}
1482
1483/**
1484 * mv_qc_prep_iie - Host specific command preparation.
1485 * @qc: queued command to prepare
1486 *
1487 * This routine simply redirects to the general purpose routine
1488 * if command is not DMA. Else, it handles prep of the CRQB
1489 * (command request block), does some sanity checking, and calls
1490 * the SG load routine.
1491 *
1492 * LOCKING:
1493 * Inherited from caller.
1494 */
1495static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1496{
1497 struct ata_port *ap = qc->ap;
1498 struct mv_port_priv *pp = ap->private_data;
1499 struct mv_crqb_iie *crqb;
1500 struct ata_taskfile *tf;
a6432436 1501 unsigned in_index;
e4e7b892
JG		 1502 u32 flags = 0;
1503
138bfdd0
ML		 1504 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1505 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1506 return;
1507
e12bef50 1508 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1509 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1510 flags |= CRQB_FLAG_READ;
1511
beec7dbc 1512 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1513 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1514 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1515 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1516
bdd4ddde 1517 /* get current queue index from software */
fcfb1f77 1518 in_index = pp->req_idx;
a6432436
ML		 1519
1520 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1521 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1522 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1523 crqb->flags = cpu_to_le32(flags);
1524
1525 tf = &qc->tf;
1526 crqb->ata_cmd[0] = cpu_to_le32(
1527 (tf->command << 16) |
1528 (tf->feature << 24)
1529 );
1530 crqb->ata_cmd[1] = cpu_to_le32(
1531 (tf->lbal << 0) |
1532 (tf->lbam << 8) |
1533 (tf->lbah << 16) |
1534 (tf->device << 24)
1535 );
1536 crqb->ata_cmd[2] = cpu_to_le32(
1537 (tf->hob_lbal << 0) |
1538 (tf->hob_lbam << 8) |
1539 (tf->hob_lbah << 16) |
1540 (tf->hob_feature << 24)
1541 );
1542 crqb->ata_cmd[3] = cpu_to_le32(
1543 (tf->nsect << 0) |
1544 (tf->hob_nsect << 8)
1545 );
1546
1547 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1548 return;
31961943
BR		 1549 mv_fill_sg(qc);
1550}
1551
05b308e1
BR		 1552/**
1553 * mv_qc_issue - Initiate a command to the host
1554 * @qc: queued command to start
1555 *
1556 * This routine simply redirects to the general purpose routine
1557 * if command is not DMA. Else, it sanity checks our local
1558 * caches of the request producer/consumer indices then enables
1559 * DMA and bumps the request producer index.
1560 *
1561 * LOCKING:
1562 * Inherited from caller.
1563 */
9a3d9eb0 1564static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1565{
c5d3e45a
JG		 1566 struct ata_port *ap = qc->ap;
1567 void __iomem *port_mmio = mv_ap_base(ap);
1568 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1569 u32 in_index;
31961943 1570
138bfdd0
ML		 1571 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1572 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1573 /*
1574 * We're about to send a non-EDMA capable command to the
31961943
BR		 1575 * port. Turn off EDMA so there won't be problems accessing
1576 * shadow block, etc registers.
1577 */
b562468c 1578 mv_stop_edma(ap);
e49856d8 1579 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1580 return ata_sff_qc_issue(qc);
31961943
BR		 1581 }
1582
72109168 1583 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1584
fcfb1f77
ML		 1585 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1586 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1587
1588 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1589 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1590 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1591
1592 return 0;
1593}
1594
8f767f8a
ML		 1595static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1596{
1597 struct mv_port_priv *pp = ap->private_data;
1598 struct ata_queued_cmd *qc;
1599
1600 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1601 return NULL;
1602 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1603 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1604 qc = NULL;
1605 return qc;
1606}
1607
29d187bb
ML		 1608static void mv_pmp_error_handler(struct ata_port *ap)
1609{
1610 unsigned int pmp, pmp_map;
1611 struct mv_port_priv *pp = ap->private_data;
1612
1613 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1614 /*
1615 * Perform NCQ error analysis on failed PMPs
1616 * before we freeze the port entirely.
1617 *
1618 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1619 */
1620 pmp_map = pp->delayed_eh_pmp_map;
1621 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1622 for (pmp = 0; pmp_map != 0; pmp++) {
1623 unsigned int this_pmp = (1 << pmp);
1624 if (pmp_map & this_pmp) {
1625 struct ata_link *link = &ap->pmp_link[pmp];
1626 pmp_map &= ~this_pmp;
1627 ata_eh_analyze_ncq_error(link);
1628 }
1629 }
1630 ata_port_freeze(ap);
1631 }
1632 sata_pmp_error_handler(ap);
1633}
1634
4c299ca3
ML		 1635static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1636{
1637 void __iomem *port_mmio = mv_ap_base(ap);
1638
1639 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1640}
1641
4c299ca3
ML		 1642static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1643{
1644 struct ata_eh_info *ehi;
1645 unsigned int pmp;
1646
1647 /*
1648 * Initialize EH info for PMPs which saw device errors
1649 */
1650 ehi = &ap->link.eh_info;
1651 for (pmp = 0; pmp_map != 0; pmp++) {
1652 unsigned int this_pmp = (1 << pmp);
1653 if (pmp_map & this_pmp) {
1654 struct ata_link *link = &ap->pmp_link[pmp];
1655
1656 pmp_map &= ~this_pmp;
1657 ehi = &link->eh_info;
1658 ata_ehi_clear_desc(ehi);
1659 ata_ehi_push_desc(ehi, "dev err");
1660 ehi->err_mask |= AC_ERR_DEV;
1661 ehi->action |= ATA_EH_RESET;
1662 ata_link_abort(link);
1663 }
1664 }
1665}
1666
1667static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1668{
1669 struct mv_port_priv *pp = ap->private_data;
1670 int failed_links;
1671 unsigned int old_map, new_map;
1672
1673 /*
1674 * Device error during FBS+NCQ operation:
1675 *
1676 * Set a port flag to prevent further I/O being enqueued.
1677 * Leave the EDMA running to drain outstanding commands from this port.
1678 * Perform the post-mortem/EH only when all responses are complete.
1679 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1680 */
1681 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1682 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1683 pp->delayed_eh_pmp_map = 0;
1684 }
1685 old_map = pp->delayed_eh_pmp_map;
1686 new_map = old_map | mv_get_err_pmp_map(ap);
1687
1688 if (old_map != new_map) {
1689 pp->delayed_eh_pmp_map = new_map;
1690 mv_pmp_eh_prep(ap, new_map & ~old_map);
1691 }
c46938cc 1692 failed_links = hweight16(new_map);
4c299ca3
ML		 1693
1694 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1695 "failed_links=%d nr_active_links=%d\n",
1696 __func__, pp->delayed_eh_pmp_map,
1697 ap->qc_active, failed_links,
1698 ap->nr_active_links);
1699
1700 if (ap->nr_active_links <= failed_links) {
1701 mv_process_crpb_entries(ap, pp);
1702 mv_stop_edma(ap);
1703 mv_eh_freeze(ap);
1704 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1705 return 1; /* handled */
1706 }
1707 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1708 return 1; /* handled */
1709}
1710
1711static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1712{
1713 /*
1714 * Possible future enhancement:
1715 *
1716 * FBS+non-NCQ operation is not yet implemented.
1717 * See related notes in mv_edma_cfg().
1718 *
1719 * Device error during FBS+non-NCQ operation:
1720 *
1721 * We need to snapshot the shadow registers for each failed command.
1722 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1723 */
1724 return 0; /* not handled */
1725}
1726
1727static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1728{
1729 struct mv_port_priv *pp = ap->private_data;
1730
1731 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1732 return 0; /* EDMA was not active: not handled */
1733 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1734 return 0; /* FBS was not active: not handled */
1735
1736 if (!(edma_err_cause & EDMA_ERR_DEV))
1737 return 0; /* non DEV error: not handled */
1738 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1739 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1740 return 0; /* other problems: not handled */
1741
1742 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1743 /*
1744 * EDMA should NOT have self-disabled for this case.
1745 * If it did, then something is wrong elsewhere,
1746 * and we cannot handle it here.
1747 */
1748 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1749 ata_port_printk(ap, KERN_WARNING,
1750 "%s: err_cause=0x%x pp_flags=0x%x\n",
1751 __func__, edma_err_cause, pp->pp_flags);
1752 return 0; /* not handled */
1753 }
1754 return mv_handle_fbs_ncq_dev_err(ap);
1755 } else {
1756 /*
1757 * EDMA should have self-disabled for this case.
1758 * If it did not, then something is wrong elsewhere,
1759 * and we cannot handle it here.
1760 */
1761 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1762 ata_port_printk(ap, KERN_WARNING,
1763 "%s: err_cause=0x%x pp_flags=0x%x\n",
1764 __func__, edma_err_cause, pp->pp_flags);
1765 return 0; /* not handled */
1766 }
1767 return mv_handle_fbs_non_ncq_dev_err(ap);
1768 }
1769 return 0; /* not handled */
1770}
1771
a9010329 1772static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1773{
8f767f8a 1774 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1775 char *when = "idle";
8f767f8a 1776
8f767f8a 1777 ata_ehi_clear_desc(ehi);
a9010329
ML		 1778 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1779 when = "disabled";
1780 } else if (edma_was_enabled) {
1781 when = "EDMA enabled";
8f767f8a
ML		 1782 } else {
1783 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1784 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1785 when = "polling";
8f767f8a 1786 }
a9010329 1787 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1788 ehi->err_mask |= AC_ERR_OTHER;
1789 ehi->action |= ATA_EH_RESET;
1790 ata_port_freeze(ap);
1791}
1792
05b308e1
BR		 1793/**
1794 * mv_err_intr - Handle error interrupts on the port
1795 * @ap: ATA channel to manipulate
8d07379d 1796 * @qc: affected command (non-NCQ), or NULL
05b308e1 1797 *
8d07379d
ML		 1798 * Most cases require a full reset of the chip's state machine,
1799 * which also performs a COMRESET.
1800 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1801 *
1802 * LOCKING:
1803 * Inherited from caller.
1804 */
37b9046a 1805static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1806{
1807 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 1808 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 1809 u32 fis_cause = 0;
bdd4ddde
JG		 1810 struct mv_port_priv *pp = ap->private_data;
1811 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1812 unsigned int action = 0, err_mask = 0;
9af5c9c9 1813 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1814 struct ata_queued_cmd *qc;
1815 int abort = 0;
20f733e7 1816
8d07379d 1817 /*
37b9046a 1818 * Read and clear the SError and err_cause bits.
e4006077
ML		 1819 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1820 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 1821 */
37b9046a
ML		 1822 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1823 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1824
bdd4ddde 1825 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 1826 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1827 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1828 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1829 }
8d07379d 1830 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1831
4c299ca3
ML		 1832 if (edma_err_cause & EDMA_ERR_DEV) {
1833 /*
1834 * Device errors during FIS-based switching operation
1835 * require special handling.
1836 */
1837 if (mv_handle_dev_err(ap, edma_err_cause))
1838 return;
1839 }
1840
37b9046a
ML		 1841 qc = mv_get_active_qc(ap);
1842 ata_ehi_clear_desc(ehi);
1843 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1844 edma_err_cause, pp->pp_flags);
e4006077 1845
c443c500 1846 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 1847 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 1848 if (fis_cause & SATA_FIS_IRQ_AN) {
1849 u32 ec = edma_err_cause &
1850 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1851 sata_async_notification(ap);
1852 if (!ec)
1853 return; /* Just an AN; no need for the nukes */
1854 ata_ehi_push_desc(ehi, "SDB notify");
1855 }
1856 }
bdd4ddde 1857 /*
352fab70 1858 * All generations share these EDMA error cause bits:
bdd4ddde 1859 */
37b9046a 1860 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1861 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1862 action |= ATA_EH_RESET;
1863 ata_ehi_push_desc(ehi, "dev error");
1864 }
bdd4ddde 1865 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1866 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1867 EDMA_ERR_INTRL_PAR)) {
1868 err_mask |= AC_ERR_ATA_BUS;
cf480626 1869 action |= ATA_EH_RESET;
b64bbc39 1870 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1871 }
1872 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1873 ata_ehi_hotplugged(ehi);
1874 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1875 "dev disconnect" : "dev connect");
cf480626 1876 action |= ATA_EH_RESET;
bdd4ddde
JG		 1877 }
1878
352fab70
ML		 1879 /*
1880 * Gen-I has a different SELF_DIS bit,
1881 * different FREEZE bits, and no SERR bit:
1882 */
ee9ccdf7 1883 if (IS_GEN_I(hpriv)) {
bdd4ddde 1884 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1885 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1886 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1887 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1888 }
1889 } else {
1890 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1891 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1892 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1893 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1894 }
bdd4ddde 1895 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1896 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1897 err_mask |= AC_ERR_ATA_BUS;
cf480626 1898 action |= ATA_EH_RESET;
bdd4ddde 1899 }
afb0edd9 1900 }
20f733e7 1901
bdd4ddde
JG		 1902 if (!err_mask) {
1903 err_mask = AC_ERR_OTHER;
cf480626 1904 action |= ATA_EH_RESET;
bdd4ddde
JG		 1905 }
1906
1907 ehi->serror |= serr;
1908 ehi->action |= action;
1909
1910 if (qc)
1911 qc->err_mask |= err_mask;
1912 else
1913 ehi->err_mask |= err_mask;
1914
37b9046a
ML		 1915 if (err_mask == AC_ERR_DEV) {
1916 /*
1917 * Cannot do ata_port_freeze() here,
1918 * because it would kill PIO access,
1919 * which is needed for further diagnosis.
1920 */
1921 mv_eh_freeze(ap);
1922 abort = 1;
1923 } else if (edma_err_cause & eh_freeze_mask) {
1924 /*
1925 * Note to self: ata_port_freeze() calls ata_port_abort()
1926 */
bdd4ddde 1927 ata_port_freeze(ap);
37b9046a
ML		 1928 } else {
1929 abort = 1;
1930 }
1931
1932 if (abort) {
1933 if (qc)
1934 ata_link_abort(qc->dev->link);
1935 else
1936 ata_port_abort(ap);
1937 }
bdd4ddde
JG		 1938}
1939
fcfb1f77
ML		 1940static void mv_process_crpb_response(struct ata_port *ap,
1941 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1942{
1943 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1944
1945 if (qc) {
1946 u8 ata_status;
1947 u16 edma_status = le16_to_cpu(response->flags);
1948 /*
1949 * edma_status from a response queue entry:
1950 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1951 * MSB is saved ATA status from command completion.
1952 */
1953 if (!ncq_enabled) {
1954 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1955 if (err_cause) {
1956 /*
1957 * Error will be seen/handled by mv_err_intr().
1958 * So do nothing at all here.
1959 */
1960 return;
1961 }
1962 }
1963 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 1964 if (!ac_err_mask(ata_status))
1965 ata_qc_complete(qc);
1966 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 1967 } else {
1968 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1969 __func__, tag);
1970 }
1971}
1972
1973static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1974{
1975 void __iomem *port_mmio = mv_ap_base(ap);
1976 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1977 u32 in_index;
bdd4ddde 1978 bool work_done = false;
fcfb1f77 1979 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1980
fcfb1f77 1981 /* Get the hardware queue position index */
bdd4ddde
JG		 1982 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1983 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1984
fcfb1f77
ML		 1985 /* Process new responses from since the last time we looked */
1986 while (in_index != pp->resp_idx) {
6c1153e0 1987 unsigned int tag;
fcfb1f77 1988 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1989
fcfb1f77 1990 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1991
fcfb1f77
ML		 1992 if (IS_GEN_I(hpriv)) {
1993 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1994 tag = ap->link.active_tag;
fcfb1f77
ML		 1995 } else {
1996 /* Gen II/IIE: get command tag from CRPB entry */
1997 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1998 }
fcfb1f77 1999 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2000 work_done = true;
bdd4ddde
JG		 2001 }
2002
352fab70 2003 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2004 if (work_done)
2005 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2006 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2007 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2008}
2009
a9010329
ML		 2010static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2011{
2012 struct mv_port_priv *pp;
2013 int edma_was_enabled;
2014
2015 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2016 mv_unexpected_intr(ap, 0);
2017 return;
2018 }
2019 /*
2020 * Grab a snapshot of the EDMA_EN flag setting,
2021 * so that we have a consistent view for this port,
2022 * even if something we call of our routines changes it.
2023 */
2024 pp = ap->private_data;
2025 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2026 /*
2027 * Process completed CRPB response(s) before other events.
2028 */
2029 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2030 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2031 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2032 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2033 }
2034 /*
2035 * Handle chip-reported errors, or continue on to handle PIO.
2036 */
2037 if (unlikely(port_cause & ERR_IRQ)) {
2038 mv_err_intr(ap);
2039 } else if (!edma_was_enabled) {
2040 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2041 if (qc)
2042 ata_sff_host_intr(ap, qc);
2043 else
2044 mv_unexpected_intr(ap, edma_was_enabled);
2045 }
2046}
2047
05b308e1
BR		 2048/**
2049 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2050 * @host: host specific structure
7368f919 2051 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2052 *
2053 * LOCKING:
2054 * Inherited from caller.
2055 */
7368f919 2056static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2057{
f351b2d6 2058 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2059 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2060 unsigned int handled = 0, port;
20f733e7 2061
a3718c1f 2062 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2063 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2064 unsigned int p, shift, hardport, port_cause;
2065
a3718c1f 2066 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2067 /*
eabd5eb1
ML		 2068 * Each hc within the host has its own hc_irq_cause register,
2069 * where the interrupting ports bits get ack'd.
a3718c1f 2070 */
eabd5eb1
ML		 2071 if (hardport == 0) { /* first port on this hc ? */
2072 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2073 u32 port_mask, ack_irqs;
2074 /*
2075 * Skip this entire hc if nothing pending for any ports
2076 */
2077 if (!hc_cause) {
2078 port += MV_PORTS_PER_HC - 1;
2079 continue;
2080 }
2081 /*
2082 * We don't need/want to read the hc_irq_cause register,
2083 * because doing so hurts performance, and
2084 * main_irq_cause already gives us everything we need.
2085 *
2086 * But we do have to *write* to the hc_irq_cause to ack
2087 * the ports that we are handling this time through.
2088 *
2089 * This requires that we create a bitmap for those
2090 * ports which interrupted us, and use that bitmap
2091 * to ack (only) those ports via hc_irq_cause.
2092 */
2093 ack_irqs = 0;
2094 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2095 if ((port + p) >= hpriv->n_ports)
2096 break;
2097 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2098 if (hc_cause & port_mask)
2099 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2100 }
a3718c1f 2101 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2102 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2103 handled = 1;
2104 }
8f767f8a 2105 /*
a9010329 2106 * Handle interrupts signalled for this port:
8f767f8a 2107 */
a9010329
ML		 2108 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2109 if (port_cause)
2110 mv_port_intr(ap, port_cause);
20f733e7 2111 }
a3718c1f 2112 return handled;
20f733e7
BR		 2113}
2114
a3718c1f 2115static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2116{
02a121da 2117 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2118 struct ata_port *ap;
2119 struct ata_queued_cmd *qc;
2120 struct ata_eh_info *ehi;
2121 unsigned int i, err_mask, printed = 0;
2122 u32 err_cause;
2123
02a121da 2124 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2125
2126 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2127 err_cause);
2128
2129 DPRINTK("All regs @ PCI error\n");
2130 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2131
02a121da 2132 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2133
2134 for (i = 0; i < host->n_ports; i++) {
2135 ap = host->ports[i];
936fd732 2136 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2137 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2138 ata_ehi_clear_desc(ehi);
2139 if (!printed++)
2140 ata_ehi_push_desc(ehi,
2141 "PCI err cause 0x%08x", err_cause);
2142 err_mask = AC_ERR_HOST_BUS;
cf480626 2143 ehi->action = ATA_EH_RESET;
9af5c9c9 2144 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2145 if (qc)
2146 qc->err_mask |= err_mask;
2147 else
2148 ehi->err_mask |= err_mask;
2149
2150 ata_port_freeze(ap);
2151 }
2152 }
a3718c1f 2153 return 1; /* handled */
bdd4ddde
JG		 2154}
2155
05b308e1 2156/**
c5d3e45a 2157 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2158 * @irq: unused
2159 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2160 *
2161 * Read the read only register to determine if any host
2162 * controllers have pending interrupts. If so, call lower level
2163 * routine to handle. Also check for PCI errors which are only
2164 * reported here.
2165 *
8b260248 2166 * LOCKING:
cca3974e 2167 * This routine holds the host lock while processing pending
05b308e1
BR		 2168 * interrupts.
2169 */
7d12e780 2170static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2171{
cca3974e 2172 struct ata_host *host = dev_instance;
f351b2d6 2173 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2174 unsigned int handled = 0;
7368f919 2175 u32 main_irq_cause, main_irq_mask;
20f733e7 2176
646a4da5 2177 spin_lock(&host->lock);
7368f919
ML		 2178 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2179 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 2180 /*
2181 * Deal with cases where we either have nothing pending, or have read
2182 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2183 */
7368f919
ML		 2184 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2185 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 2186 handled = mv_pci_error(host, hpriv->base);
2187 else
7368f919 2188 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 2189 }
cca3974e 2190 spin_unlock(&host->lock);
20f733e7
BR		 2191 return IRQ_RETVAL(handled);
2192}
2193
c9d39130
JG		 2194static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2195{
2196 unsigned int ofs;
2197
2198 switch (sc_reg_in) {
2199 case SCR_STATUS:
2200 case SCR_ERROR:
2201 case SCR_CONTROL:
2202 ofs = sc_reg_in * sizeof(u32);
2203 break;
2204 default:
2205 ofs = 0xffffffffU;
2206 break;
2207 }
2208 return ofs;
2209}
2210
da3dbb17 2211static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 2212{
f351b2d6
SB		 2213 struct mv_host_priv *hpriv = ap->host->private_data;
2214 void __iomem *mmio = hpriv->base;
0d5ff566 2215 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2216 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2217
da3dbb17
TH		 2218 if (ofs != 0xffffffffU) {
2219 *val = readl(addr + ofs);
2220 return 0;
2221 } else
2222 return -EINVAL;
c9d39130
JG		 2223}
2224
da3dbb17 2225static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 2226{
f351b2d6
SB		 2227 struct mv_host_priv *hpriv = ap->host->private_data;
2228 void __iomem *mmio = hpriv->base;
0d5ff566 2229 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2230 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2231
da3dbb17 2232 if (ofs != 0xffffffffU) {
0d5ff566 2233 writelfl(val, addr + ofs);
da3dbb17
TH		 2234 return 0;
2235 } else
2236 return -EINVAL;
c9d39130
JG		 2237}
2238
7bb3c529 2239static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2240{
7bb3c529 2241 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2242 int early_5080;
2243
44c10138 2244 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2245
2246 if (!early_5080) {
2247 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2248 tmp |= (1 << 0);
2249 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2250 }
2251
7bb3c529 2252 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2253}
2254
2255static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2256{
8e7decdb 2257 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2258}
2259
47c2b677 2260static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2261 void __iomem *mmio)
2262{
c9d39130
JG		 2263 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2264 u32 tmp;
2265
2266 tmp = readl(phy_mmio + MV5_PHY_MODE);
2267
2268 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2269 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2270}
2271
47c2b677 2272static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2273{
522479fb
JG		 2274 u32 tmp;
2275
8e7decdb 2276 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2277
2278 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2279
2280 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2281 tmp |= ~(1 << 0);
2282 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2283}
2284
2a47ce06
JG		 2285static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2286 unsigned int port)
bca1c4eb 2287{
c9d39130
JG		 2288 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2289 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2290 u32 tmp;
2291 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2292
2293 if (fix_apm_sq) {
8e7decdb 2294 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2295 tmp |= (1 << 19);
8e7decdb 2296 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2297
8e7decdb 2298 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2299 tmp &= ~0x3;
2300 tmp |= 0x1;
8e7decdb 2301 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2302 }
2303
2304 tmp = readl(phy_mmio + MV5_PHY_MODE);
2305 tmp &= ~mask;
2306 tmp |= hpriv->signal[port].pre;
2307 tmp |= hpriv->signal[port].amps;
2308 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2309}
2310
c9d39130
JG		 2311
2312#undef ZERO
2313#define ZERO(reg) writel(0, port_mmio + (reg))
2314static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2315 unsigned int port)
2316{
2317 void __iomem *port_mmio = mv_port_base(mmio, port);
2318
e12bef50 2319 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2320
2321 ZERO(0x028); /* command */
2322 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2323 ZERO(0x004); /* timer */
2324 ZERO(0x008); /* irq err cause */
2325 ZERO(0x00c); /* irq err mask */
2326 ZERO(0x010); /* rq bah */
2327 ZERO(0x014); /* rq inp */
2328 ZERO(0x018); /* rq outp */
2329 ZERO(0x01c); /* respq bah */
2330 ZERO(0x024); /* respq outp */
2331 ZERO(0x020); /* respq inp */
2332 ZERO(0x02c); /* test control */
8e7decdb 2333 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2334}
2335#undef ZERO
2336
2337#define ZERO(reg) writel(0, hc_mmio + (reg))
2338static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2339 unsigned int hc)
47c2b677 2340{
c9d39130
JG		 2341 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2342 u32 tmp;
2343
2344 ZERO(0x00c);
2345 ZERO(0x010);
2346 ZERO(0x014);
2347 ZERO(0x018);
2348
2349 tmp = readl(hc_mmio + 0x20);
2350 tmp &= 0x1c1c1c1c;
2351 tmp |= 0x03030303;
2352 writel(tmp, hc_mmio + 0x20);
2353}
2354#undef ZERO
2355
2356static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2357 unsigned int n_hc)
2358{
2359 unsigned int hc, port;
2360
2361 for (hc = 0; hc < n_hc; hc++) {
2362 for (port = 0; port < MV_PORTS_PER_HC; port++)
2363 mv5_reset_hc_port(hpriv, mmio,
2364 (hc * MV_PORTS_PER_HC) + port);
2365
2366 mv5_reset_one_hc(hpriv, mmio, hc);
2367 }
2368
2369 return 0;
47c2b677
JG		 2370}
2371
101ffae2
JG		 2372#undef ZERO
2373#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2374static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2375{
02a121da 2376 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2377 u32 tmp;
2378
8e7decdb 2379 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2380 tmp &= 0xff00ffff;
8e7decdb 2381 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2382
2383 ZERO(MV_PCI_DISC_TIMER);
2384 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2385 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
7368f919 2386 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2387 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2388 ZERO(hpriv->irq_cause_ofs);
2389 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2390 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2391 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2392 ZERO(MV_PCI_ERR_ATTRIBUTE);
2393 ZERO(MV_PCI_ERR_COMMAND);
2394}
2395#undef ZERO
2396
2397static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2398{
2399 u32 tmp;
2400
2401 mv5_reset_flash(hpriv, mmio);
2402
8e7decdb 2403 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2404 tmp &= 0x3;
2405 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2406 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2407}
2408
2409/**
2410 * mv6_reset_hc - Perform the 6xxx global soft reset
2411 * @mmio: base address of the HBA
2412 *
2413 * This routine only applies to 6xxx parts.
2414 *
2415 * LOCKING:
2416 * Inherited from caller.
2417 */
c9d39130
JG		 2418static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2419 unsigned int n_hc)
101ffae2
JG		 2420{
2421 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2422 int i, rc = 0;
2423 u32 t;
2424
2425 /* Following procedure defined in PCI "main command and status
2426 * register" table.
2427 */
2428 t = readl(reg);
2429 writel(t | STOP_PCI_MASTER, reg);
2430
2431 for (i = 0; i < 1000; i++) {
2432 udelay(1);
2433 t = readl(reg);
2dcb407e 2434 if (PCI_MASTER_EMPTY & t)
101ffae2 2435 break;
101ffae2
JG		 2436 }
2437 if (!(PCI_MASTER_EMPTY & t)) {
2438 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2439 rc = 1;
2440 goto done;
2441 }
2442
2443 /* set reset */
2444 i = 5;
2445 do {
2446 writel(t | GLOB_SFT_RST, reg);
2447 t = readl(reg);
2448 udelay(1);
2449 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2450
2451 if (!(GLOB_SFT_RST & t)) {
2452 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2453 rc = 1;
2454 goto done;
2455 }
2456
2457 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2458 i = 5;
2459 do {
2460 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2461 t = readl(reg);
2462 udelay(1);
2463 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2464
2465 if (GLOB_SFT_RST & t) {
2466 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2467 rc = 1;
2468 }
2469done:
2470 return rc;
2471}
2472
47c2b677 2473static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2474 void __iomem *mmio)
2475{
2476 void __iomem *port_mmio;
2477 u32 tmp;
2478
8e7decdb 2479 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2480 if ((tmp & (1 << 0)) == 0) {
47c2b677 2481 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2482 hpriv->signal[idx].pre = 0x1 << 5;
2483 return;
2484 }
2485
2486 port_mmio = mv_port_base(mmio, idx);
2487 tmp = readl(port_mmio + PHY_MODE2);
2488
2489 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2490 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2491}
2492
47c2b677 2493static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2494{
8e7decdb 2495 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2496}
2497
c9d39130 2498static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2499 unsigned int port)
bca1c4eb 2500{
c9d39130
JG		 2501 void __iomem *port_mmio = mv_port_base(mmio, port);
2502
bca1c4eb 2503 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2504 int fix_phy_mode2 =
2505 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2506 int fix_phy_mode4 =
47c2b677
JG		 2507 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2508 u32 m2, tmp;
2509
2510 if (fix_phy_mode2) {
2511 m2 = readl(port_mmio + PHY_MODE2);
2512 m2 &= ~(1 << 16);
2513 m2 |= (1 << 31);
2514 writel(m2, port_mmio + PHY_MODE2);
2515
2516 udelay(200);
2517
2518 m2 = readl(port_mmio + PHY_MODE2);
2519 m2 &= ~((1 << 16) | (1 << 31));
2520 writel(m2, port_mmio + PHY_MODE2);
2521
2522 udelay(200);
2523 }
2524
2525 /* who knows what this magic does */
2526 tmp = readl(port_mmio + PHY_MODE3);
2527 tmp &= ~0x7F800000;
2528 tmp |= 0x2A800000;
2529 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2530
2531 if (fix_phy_mode4) {
47c2b677 2532 u32 m4;
bca1c4eb
JG		 2533
2534 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2535
2536 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2537 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2538
e12bef50 2539 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2540 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2541
2542 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2543
2544 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2545 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2546 }
2547
2548 /* Revert values of pre-emphasis and signal amps to the saved ones */
2549 m2 = readl(port_mmio + PHY_MODE2);
2550
2551 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2552 m2 |= hpriv->signal[port].amps;
2553 m2 |= hpriv->signal[port].pre;
47c2b677 2554 m2 &= ~(1 << 16);
bca1c4eb 2555
e4e7b892
JG		 2556 /* according to mvSata 3.6.1, some IIE values are fixed */
2557 if (IS_GEN_IIE(hpriv)) {
2558 m2 &= ~0xC30FF01F;
2559 m2 |= 0x0000900F;
2560 }
2561
bca1c4eb
JG		 2562 writel(m2, port_mmio + PHY_MODE2);
2563}
2564
f351b2d6
SB		 2565/* TODO: use the generic LED interface to configure the SATA Presence */
2566/* & Acitivy LEDs on the board */
2567static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2568 void __iomem *mmio)
2569{
2570 return;
2571}
2572
2573static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2574 void __iomem *mmio)
2575{
2576 void __iomem *port_mmio;
2577 u32 tmp;
2578
2579 port_mmio = mv_port_base(mmio, idx);
2580 tmp = readl(port_mmio + PHY_MODE2);
2581
2582 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2583 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2584}
2585
2586#undef ZERO
2587#define ZERO(reg) writel(0, port_mmio + (reg))
2588static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2589 void __iomem *mmio, unsigned int port)
2590{
2591 void __iomem *port_mmio = mv_port_base(mmio, port);
2592
e12bef50 2593 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2594
2595 ZERO(0x028); /* command */
2596 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2597 ZERO(0x004); /* timer */
2598 ZERO(0x008); /* irq err cause */
2599 ZERO(0x00c); /* irq err mask */
2600 ZERO(0x010); /* rq bah */
2601 ZERO(0x014); /* rq inp */
2602 ZERO(0x018); /* rq outp */
2603 ZERO(0x01c); /* respq bah */
2604 ZERO(0x024); /* respq outp */
2605 ZERO(0x020); /* respq inp */
2606 ZERO(0x02c); /* test control */
8e7decdb 2607 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2608}
2609
2610#undef ZERO
2611
2612#define ZERO(reg) writel(0, hc_mmio + (reg))
2613static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2614 void __iomem *mmio)
2615{
2616 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2617
2618 ZERO(0x00c);
2619 ZERO(0x010);
2620 ZERO(0x014);
2621
2622}
2623
2624#undef ZERO
2625
2626static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2627 void __iomem *mmio, unsigned int n_hc)
2628{
2629 unsigned int port;
2630
2631 for (port = 0; port < hpriv->n_ports; port++)
2632 mv_soc_reset_hc_port(hpriv, mmio, port);
2633
2634 mv_soc_reset_one_hc(hpriv, mmio);
2635
2636 return 0;
2637}
2638
2639static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2640 void __iomem *mmio)
2641{
2642 return;
2643}
2644
2645static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2646{
2647 return;
2648}
2649
8e7decdb 2650static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2651{
8e7decdb 2652 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2653
8e7decdb 2654 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2655 if (want_gen2i)
8e7decdb
ML		 2656 ifcfg |= (1 << 7); /* enable gen2i speed */
2657 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2658}
2659
e12bef50 2660static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2661 unsigned int port_no)
2662{
2663 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2664
8e7decdb
ML		 2665 /*
2666 * The datasheet warns against setting EDMA_RESET when EDMA is active
2667 * (but doesn't say what the problem might be). So we first try
2668 * to disable the EDMA engine before doing the EDMA_RESET operation.
2669 */
0d8be5cb 2670 mv_stop_edma_engine(port_mmio);
8e7decdb 2671 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2672
b67a1064 2673 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2674 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2675 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2676 }
b67a1064 2677 /*
8e7decdb 2678 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2679 * link, and physical layers. It resets all SATA interface registers
2680 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2681 */
8e7decdb 2682 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2683 udelay(25); /* allow reset propagation */
c9d39130
JG		 2684 writelfl(0, port_mmio + EDMA_CMD_OFS);
2685
2686 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2687
ee9ccdf7 2688 if (IS_GEN_I(hpriv))
c9d39130
JG		 2689 mdelay(1);
2690}
2691
e49856d8 2692static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2693{
e49856d8
ML		 2694 if (sata_pmp_supported(ap)) {
2695 void __iomem *port_mmio = mv_ap_base(ap);
2696 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2697 int old = reg & 0xf;
22374677 2698
e49856d8
ML		 2699 if (old != pmp) {
2700 reg = (reg & ~0xf) | pmp;
2701 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2702 }
22374677 2703 }
20f733e7
BR		 2704}
2705
e49856d8
ML		 2706static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2707 unsigned long deadline)
22374677 2708{
e49856d8
ML		 2709 mv_pmp_select(link->ap, sata_srst_pmp(link));
2710 return sata_std_hardreset(link, class, deadline);
2711}
bdd4ddde 2712
e49856d8
ML		 2713static int mv_softreset(struct ata_link *link, unsigned int *class,
2714 unsigned long deadline)
2715{
2716 mv_pmp_select(link->ap, sata_srst_pmp(link));
2717 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2718}
2719
cc0680a5 2720static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2721 unsigned long deadline)
31961943 2722{
cc0680a5 2723 struct ata_port *ap = link->ap;
bdd4ddde 2724 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2725 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2726 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2727 int rc, attempts = 0, extra = 0;
2728 u32 sstatus;
2729 bool online;
31961943 2730
e12bef50 2731 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2732 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2733
0d8be5cb
ML		 2734 /* Workaround for errata FEr SATA#10 (part 2) */
2735 do {
17c5aab5
ML		 2736 const unsigned long *timing =
2737 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2738
17c5aab5
ML		 2739 rc = sata_link_hardreset(link, timing, deadline + extra,
2740 &online, NULL);
9dcffd99 2741 rc = online ? -EAGAIN : rc;
17c5aab5 2742 if (rc)
0d8be5cb 2743 return rc;
0d8be5cb
ML		 2744 sata_scr_read(link, SCR_STATUS, &sstatus);
2745 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2746 /* Force 1.5gb/s link speed and try again */
8e7decdb 2747 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2748 if (time_after(jiffies + HZ, deadline))
2749 extra = HZ; /* only extend it once, max */
2750 }
2751 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2752
17c5aab5 2753 return rc;
bdd4ddde
JG		 2754}
2755
bdd4ddde
JG		 2756static void mv_eh_freeze(struct ata_port *ap)
2757{
f351b2d6 2758 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2759 unsigned int shift, hardport, port = ap->port_no;
7368f919 2760 u32 main_irq_mask;
bdd4ddde
JG		 2761
2762 /* FIXME: handle coalescing completion events properly */
2763
1cfd19ae
ML		 2764 mv_stop_edma(ap);
2765 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2766
bdd4ddde 2767 /* disable assertion of portN err, done events */
7368f919
ML		 2768 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2769 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2770 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2771}
2772
2773static void mv_eh_thaw(struct ata_port *ap)
2774{
f351b2d6 2775 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2776 unsigned int shift, hardport, port = ap->port_no;
2777 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2778 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2779 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2780
2781 /* FIXME: handle coalescing completion events properly */
2782
1cfd19ae 2783 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2784
bdd4ddde
JG		 2785 /* clear EDMA errors on this port */
2786 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2787
2788 /* clear pending irq events */
2789 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2790 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2791 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2792
2793 /* enable assertion of portN err, done events */
7368f919
ML		 2794 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2795 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2796 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2797}
2798
05b308e1
BR		 2799/**
2800 * mv_port_init - Perform some early initialization on a single port.
2801 * @port: libata data structure storing shadow register addresses
2802 * @port_mmio: base address of the port
2803 *
2804 * Initialize shadow register mmio addresses, clear outstanding
2805 * interrupts on the port, and unmask interrupts for the future
2806 * start of the port.
2807 *
2808 * LOCKING:
2809 * Inherited from caller.
2810 */
31961943 2811static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2812{
0d5ff566 2813 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2814 unsigned serr_ofs;
2815
8b260248 2816 /* PIO related setup
31961943
BR		 2817 */
2818 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2819 port->error_addr =
31961943
BR		 2820 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2821 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2822 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2823 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2824 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2825 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2826 port->status_addr =
31961943
BR		 2827 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2828 /* special case: control/altstatus doesn't have ATA_REG_ address */
2829 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2830
2831 /* unused: */
8d9db2d2 2832 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2833
31961943
BR		 2834 /* Clear any currently outstanding port interrupt conditions */
2835 serr_ofs = mv_scr_offset(SCR_ERROR);
2836 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2837 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2838
646a4da5
ML		 2839 /* unmask all non-transient EDMA error interrupts */
2840 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2841
8b260248 2842 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2843 readl(port_mmio + EDMA_CFG_OFS),
2844 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2845 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2846}
2847
616d4a98
ML		 2848static unsigned int mv_in_pcix_mode(struct ata_host *host)
2849{
2850 struct mv_host_priv *hpriv = host->private_data;
2851 void __iomem *mmio = hpriv->base;
2852 u32 reg;
2853
2854 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2855 return 0; /* not PCI-X capable */
2856 reg = readl(mmio + MV_PCI_MODE_OFS);
2857 if ((reg & MV_PCI_MODE_MASK) == 0)
2858 return 0; /* conventional PCI mode */
2859 return 1; /* chip is in PCI-X mode */
2860}
2861
2862static int mv_pci_cut_through_okay(struct ata_host *host)
2863{
2864 struct mv_host_priv *hpriv = host->private_data;
2865 void __iomem *mmio = hpriv->base;
2866 u32 reg;
2867
2868 if (!mv_in_pcix_mode(host)) {
2869 reg = readl(mmio + PCI_COMMAND_OFS);
2870 if (reg & PCI_COMMAND_MRDTRIG)
2871 return 0; /* not okay */
2872 }
2873 return 1; /* okay */
2874}
2875
4447d351 2876static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2877{
4447d351
TH		 2878 struct pci_dev *pdev = to_pci_dev(host->dev);
2879 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2880 u32 hp_flags = hpriv->hp_flags;
2881
5796d1c4 2882 switch (board_idx) {
47c2b677
JG		 2883 case chip_5080:
2884 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2885 hp_flags |= MV_HP_GEN_I;
47c2b677 2886
44c10138 2887 switch (pdev->revision) {
47c2b677
JG		 2888 case 0x1:
2889 hp_flags |= MV_HP_ERRATA_50XXB0;
2890 break;
2891 case 0x3:
2892 hp_flags |= MV_HP_ERRATA_50XXB2;
2893 break;
2894 default:
2895 dev_printk(KERN_WARNING, &pdev->dev,
2896 "Applying 50XXB2 workarounds to unknown rev\n");
2897 hp_flags |= MV_HP_ERRATA_50XXB2;
2898 break;
2899 }
2900 break;
2901
bca1c4eb
JG		 2902 case chip_504x:
2903 case chip_508x:
47c2b677 2904 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2905 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2906
44c10138 2907 switch (pdev->revision) {
47c2b677
JG		 2908 case 0x0:
2909 hp_flags |= MV_HP_ERRATA_50XXB0;
2910 break;
2911 case 0x3:
2912 hp_flags |= MV_HP_ERRATA_50XXB2;
2913 break;
2914 default:
2915 dev_printk(KERN_WARNING, &pdev->dev,
2916 "Applying B2 workarounds to unknown rev\n");
2917 hp_flags |= MV_HP_ERRATA_50XXB2;
2918 break;
bca1c4eb
JG		 2919 }
2920 break;
2921
2922 case chip_604x:
2923 case chip_608x:
47c2b677 2924 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2925 hp_flags |= MV_HP_GEN_II;
47c2b677 2926
44c10138 2927 switch (pdev->revision) {
47c2b677
JG		 2928 case 0x7:
2929 hp_flags |= MV_HP_ERRATA_60X1B2;
2930 break;
2931 case 0x9:
2932 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2933 break;
2934 default:
2935 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2936 "Applying B2 workarounds to unknown rev\n");
2937 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2938 break;
2939 }
2940 break;
2941
e4e7b892 2942 case chip_7042:
616d4a98 2943 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2944 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2945 (pdev->device == 0x2300 || pdev->device == 0x2310))
2946 {
4e520033
ML		 2947 /*
2948 * Highpoint RocketRAID PCIe 23xx series cards:
2949 *
2950 * Unconfigured drives are treated as "Legacy"
2951 * by the BIOS, and it overwrites sector 8 with
2952 * a "Lgcy" metadata block prior to Linux boot.
2953 *
2954 * Configured drives (RAID or JBOD) leave sector 8
2955 * alone, but instead overwrite a high numbered
2956 * sector for the RAID metadata. This sector can
2957 * be determined exactly, by truncating the physical
2958 * drive capacity to a nice even GB value.
2959 *
2960 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2961 *
2962 * Warn the user, lest they think we're just buggy.
2963 */
2964 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2965 " BIOS CORRUPTS DATA on all attached drives,"
2966 " regardless of if/how they are configured."
2967 " BEWARE!\n");
2968 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2969 " use sectors 8-9 on \"Legacy\" drives,"
2970 " and avoid the final two gigabytes on"
2971 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2972 }
8e7decdb 2973 /* drop through */
e4e7b892
JG		 2974 case chip_6042:
2975 hpriv->ops = &mv6xxx_ops;
e4e7b892 2976 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2977 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2978 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2979
44c10138 2980 switch (pdev->revision) {
e4e7b892
JG		 2981 case 0x0:
2982 hp_flags |= MV_HP_ERRATA_XX42A0;
2983 break;
2984 case 0x1:
2985 hp_flags |= MV_HP_ERRATA_60X1C0;
2986 break;
2987 default:
2988 dev_printk(KERN_WARNING, &pdev->dev,
2989 "Applying 60X1C0 workarounds to unknown rev\n");
2990 hp_flags |= MV_HP_ERRATA_60X1C0;
2991 break;
2992 }
2993 break;
f351b2d6
SB		 2994 case chip_soc:
2995 hpriv->ops = &mv_soc_ops;
2996 hp_flags |= MV_HP_ERRATA_60X1C0;
2997 break;
e4e7b892 2998
bca1c4eb 2999 default:
f351b2d6 3000 dev_printk(KERN_ERR, host->dev,
5796d1c4 3001 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3002 return 1;
3003 }
3004
3005 hpriv->hp_flags = hp_flags;
02a121da
ML		 3006 if (hp_flags & MV_HP_PCIE) {
3007 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3008 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3009 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3010 } else {
3011 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3012 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3013 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3014 }
bca1c4eb
JG		 3015
3016 return 0;
3017}
3018
05b308e1 3019/**
47c2b677 3020 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3021 * @host: ATA host to initialize
3022 * @board_idx: controller index
05b308e1
BR		 3023 *
3024 * If possible, do an early global reset of the host. Then do
3025 * our port init and clear/unmask all/relevant host interrupts.
3026 *
3027 * LOCKING:
3028 * Inherited from caller.
3029 */
4447d351 3030static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3031{
3032 int rc = 0, n_hc, port, hc;
4447d351 3033 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3034 void __iomem *mmio = hpriv->base;
47c2b677 3035
4447d351 3036 rc = mv_chip_id(host, board_idx);
bca1c4eb 3037 if (rc)
352fab70 3038 goto done;
f351b2d6
SB		 3039
3040 if (HAS_PCI(host)) {
7368f919
ML		 3041 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3042 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3043 } else {
7368f919
ML		 3044 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3045 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3046 }
352fab70
ML		 3047
3048 /* global interrupt mask: 0 == mask everything */
7368f919 3049 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 3050
4447d351 3051 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3052
4447d351 3053 for (port = 0; port < host->n_ports; port++)
47c2b677 3054 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3055
c9d39130 3056 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3057 if (rc)
20f733e7 3058 goto done;
20f733e7 3059
522479fb 3060 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3061 hpriv->ops->reset_bus(host, mmio);
47c2b677 3062 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3063
4447d351 3064 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3065 struct ata_port *ap = host->ports[port];
2a47ce06 3066 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3067
3068 mv_port_init(&ap->ioaddr, port_mmio);
3069
7bb3c529 3070#ifdef CONFIG_PCI
f351b2d6
SB		 3071 if (HAS_PCI(host)) {
3072 unsigned int offset = port_mmio - mmio;
3073 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3074 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3075 }
7bb3c529 3076#endif
20f733e7
BR		 3077 }
3078
3079 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3080 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3081
3082 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3083 "(before clear)=0x%08x\n", hc,
3084 readl(hc_mmio + HC_CFG_OFS),
3085 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3086
3087 /* Clear any currently outstanding hc interrupt conditions */
3088 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3089 }
3090
f351b2d6
SB		 3091 if (HAS_PCI(host)) {
3092 /* Clear any currently outstanding host interrupt conditions */
3093 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3094
f351b2d6
SB		 3095 /* and unmask interrupt generation for host regs */
3096 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2
ML		 3097
3098 /*
3099 * enable only global host interrupts for now.
3100 * The per-port interrupts get done later as ports are set up.
3101 */
3102 writelfl(PCI_ERR, hpriv->main_irq_mask_addr);
f351b2d6
SB		 3103 }
3104done:
3105 return rc;
3106}
fb621e2f 3107
fbf14e2f
BB		 3108static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3109{
3110 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3111 MV_CRQB_Q_SZ, 0);
3112 if (!hpriv->crqb_pool)
3113 return -ENOMEM;
3114
3115 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3116 MV_CRPB_Q_SZ, 0);
3117 if (!hpriv->crpb_pool)
3118 return -ENOMEM;
3119
3120 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3121 MV_SG_TBL_SZ, 0);
3122 if (!hpriv->sg_tbl_pool)
3123 return -ENOMEM;
3124
3125 return 0;
3126}
3127
15a32632
LB		 3128static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3129 struct mbus_dram_target_info *dram)
3130{
3131 int i;
3132
3133 for (i = 0; i < 4; i++) {
3134 writel(0, hpriv->base + WINDOW_CTRL(i));
3135 writel(0, hpriv->base + WINDOW_BASE(i));
3136 }
3137
3138 for (i = 0; i < dram->num_cs; i++) {
3139 struct mbus_dram_window *cs = dram->cs + i;
3140
3141 writel(((cs->size - 1) & 0xffff0000) |
3142 (cs->mbus_attr << 8) |
3143 (dram->mbus_dram_target_id << 4) | 1,
3144 hpriv->base + WINDOW_CTRL(i));
3145 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3146 }
3147}
3148
f351b2d6
SB		 3149/**
3150 * mv_platform_probe - handle a positive probe of an soc Marvell
3151 * host
3152 * @pdev: platform device found
3153 *
3154 * LOCKING:
3155 * Inherited from caller.
3156 */
3157static int mv_platform_probe(struct platform_device *pdev)
3158{
3159 static int printed_version;
3160 const struct mv_sata_platform_data *mv_platform_data;
3161 const struct ata_port_info *ppi[] =
3162 { &mv_port_info[chip_soc], NULL };
3163 struct ata_host *host;
3164 struct mv_host_priv *hpriv;
3165 struct resource *res;
3166 int n_ports, rc;
20f733e7 3167
f351b2d6
SB		 3168 if (!printed_version++)
3169 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3170
f351b2d6
SB		 3171 /*
3172 * Simple resource validation ..
3173 */
3174 if (unlikely(pdev->num_resources != 2)) {
3175 dev_err(&pdev->dev, "invalid number of resources\n");
3176 return -EINVAL;
3177 }
3178
3179 /*
3180 * Get the register base first
3181 */
3182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3183 if (res == NULL)
3184 return -EINVAL;
3185
3186 /* allocate host */
3187 mv_platform_data = pdev->dev.platform_data;
3188 n_ports = mv_platform_data->n_ports;
3189
3190 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3191 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3192
3193 if (!host || !hpriv)
3194 return -ENOMEM;
3195 host->private_data = hpriv;
3196 hpriv->n_ports = n_ports;
3197
3198 host->iomap = NULL;
f1cb0ea1
SB		 3199 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3200 res->end - res->start + 1);
f351b2d6
SB		 3201 hpriv->base -= MV_SATAHC0_REG_BASE;
3202
15a32632
LB		 3203 /*
3204 * (Re-)program MBUS remapping windows if we are asked to.
3205 */
3206 if (mv_platform_data->dram != NULL)
3207 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3208
fbf14e2f
BB		 3209 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3210 if (rc)
3211 return rc;
3212
f351b2d6
SB		 3213 /* initialize adapter */
3214 rc = mv_init_host(host, chip_soc);
3215 if (rc)
3216 return rc;
3217
3218 dev_printk(KERN_INFO, &pdev->dev,
3219 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3220 host->n_ports);
3221
3222 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3223 IRQF_SHARED, &mv6_sht);
3224}
3225
3226/*
3227 *
3228 * mv_platform_remove - unplug a platform interface
3229 * @pdev: platform device
3230 *
3231 * A platform bus SATA device has been unplugged. Perform the needed
3232 * cleanup. Also called on module unload for any active devices.
3233 */
3234static int __devexit mv_platform_remove(struct platform_device *pdev)
3235{
3236 struct device *dev = &pdev->dev;
3237 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3238
3239 ata_host_detach(host);
f351b2d6 3240 return 0;
20f733e7
BR		 3241}
3242
f351b2d6
SB		 3243static struct platform_driver mv_platform_driver = {
3244 .probe = mv_platform_probe,
3245 .remove = __devexit_p(mv_platform_remove),
3246 .driver = {
3247 .name = DRV_NAME,
3248 .owner = THIS_MODULE,
3249 },
3250};
3251
3252
7bb3c529 3253#ifdef CONFIG_PCI
f351b2d6
SB		 3254static int mv_pci_init_one(struct pci_dev *pdev,
3255 const struct pci_device_id *ent);
3256
7bb3c529
SB		 3257
3258static struct pci_driver mv_pci_driver = {
3259 .name = DRV_NAME,
3260 .id_table = mv_pci_tbl,
f351b2d6 3261 .probe = mv_pci_init_one,
7bb3c529
SB		 3262 .remove = ata_pci_remove_one,
3263};
3264
3265/*
3266 * module options
3267 */
3268static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3269
3270
3271/* move to PCI layer or libata core? */
3272static int pci_go_64(struct pci_dev *pdev)
3273{
3274 int rc;
3275
3276 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3277 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3278 if (rc) {
3279 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3280 if (rc) {
3281 dev_printk(KERN_ERR, &pdev->dev,
3282 "64-bit DMA enable failed\n");
3283 return rc;
3284 }
3285 }
3286 } else {
3287 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3288 if (rc) {
3289 dev_printk(KERN_ERR, &pdev->dev,
3290 "32-bit DMA enable failed\n");
3291 return rc;
3292 }
3293 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3294 if (rc) {
3295 dev_printk(KERN_ERR, &pdev->dev,
3296 "32-bit consistent DMA enable failed\n");
3297 return rc;
3298 }
3299 }
3300
3301 return rc;
3302}
3303
05b308e1
BR		 3304/**
3305 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3306 * @host: ATA host to print info about
05b308e1
BR		 3307 *
3308 * FIXME: complete this.
3309 *
3310 * LOCKING:
3311 * Inherited from caller.
3312 */
4447d351 3313static void mv_print_info(struct ata_host *host)
31961943 3314{
4447d351
TH		 3315 struct pci_dev *pdev = to_pci_dev(host->dev);
3316 struct mv_host_priv *hpriv = host->private_data;
44c10138 3317 u8 scc;
c1e4fe71 3318 const char *scc_s, *gen;
31961943
BR		 3319
3320 /* Use this to determine the HW stepping of the chip so we know
3321 * what errata to workaround
3322 */
31961943
BR		 3323 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3324 if (scc == 0)
3325 scc_s = "SCSI";
3326 else if (scc == 0x01)
3327 scc_s = "RAID";
3328 else
c1e4fe71
JG		 3329 scc_s = "?";
3330
3331 if (IS_GEN_I(hpriv))
3332 gen = "I";
3333 else if (IS_GEN_II(hpriv))
3334 gen = "II";
3335 else if (IS_GEN_IIE(hpriv))
3336 gen = "IIE";
3337 else
3338 gen = "?";
31961943 3339
a9524a76 3340 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3341 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3342 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3343 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3344}
3345
05b308e1 3346/**
f351b2d6 3347 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3348 * @pdev: PCI device found
3349 * @ent: PCI device ID entry for the matched host
3350 *
3351 * LOCKING:
3352 * Inherited from caller.
3353 */
f351b2d6
SB		 3354static int mv_pci_init_one(struct pci_dev *pdev,
3355 const struct pci_device_id *ent)
20f733e7 3356{
2dcb407e 3357 static int printed_version;
20f733e7 3358 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3359 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3360 struct ata_host *host;
3361 struct mv_host_priv *hpriv;
3362 int n_ports, rc;
20f733e7 3363
a9524a76
JG		 3364 if (!printed_version++)
3365 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3366
4447d351
TH		 3367 /* allocate host */
3368 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3369
3370 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3371 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3372 if (!host || !hpriv)
3373 return -ENOMEM;
3374 host->private_data = hpriv;
f351b2d6 3375 hpriv->n_ports = n_ports;
4447d351
TH		 3376
3377 /* acquire resources */
24dc5f33
TH		 3378 rc = pcim_enable_device(pdev);
3379 if (rc)
20f733e7 3380 return rc;
20f733e7 3381
0d5ff566
TH		 3382 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3383 if (rc == -EBUSY)
24dc5f33 3384 pcim_pin_device(pdev);
0d5ff566 3385 if (rc)
24dc5f33 3386 return rc;
4447d351 3387 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3388 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3389
d88184fb
JG		 3390 rc = pci_go_64(pdev);
3391 if (rc)
3392 return rc;
3393
da2fa9ba
ML		 3394 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3395 if (rc)
3396 return rc;
3397
20f733e7 3398 /* initialize adapter */
4447d351 3399 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3400 if (rc)
3401 return rc;
20f733e7 3402
31961943 3403 /* Enable interrupts */
6a59dcf8 3404 if (msi && pci_enable_msi(pdev))
31961943 3405 pci_intx(pdev, 1);
20f733e7 3406
31961943 3407 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3408 mv_print_info(host);
20f733e7 3409
4447d351 3410 pci_set_master(pdev);
ea8b4db9 3411 pci_try_set_mwi(pdev);
4447d351 3412 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3413 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3414}
7bb3c529 3415#endif
20f733e7 3416
f351b2d6
SB		 3417static int mv_platform_probe(struct platform_device *pdev);
3418static int __devexit mv_platform_remove(struct platform_device *pdev);
3419
20f733e7
BR		 3420static int __init mv_init(void)
3421{
7bb3c529
SB		 3422 int rc = -ENODEV;
3423#ifdef CONFIG_PCI
3424 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3425 if (rc < 0)
3426 return rc;
3427#endif
3428 rc = platform_driver_register(&mv_platform_driver);
3429
3430#ifdef CONFIG_PCI
3431 if (rc < 0)
3432 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3433#endif
3434 return rc;
20f733e7
BR		 3435}
3436
3437static void __exit mv_exit(void)
3438{
7bb3c529 3439#ifdef CONFIG_PCI
20f733e7 3440 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3441#endif
f351b2d6 3442 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3443}
3444
3445MODULE_AUTHOR("Brett Russ");
3446MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3447MODULE_LICENSE("GPL");
3448MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3449MODULE_VERSION(DRV_VERSION);
17c5aab5 3450MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3451
7bb3c529 3452#ifdef CONFIG_PCI
ddef9bb3
JG		 3453module_param(msi, int, 0444);
3454MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3455#endif
ddef9bb3 3456
20f733e7
BR		 3457module_init(mv_init);
3458module_exit(mv_exit);
Linux kernel - Deliverables
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