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sata_mv pci features
[deliverable/linux.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
1fd2e1c2 74#define DRV_VERSION "1.20"
20f733e7
BR		 75
76enum {
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
84
85 MV_PCI_REG_BASE = 0,
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92
20f733e7 93 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
31961943
BR		 103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 112 MV_MAX_SG_CT = 256,
31961943 113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 114
352fab70 115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 116 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 124 /* SoC integrated controllers, no PCI interface */
e12bef50 125 MV_FLAG_SOC = (1 << 28),
7bb3c529 126
c5d3e45a 127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
47c2b677 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 131
31961943
BR		 132 CRQB_FLAG_READ = (1 << 0),
133 CRQB_TAG_SHIFT = 1,
c5d3e45a 134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
20f733e7
BR		 147 /* PCI interface registers */
148
31961943 149 PCI_COMMAND_OFS = 0xc00,
8e7decdb 150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 151
20f733e7
BR		 152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
156
8e7decdb
ML		 157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
159
522479fb
JG		 160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
169
02a121da
ML		 170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173
02a121da
ML		 174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 177
7368f919
ML		 178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 PCI_ERR = (1 << 18),
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
8b260248 199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
f9f7fe01 200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
20f733e7
BR		 201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
202 HC_MAIN_RSVD),
fb621e2f
JG		 203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
204 HC_MAIN_RSVD_5),
f351b2d6 205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
20f733e7
BR		 206
207 /* SATAHC registers */
208 HC_CFG_OFS = 0,
209
210 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 213 DEV_IRQ = (1 << 8), /* shift by port # */
214
215 /* Shadow block registers */
31961943
BR		 216 SHD_BLK_OFS = 0x100,
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 218
219 /* SATA registers */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
0c58912e 222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
17c5aab5 223
e12bef50 224 LTMODE_OFS = 0x30c,
17c5aab5
ML		 225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
47c2b677 227 PHY_MODE3 = 0x310,
bca1c4eb
JG		 228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
e12bef50 230 SATA_IFCTL_OFS = 0x344,
8e7decdb 231 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 234
8e7decdb
ML		 235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 238
c9d39130 239 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 243
244 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
0c58912e
ML		 248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 272
6c1153e0 273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
6c1153e0 279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 280
6c1153e0 281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
6c1153e0 288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 289
6c1153e0 290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 297 EDMA_ERR_LNK_CTRL_TX,
646a4da5 298
bdd4ddde
JG		 299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
6c1153e0 305 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
e12bef50 313
bdd4ddde
JG		 314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
6c1153e0 321 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
20f733e7 325
31961943
BR		 326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
0ea9e179
JG		 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 345
8e7decdb
ML		 346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 350
352fab70
ML		 351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
31961943
BR		 353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 359 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 365
31961943 366 /* Port private flags (pp_flags) */
0ea9e179 367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
20f733e7
BR		 369};
370
ee9ccdf7
JG		 371#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
372#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 373#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 374#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 375#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 376
15a32632
LB		 377#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
378#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
379
095fec88 380enum {
baf14aa1
JG		 381 /* DMA boundary 0xffff is required by the s/g splitting
382 * we need on /length/ in mv_fill-sg().
383 */
384 MV_DMA_BOUNDARY = 0xffffU,
095fec88 385
0ea9e179
JG		 386 /* mask of register bits containing lower 32 bits
387 * of EDMA request queue DMA address
388 */
095fec88
JG		 389 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
390
0ea9e179 391 /* ditto, for response queue */
095fec88
JG		 392 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
393};
394
522479fb
JG		 395enum chip_type {
396 chip_504x,
397 chip_508x,
398 chip_5080,
399 chip_604x,
400 chip_608x,
e4e7b892
JG		 401 chip_6042,
402 chip_7042,
f351b2d6 403 chip_soc,
522479fb
JG		 404};
405
31961943
BR		 406/* Command ReQuest Block: 32B */
407struct mv_crqb {
e1469874
ML		 408 __le32 sg_addr;
409 __le32 sg_addr_hi;
410 __le16 ctrl_flags;
411 __le16 ata_cmd[11];
31961943 412};
20f733e7 413
e4e7b892 414struct mv_crqb_iie {
e1469874
ML		 415 __le32 addr;
416 __le32 addr_hi;
417 __le32 flags;
418 __le32 len;
419 __le32 ata_cmd[4];
e4e7b892
JG		 420};
421
31961943
BR		 422/* Command ResPonse Block: 8B */
423struct mv_crpb {
e1469874
ML		 424 __le16 id;
425 __le16 flags;
426 __le32 tmstmp;
20f733e7
BR		 427};
428
31961943
BR		 429/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
430struct mv_sg {
e1469874
ML		 431 __le32 addr;
432 __le32 flags_size;
433 __le32 addr_hi;
434 __le32 reserved;
31961943 435};
20f733e7 436
31961943
BR		 437struct mv_port_priv {
438 struct mv_crqb *crqb;
439 dma_addr_t crqb_dma;
440 struct mv_crpb *crpb;
441 dma_addr_t crpb_dma;
eb73d558
ML		 442 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
443 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 444
445 unsigned int req_idx;
446 unsigned int resp_idx;
447
31961943
BR		 448 u32 pp_flags;
449};
450
bca1c4eb
JG		 451struct mv_port_signal {
452 u32 amps;
453 u32 pre;
454};
455
02a121da
ML		 456struct mv_host_priv {
457 u32 hp_flags;
458 struct mv_port_signal signal[8];
459 const struct mv_hw_ops *ops;
f351b2d6
SB		 460 int n_ports;
461 void __iomem *base;
7368f919
ML		 462 void __iomem *main_irq_cause_addr;
463 void __iomem *main_irq_mask_addr;
02a121da
ML		 464 u32 irq_cause_ofs;
465 u32 irq_mask_ofs;
466 u32 unmask_all_irqs;
da2fa9ba
ML		 467 /*
468 * These consistent DMA memory pools give us guaranteed
469 * alignment for hardware-accessed data structures,
470 * and less memory waste in accomplishing the alignment.
471 */
472 struct dma_pool *crqb_pool;
473 struct dma_pool *crpb_pool;
474 struct dma_pool *sg_tbl_pool;
02a121da
ML		 475};
476
47c2b677 477struct mv_hw_ops {
2a47ce06
JG		 478 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
479 unsigned int port);
47c2b677
JG		 480 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
481 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
482 void __iomem *mmio);
c9d39130
JG		 483 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
484 unsigned int n_hc);
522479fb 485 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 486 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 487};
488
da3dbb17
TH		 489static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
490static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
491static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
492static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 493static int mv_port_start(struct ata_port *ap);
494static void mv_port_stop(struct ata_port *ap);
495static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 496static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 497static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 498static int mv_hardreset(struct ata_link *link, unsigned int *class,
499 unsigned long deadline);
bdd4ddde
JG		 500static void mv_eh_freeze(struct ata_port *ap);
501static void mv_eh_thaw(struct ata_port *ap);
f273827e 502static void mv6_dev_config(struct ata_device *dev);
20f733e7 503
2a47ce06
JG		 504static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
505 unsigned int port);
47c2b677
JG		 506static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
507static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
508 void __iomem *mmio);
c9d39130
JG		 509static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
510 unsigned int n_hc);
522479fb 511static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 512static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 513
2a47ce06
JG		 514static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
515 unsigned int port);
47c2b677
JG		 516static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
517static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
518 void __iomem *mmio);
c9d39130
JG		 519static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
520 unsigned int n_hc);
522479fb 521static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 522static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
523 void __iomem *mmio);
524static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
525 void __iomem *mmio);
526static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
527 void __iomem *mmio, unsigned int n_hc);
528static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
529 void __iomem *mmio);
530static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 531static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 532static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 533 unsigned int port_no);
e12bef50 534static int mv_stop_edma(struct ata_port *ap);
b562468c 535static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 536static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 537
e49856d8
ML		 538static void mv_pmp_select(struct ata_port *ap, int pmp);
539static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
540 unsigned long deadline);
541static int mv_softreset(struct ata_link *link, unsigned int *class,
542 unsigned long deadline);
47c2b677 543
eb73d558
ML		 544/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
545 * because we have to allow room for worst case splitting of
546 * PRDs for 64K boundaries in mv_fill_sg().
547 */
c5d3e45a 548static struct scsi_host_template mv5_sht = {
68d1d07b 549 ATA_BASE_SHT(DRV_NAME),
baf14aa1 550 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 551 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 552};
553
554static struct scsi_host_template mv6_sht = {
68d1d07b 555 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 556 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 557 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 558 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 559};
560
029cfd6b
TH		 561static struct ata_port_operations mv5_ops = {
562 .inherits = &ata_sff_port_ops,
c9d39130
JG		 563
564 .qc_prep = mv_qc_prep,
565 .qc_issue = mv_qc_issue,
c9d39130 566
bdd4ddde
JG		 567 .freeze = mv_eh_freeze,
568 .thaw = mv_eh_thaw,
a1efdaba 569 .hardreset = mv_hardreset,
a1efdaba 570 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 571 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 572
c9d39130
JG		 573 .scr_read = mv5_scr_read,
574 .scr_write = mv5_scr_write,
575
576 .port_start = mv_port_start,
577 .port_stop = mv_port_stop,
c9d39130
JG		 578};
579
029cfd6b
TH		 580static struct ata_port_operations mv6_ops = {
581 .inherits = &mv5_ops,
e49856d8 582 .qc_defer = sata_pmp_qc_defer_cmd_switch,
f273827e 583 .dev_config = mv6_dev_config,
20f733e7
BR		 584 .scr_read = mv_scr_read,
585 .scr_write = mv_scr_write,
586
e49856d8
ML		 587 .pmp_hardreset = mv_pmp_hardreset,
588 .pmp_softreset = mv_softreset,
589 .softreset = mv_softreset,
590 .error_handler = sata_pmp_error_handler,
20f733e7
BR		 591};
592
029cfd6b
TH		 593static struct ata_port_operations mv_iie_ops = {
594 .inherits = &mv6_ops,
e49856d8 595 .qc_defer = ata_std_qc_defer, /* FIS-based switching */
029cfd6b 596 .dev_config = ATA_OP_NULL,
e4e7b892 597 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 598};
599
98ac62de 600static const struct ata_port_info mv_port_info[] = {
20f733e7 601 { /* chip_504x */
cca3974e 602 .flags = MV_COMMON_FLAGS,
31961943 603 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 604 .udma_mask = ATA_UDMA6,
c9d39130 605 .port_ops = &mv5_ops,
20f733e7
BR		 606 },
607 { /* chip_508x */
c5d3e45a 608 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 609 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 610 .udma_mask = ATA_UDMA6,
c9d39130 611 .port_ops = &mv5_ops,
20f733e7 612 },
47c2b677 613 { /* chip_5080 */
c5d3e45a 614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 615 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
c9d39130 617 .port_ops = &mv5_ops,
47c2b677 618 },
20f733e7 619 { /* chip_604x */
138bfdd0 620 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 621 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 622 ATA_FLAG_NCQ,
31961943 623 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 624 .udma_mask = ATA_UDMA6,
c9d39130 625 .port_ops = &mv6_ops,
20f733e7
BR		 626 },
627 { /* chip_608x */
c5d3e45a 628 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 629 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 630 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 631 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 632 .udma_mask = ATA_UDMA6,
c9d39130 633 .port_ops = &mv6_ops,
20f733e7 634 },
e4e7b892 635 { /* chip_6042 */
138bfdd0 636 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 637 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 638 ATA_FLAG_NCQ,
e4e7b892 639 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 640 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 641 .port_ops = &mv_iie_ops,
642 },
643 { /* chip_7042 */
138bfdd0 644 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 645 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 646 ATA_FLAG_NCQ,
e4e7b892 647 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 648 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 649 .port_ops = &mv_iie_ops,
650 },
f351b2d6 651 { /* chip_soc */
02c1f32f 652 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 653 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
02c1f32f 654 ATA_FLAG_NCQ | MV_FLAG_SOC,
17c5aab5
ML		 655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
f351b2d6 658 },
20f733e7
BR		 659};
660
3b7d697d 661static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 666 /* RocketRAID 1740/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
668 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 669
670 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
673 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
674 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
675
676 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
677
d9f9c6bc
FA		 678 /* Adaptec 1430SA */
679 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
680
02a121da 681 /* Marvell 7042 support */
6a3d586d
MT		 682 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
683
02a121da
ML		 684 /* Highpoint RocketRAID PCIe series */
685 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
686 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
687
2d2744fc 688 { } /* terminate list */
20f733e7
BR		 689};
690
47c2b677
JG		 691static const struct mv_hw_ops mv5xxx_ops = {
692 .phy_errata = mv5_phy_errata,
693 .enable_leds = mv5_enable_leds,
694 .read_preamp = mv5_read_preamp,
695 .reset_hc = mv5_reset_hc,
522479fb
JG		 696 .reset_flash = mv5_reset_flash,
697 .reset_bus = mv5_reset_bus,
47c2b677
JG		 698};
699
700static const struct mv_hw_ops mv6xxx_ops = {
701 .phy_errata = mv6_phy_errata,
702 .enable_leds = mv6_enable_leds,
703 .read_preamp = mv6_read_preamp,
704 .reset_hc = mv6_reset_hc,
522479fb
JG		 705 .reset_flash = mv6_reset_flash,
706 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 707};
708
f351b2d6
SB		 709static const struct mv_hw_ops mv_soc_ops = {
710 .phy_errata = mv6_phy_errata,
711 .enable_leds = mv_soc_enable_leds,
712 .read_preamp = mv_soc_read_preamp,
713 .reset_hc = mv_soc_reset_hc,
714 .reset_flash = mv_soc_reset_flash,
715 .reset_bus = mv_soc_reset_bus,
716};
717
20f733e7
BR		 718/*
719 * Functions
720 */
721
722static inline void writelfl(unsigned long data, void __iomem *addr)
723{
724 writel(data, addr);
725 (void) readl(addr); /* flush to avoid PCI posted write */
726}
727
c9d39130
JG		 728static inline unsigned int mv_hc_from_port(unsigned int port)
729{
730 return port >> MV_PORT_HC_SHIFT;
731}
732
733static inline unsigned int mv_hardport_from_port(unsigned int port)
734{
735 return port & MV_PORT_MASK;
736}
737
1cfd19ae
ML		 738/*
739 * Consolidate some rather tricky bit shift calculations.
740 * This is hot-path stuff, so not a function.
741 * Simple code, with two return values, so macro rather than inline.
742 *
743 * port is the sole input, in range 0..7.
7368f919
ML		 744 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
745 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 746 *
747 * Note that port and hardport may be the same variable in some cases.
748 */
749#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
750{ \
751 shift = mv_hc_from_port(port) * HC_SHIFT; \
752 hardport = mv_hardport_from_port(port); \
753 shift += hardport * 2; \
754}
755
352fab70
ML		 756static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
757{
758 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
759}
760
c9d39130
JG		 761static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
762 unsigned int port)
763{
764 return mv_hc_base(base, mv_hc_from_port(port));
765}
766
20f733e7
BR		 767static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
768{
c9d39130 769 return mv_hc_base_from_port(base, port) +
8b260248 770 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 771 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 772}
773
e12bef50
ML		 774static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
775{
776 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
777 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
778
779 return hc_mmio + ofs;
780}
781
f351b2d6
SB		 782static inline void __iomem *mv_host_base(struct ata_host *host)
783{
784 struct mv_host_priv *hpriv = host->private_data;
785 return hpriv->base;
786}
787
20f733e7
BR		 788static inline void __iomem *mv_ap_base(struct ata_port *ap)
789{
f351b2d6 790 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 791}
792
cca3974e 793static inline int mv_get_hc_count(unsigned long port_flags)
31961943 794{
cca3974e 795 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 796}
797
c5d3e45a
JG		 798static void mv_set_edma_ptrs(void __iomem *port_mmio,
799 struct mv_host_priv *hpriv,
800 struct mv_port_priv *pp)
801{
bdd4ddde
JG		 802 u32 index;
803
c5d3e45a
JG		 804 /*
805 * initialize request queue
806 */
fcfb1f77
ML		 807 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
808 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 809
c5d3e45a
JG		 810 WARN_ON(pp->crqb_dma & 0x3ff);
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
814
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 816 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
818 else
bdd4ddde 819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 820
821 /*
822 * initialize response queue
823 */
fcfb1f77
ML		 824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 826
c5d3e45a
JG		 827 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
829
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 831 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
833 else
bdd4ddde 834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 835
bdd4ddde 836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 838}
839
05b308e1
BR		 840/**
841 * mv_start_dma - Enable eDMA engine
842 * @base: port base address
843 * @pp: port private data
844 *
beec7dbc
TH		 845 * Verify the local cache of the eDMA state is accurate with a
846 * WARN_ON.
05b308e1
BR		 847 *
848 * LOCKING:
849 * Inherited from caller.
850 */
0c58912e 851static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 852 struct mv_port_priv *pp, u8 protocol)
20f733e7 853{
72109168
ML		 854 int want_ncq = (protocol == ATA_PROT_NCQ);
855
856 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
857 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
858 if (want_ncq != using_ncq)
b562468c 859 mv_stop_edma(ap);
72109168 860 }
c5d3e45a 861 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 862 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 863 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 864 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 865 mv_host_base(ap->host), hardport);
0c58912e
ML		 866 u32 hc_irq_cause, ipending;
867
bdd4ddde 868 /* clear EDMA event indicators, if any */
f630d562 869 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 870
0c58912e
ML		 871 /* clear EDMA interrupt indicator, if any */
872 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 873 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 874 if (hc_irq_cause & ipending) {
875 writelfl(hc_irq_cause & ~ipending,
876 hc_mmio + HC_IRQ_CAUSE_OFS);
877 }
878
e12bef50 879 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 880
881 /* clear FIS IRQ Cause */
882 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
883
f630d562 884 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 885
f630d562 886 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 887 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
888 }
20f733e7
BR		 889}
890
05b308e1 891/**
e12bef50 892 * mv_stop_edma_engine - Disable eDMA engine
b562468c 893 * @port_mmio: io base address
05b308e1
BR		 894 *
895 * LOCKING:
896 * Inherited from caller.
897 */
b562468c 898static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 899{
b562468c 900 int i;
31961943 901
b562468c
ML		 902 /* Disable eDMA. The disable bit auto clears. */
903 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 904
b562468c
ML		 905 /* Wait for the chip to confirm eDMA is off. */
906 for (i = 10000; i > 0; i--) {
907 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 908 if (!(reg & EDMA_EN))
b562468c
ML		 909 return 0;
910 udelay(10);
31961943 911 }
b562468c 912 return -EIO;
20f733e7
BR		 913}
914
e12bef50 915static int mv_stop_edma(struct ata_port *ap)
0ea9e179 916{
b562468c
ML		 917 void __iomem *port_mmio = mv_ap_base(ap);
918 struct mv_port_priv *pp = ap->private_data;
0ea9e179 919
b562468c
ML		 920 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
921 return 0;
922 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
923 if (mv_stop_edma_engine(port_mmio)) {
924 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
925 return -EIO;
926 }
927 return 0;
0ea9e179
JG		 928}
929
8a70f8dc 930#ifdef ATA_DEBUG
31961943 931static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 932{
31961943
BR		 933 int b, w;
934 for (b = 0; b < bytes; ) {
935 DPRINTK("%p: ", start + b);
936 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 937 printk("%08x ", readl(start + b));
31961943
BR		 938 b += sizeof(u32);
939 }
940 printk("\n");
941 }
31961943 942}
8a70f8dc
JG		 943#endif
944
31961943
BR		 945static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
946{
947#ifdef ATA_DEBUG
948 int b, w;
949 u32 dw;
950 for (b = 0; b < bytes; ) {
951 DPRINTK("%02x: ", b);
952 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 953 (void) pci_read_config_dword(pdev, b, &dw);
954 printk("%08x ", dw);
31961943
BR		 955 b += sizeof(u32);
956 }
957 printk("\n");
958 }
959#endif
960}
961static void mv_dump_all_regs(void __iomem *mmio_base, int port,
962 struct pci_dev *pdev)
963{
964#ifdef ATA_DEBUG
8b260248 965 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 966 port >> MV_PORT_HC_SHIFT);
967 void __iomem *port_base;
968 int start_port, num_ports, p, start_hc, num_hcs, hc;
969
970 if (0 > port) {
971 start_hc = start_port = 0;
972 num_ports = 8; /* shld be benign for 4 port devs */
973 num_hcs = 2;
974 } else {
975 start_hc = port >> MV_PORT_HC_SHIFT;
976 start_port = port;
977 num_ports = num_hcs = 1;
978 }
8b260248 979 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 980 num_ports > 1 ? num_ports - 1 : start_port);
981
982 if (NULL != pdev) {
983 DPRINTK("PCI config space regs:\n");
984 mv_dump_pci_cfg(pdev, 0x68);
985 }
986 DPRINTK("PCI regs:\n");
987 mv_dump_mem(mmio_base+0xc00, 0x3c);
988 mv_dump_mem(mmio_base+0xd00, 0x34);
989 mv_dump_mem(mmio_base+0xf00, 0x4);
990 mv_dump_mem(mmio_base+0x1d00, 0x6c);
991 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 992 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 993 DPRINTK("HC regs (HC %i):\n", hc);
994 mv_dump_mem(hc_base, 0x1c);
995 }
996 for (p = start_port; p < start_port + num_ports; p++) {
997 port_base = mv_port_base(mmio_base, p);
2dcb407e 998 DPRINTK("EDMA regs (port %i):\n", p);
31961943 999 mv_dump_mem(port_base, 0x54);
2dcb407e 1000 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1001 mv_dump_mem(port_base+0x300, 0x60);
1002 }
1003#endif
20f733e7
BR		 1004}
1005
1006static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1007{
1008 unsigned int ofs;
1009
1010 switch (sc_reg_in) {
1011 case SCR_STATUS:
1012 case SCR_CONTROL:
1013 case SCR_ERROR:
1014 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1015 break;
1016 case SCR_ACTIVE:
1017 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1018 break;
1019 default:
1020 ofs = 0xffffffffU;
1021 break;
1022 }
1023 return ofs;
1024}
1025
da3dbb17 1026static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1027{
1028 unsigned int ofs = mv_scr_offset(sc_reg_in);
1029
da3dbb17
TH		 1030 if (ofs != 0xffffffffU) {
1031 *val = readl(mv_ap_base(ap) + ofs);
1032 return 0;
1033 } else
1034 return -EINVAL;
20f733e7
BR		 1035}
1036
da3dbb17 1037static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1038{
1039 unsigned int ofs = mv_scr_offset(sc_reg_in);
1040
da3dbb17 1041 if (ofs != 0xffffffffU) {
20f733e7 1042 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1043 return 0;
1044 } else
1045 return -EINVAL;
20f733e7
BR		 1046}
1047
f273827e
ML		 1048static void mv6_dev_config(struct ata_device *adev)
1049{
1050 /*
e49856d8
ML		 1051 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1052 *
1053 * Gen-II does not support NCQ over a port multiplier
1054 * (no FIS-based switching).
1055 *
f273827e
ML		 1056 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1057 * See mv_qc_prep() for more info.
1058 */
e49856d8 1059 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1060 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1061 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1062 ata_dev_printk(adev, KERN_INFO,
1063 "NCQ disabled for command-based switching\n");
1064 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1065 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1066 ata_dev_printk(adev, KERN_INFO,
1067 "max_sectors limited to %u for NCQ\n",
1068 adev->max_sectors);
1069 }
e49856d8 1070 }
f273827e
ML		 1071}
1072
e49856d8
ML		 1073static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
1074{
8e7decdb 1075 u32 old_fiscfg, new_fiscfg, old_ltmode, new_ltmode;
e49856d8
ML		 1076 /*
1077 * Various bit settings required for operation
1078 * in FIS-based switching (fbs) mode on GenIIe:
1079 */
8e7decdb 1080 old_fiscfg = readl(port_mmio + FISCFG_OFS);
e49856d8
ML		 1081 old_ltmode = readl(port_mmio + LTMODE_OFS);
1082 if (enable_fbs) {
8e7decdb 1083 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
e49856d8
ML		 1084 new_ltmode = old_ltmode | LTMODE_BIT8;
1085 } else { /* disable fbs */
8e7decdb 1086 new_fiscfg = old_fiscfg & ~FISCFG_SINGLE_SYNC;
e49856d8
ML		 1087 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1088 }
8e7decdb
ML		 1089 if (new_fiscfg != old_fiscfg)
1090 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1091 if (new_ltmode != old_ltmode)
1092 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
f273827e
ML		 1093}
1094
e12bef50 1095static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1096{
0c58912e 1097 u32 cfg;
e12bef50
ML		 1098 struct mv_port_priv *pp = ap->private_data;
1099 struct mv_host_priv *hpriv = ap->host->private_data;
1100 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1101
1102 /* set up non-NCQ EDMA configuration */
0c58912e 1103 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
e4e7b892 1104
0c58912e 1105 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1106 cfg |= (1 << 8); /* enab config burst size mask */
1107
0c58912e 1108 else if (IS_GEN_II(hpriv))
e4e7b892
JG		 1109 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1110
1111 else if (IS_GEN_IIE(hpriv)) {
e728eabe
JG		 1112 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1113 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1114 if (HAS_PCI(ap->host))
1115 cfg |= (1 << 18); /* enab early completion */
1116 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1117 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e49856d8
ML		 1118
1119 if (want_ncq && sata_pmp_attached(ap)) {
1120 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1121 mv_config_fbs(port_mmio, 1);
1122 } else {
1123 mv_config_fbs(port_mmio, 0);
1124 }
e4e7b892
JG		 1125 }
1126
72109168
ML		 1127 if (want_ncq) {
1128 cfg |= EDMA_CFG_NCQ;
1129 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1130 } else
1131 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1132
e4e7b892
JG		 1133 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1134}
1135
da2fa9ba
ML		 1136static void mv_port_free_dma_mem(struct ata_port *ap)
1137{
1138 struct mv_host_priv *hpriv = ap->host->private_data;
1139 struct mv_port_priv *pp = ap->private_data;
eb73d558 1140 int tag;
da2fa9ba
ML		 1141
1142 if (pp->crqb) {
1143 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1144 pp->crqb = NULL;
1145 }
1146 if (pp->crpb) {
1147 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1148 pp->crpb = NULL;
1149 }
eb73d558
ML		 1150 /*
1151 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1152 * For later hardware, we have one unique sg_tbl per NCQ tag.
1153 */
1154 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1155 if (pp->sg_tbl[tag]) {
1156 if (tag == 0 || !IS_GEN_I(hpriv))
1157 dma_pool_free(hpriv->sg_tbl_pool,
1158 pp->sg_tbl[tag],
1159 pp->sg_tbl_dma[tag]);
1160 pp->sg_tbl[tag] = NULL;
1161 }
da2fa9ba
ML		 1162 }
1163}
1164
05b308e1
BR		 1165/**
1166 * mv_port_start - Port specific init/start routine.
1167 * @ap: ATA channel to manipulate
1168 *
1169 * Allocate and point to DMA memory, init port private memory,
1170 * zero indices.
1171 *
1172 * LOCKING:
1173 * Inherited from caller.
1174 */
31961943
BR		 1175static int mv_port_start(struct ata_port *ap)
1176{
cca3974e
JG		 1177 struct device *dev = ap->host->dev;
1178 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1179 struct mv_port_priv *pp;
dde20207 1180 int tag;
31961943 1181
24dc5f33 1182 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1183 if (!pp)
24dc5f33 1184 return -ENOMEM;
da2fa9ba 1185 ap->private_data = pp;
31961943 1186
da2fa9ba
ML		 1187 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1188 if (!pp->crqb)
1189 return -ENOMEM;
1190 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1191
da2fa9ba
ML		 1192 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1193 if (!pp->crpb)
1194 goto out_port_free_dma_mem;
1195 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1196
eb73d558
ML		 1197 /*
1198 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1199 * For later hardware, we need one unique sg_tbl per NCQ tag.
1200 */
1201 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1202 if (tag == 0 || !IS_GEN_I(hpriv)) {
1203 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1204 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1205 if (!pp->sg_tbl[tag])
1206 goto out_port_free_dma_mem;
1207 } else {
1208 pp->sg_tbl[tag] = pp->sg_tbl[0];
1209 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1210 }
1211 }
31961943 1212 return 0;
da2fa9ba
ML		 1213
1214out_port_free_dma_mem:
1215 mv_port_free_dma_mem(ap);
1216 return -ENOMEM;
31961943
BR		 1217}
1218
05b308e1
BR		 1219/**
1220 * mv_port_stop - Port specific cleanup/stop routine.
1221 * @ap: ATA channel to manipulate
1222 *
1223 * Stop DMA, cleanup port memory.
1224 *
1225 * LOCKING:
cca3974e 1226 * This routine uses the host lock to protect the DMA stop.
05b308e1 1227 */
31961943
BR		 1228static void mv_port_stop(struct ata_port *ap)
1229{
e12bef50 1230 mv_stop_edma(ap);
da2fa9ba 1231 mv_port_free_dma_mem(ap);
31961943
BR		 1232}
1233
05b308e1
BR		 1234/**
1235 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1236 * @qc: queued command whose SG list to source from
1237 *
1238 * Populate the SG list and mark the last entry.
1239 *
1240 * LOCKING:
1241 * Inherited from caller.
1242 */
6c08772e 1243static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1244{
1245 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1246 struct scatterlist *sg;
3be6cbd7 1247 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1248 unsigned int si;
31961943 1249
eb73d558 1250 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1251 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1252 dma_addr_t addr = sg_dma_address(sg);
1253 u32 sg_len = sg_dma_len(sg);
22374677 1254
4007b493
OJ		 1255 while (sg_len) {
1256 u32 offset = addr & 0xffff;
1257 u32 len = sg_len;
22374677 1258
4007b493
OJ		 1259 if ((offset + sg_len > 0x10000))
1260 len = 0x10000 - offset;
1261
1262 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1263 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1264 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1265
1266 sg_len -= len;
1267 addr += len;
1268
3be6cbd7 1269 last_sg = mv_sg;
4007b493 1270 mv_sg++;
4007b493 1271 }
31961943 1272 }
3be6cbd7
JG		 1273
1274 if (likely(last_sg))
1275 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1276}
1277
5796d1c4 1278static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1279{
559eedad 1280 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1281 (last ? CRQB_CMD_LAST : 0);
559eedad 1282 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1283}
1284
05b308e1
BR		 1285/**
1286 * mv_qc_prep - Host specific command preparation.
1287 * @qc: queued command to prepare
1288 *
1289 * This routine simply redirects to the general purpose routine
1290 * if command is not DMA. Else, it handles prep of the CRQB
1291 * (command request block), does some sanity checking, and calls
1292 * the SG load routine.
1293 *
1294 * LOCKING:
1295 * Inherited from caller.
1296 */
31961943
BR		 1297static void mv_qc_prep(struct ata_queued_cmd *qc)
1298{
1299 struct ata_port *ap = qc->ap;
1300 struct mv_port_priv *pp = ap->private_data;
e1469874 1301 __le16 *cw;
31961943
BR		 1302 struct ata_taskfile *tf;
1303 u16 flags = 0;
a6432436 1304 unsigned in_index;
31961943 1305
138bfdd0
ML		 1306 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1307 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1308 return;
20f733e7 1309
31961943
BR		 1310 /* Fill in command request block
1311 */
e4e7b892 1312 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1313 flags |= CRQB_FLAG_READ;
beec7dbc 1314 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1315 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1316 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1317
bdd4ddde 1318 /* get current queue index from software */
fcfb1f77 1319 in_index = pp->req_idx;
a6432436
ML		 1320
1321 pp->crqb[in_index].sg_addr =
eb73d558 1322 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1323 pp->crqb[in_index].sg_addr_hi =
eb73d558 1324 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1325 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1326
a6432436 1327 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1328 tf = &qc->tf;
1329
1330 /* Sadly, the CRQB cannot accomodate all registers--there are
1331 * only 11 bytes...so we must pick and choose required
1332 * registers based on the command. So, we drop feature and
1333 * hob_feature for [RW] DMA commands, but they are needed for
1334 * NCQ. NCQ will drop hob_nsect.
20f733e7 1335 */
31961943
BR		 1336 switch (tf->command) {
1337 case ATA_CMD_READ:
1338 case ATA_CMD_READ_EXT:
1339 case ATA_CMD_WRITE:
1340 case ATA_CMD_WRITE_EXT:
c15d85c8 1341 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1342 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1343 break;
31961943
BR		 1344 case ATA_CMD_FPDMA_READ:
1345 case ATA_CMD_FPDMA_WRITE:
8b260248 1346 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1347 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1348 break;
31961943
BR		 1349 default:
1350 /* The only other commands EDMA supports in non-queued and
1351 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1352 * of which are defined/used by Linux. If we get here, this
1353 * driver needs work.
1354 *
1355 * FIXME: modify libata to give qc_prep a return value and
1356 * return error here.
1357 */
1358 BUG_ON(tf->command);
1359 break;
1360 }
1361 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1362 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1363 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1364 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1365 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1366 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1367 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1368 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1369 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1370
e4e7b892
JG		 1371 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1372 return;
1373 mv_fill_sg(qc);
1374}
1375
1376/**
1377 * mv_qc_prep_iie - Host specific command preparation.
1378 * @qc: queued command to prepare
1379 *
1380 * This routine simply redirects to the general purpose routine
1381 * if command is not DMA. Else, it handles prep of the CRQB
1382 * (command request block), does some sanity checking, and calls
1383 * the SG load routine.
1384 *
1385 * LOCKING:
1386 * Inherited from caller.
1387 */
1388static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1389{
1390 struct ata_port *ap = qc->ap;
1391 struct mv_port_priv *pp = ap->private_data;
1392 struct mv_crqb_iie *crqb;
1393 struct ata_taskfile *tf;
a6432436 1394 unsigned in_index;
e4e7b892
JG		 1395 u32 flags = 0;
1396
138bfdd0
ML		 1397 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1398 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1399 return;
1400
e12bef50 1401 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1402 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1403 flags |= CRQB_FLAG_READ;
1404
beec7dbc 1405 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1406 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1407 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1408 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1409
bdd4ddde 1410 /* get current queue index from software */
fcfb1f77 1411 in_index = pp->req_idx;
a6432436
ML		 1412
1413 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1414 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1415 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1416 crqb->flags = cpu_to_le32(flags);
1417
1418 tf = &qc->tf;
1419 crqb->ata_cmd[0] = cpu_to_le32(
1420 (tf->command << 16) |
1421 (tf->feature << 24)
1422 );
1423 crqb->ata_cmd[1] = cpu_to_le32(
1424 (tf->lbal << 0) |
1425 (tf->lbam << 8) |
1426 (tf->lbah << 16) |
1427 (tf->device << 24)
1428 );
1429 crqb->ata_cmd[2] = cpu_to_le32(
1430 (tf->hob_lbal << 0) |
1431 (tf->hob_lbam << 8) |
1432 (tf->hob_lbah << 16) |
1433 (tf->hob_feature << 24)
1434 );
1435 crqb->ata_cmd[3] = cpu_to_le32(
1436 (tf->nsect << 0) |
1437 (tf->hob_nsect << 8)
1438 );
1439
1440 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1441 return;
31961943
BR		 1442 mv_fill_sg(qc);
1443}
1444
05b308e1
BR		 1445/**
1446 * mv_qc_issue - Initiate a command to the host
1447 * @qc: queued command to start
1448 *
1449 * This routine simply redirects to the general purpose routine
1450 * if command is not DMA. Else, it sanity checks our local
1451 * caches of the request producer/consumer indices then enables
1452 * DMA and bumps the request producer index.
1453 *
1454 * LOCKING:
1455 * Inherited from caller.
1456 */
9a3d9eb0 1457static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1458{
c5d3e45a
JG		 1459 struct ata_port *ap = qc->ap;
1460 void __iomem *port_mmio = mv_ap_base(ap);
1461 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1462 u32 in_index;
31961943 1463
138bfdd0
ML		 1464 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1465 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1466 /*
1467 * We're about to send a non-EDMA capable command to the
31961943
BR		 1468 * port. Turn off EDMA so there won't be problems accessing
1469 * shadow block, etc registers.
1470 */
b562468c 1471 mv_stop_edma(ap);
e49856d8 1472 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1473 return ata_sff_qc_issue(qc);
31961943
BR		 1474 }
1475
72109168 1476 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1477
fcfb1f77
ML		 1478 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1479 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1480
1481 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1482 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1483 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1484
1485 return 0;
1486}
1487
8f767f8a
ML		 1488static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1489{
1490 struct mv_port_priv *pp = ap->private_data;
1491 struct ata_queued_cmd *qc;
1492
1493 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1494 return NULL;
1495 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1496 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1497 qc = NULL;
1498 return qc;
1499}
1500
1501static void mv_unexpected_intr(struct ata_port *ap)
1502{
1503 struct mv_port_priv *pp = ap->private_data;
1504 struct ata_eh_info *ehi = &ap->link.eh_info;
1505 char *when = "";
1506
1507 /*
1508 * We got a device interrupt from something that
1509 * was supposed to be using EDMA or polling.
1510 */
1511 ata_ehi_clear_desc(ehi);
1512 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1513 when = " while EDMA enabled";
1514 } else {
1515 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1516 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1517 when = " while polling";
1518 }
1519 ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when);
1520 ehi->err_mask |= AC_ERR_OTHER;
1521 ehi->action |= ATA_EH_RESET;
1522 ata_port_freeze(ap);
1523}
1524
05b308e1
BR		 1525/**
1526 * mv_err_intr - Handle error interrupts on the port
1527 * @ap: ATA channel to manipulate
8d07379d 1528 * @qc: affected command (non-NCQ), or NULL
05b308e1 1529 *
8d07379d
ML		 1530 * Most cases require a full reset of the chip's state machine,
1531 * which also performs a COMRESET.
1532 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1533 *
1534 * LOCKING:
1535 * Inherited from caller.
1536 */
bdd4ddde 1537static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
31961943
BR		 1538{
1539 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde
JG		 1540 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1541 struct mv_port_priv *pp = ap->private_data;
1542 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1543 unsigned int action = 0, err_mask = 0;
9af5c9c9 1544 struct ata_eh_info *ehi = &ap->link.eh_info;
20f733e7 1545
bdd4ddde 1546 ata_ehi_clear_desc(ehi);
20f733e7 1547
8d07379d
ML		 1548 /*
1549 * Read and clear the err_cause bits. This won't actually
1550 * clear for some errors (eg. SError), but we will be doing
1551 * a hard reset in those cases regardless, which *will* clear it.
1552 */
bdd4ddde 1553 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
8d07379d 1554 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1555
352fab70 1556 ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause);
bdd4ddde
JG		 1557
1558 /*
352fab70 1559 * All generations share these EDMA error cause bits:
bdd4ddde 1560 */
bdd4ddde
JG		 1561 if (edma_err_cause & EDMA_ERR_DEV)
1562 err_mask |= AC_ERR_DEV;
1563 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1564 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1565 EDMA_ERR_INTRL_PAR)) {
1566 err_mask |= AC_ERR_ATA_BUS;
cf480626 1567 action |= ATA_EH_RESET;
b64bbc39 1568 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1569 }
1570 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1571 ata_ehi_hotplugged(ehi);
1572 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1573 "dev disconnect" : "dev connect");
cf480626 1574 action |= ATA_EH_RESET;
bdd4ddde
JG		 1575 }
1576
352fab70
ML		 1577 /*
1578 * Gen-I has a different SELF_DIS bit,
1579 * different FREEZE bits, and no SERR bit:
1580 */
ee9ccdf7 1581 if (IS_GEN_I(hpriv)) {
bdd4ddde 1582 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1583 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1584 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1585 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1586 }
1587 } else {
1588 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1589 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1590 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1591 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1592 }
bdd4ddde 1593 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1594 /*
1595 * Ensure that we read our own SCR, not a pmp link SCR:
1596 */
1597 ap->ops->scr_read(ap, SCR_ERROR, &serr);
1598 /*
1599 * Don't clear SError here; leave it for libata-eh:
1600 */
1601 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1602 err_mask |= AC_ERR_ATA_BUS;
cf480626 1603 action |= ATA_EH_RESET;
bdd4ddde 1604 }
afb0edd9 1605 }
20f733e7 1606
bdd4ddde
JG		 1607 if (!err_mask) {
1608 err_mask = AC_ERR_OTHER;
cf480626 1609 action |= ATA_EH_RESET;
bdd4ddde
JG		 1610 }
1611
1612 ehi->serror |= serr;
1613 ehi->action |= action;
1614
1615 if (qc)
1616 qc->err_mask |= err_mask;
1617 else
1618 ehi->err_mask |= err_mask;
1619
1620 if (edma_err_cause & eh_freeze_mask)
1621 ata_port_freeze(ap);
1622 else
1623 ata_port_abort(ap);
1624}
1625
fcfb1f77
ML		 1626static void mv_process_crpb_response(struct ata_port *ap,
1627 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1628{
1629 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1630
1631 if (qc) {
1632 u8 ata_status;
1633 u16 edma_status = le16_to_cpu(response->flags);
1634 /*
1635 * edma_status from a response queue entry:
1636 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1637 * MSB is saved ATA status from command completion.
1638 */
1639 if (!ncq_enabled) {
1640 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1641 if (err_cause) {
1642 /*
1643 * Error will be seen/handled by mv_err_intr().
1644 * So do nothing at all here.
1645 */
1646 return;
1647 }
1648 }
1649 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1650 qc->err_mask |= ac_err_mask(ata_status);
1651 ata_qc_complete(qc);
1652 } else {
1653 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1654 __func__, tag);
1655 }
1656}
1657
1658static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1659{
1660 void __iomem *port_mmio = mv_ap_base(ap);
1661 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1662 u32 in_index;
bdd4ddde 1663 bool work_done = false;
fcfb1f77 1664 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1665
fcfb1f77 1666 /* Get the hardware queue position index */
bdd4ddde
JG		 1667 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1668 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1669
fcfb1f77
ML		 1670 /* Process new responses from since the last time we looked */
1671 while (in_index != pp->resp_idx) {
6c1153e0 1672 unsigned int tag;
fcfb1f77 1673 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1674
fcfb1f77 1675 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1676
fcfb1f77
ML		 1677 if (IS_GEN_I(hpriv)) {
1678 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1679 tag = ap->link.active_tag;
fcfb1f77
ML		 1680 } else {
1681 /* Gen II/IIE: get command tag from CRPB entry */
1682 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1683 }
fcfb1f77 1684 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 1685 work_done = true;
bdd4ddde
JG		 1686 }
1687
352fab70 1688 /* Update the software queue position index in hardware */
bdd4ddde
JG		 1689 if (work_done)
1690 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 1691 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 1692 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 1693}
1694
05b308e1
BR		 1695/**
1696 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1697 * @host: host specific structure
7368f919 1698 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 1699 *
1700 * LOCKING:
1701 * Inherited from caller.
1702 */
7368f919 1703static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 1704{
f351b2d6 1705 struct mv_host_priv *hpriv = host->private_data;
a3718c1f
ML		 1706 void __iomem *mmio = hpriv->base, *hc_mmio = NULL;
1707 u32 hc_irq_cause = 0;
1708 unsigned int handled = 0, port;
20f733e7 1709
a3718c1f 1710 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 1711 struct ata_port *ap = host->ports[port];
8f71efe2 1712 struct mv_port_priv *pp;
a3718c1f
ML		 1713 unsigned int shift, hardport, port_cause;
1714 /*
1715 * When we move to the second hc, flag our cached
1716 * copies of hc_mmio (and hc_irq_cause) as invalid again.
1717 */
1718 if (port == MV_PORTS_PER_HC)
1719 hc_mmio = NULL;
1720 /*
1721 * Do nothing if port is not interrupting or is disabled:
1722 */
1723 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
7368f919 1724 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
a3718c1f 1725 if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED))
a2c91a88 1726 continue;
a3718c1f
ML		 1727 /*
1728 * Each hc within the host has its own hc_irq_cause register.
1729 * We defer reading it until we know we need it, right now:
1730 *
1731 * FIXME later: we don't really need to read this register
1732 * (some logic changes required below if we go that way),
1733 * because it doesn't tell us anything new. But we do need
1734 * to write to it, outside the top of this loop,
1735 * to reset the interrupt triggers for next time.
1736 */
1737 if (!hc_mmio) {
1738 hc_mmio = mv_hc_base_from_port(mmio, port);
1739 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1740 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1741 handled = 1;
1742 }
8f767f8a
ML		 1743 /*
1744 * Process completed CRPB response(s) before other events.
1745 */
a3718c1f 1746 pp = ap->private_data;
8f767f8a
ML		 1747 if (hc_irq_cause & (DMA_IRQ << hardport)) {
1748 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN)
fcfb1f77 1749 mv_process_crpb_entries(ap, pp);
8f767f8a
ML		 1750 }
1751 /*
1752 * Handle chip-reported errors, or continue on to handle PIO.
1753 */
1754 if (unlikely(port_cause & ERR_IRQ)) {
1755 mv_err_intr(ap, mv_get_active_qc(ap));
1756 } else if (hc_irq_cause & (DEV_IRQ << hardport)) {
1757 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1758 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
1759 if (qc) {
1760 ata_sff_host_intr(ap, qc);
1761 continue;
1762 }
1763 }
1764 mv_unexpected_intr(ap);
20f733e7
BR		 1765 }
1766 }
a3718c1f 1767 return handled;
20f733e7
BR		 1768}
1769
a3718c1f 1770static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 1771{
02a121da 1772 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 1773 struct ata_port *ap;
1774 struct ata_queued_cmd *qc;
1775 struct ata_eh_info *ehi;
1776 unsigned int i, err_mask, printed = 0;
1777 u32 err_cause;
1778
02a121da 1779 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1780
1781 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1782 err_cause);
1783
1784 DPRINTK("All regs @ PCI error\n");
1785 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1786
02a121da 1787 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1788
1789 for (i = 0; i < host->n_ports; i++) {
1790 ap = host->ports[i];
936fd732 1791 if (!ata_link_offline(&ap->link)) {
9af5c9c9 1792 ehi = &ap->link.eh_info;
bdd4ddde
JG		 1793 ata_ehi_clear_desc(ehi);
1794 if (!printed++)
1795 ata_ehi_push_desc(ehi,
1796 "PCI err cause 0x%08x", err_cause);
1797 err_mask = AC_ERR_HOST_BUS;
cf480626 1798 ehi->action = ATA_EH_RESET;
9af5c9c9 1799 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 1800 if (qc)
1801 qc->err_mask |= err_mask;
1802 else
1803 ehi->err_mask |= err_mask;
1804
1805 ata_port_freeze(ap);
1806 }
1807 }
a3718c1f 1808 return 1; /* handled */
bdd4ddde
JG		 1809}
1810
05b308e1 1811/**
c5d3e45a 1812 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 1813 * @irq: unused
1814 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 1815 *
1816 * Read the read only register to determine if any host
1817 * controllers have pending interrupts. If so, call lower level
1818 * routine to handle. Also check for PCI errors which are only
1819 * reported here.
1820 *
8b260248 1821 * LOCKING:
cca3974e 1822 * This routine holds the host lock while processing pending
05b308e1
BR		 1823 * interrupts.
1824 */
7d12e780 1825static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1826{
cca3974e 1827 struct ata_host *host = dev_instance;
f351b2d6 1828 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 1829 unsigned int handled = 0;
7368f919 1830 u32 main_irq_cause, main_irq_mask;
20f733e7 1831
646a4da5 1832 spin_lock(&host->lock);
7368f919
ML		 1833 main_irq_cause = readl(hpriv->main_irq_cause_addr);
1834 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 1835 /*
1836 * Deal with cases where we either have nothing pending, or have read
1837 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 1838 */
7368f919
ML		 1839 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
1840 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 1841 handled = mv_pci_error(host, hpriv->base);
1842 else
7368f919 1843 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 1844 }
cca3974e 1845 spin_unlock(&host->lock);
20f733e7
BR		 1846 return IRQ_RETVAL(handled);
1847}
1848
c9d39130
JG		 1849static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1850{
1851 unsigned int ofs;
1852
1853 switch (sc_reg_in) {
1854 case SCR_STATUS:
1855 case SCR_ERROR:
1856 case SCR_CONTROL:
1857 ofs = sc_reg_in * sizeof(u32);
1858 break;
1859 default:
1860 ofs = 0xffffffffU;
1861 break;
1862 }
1863 return ofs;
1864}
1865
da3dbb17 1866static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 1867{
f351b2d6
SB		 1868 struct mv_host_priv *hpriv = ap->host->private_data;
1869 void __iomem *mmio = hpriv->base;
0d5ff566 1870 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1871 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1872
da3dbb17
TH		 1873 if (ofs != 0xffffffffU) {
1874 *val = readl(addr + ofs);
1875 return 0;
1876 } else
1877 return -EINVAL;
c9d39130
JG		 1878}
1879
da3dbb17 1880static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 1881{
f351b2d6
SB		 1882 struct mv_host_priv *hpriv = ap->host->private_data;
1883 void __iomem *mmio = hpriv->base;
0d5ff566 1884 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1885 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1886
da3dbb17 1887 if (ofs != 0xffffffffU) {
0d5ff566 1888 writelfl(val, addr + ofs);
da3dbb17
TH		 1889 return 0;
1890 } else
1891 return -EINVAL;
c9d39130
JG		 1892}
1893
7bb3c529 1894static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 1895{
7bb3c529 1896 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 1897 int early_5080;
1898
44c10138 1899 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 1900
1901 if (!early_5080) {
1902 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1903 tmp |= (1 << 0);
1904 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1905 }
1906
7bb3c529 1907 mv_reset_pci_bus(host, mmio);
522479fb
JG		 1908}
1909
1910static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1911{
8e7decdb 1912 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 1913}
1914
47c2b677 1915static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1916 void __iomem *mmio)
1917{
c9d39130
JG		 1918 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1919 u32 tmp;
1920
1921 tmp = readl(phy_mmio + MV5_PHY_MODE);
1922
1923 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1924 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1925}
1926
47c2b677 1927static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1928{
522479fb
JG		 1929 u32 tmp;
1930
8e7decdb 1931 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 1932
1933 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1934
1935 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1936 tmp |= ~(1 << 0);
1937 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1938}
1939
2a47ce06
JG		 1940static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1941 unsigned int port)
bca1c4eb 1942{
c9d39130
JG		 1943 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1944 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1945 u32 tmp;
1946 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1947
1948 if (fix_apm_sq) {
8e7decdb 1949 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 1950 tmp |= (1 << 19);
8e7decdb 1951 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 1952
8e7decdb 1953 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 1954 tmp &= ~0x3;
1955 tmp |= 0x1;
8e7decdb 1956 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 1957 }
1958
1959 tmp = readl(phy_mmio + MV5_PHY_MODE);
1960 tmp &= ~mask;
1961 tmp |= hpriv->signal[port].pre;
1962 tmp |= hpriv->signal[port].amps;
1963 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1964}
1965
c9d39130
JG		 1966
1967#undef ZERO
1968#define ZERO(reg) writel(0, port_mmio + (reg))
1969static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1970 unsigned int port)
1971{
1972 void __iomem *port_mmio = mv_port_base(mmio, port);
1973
e12bef50 1974 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 1975
1976 ZERO(0x028); /* command */
1977 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1978 ZERO(0x004); /* timer */
1979 ZERO(0x008); /* irq err cause */
1980 ZERO(0x00c); /* irq err mask */
1981 ZERO(0x010); /* rq bah */
1982 ZERO(0x014); /* rq inp */
1983 ZERO(0x018); /* rq outp */
1984 ZERO(0x01c); /* respq bah */
1985 ZERO(0x024); /* respq outp */
1986 ZERO(0x020); /* respq inp */
1987 ZERO(0x02c); /* test control */
8e7decdb 1988 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 1989}
1990#undef ZERO
1991
1992#define ZERO(reg) writel(0, hc_mmio + (reg))
1993static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1994 unsigned int hc)
47c2b677 1995{
c9d39130
JG		 1996 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1997 u32 tmp;
1998
1999 ZERO(0x00c);
2000 ZERO(0x010);
2001 ZERO(0x014);
2002 ZERO(0x018);
2003
2004 tmp = readl(hc_mmio + 0x20);
2005 tmp &= 0x1c1c1c1c;
2006 tmp |= 0x03030303;
2007 writel(tmp, hc_mmio + 0x20);
2008}
2009#undef ZERO
2010
2011static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2012 unsigned int n_hc)
2013{
2014 unsigned int hc, port;
2015
2016 for (hc = 0; hc < n_hc; hc++) {
2017 for (port = 0; port < MV_PORTS_PER_HC; port++)
2018 mv5_reset_hc_port(hpriv, mmio,
2019 (hc * MV_PORTS_PER_HC) + port);
2020
2021 mv5_reset_one_hc(hpriv, mmio, hc);
2022 }
2023
2024 return 0;
47c2b677
JG		 2025}
2026
101ffae2
JG		 2027#undef ZERO
2028#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2029static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2030{
02a121da 2031 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2032 u32 tmp;
2033
8e7decdb 2034 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2035 tmp &= 0xff00ffff;
8e7decdb 2036 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2037
2038 ZERO(MV_PCI_DISC_TIMER);
2039 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2040 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
7368f919 2041 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2042 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2043 ZERO(hpriv->irq_cause_ofs);
2044 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2045 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2046 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2047 ZERO(MV_PCI_ERR_ATTRIBUTE);
2048 ZERO(MV_PCI_ERR_COMMAND);
2049}
2050#undef ZERO
2051
2052static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2053{
2054 u32 tmp;
2055
2056 mv5_reset_flash(hpriv, mmio);
2057
8e7decdb 2058 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2059 tmp &= 0x3;
2060 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2061 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2062}
2063
2064/**
2065 * mv6_reset_hc - Perform the 6xxx global soft reset
2066 * @mmio: base address of the HBA
2067 *
2068 * This routine only applies to 6xxx parts.
2069 *
2070 * LOCKING:
2071 * Inherited from caller.
2072 */
c9d39130
JG		 2073static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2074 unsigned int n_hc)
101ffae2
JG		 2075{
2076 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2077 int i, rc = 0;
2078 u32 t;
2079
2080 /* Following procedure defined in PCI "main command and status
2081 * register" table.
2082 */
2083 t = readl(reg);
2084 writel(t | STOP_PCI_MASTER, reg);
2085
2086 for (i = 0; i < 1000; i++) {
2087 udelay(1);
2088 t = readl(reg);
2dcb407e 2089 if (PCI_MASTER_EMPTY & t)
101ffae2 2090 break;
101ffae2
JG		 2091 }
2092 if (!(PCI_MASTER_EMPTY & t)) {
2093 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2094 rc = 1;
2095 goto done;
2096 }
2097
2098 /* set reset */
2099 i = 5;
2100 do {
2101 writel(t | GLOB_SFT_RST, reg);
2102 t = readl(reg);
2103 udelay(1);
2104 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2105
2106 if (!(GLOB_SFT_RST & t)) {
2107 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2108 rc = 1;
2109 goto done;
2110 }
2111
2112 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2113 i = 5;
2114 do {
2115 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2116 t = readl(reg);
2117 udelay(1);
2118 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2119
2120 if (GLOB_SFT_RST & t) {
2121 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2122 rc = 1;
2123 }
2124done:
2125 return rc;
2126}
2127
47c2b677 2128static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2129 void __iomem *mmio)
2130{
2131 void __iomem *port_mmio;
2132 u32 tmp;
2133
8e7decdb 2134 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2135 if ((tmp & (1 << 0)) == 0) {
47c2b677 2136 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2137 hpriv->signal[idx].pre = 0x1 << 5;
2138 return;
2139 }
2140
2141 port_mmio = mv_port_base(mmio, idx);
2142 tmp = readl(port_mmio + PHY_MODE2);
2143
2144 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2145 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2146}
2147
47c2b677 2148static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2149{
8e7decdb 2150 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2151}
2152
c9d39130 2153static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2154 unsigned int port)
bca1c4eb 2155{
c9d39130
JG		 2156 void __iomem *port_mmio = mv_port_base(mmio, port);
2157
bca1c4eb 2158 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2159 int fix_phy_mode2 =
2160 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2161 int fix_phy_mode4 =
47c2b677
JG		 2162 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2163 u32 m2, tmp;
2164
2165 if (fix_phy_mode2) {
2166 m2 = readl(port_mmio + PHY_MODE2);
2167 m2 &= ~(1 << 16);
2168 m2 |= (1 << 31);
2169 writel(m2, port_mmio + PHY_MODE2);
2170
2171 udelay(200);
2172
2173 m2 = readl(port_mmio + PHY_MODE2);
2174 m2 &= ~((1 << 16) | (1 << 31));
2175 writel(m2, port_mmio + PHY_MODE2);
2176
2177 udelay(200);
2178 }
2179
2180 /* who knows what this magic does */
2181 tmp = readl(port_mmio + PHY_MODE3);
2182 tmp &= ~0x7F800000;
2183 tmp |= 0x2A800000;
2184 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2185
2186 if (fix_phy_mode4) {
47c2b677 2187 u32 m4;
bca1c4eb
JG		 2188
2189 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2190
2191 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2192 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2193
e12bef50 2194 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2195 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2196
2197 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2198
2199 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2200 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2201 }
2202
2203 /* Revert values of pre-emphasis and signal amps to the saved ones */
2204 m2 = readl(port_mmio + PHY_MODE2);
2205
2206 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2207 m2 |= hpriv->signal[port].amps;
2208 m2 |= hpriv->signal[port].pre;
47c2b677 2209 m2 &= ~(1 << 16);
bca1c4eb 2210
e4e7b892
JG		 2211 /* according to mvSata 3.6.1, some IIE values are fixed */
2212 if (IS_GEN_IIE(hpriv)) {
2213 m2 &= ~0xC30FF01F;
2214 m2 |= 0x0000900F;
2215 }
2216
bca1c4eb
JG		 2217 writel(m2, port_mmio + PHY_MODE2);
2218}
2219
f351b2d6
SB		 2220/* TODO: use the generic LED interface to configure the SATA Presence */
2221/* & Acitivy LEDs on the board */
2222static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2223 void __iomem *mmio)
2224{
2225 return;
2226}
2227
2228static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2229 void __iomem *mmio)
2230{
2231 void __iomem *port_mmio;
2232 u32 tmp;
2233
2234 port_mmio = mv_port_base(mmio, idx);
2235 tmp = readl(port_mmio + PHY_MODE2);
2236
2237 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2238 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2239}
2240
2241#undef ZERO
2242#define ZERO(reg) writel(0, port_mmio + (reg))
2243static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2244 void __iomem *mmio, unsigned int port)
2245{
2246 void __iomem *port_mmio = mv_port_base(mmio, port);
2247
e12bef50 2248 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2249
2250 ZERO(0x028); /* command */
2251 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2252 ZERO(0x004); /* timer */
2253 ZERO(0x008); /* irq err cause */
2254 ZERO(0x00c); /* irq err mask */
2255 ZERO(0x010); /* rq bah */
2256 ZERO(0x014); /* rq inp */
2257 ZERO(0x018); /* rq outp */
2258 ZERO(0x01c); /* respq bah */
2259 ZERO(0x024); /* respq outp */
2260 ZERO(0x020); /* respq inp */
2261 ZERO(0x02c); /* test control */
8e7decdb 2262 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2263}
2264
2265#undef ZERO
2266
2267#define ZERO(reg) writel(0, hc_mmio + (reg))
2268static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2269 void __iomem *mmio)
2270{
2271 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2272
2273 ZERO(0x00c);
2274 ZERO(0x010);
2275 ZERO(0x014);
2276
2277}
2278
2279#undef ZERO
2280
2281static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2282 void __iomem *mmio, unsigned int n_hc)
2283{
2284 unsigned int port;
2285
2286 for (port = 0; port < hpriv->n_ports; port++)
2287 mv_soc_reset_hc_port(hpriv, mmio, port);
2288
2289 mv_soc_reset_one_hc(hpriv, mmio);
2290
2291 return 0;
2292}
2293
2294static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2295 void __iomem *mmio)
2296{
2297 return;
2298}
2299
2300static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2301{
2302 return;
2303}
2304
8e7decdb 2305static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2306{
8e7decdb 2307 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2308
8e7decdb 2309 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2310 if (want_gen2i)
8e7decdb
ML		 2311 ifcfg |= (1 << 7); /* enable gen2i speed */
2312 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2313}
2314
e12bef50 2315static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2316 unsigned int port_no)
2317{
2318 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2319
8e7decdb
ML		 2320 /*
2321 * The datasheet warns against setting EDMA_RESET when EDMA is active
2322 * (but doesn't say what the problem might be). So we first try
2323 * to disable the EDMA engine before doing the EDMA_RESET operation.
2324 */
0d8be5cb 2325 mv_stop_edma_engine(port_mmio);
8e7decdb 2326 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2327
b67a1064 2328 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2329 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2330 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2331 }
b67a1064 2332 /*
8e7decdb 2333 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2334 * link, and physical layers. It resets all SATA interface registers
2335 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2336 */
8e7decdb 2337 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2338 udelay(25); /* allow reset propagation */
c9d39130
JG		 2339 writelfl(0, port_mmio + EDMA_CMD_OFS);
2340
2341 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2342
ee9ccdf7 2343 if (IS_GEN_I(hpriv))
c9d39130
JG		 2344 mdelay(1);
2345}
2346
e49856d8 2347static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2348{
e49856d8
ML		 2349 if (sata_pmp_supported(ap)) {
2350 void __iomem *port_mmio = mv_ap_base(ap);
2351 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2352 int old = reg & 0xf;
22374677 2353
e49856d8
ML		 2354 if (old != pmp) {
2355 reg = (reg & ~0xf) | pmp;
2356 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2357 }
22374677 2358 }
20f733e7
BR		 2359}
2360
e49856d8
ML		 2361static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2362 unsigned long deadline)
22374677 2363{
e49856d8
ML		 2364 mv_pmp_select(link->ap, sata_srst_pmp(link));
2365 return sata_std_hardreset(link, class, deadline);
2366}
bdd4ddde 2367
e49856d8
ML		 2368static int mv_softreset(struct ata_link *link, unsigned int *class,
2369 unsigned long deadline)
2370{
2371 mv_pmp_select(link->ap, sata_srst_pmp(link));
2372 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2373}
2374
cc0680a5 2375static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2376 unsigned long deadline)
31961943 2377{
cc0680a5 2378 struct ata_port *ap = link->ap;
bdd4ddde 2379 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2380 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2381 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2382 int rc, attempts = 0, extra = 0;
2383 u32 sstatus;
2384 bool online;
31961943 2385
e12bef50 2386 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2387 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2388
0d8be5cb
ML		 2389 /* Workaround for errata FEr SATA#10 (part 2) */
2390 do {
17c5aab5
ML		 2391 const unsigned long *timing =
2392 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2393
17c5aab5
ML		 2394 rc = sata_link_hardreset(link, timing, deadline + extra,
2395 &online, NULL);
2396 if (rc)
0d8be5cb 2397 return rc;
0d8be5cb
ML		 2398 sata_scr_read(link, SCR_STATUS, &sstatus);
2399 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2400 /* Force 1.5gb/s link speed and try again */
8e7decdb 2401 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2402 if (time_after(jiffies + HZ, deadline))
2403 extra = HZ; /* only extend it once, max */
2404 }
2405 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2406
17c5aab5 2407 return rc;
bdd4ddde
JG		 2408}
2409
bdd4ddde
JG		 2410static void mv_eh_freeze(struct ata_port *ap)
2411{
f351b2d6 2412 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2413 unsigned int shift, hardport, port = ap->port_no;
7368f919 2414 u32 main_irq_mask;
bdd4ddde
JG		 2415
2416 /* FIXME: handle coalescing completion events properly */
2417
1cfd19ae
ML		 2418 mv_stop_edma(ap);
2419 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2420
bdd4ddde 2421 /* disable assertion of portN err, done events */
7368f919
ML		 2422 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2423 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2424 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2425}
2426
2427static void mv_eh_thaw(struct ata_port *ap)
2428{
f351b2d6 2429 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2430 unsigned int shift, hardport, port = ap->port_no;
2431 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2432 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2433 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2434
2435 /* FIXME: handle coalescing completion events properly */
2436
1cfd19ae 2437 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2438
bdd4ddde
JG		 2439 /* clear EDMA errors on this port */
2440 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2441
2442 /* clear pending irq events */
2443 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2444 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2445 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2446
2447 /* enable assertion of portN err, done events */
7368f919
ML		 2448 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2449 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2450 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2451}
2452
05b308e1
BR		 2453/**
2454 * mv_port_init - Perform some early initialization on a single port.
2455 * @port: libata data structure storing shadow register addresses
2456 * @port_mmio: base address of the port
2457 *
2458 * Initialize shadow register mmio addresses, clear outstanding
2459 * interrupts on the port, and unmask interrupts for the future
2460 * start of the port.
2461 *
2462 * LOCKING:
2463 * Inherited from caller.
2464 */
31961943 2465static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2466{
0d5ff566 2467 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2468 unsigned serr_ofs;
2469
8b260248 2470 /* PIO related setup
31961943
BR		 2471 */
2472 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2473 port->error_addr =
31961943
BR		 2474 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2475 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2476 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2477 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2478 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2479 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2480 port->status_addr =
31961943
BR		 2481 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2482 /* special case: control/altstatus doesn't have ATA_REG_ address */
2483 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2484
2485 /* unused: */
8d9db2d2 2486 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2487
31961943
BR		 2488 /* Clear any currently outstanding port interrupt conditions */
2489 serr_ofs = mv_scr_offset(SCR_ERROR);
2490 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2491 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2492
646a4da5
ML		 2493 /* unmask all non-transient EDMA error interrupts */
2494 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2495
8b260248 2496 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2497 readl(port_mmio + EDMA_CFG_OFS),
2498 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2499 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2500}
2501
616d4a98
ML		 2502static unsigned int mv_in_pcix_mode(struct ata_host *host)
2503{
2504 struct mv_host_priv *hpriv = host->private_data;
2505 void __iomem *mmio = hpriv->base;
2506 u32 reg;
2507
2508 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2509 return 0; /* not PCI-X capable */
2510 reg = readl(mmio + MV_PCI_MODE_OFS);
2511 if ((reg & MV_PCI_MODE_MASK) == 0)
2512 return 0; /* conventional PCI mode */
2513 return 1; /* chip is in PCI-X mode */
2514}
2515
2516static int mv_pci_cut_through_okay(struct ata_host *host)
2517{
2518 struct mv_host_priv *hpriv = host->private_data;
2519 void __iomem *mmio = hpriv->base;
2520 u32 reg;
2521
2522 if (!mv_in_pcix_mode(host)) {
2523 reg = readl(mmio + PCI_COMMAND_OFS);
2524 if (reg & PCI_COMMAND_MRDTRIG)
2525 return 0; /* not okay */
2526 }
2527 return 1; /* okay */
2528}
2529
4447d351 2530static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2531{
4447d351
TH		 2532 struct pci_dev *pdev = to_pci_dev(host->dev);
2533 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2534 u32 hp_flags = hpriv->hp_flags;
2535
5796d1c4 2536 switch (board_idx) {
47c2b677
JG		 2537 case chip_5080:
2538 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2539 hp_flags |= MV_HP_GEN_I;
47c2b677 2540
44c10138 2541 switch (pdev->revision) {
47c2b677
JG		 2542 case 0x1:
2543 hp_flags |= MV_HP_ERRATA_50XXB0;
2544 break;
2545 case 0x3:
2546 hp_flags |= MV_HP_ERRATA_50XXB2;
2547 break;
2548 default:
2549 dev_printk(KERN_WARNING, &pdev->dev,
2550 "Applying 50XXB2 workarounds to unknown rev\n");
2551 hp_flags |= MV_HP_ERRATA_50XXB2;
2552 break;
2553 }
2554 break;
2555
bca1c4eb
JG		 2556 case chip_504x:
2557 case chip_508x:
47c2b677 2558 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2559 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2560
44c10138 2561 switch (pdev->revision) {
47c2b677
JG		 2562 case 0x0:
2563 hp_flags |= MV_HP_ERRATA_50XXB0;
2564 break;
2565 case 0x3:
2566 hp_flags |= MV_HP_ERRATA_50XXB2;
2567 break;
2568 default:
2569 dev_printk(KERN_WARNING, &pdev->dev,
2570 "Applying B2 workarounds to unknown rev\n");
2571 hp_flags |= MV_HP_ERRATA_50XXB2;
2572 break;
bca1c4eb
JG		 2573 }
2574 break;
2575
2576 case chip_604x:
2577 case chip_608x:
47c2b677 2578 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2579 hp_flags |= MV_HP_GEN_II;
47c2b677 2580
44c10138 2581 switch (pdev->revision) {
47c2b677
JG		 2582 case 0x7:
2583 hp_flags |= MV_HP_ERRATA_60X1B2;
2584 break;
2585 case 0x9:
2586 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2587 break;
2588 default:
2589 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2590 "Applying B2 workarounds to unknown rev\n");
2591 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2592 break;
2593 }
2594 break;
2595
e4e7b892 2596 case chip_7042:
616d4a98 2597 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2598 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2599 (pdev->device == 0x2300 || pdev->device == 0x2310))
2600 {
4e520033
ML		 2601 /*
2602 * Highpoint RocketRAID PCIe 23xx series cards:
2603 *
2604 * Unconfigured drives are treated as "Legacy"
2605 * by the BIOS, and it overwrites sector 8 with
2606 * a "Lgcy" metadata block prior to Linux boot.
2607 *
2608 * Configured drives (RAID or JBOD) leave sector 8
2609 * alone, but instead overwrite a high numbered
2610 * sector for the RAID metadata. This sector can
2611 * be determined exactly, by truncating the physical
2612 * drive capacity to a nice even GB value.
2613 *
2614 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2615 *
2616 * Warn the user, lest they think we're just buggy.
2617 */
2618 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2619 " BIOS CORRUPTS DATA on all attached drives,"
2620 " regardless of if/how they are configured."
2621 " BEWARE!\n");
2622 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2623 " use sectors 8-9 on \"Legacy\" drives,"
2624 " and avoid the final two gigabytes on"
2625 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2626 }
8e7decdb 2627 /* drop through */
e4e7b892
JG		 2628 case chip_6042:
2629 hpriv->ops = &mv6xxx_ops;
e4e7b892 2630 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2631 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2632 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2633
44c10138 2634 switch (pdev->revision) {
e4e7b892
JG		 2635 case 0x0:
2636 hp_flags |= MV_HP_ERRATA_XX42A0;
2637 break;
2638 case 0x1:
2639 hp_flags |= MV_HP_ERRATA_60X1C0;
2640 break;
2641 default:
2642 dev_printk(KERN_WARNING, &pdev->dev,
2643 "Applying 60X1C0 workarounds to unknown rev\n");
2644 hp_flags |= MV_HP_ERRATA_60X1C0;
2645 break;
2646 }
2647 break;
f351b2d6
SB		 2648 case chip_soc:
2649 hpriv->ops = &mv_soc_ops;
2650 hp_flags |= MV_HP_ERRATA_60X1C0;
2651 break;
e4e7b892 2652
bca1c4eb 2653 default:
f351b2d6 2654 dev_printk(KERN_ERR, host->dev,
5796d1c4 2655 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2656 return 1;
2657 }
2658
2659 hpriv->hp_flags = hp_flags;
02a121da
ML		 2660 if (hp_flags & MV_HP_PCIE) {
2661 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2662 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2663 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2664 } else {
2665 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2666 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2667 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2668 }
bca1c4eb
JG		 2669
2670 return 0;
2671}
2672
05b308e1 2673/**
47c2b677 2674 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 2675 * @host: ATA host to initialize
2676 * @board_idx: controller index
05b308e1
BR		 2677 *
2678 * If possible, do an early global reset of the host. Then do
2679 * our port init and clear/unmask all/relevant host interrupts.
2680 *
2681 * LOCKING:
2682 * Inherited from caller.
2683 */
4447d351 2684static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 2685{
2686 int rc = 0, n_hc, port, hc;
4447d351 2687 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 2688 void __iomem *mmio = hpriv->base;
47c2b677 2689
4447d351 2690 rc = mv_chip_id(host, board_idx);
bca1c4eb 2691 if (rc)
352fab70 2692 goto done;
f351b2d6
SB		 2693
2694 if (HAS_PCI(host)) {
7368f919
ML		 2695 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
2696 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2697 } else {
7368f919
ML		 2698 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
2699 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2700 }
352fab70
ML		 2701
2702 /* global interrupt mask: 0 == mask everything */
7368f919 2703 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 2704
4447d351 2705 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 2706
4447d351 2707 for (port = 0; port < host->n_ports; port++)
47c2b677 2708 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2709
c9d39130 2710 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2711 if (rc)
20f733e7 2712 goto done;
20f733e7 2713
522479fb 2714 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 2715 hpriv->ops->reset_bus(host, mmio);
47c2b677 2716 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 2717
4447d351 2718 for (port = 0; port < host->n_ports; port++) {
cbcdd875 2719 struct ata_port *ap = host->ports[port];
2a47ce06 2720 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 2721
2722 mv_port_init(&ap->ioaddr, port_mmio);
2723
7bb3c529 2724#ifdef CONFIG_PCI
f351b2d6
SB		 2725 if (HAS_PCI(host)) {
2726 unsigned int offset = port_mmio - mmio;
2727 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2728 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2729 }
7bb3c529 2730#endif
20f733e7
BR		 2731 }
2732
2733 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2734 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2735
2736 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2737 "(before clear)=0x%08x\n", hc,
2738 readl(hc_mmio + HC_CFG_OFS),
2739 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2740
2741 /* Clear any currently outstanding hc interrupt conditions */
2742 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2743 }
2744
f351b2d6
SB		 2745 if (HAS_PCI(host)) {
2746 /* Clear any currently outstanding host interrupt conditions */
2747 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 2748
f351b2d6
SB		 2749 /* and unmask interrupt generation for host regs */
2750 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2751 if (IS_GEN_I(hpriv))
2752 writelfl(~HC_MAIN_MASKED_IRQS_5,
7368f919 2753 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2754 else
2755 writelfl(~HC_MAIN_MASKED_IRQS,
7368f919 2756 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2757
2758 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2759 "PCI int cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2760 readl(hpriv->main_irq_cause_addr),
2761 readl(hpriv->main_irq_mask_addr),
f351b2d6
SB		 2762 readl(mmio + hpriv->irq_cause_ofs),
2763 readl(mmio + hpriv->irq_mask_ofs));
2764 } else {
2765 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
7368f919 2766 hpriv->main_irq_mask_addr);
f351b2d6 2767 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2768 readl(hpriv->main_irq_cause_addr),
2769 readl(hpriv->main_irq_mask_addr));
f351b2d6
SB		 2770 }
2771done:
2772 return rc;
2773}
fb621e2f 2774
fbf14e2f
BB		 2775static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2776{
2777 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
2778 MV_CRQB_Q_SZ, 0);
2779 if (!hpriv->crqb_pool)
2780 return -ENOMEM;
2781
2782 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
2783 MV_CRPB_Q_SZ, 0);
2784 if (!hpriv->crpb_pool)
2785 return -ENOMEM;
2786
2787 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
2788 MV_SG_TBL_SZ, 0);
2789 if (!hpriv->sg_tbl_pool)
2790 return -ENOMEM;
2791
2792 return 0;
2793}
2794
15a32632
LB		 2795static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
2796 struct mbus_dram_target_info *dram)
2797{
2798 int i;
2799
2800 for (i = 0; i < 4; i++) {
2801 writel(0, hpriv->base + WINDOW_CTRL(i));
2802 writel(0, hpriv->base + WINDOW_BASE(i));
2803 }
2804
2805 for (i = 0; i < dram->num_cs; i++) {
2806 struct mbus_dram_window *cs = dram->cs + i;
2807
2808 writel(((cs->size - 1) & 0xffff0000) |
2809 (cs->mbus_attr << 8) |
2810 (dram->mbus_dram_target_id << 4) | 1,
2811 hpriv->base + WINDOW_CTRL(i));
2812 writel(cs->base, hpriv->base + WINDOW_BASE(i));
2813 }
2814}
2815
f351b2d6
SB		 2816/**
2817 * mv_platform_probe - handle a positive probe of an soc Marvell
2818 * host
2819 * @pdev: platform device found
2820 *
2821 * LOCKING:
2822 * Inherited from caller.
2823 */
2824static int mv_platform_probe(struct platform_device *pdev)
2825{
2826 static int printed_version;
2827 const struct mv_sata_platform_data *mv_platform_data;
2828 const struct ata_port_info *ppi[] =
2829 { &mv_port_info[chip_soc], NULL };
2830 struct ata_host *host;
2831 struct mv_host_priv *hpriv;
2832 struct resource *res;
2833 int n_ports, rc;
20f733e7 2834
f351b2d6
SB		 2835 if (!printed_version++)
2836 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 2837
f351b2d6
SB		 2838 /*
2839 * Simple resource validation ..
2840 */
2841 if (unlikely(pdev->num_resources != 2)) {
2842 dev_err(&pdev->dev, "invalid number of resources\n");
2843 return -EINVAL;
2844 }
2845
2846 /*
2847 * Get the register base first
2848 */
2849 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2850 if (res == NULL)
2851 return -EINVAL;
2852
2853 /* allocate host */
2854 mv_platform_data = pdev->dev.platform_data;
2855 n_ports = mv_platform_data->n_ports;
2856
2857 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2858 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2859
2860 if (!host || !hpriv)
2861 return -ENOMEM;
2862 host->private_data = hpriv;
2863 hpriv->n_ports = n_ports;
2864
2865 host->iomap = NULL;
f1cb0ea1
SB		 2866 hpriv->base = devm_ioremap(&pdev->dev, res->start,
2867 res->end - res->start + 1);
f351b2d6
SB		 2868 hpriv->base -= MV_SATAHC0_REG_BASE;
2869
15a32632
LB		 2870 /*
2871 * (Re-)program MBUS remapping windows if we are asked to.
2872 */
2873 if (mv_platform_data->dram != NULL)
2874 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
2875
fbf14e2f
BB		 2876 rc = mv_create_dma_pools(hpriv, &pdev->dev);
2877 if (rc)
2878 return rc;
2879
f351b2d6
SB		 2880 /* initialize adapter */
2881 rc = mv_init_host(host, chip_soc);
2882 if (rc)
2883 return rc;
2884
2885 dev_printk(KERN_INFO, &pdev->dev,
2886 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
2887 host->n_ports);
2888
2889 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
2890 IRQF_SHARED, &mv6_sht);
2891}
2892
2893/*
2894 *
2895 * mv_platform_remove - unplug a platform interface
2896 * @pdev: platform device
2897 *
2898 * A platform bus SATA device has been unplugged. Perform the needed
2899 * cleanup. Also called on module unload for any active devices.
2900 */
2901static int __devexit mv_platform_remove(struct platform_device *pdev)
2902{
2903 struct device *dev = &pdev->dev;
2904 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 2905
2906 ata_host_detach(host);
f351b2d6 2907 return 0;
20f733e7
BR		 2908}
2909
f351b2d6
SB		 2910static struct platform_driver mv_platform_driver = {
2911 .probe = mv_platform_probe,
2912 .remove = __devexit_p(mv_platform_remove),
2913 .driver = {
2914 .name = DRV_NAME,
2915 .owner = THIS_MODULE,
2916 },
2917};
2918
2919
7bb3c529 2920#ifdef CONFIG_PCI
f351b2d6
SB		 2921static int mv_pci_init_one(struct pci_dev *pdev,
2922 const struct pci_device_id *ent);
2923
7bb3c529
SB		 2924
2925static struct pci_driver mv_pci_driver = {
2926 .name = DRV_NAME,
2927 .id_table = mv_pci_tbl,
f351b2d6 2928 .probe = mv_pci_init_one,
7bb3c529
SB		 2929 .remove = ata_pci_remove_one,
2930};
2931
2932/*
2933 * module options
2934 */
2935static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
2936
2937
2938/* move to PCI layer or libata core? */
2939static int pci_go_64(struct pci_dev *pdev)
2940{
2941 int rc;
2942
2943 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2944 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2945 if (rc) {
2946 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2947 if (rc) {
2948 dev_printk(KERN_ERR, &pdev->dev,
2949 "64-bit DMA enable failed\n");
2950 return rc;
2951 }
2952 }
2953 } else {
2954 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2955 if (rc) {
2956 dev_printk(KERN_ERR, &pdev->dev,
2957 "32-bit DMA enable failed\n");
2958 return rc;
2959 }
2960 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2961 if (rc) {
2962 dev_printk(KERN_ERR, &pdev->dev,
2963 "32-bit consistent DMA enable failed\n");
2964 return rc;
2965 }
2966 }
2967
2968 return rc;
2969}
2970
05b308e1
BR		 2971/**
2972 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 2973 * @host: ATA host to print info about
05b308e1
BR		 2974 *
2975 * FIXME: complete this.
2976 *
2977 * LOCKING:
2978 * Inherited from caller.
2979 */
4447d351 2980static void mv_print_info(struct ata_host *host)
31961943 2981{
4447d351
TH		 2982 struct pci_dev *pdev = to_pci_dev(host->dev);
2983 struct mv_host_priv *hpriv = host->private_data;
44c10138 2984 u8 scc;
c1e4fe71 2985 const char *scc_s, *gen;
31961943
BR		 2986
2987 /* Use this to determine the HW stepping of the chip so we know
2988 * what errata to workaround
2989 */
31961943
BR		 2990 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2991 if (scc == 0)
2992 scc_s = "SCSI";
2993 else if (scc == 0x01)
2994 scc_s = "RAID";
2995 else
c1e4fe71
JG		 2996 scc_s = "?";
2997
2998 if (IS_GEN_I(hpriv))
2999 gen = "I";
3000 else if (IS_GEN_II(hpriv))
3001 gen = "II";
3002 else if (IS_GEN_IIE(hpriv))
3003 gen = "IIE";
3004 else
3005 gen = "?";
31961943 3006
a9524a76 3007 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3008 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3009 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3010 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3011}
3012
05b308e1 3013/**
f351b2d6 3014 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3015 * @pdev: PCI device found
3016 * @ent: PCI device ID entry for the matched host
3017 *
3018 * LOCKING:
3019 * Inherited from caller.
3020 */
f351b2d6
SB		 3021static int mv_pci_init_one(struct pci_dev *pdev,
3022 const struct pci_device_id *ent)
20f733e7 3023{
2dcb407e 3024 static int printed_version;
20f733e7 3025 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3026 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3027 struct ata_host *host;
3028 struct mv_host_priv *hpriv;
3029 int n_ports, rc;
20f733e7 3030
a9524a76
JG		 3031 if (!printed_version++)
3032 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3033
4447d351
TH		 3034 /* allocate host */
3035 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3036
3037 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3038 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3039 if (!host || !hpriv)
3040 return -ENOMEM;
3041 host->private_data = hpriv;
f351b2d6 3042 hpriv->n_ports = n_ports;
4447d351
TH		 3043
3044 /* acquire resources */
24dc5f33
TH		 3045 rc = pcim_enable_device(pdev);
3046 if (rc)
20f733e7 3047 return rc;
20f733e7 3048
0d5ff566
TH		 3049 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3050 if (rc == -EBUSY)
24dc5f33 3051 pcim_pin_device(pdev);
0d5ff566 3052 if (rc)
24dc5f33 3053 return rc;
4447d351 3054 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3055 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3056
d88184fb
JG		 3057 rc = pci_go_64(pdev);
3058 if (rc)
3059 return rc;
3060
da2fa9ba
ML		 3061 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3062 if (rc)
3063 return rc;
3064
20f733e7 3065 /* initialize adapter */
4447d351 3066 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3067 if (rc)
3068 return rc;
20f733e7 3069
31961943 3070 /* Enable interrupts */
6a59dcf8 3071 if (msi && pci_enable_msi(pdev))
31961943 3072 pci_intx(pdev, 1);
20f733e7 3073
31961943 3074 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3075 mv_print_info(host);
20f733e7 3076
4447d351 3077 pci_set_master(pdev);
ea8b4db9 3078 pci_try_set_mwi(pdev);
4447d351 3079 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3080 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3081}
7bb3c529 3082#endif
20f733e7 3083
f351b2d6
SB		 3084static int mv_platform_probe(struct platform_device *pdev);
3085static int __devexit mv_platform_remove(struct platform_device *pdev);
3086
20f733e7
BR		 3087static int __init mv_init(void)
3088{
7bb3c529
SB		 3089 int rc = -ENODEV;
3090#ifdef CONFIG_PCI
3091 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3092 if (rc < 0)
3093 return rc;
3094#endif
3095 rc = platform_driver_register(&mv_platform_driver);
3096
3097#ifdef CONFIG_PCI
3098 if (rc < 0)
3099 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3100#endif
3101 return rc;
20f733e7
BR		 3102}
3103
3104static void __exit mv_exit(void)
3105{
7bb3c529 3106#ifdef CONFIG_PCI
20f733e7 3107 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3108#endif
f351b2d6 3109 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3110}
3111
3112MODULE_AUTHOR("Brett Russ");
3113MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3114MODULE_LICENSE("GPL");
3115MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3116MODULE_VERSION(DRV_VERSION);
17c5aab5 3117MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3118
7bb3c529 3119#ifdef CONFIG_PCI
ddef9bb3
JG		 3120module_param(msi, int, 0444);
3121MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3122#endif
ddef9bb3 3123
20f733e7
BR		 3124module_init(mv_init);
3125module_exit(mv_exit);
Linux kernel - Deliverables
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