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sata_mv: always do softreset
[deliverable/linux.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
c46938cc 68#include <linux/bitops.h>
20f733e7 69#include <scsi/scsi_host.h>
193515d5 70#include <scsi/scsi_cmnd.h>
6c08772e 71#include <scsi/scsi_device.h>
20f733e7 72#include <linux/libata.h>
20f733e7
BR		 73
74#define DRV_NAME "sata_mv"
1fd2e1c2 75#define DRV_VERSION "1.20"
20f733e7
BR		 76
77enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85
86 MV_PCI_REG_BASE = 0,
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93
20f733e7 94 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 98
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103
31961943
BR		 104 MV_MAX_Q_DEPTH = 32,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 */
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 113 MV_MAX_SG_CT = 256,
31961943 114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 115
352fab70 116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 117 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 121
122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 125 /* SoC integrated controllers, no PCI interface */
e12bef50 126 MV_FLAG_SOC = (1 << 28),
7bb3c529 127
c5d3e45a 128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
47c2b677 131 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 132
31961943
BR		 133 CRQB_FLAG_READ = (1 << 0),
134 CRQB_TAG_SHIFT = 1,
c5d3e45a 135 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 136 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 137 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 138 CRQB_CMD_ADDR_SHIFT = 8,
139 CRQB_CMD_CS = (0x2 << 11),
140 CRQB_CMD_LAST = (1 << 15),
141
142 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 143 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
144 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 145
146 EPRD_FLAG_END_OF_TBL = (1 << 31),
147
20f733e7
BR		 148 /* PCI interface registers */
149
31961943 150 PCI_COMMAND_OFS = 0xc00,
8e7decdb 151 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 152
20f733e7
BR		 153 PCI_MAIN_CMD_STS_OFS = 0xd30,
154 STOP_PCI_MASTER = (1 << 2),
155 PCI_MASTER_EMPTY = (1 << 3),
156 GLOB_SFT_RST = (1 << 4),
157
8e7decdb
ML		 158 MV_PCI_MODE_OFS = 0xd00,
159 MV_PCI_MODE_MASK = 0x30,
160
522479fb
JG		 161 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
162 MV_PCI_DISC_TIMER = 0xd04,
163 MV_PCI_MSI_TRIGGER = 0xc38,
164 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 165 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 166 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
167 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
168 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
169 MV_PCI_ERR_COMMAND = 0x1d50,
170
02a121da
ML		 171 PCI_IRQ_CAUSE_OFS = 0x1d58,
172 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 173 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
174
02a121da
ML		 175 PCIE_IRQ_CAUSE_OFS = 0x1900,
176 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 177 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 178
7368f919
ML		 179 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
180 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
181 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
182 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
183 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 184 ERR_IRQ = (1 << 0), /* shift by port # */
185 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 186 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
187 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
188 PCI_ERR = (1 << 18),
189 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
190 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 191 PORTS_0_3_COAL_DONE = (1 << 8),
192 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 193 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
194 GPIO_INT = (1 << 22),
195 SELF_INT = (1 << 23),
196 TWSI_INT = (1 << 24),
197 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 198 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 199 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
8b260248 200 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
f9f7fe01 201 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
20f733e7
BR		 202 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
203 HC_MAIN_RSVD),
fb621e2f
JG		 204 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
205 HC_MAIN_RSVD_5),
f351b2d6 206 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
20f733e7
BR		 207
208 /* SATAHC registers */
209 HC_CFG_OFS = 0,
210
211 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 212 DMA_IRQ = (1 << 0), /* shift by port # */
213 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 214 DEV_IRQ = (1 << 8), /* shift by port # */
215
216 /* Shadow block registers */
31961943
BR		 217 SHD_BLK_OFS = 0x100,
218 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 219
220 /* SATA registers */
221 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
222 SATA_ACTIVE_OFS = 0x350,
0c58912e 223 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
17c5aab5 224
e12bef50 225 LTMODE_OFS = 0x30c,
17c5aab5
ML		 226 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
227
47c2b677 228 PHY_MODE3 = 0x310,
bca1c4eb
JG		 229 PHY_MODE4 = 0x314,
230 PHY_MODE2 = 0x330,
e12bef50 231 SATA_IFCTL_OFS = 0x344,
8e7decdb 232 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 233 SATA_IFSTAT_OFS = 0x34c,
234 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 235
8e7decdb
ML		 236 FISCFG_OFS = 0x360,
237 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
238 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 239
c9d39130 240 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 241 MV5_LTMODE_OFS = 0x30,
242 MV5_PHY_CTL_OFS = 0x0C,
243 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 244
245 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 246
247 /* Port registers */
248 EDMA_CFG_OFS = 0,
0c58912e
ML		 249 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
250 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
251 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
252 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
253 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 254 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
255 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 256
257 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
258 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 259 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
260 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
261 EDMA_ERR_DEV = (1 << 2), /* device error */
262 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
263 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
264 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 265 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
266 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 267 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 268 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 269 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
270 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
271 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
272 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 273
6c1153e0 274 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 275 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
276 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
277 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
278 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279
6c1153e0 280 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 281
6c1153e0 282 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 283 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
284 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
285 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
286 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
287 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288
6c1153e0 289 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 290
6c1153e0 291 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 292 EDMA_ERR_OVERRUN_5 = (1 << 5),
293 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 294
295 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
296 EDMA_ERR_LNK_CTRL_RX_1 |
297 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 298 EDMA_ERR_LNK_CTRL_TX,
646a4da5 299
bdd4ddde
JG		 300 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
301 EDMA_ERR_PRD_PAR |
302 EDMA_ERR_DEV_DCON |
303 EDMA_ERR_DEV_CON |
304 EDMA_ERR_SERR |
305 EDMA_ERR_SELF_DIS |
6c1153e0 306 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 307 EDMA_ERR_CRPB_PAR |
308 EDMA_ERR_INTRL_PAR |
309 EDMA_ERR_IORDY |
310 EDMA_ERR_LNK_CTRL_RX_2 |
311 EDMA_ERR_LNK_DATA_RX |
312 EDMA_ERR_LNK_DATA_TX |
313 EDMA_ERR_TRANS_PROTO,
e12bef50 314
bdd4ddde
JG		 315 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
316 EDMA_ERR_PRD_PAR |
317 EDMA_ERR_DEV_DCON |
318 EDMA_ERR_DEV_CON |
319 EDMA_ERR_OVERRUN_5 |
320 EDMA_ERR_UNDERRUN_5 |
321 EDMA_ERR_SELF_DIS_5 |
6c1153e0 322 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 323 EDMA_ERR_CRPB_PAR |
324 EDMA_ERR_INTRL_PAR |
325 EDMA_ERR_IORDY,
20f733e7 326
31961943
BR		 327 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
328 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 329
330 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
331 EDMA_REQ_Q_PTR_SHIFT = 5,
332
333 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
334 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
335 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 336 EDMA_RSP_Q_PTR_SHIFT = 3,
337
0ea9e179
JG		 338 EDMA_CMD_OFS = 0x28, /* EDMA command register */
339 EDMA_EN = (1 << 0), /* enable EDMA */
340 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 341 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
342
343 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
344 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
345 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 346
8e7decdb
ML		 347 EDMA_IORDY_TMOUT_OFS = 0x34,
348 EDMA_ARB_CFG_OFS = 0x38,
349
350 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 351
352fab70
ML		 352 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
353
31961943
BR		 354 /* Host private flags (hp_flags) */
355 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 356 MV_HP_ERRATA_50XXB0 = (1 << 1),
357 MV_HP_ERRATA_50XXB2 = (1 << 2),
358 MV_HP_ERRATA_60X1B2 = (1 << 3),
359 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 360 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 361 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
362 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
363 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 364 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 365 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 366
31961943 367 /* Port private flags (pp_flags) */
0ea9e179 368 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 369 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 370 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 371 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 372};
373
ee9ccdf7
JG		 374#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
375#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 376#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 377#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 378#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 379
15a32632
LB		 380#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
381#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
382
095fec88 383enum {
baf14aa1
JG		 384 /* DMA boundary 0xffff is required by the s/g splitting
385 * we need on /length/ in mv_fill-sg().
386 */
387 MV_DMA_BOUNDARY = 0xffffU,
095fec88 388
0ea9e179
JG		 389 /* mask of register bits containing lower 32 bits
390 * of EDMA request queue DMA address
391 */
095fec88
JG		 392 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
393
0ea9e179 394 /* ditto, for response queue */
095fec88
JG		 395 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
396};
397
522479fb
JG		 398enum chip_type {
399 chip_504x,
400 chip_508x,
401 chip_5080,
402 chip_604x,
403 chip_608x,
e4e7b892
JG		 404 chip_6042,
405 chip_7042,
f351b2d6 406 chip_soc,
522479fb
JG		 407};
408
31961943
BR		 409/* Command ReQuest Block: 32B */
410struct mv_crqb {
e1469874
ML		 411 __le32 sg_addr;
412 __le32 sg_addr_hi;
413 __le16 ctrl_flags;
414 __le16 ata_cmd[11];
31961943 415};
20f733e7 416
e4e7b892 417struct mv_crqb_iie {
e1469874
ML		 418 __le32 addr;
419 __le32 addr_hi;
420 __le32 flags;
421 __le32 len;
422 __le32 ata_cmd[4];
e4e7b892
JG		 423};
424
31961943
BR		 425/* Command ResPonse Block: 8B */
426struct mv_crpb {
e1469874
ML		 427 __le16 id;
428 __le16 flags;
429 __le32 tmstmp;
20f733e7
BR		 430};
431
31961943
BR		 432/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
433struct mv_sg {
e1469874
ML		 434 __le32 addr;
435 __le32 flags_size;
436 __le32 addr_hi;
437 __le32 reserved;
31961943 438};
20f733e7 439
31961943
BR		 440struct mv_port_priv {
441 struct mv_crqb *crqb;
442 dma_addr_t crqb_dma;
443 struct mv_crpb *crpb;
444 dma_addr_t crpb_dma;
eb73d558
ML		 445 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
446 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 447
448 unsigned int req_idx;
449 unsigned int resp_idx;
450
31961943 451 u32 pp_flags;
29d187bb 452 unsigned int delayed_eh_pmp_map;
31961943
BR		 453};
454
bca1c4eb
JG		 455struct mv_port_signal {
456 u32 amps;
457 u32 pre;
458};
459
02a121da
ML		 460struct mv_host_priv {
461 u32 hp_flags;
462 struct mv_port_signal signal[8];
463 const struct mv_hw_ops *ops;
f351b2d6
SB		 464 int n_ports;
465 void __iomem *base;
7368f919
ML		 466 void __iomem *main_irq_cause_addr;
467 void __iomem *main_irq_mask_addr;
02a121da
ML		 468 u32 irq_cause_ofs;
469 u32 irq_mask_ofs;
470 u32 unmask_all_irqs;
da2fa9ba
ML		 471 /*
472 * These consistent DMA memory pools give us guaranteed
473 * alignment for hardware-accessed data structures,
474 * and less memory waste in accomplishing the alignment.
475 */
476 struct dma_pool *crqb_pool;
477 struct dma_pool *crpb_pool;
478 struct dma_pool *sg_tbl_pool;
02a121da
ML		 479};
480
47c2b677 481struct mv_hw_ops {
2a47ce06
JG		 482 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
483 unsigned int port);
47c2b677
JG		 484 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
485 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
486 void __iomem *mmio);
c9d39130
JG		 487 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 unsigned int n_hc);
522479fb 489 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 490 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 491};
492
da3dbb17
TH		 493static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
494static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
495static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
496static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 497static int mv_port_start(struct ata_port *ap);
498static void mv_port_stop(struct ata_port *ap);
3e4a1391 499static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 500static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 501static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 502static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 503static int mv_hardreset(struct ata_link *link, unsigned int *class,
504 unsigned long deadline);
bdd4ddde
JG		 505static void mv_eh_freeze(struct ata_port *ap);
506static void mv_eh_thaw(struct ata_port *ap);
f273827e 507static void mv6_dev_config(struct ata_device *dev);
20f733e7 508
2a47ce06
JG		 509static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
510 unsigned int port);
47c2b677
JG		 511static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
512static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
513 void __iomem *mmio);
c9d39130
JG		 514static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
515 unsigned int n_hc);
522479fb 516static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 517static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 518
2a47ce06
JG		 519static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
520 unsigned int port);
47c2b677
JG		 521static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
522static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
523 void __iomem *mmio);
c9d39130
JG		 524static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
525 unsigned int n_hc);
522479fb 526static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 527static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
528 void __iomem *mmio);
529static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
530 void __iomem *mmio);
531static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
532 void __iomem *mmio, unsigned int n_hc);
533static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
534 void __iomem *mmio);
535static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 536static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 537static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 538 unsigned int port_no);
e12bef50 539static int mv_stop_edma(struct ata_port *ap);
b562468c 540static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 541static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 542
e49856d8
ML		 543static void mv_pmp_select(struct ata_port *ap, int pmp);
544static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
545 unsigned long deadline);
546static int mv_softreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline);
29d187bb 548static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 549static void mv_process_crpb_entries(struct ata_port *ap,
550 struct mv_port_priv *pp);
47c2b677 551
eb73d558
ML		 552/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
553 * because we have to allow room for worst case splitting of
554 * PRDs for 64K boundaries in mv_fill_sg().
555 */
c5d3e45a 556static struct scsi_host_template mv5_sht = {
68d1d07b 557 ATA_BASE_SHT(DRV_NAME),
baf14aa1 558 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 559 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 560};
561
562static struct scsi_host_template mv6_sht = {
68d1d07b 563 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 564 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 565 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 566 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 567};
568
029cfd6b
TH		 569static struct ata_port_operations mv5_ops = {
570 .inherits = &ata_sff_port_ops,
c9d39130 571
3e4a1391 572 .qc_defer = mv_qc_defer,
c9d39130
JG		 573 .qc_prep = mv_qc_prep,
574 .qc_issue = mv_qc_issue,
c9d39130 575
bdd4ddde
JG		 576 .freeze = mv_eh_freeze,
577 .thaw = mv_eh_thaw,
a1efdaba 578 .hardreset = mv_hardreset,
a1efdaba 579 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 580 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 581
c9d39130
JG		 582 .scr_read = mv5_scr_read,
583 .scr_write = mv5_scr_write,
584
585 .port_start = mv_port_start,
586 .port_stop = mv_port_stop,
c9d39130
JG		 587};
588
029cfd6b
TH		 589static struct ata_port_operations mv6_ops = {
590 .inherits = &mv5_ops,
f273827e 591 .dev_config = mv6_dev_config,
20f733e7
BR		 592 .scr_read = mv_scr_read,
593 .scr_write = mv_scr_write,
594
e49856d8
ML		 595 .pmp_hardreset = mv_pmp_hardreset,
596 .pmp_softreset = mv_softreset,
597 .softreset = mv_softreset,
29d187bb 598 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 599};
600
029cfd6b
TH		 601static struct ata_port_operations mv_iie_ops = {
602 .inherits = &mv6_ops,
603 .dev_config = ATA_OP_NULL,
e4e7b892 604 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 605};
606
98ac62de 607static const struct ata_port_info mv_port_info[] = {
20f733e7 608 { /* chip_504x */
cca3974e 609 .flags = MV_COMMON_FLAGS,
31961943 610 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 611 .udma_mask = ATA_UDMA6,
c9d39130 612 .port_ops = &mv5_ops,
20f733e7
BR		 613 },
614 { /* chip_508x */
c5d3e45a 615 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 616 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 617 .udma_mask = ATA_UDMA6,
c9d39130 618 .port_ops = &mv5_ops,
20f733e7 619 },
47c2b677 620 { /* chip_5080 */
c5d3e45a 621 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 622 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 623 .udma_mask = ATA_UDMA6,
c9d39130 624 .port_ops = &mv5_ops,
47c2b677 625 },
20f733e7 626 { /* chip_604x */
138bfdd0 627 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 628 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 629 ATA_FLAG_NCQ,
31961943 630 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 631 .udma_mask = ATA_UDMA6,
c9d39130 632 .port_ops = &mv6_ops,
20f733e7
BR		 633 },
634 { /* chip_608x */
c5d3e45a 635 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 636 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 637 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 638 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 639 .udma_mask = ATA_UDMA6,
c9d39130 640 .port_ops = &mv6_ops,
20f733e7 641 },
e4e7b892 642 { /* chip_6042 */
138bfdd0 643 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 644 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 645 ATA_FLAG_NCQ,
e4e7b892 646 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 647 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 648 .port_ops = &mv_iie_ops,
649 },
650 { /* chip_7042 */
138bfdd0 651 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 652 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 653 ATA_FLAG_NCQ,
e4e7b892 654 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 655 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 656 .port_ops = &mv_iie_ops,
657 },
f351b2d6 658 { /* chip_soc */
02c1f32f 659 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 660 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
02c1f32f 661 ATA_FLAG_NCQ | MV_FLAG_SOC,
17c5aab5
ML		 662 .pio_mask = 0x1f, /* pio0-4 */
663 .udma_mask = ATA_UDMA6,
664 .port_ops = &mv_iie_ops,
f351b2d6 665 },
20f733e7
BR		 666};
667
3b7d697d 668static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 669 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
670 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
671 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
672 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 673 /* RocketRAID 1740/174x have different identifiers */
674 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
675 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 676
677 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
678 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
679 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
680 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
681 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
682
683 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
684
d9f9c6bc
FA		 685 /* Adaptec 1430SA */
686 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
687
02a121da 688 /* Marvell 7042 support */
6a3d586d
MT		 689 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
690
02a121da
ML		 691 /* Highpoint RocketRAID PCIe series */
692 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
693 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
694
2d2744fc 695 { } /* terminate list */
20f733e7
BR		 696};
697
47c2b677
JG		 698static const struct mv_hw_ops mv5xxx_ops = {
699 .phy_errata = mv5_phy_errata,
700 .enable_leds = mv5_enable_leds,
701 .read_preamp = mv5_read_preamp,
702 .reset_hc = mv5_reset_hc,
522479fb
JG		 703 .reset_flash = mv5_reset_flash,
704 .reset_bus = mv5_reset_bus,
47c2b677
JG		 705};
706
707static const struct mv_hw_ops mv6xxx_ops = {
708 .phy_errata = mv6_phy_errata,
709 .enable_leds = mv6_enable_leds,
710 .read_preamp = mv6_read_preamp,
711 .reset_hc = mv6_reset_hc,
522479fb
JG		 712 .reset_flash = mv6_reset_flash,
713 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 714};
715
f351b2d6
SB		 716static const struct mv_hw_ops mv_soc_ops = {
717 .phy_errata = mv6_phy_errata,
718 .enable_leds = mv_soc_enable_leds,
719 .read_preamp = mv_soc_read_preamp,
720 .reset_hc = mv_soc_reset_hc,
721 .reset_flash = mv_soc_reset_flash,
722 .reset_bus = mv_soc_reset_bus,
723};
724
20f733e7
BR		 725/*
726 * Functions
727 */
728
729static inline void writelfl(unsigned long data, void __iomem *addr)
730{
731 writel(data, addr);
732 (void) readl(addr); /* flush to avoid PCI posted write */
733}
734
c9d39130
JG		 735static inline unsigned int mv_hc_from_port(unsigned int port)
736{
737 return port >> MV_PORT_HC_SHIFT;
738}
739
740static inline unsigned int mv_hardport_from_port(unsigned int port)
741{
742 return port & MV_PORT_MASK;
743}
744
1cfd19ae
ML		 745/*
746 * Consolidate some rather tricky bit shift calculations.
747 * This is hot-path stuff, so not a function.
748 * Simple code, with two return values, so macro rather than inline.
749 *
750 * port is the sole input, in range 0..7.
7368f919
ML		 751 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
752 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 753 *
754 * Note that port and hardport may be the same variable in some cases.
755 */
756#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
757{ \
758 shift = mv_hc_from_port(port) * HC_SHIFT; \
759 hardport = mv_hardport_from_port(port); \
760 shift += hardport * 2; \
761}
762
352fab70
ML		 763static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
764{
765 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
766}
767
c9d39130
JG		 768static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
769 unsigned int port)
770{
771 return mv_hc_base(base, mv_hc_from_port(port));
772}
773
20f733e7
BR		 774static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
775{
c9d39130 776 return mv_hc_base_from_port(base, port) +
8b260248 777 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 778 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 779}
780
e12bef50
ML		 781static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
782{
783 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
784 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
785
786 return hc_mmio + ofs;
787}
788
f351b2d6
SB		 789static inline void __iomem *mv_host_base(struct ata_host *host)
790{
791 struct mv_host_priv *hpriv = host->private_data;
792 return hpriv->base;
793}
794
20f733e7
BR		 795static inline void __iomem *mv_ap_base(struct ata_port *ap)
796{
f351b2d6 797 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 798}
799
cca3974e 800static inline int mv_get_hc_count(unsigned long port_flags)
31961943 801{
cca3974e 802 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 803}
804
c5d3e45a
JG		 805static void mv_set_edma_ptrs(void __iomem *port_mmio,
806 struct mv_host_priv *hpriv,
807 struct mv_port_priv *pp)
808{
bdd4ddde
JG		 809 u32 index;
810
c5d3e45a
JG		 811 /*
812 * initialize request queue
813 */
fcfb1f77
ML		 814 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
815 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 816
c5d3e45a
JG		 817 WARN_ON(pp->crqb_dma & 0x3ff);
818 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 819 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 820 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
821
822 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 823 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 824 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
825 else
bdd4ddde 826 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 827
828 /*
829 * initialize response queue
830 */
fcfb1f77
ML		 831 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
832 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 833
c5d3e45a
JG		 834 WARN_ON(pp->crpb_dma & 0xff);
835 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
836
837 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 838 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 839 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
840 else
bdd4ddde 841 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 842
bdd4ddde 843 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 844 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 845}
846
05b308e1
BR		 847/**
848 * mv_start_dma - Enable eDMA engine
849 * @base: port base address
850 * @pp: port private data
851 *
beec7dbc
TH		 852 * Verify the local cache of the eDMA state is accurate with a
853 * WARN_ON.
05b308e1
BR		 854 *
855 * LOCKING:
856 * Inherited from caller.
857 */
0c58912e 858static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 859 struct mv_port_priv *pp, u8 protocol)
20f733e7 860{
72109168
ML		 861 int want_ncq = (protocol == ATA_PROT_NCQ);
862
863 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
864 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
865 if (want_ncq != using_ncq)
b562468c 866 mv_stop_edma(ap);
72109168 867 }
c5d3e45a 868 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 869 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 870 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 871 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 872 mv_host_base(ap->host), hardport);
0c58912e
ML		 873 u32 hc_irq_cause, ipending;
874
bdd4ddde 875 /* clear EDMA event indicators, if any */
f630d562 876 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 877
0c58912e
ML		 878 /* clear EDMA interrupt indicator, if any */
879 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 880 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 881 if (hc_irq_cause & ipending) {
882 writelfl(hc_irq_cause & ~ipending,
883 hc_mmio + HC_IRQ_CAUSE_OFS);
884 }
885
e12bef50 886 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 887
888 /* clear FIS IRQ Cause */
889 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
890
f630d562 891 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 892
f630d562 893 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 894 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
895 }
20f733e7
BR		 896}
897
9b2c4e0b
ML		 898static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
899{
900 void __iomem *port_mmio = mv_ap_base(ap);
901 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
902 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
903 int i;
904
905 /*
906 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 907 * No idea what a good "timeout" value might be, but measurements
908 * indicate that it often requires hundreds of microseconds
909 * with two drives in-use. So we use the 15msec value above
910 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 911 */
912 for (i = 0; i < timeout; ++i) {
913 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
914 if ((edma_stat & empty_idle) == empty_idle)
915 break;
916 udelay(per_loop);
917 }
918 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
919}
920
05b308e1 921/**
e12bef50 922 * mv_stop_edma_engine - Disable eDMA engine
b562468c 923 * @port_mmio: io base address
05b308e1
BR		 924 *
925 * LOCKING:
926 * Inherited from caller.
927 */
b562468c 928static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 929{
b562468c 930 int i;
31961943 931
b562468c
ML		 932 /* Disable eDMA. The disable bit auto clears. */
933 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 934
b562468c
ML		 935 /* Wait for the chip to confirm eDMA is off. */
936 for (i = 10000; i > 0; i--) {
937 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 938 if (!(reg & EDMA_EN))
b562468c
ML		 939 return 0;
940 udelay(10);
31961943 941 }
b562468c 942 return -EIO;
20f733e7
BR		 943}
944
e12bef50 945static int mv_stop_edma(struct ata_port *ap)
0ea9e179 946{
b562468c
ML		 947 void __iomem *port_mmio = mv_ap_base(ap);
948 struct mv_port_priv *pp = ap->private_data;
0ea9e179 949
b562468c
ML		 950 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
951 return 0;
952 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 953 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 954 if (mv_stop_edma_engine(port_mmio)) {
955 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
956 return -EIO;
957 }
958 return 0;
0ea9e179
JG		 959}
960
8a70f8dc 961#ifdef ATA_DEBUG
31961943 962static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 963{
31961943
BR		 964 int b, w;
965 for (b = 0; b < bytes; ) {
966 DPRINTK("%p: ", start + b);
967 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 968 printk("%08x ", readl(start + b));
31961943
BR		 969 b += sizeof(u32);
970 }
971 printk("\n");
972 }
31961943 973}
8a70f8dc
JG		 974#endif
975
31961943
BR		 976static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
977{
978#ifdef ATA_DEBUG
979 int b, w;
980 u32 dw;
981 for (b = 0; b < bytes; ) {
982 DPRINTK("%02x: ", b);
983 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 984 (void) pci_read_config_dword(pdev, b, &dw);
985 printk("%08x ", dw);
31961943
BR		 986 b += sizeof(u32);
987 }
988 printk("\n");
989 }
990#endif
991}
992static void mv_dump_all_regs(void __iomem *mmio_base, int port,
993 struct pci_dev *pdev)
994{
995#ifdef ATA_DEBUG
8b260248 996 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 997 port >> MV_PORT_HC_SHIFT);
998 void __iomem *port_base;
999 int start_port, num_ports, p, start_hc, num_hcs, hc;
1000
1001 if (0 > port) {
1002 start_hc = start_port = 0;
1003 num_ports = 8; /* shld be benign for 4 port devs */
1004 num_hcs = 2;
1005 } else {
1006 start_hc = port >> MV_PORT_HC_SHIFT;
1007 start_port = port;
1008 num_ports = num_hcs = 1;
1009 }
8b260248 1010 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1011 num_ports > 1 ? num_ports - 1 : start_port);
1012
1013 if (NULL != pdev) {
1014 DPRINTK("PCI config space regs:\n");
1015 mv_dump_pci_cfg(pdev, 0x68);
1016 }
1017 DPRINTK("PCI regs:\n");
1018 mv_dump_mem(mmio_base+0xc00, 0x3c);
1019 mv_dump_mem(mmio_base+0xd00, 0x34);
1020 mv_dump_mem(mmio_base+0xf00, 0x4);
1021 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1022 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1023 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1024 DPRINTK("HC regs (HC %i):\n", hc);
1025 mv_dump_mem(hc_base, 0x1c);
1026 }
1027 for (p = start_port; p < start_port + num_ports; p++) {
1028 port_base = mv_port_base(mmio_base, p);
2dcb407e 1029 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1030 mv_dump_mem(port_base, 0x54);
2dcb407e 1031 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1032 mv_dump_mem(port_base+0x300, 0x60);
1033 }
1034#endif
20f733e7
BR		 1035}
1036
1037static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1038{
1039 unsigned int ofs;
1040
1041 switch (sc_reg_in) {
1042 case SCR_STATUS:
1043 case SCR_CONTROL:
1044 case SCR_ERROR:
1045 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1046 break;
1047 case SCR_ACTIVE:
1048 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1049 break;
1050 default:
1051 ofs = 0xffffffffU;
1052 break;
1053 }
1054 return ofs;
1055}
1056
da3dbb17 1057static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1058{
1059 unsigned int ofs = mv_scr_offset(sc_reg_in);
1060
da3dbb17
TH		 1061 if (ofs != 0xffffffffU) {
1062 *val = readl(mv_ap_base(ap) + ofs);
1063 return 0;
1064 } else
1065 return -EINVAL;
20f733e7
BR		 1066}
1067
da3dbb17 1068static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1069{
1070 unsigned int ofs = mv_scr_offset(sc_reg_in);
1071
da3dbb17 1072 if (ofs != 0xffffffffU) {
20f733e7 1073 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1074 return 0;
1075 } else
1076 return -EINVAL;
20f733e7
BR		 1077}
1078
f273827e
ML		 1079static void mv6_dev_config(struct ata_device *adev)
1080{
1081 /*
e49856d8
ML		 1082 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1083 *
1084 * Gen-II does not support NCQ over a port multiplier
1085 * (no FIS-based switching).
1086 *
f273827e
ML		 1087 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1088 * See mv_qc_prep() for more info.
1089 */
e49856d8 1090 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1091 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1092 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1093 ata_dev_printk(adev, KERN_INFO,
1094 "NCQ disabled for command-based switching\n");
1095 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1096 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1097 ata_dev_printk(adev, KERN_INFO,
1098 "max_sectors limited to %u for NCQ\n",
1099 adev->max_sectors);
1100 }
e49856d8 1101 }
f273827e
ML		 1102}
1103
3e4a1391
ML		 1104static int mv_qc_defer(struct ata_queued_cmd *qc)
1105{
1106 struct ata_link *link = qc->dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct mv_port_priv *pp = ap->private_data;
1109
29d187bb
ML		 1110 /*
1111 * Don't allow new commands if we're in a delayed EH state
1112 * for NCQ and/or FIS-based switching.
1113 */
1114 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1115 return ATA_DEFER_PORT;
3e4a1391
ML		 1116 /*
1117 * If the port is completely idle, then allow the new qc.
1118 */
1119 if (ap->nr_active_links == 0)
1120 return 0;
1121
1122 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1123 /*
1124 * The port is operating in host queuing mode (EDMA).
1125 * It can accomodate a new qc if the qc protocol
1126 * is compatible with the current host queue mode.
1127 */
1128 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1129 /*
1130 * The host queue (EDMA) is in NCQ mode.
1131 * If the new qc is also an NCQ command,
1132 * then allow the new qc.
1133 */
1134 if (qc->tf.protocol == ATA_PROT_NCQ)
1135 return 0;
1136 } else {
1137 /*
1138 * The host queue (EDMA) is in non-NCQ, DMA mode.
1139 * If the new qc is also a non-NCQ, DMA command,
1140 * then allow the new qc.
1141 */
1142 if (qc->tf.protocol == ATA_PROT_DMA)
1143 return 0;
1144 }
1145 }
1146 return ATA_DEFER_PORT;
1147}
1148
00f42eab 1149static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1150{
00f42eab
ML		 1151 u32 new_fiscfg, old_fiscfg;
1152 u32 new_ltmode, old_ltmode;
1153 u32 new_haltcond, old_haltcond;
1154
1155 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1156 old_ltmode = readl(port_mmio + LTMODE_OFS);
1157 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1158
1159 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1160 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1161 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1162
1163 if (want_fbs) {
1164 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1165 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1166 if (want_ncq)
1167 new_haltcond &= ~EDMA_ERR_DEV;
1168 else
1169 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1170 }
00f42eab 1171
8e7decdb
ML		 1172 if (new_fiscfg != old_fiscfg)
1173 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1174 if (new_ltmode != old_ltmode)
1175 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1176 if (new_haltcond != old_haltcond)
1177 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1178}
1179
dd2890f6
ML		 1180static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1181{
1182 struct mv_host_priv *hpriv = ap->host->private_data;
1183 u32 old, new;
1184
1185 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1186 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1187 if (want_ncq)
1188 new = old | (1 << 22);
1189 else
1190 new = old & ~(1 << 22);
1191 if (new != old)
1192 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1193}
1194
e12bef50 1195static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1196{
0c58912e 1197 u32 cfg;
e12bef50
ML		 1198 struct mv_port_priv *pp = ap->private_data;
1199 struct mv_host_priv *hpriv = ap->host->private_data;
1200 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1201
1202 /* set up non-NCQ EDMA configuration */
0c58912e 1203 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00f42eab 1204 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
e4e7b892 1205
0c58912e 1206 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1207 cfg |= (1 << 8); /* enab config burst size mask */
1208
dd2890f6 1209 else if (IS_GEN_II(hpriv)) {
e4e7b892 1210 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1211 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1212
dd2890f6 1213 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1214 int want_fbs = sata_pmp_attached(ap);
1215 /*
1216 * Possible future enhancement:
1217 *
1218 * The chip can use FBS with non-NCQ, if we allow it,
1219 * But first we need to have the error handling in place
1220 * for this mode (datasheet section 7.3.15.4.2.3).
1221 * So disallow non-NCQ FBS for now.
1222 */
1223 want_fbs &= want_ncq;
1224
1225 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1226
1227 if (want_fbs) {
1228 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1229 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1230 }
1231
e728eabe
JG		 1232 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1233 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1234 if (HAS_PCI(ap->host))
1235 cfg |= (1 << 18); /* enab early completion */
1236 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1237 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1238 }
1239
72109168
ML		 1240 if (want_ncq) {
1241 cfg |= EDMA_CFG_NCQ;
1242 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1243 } else
1244 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1245
e4e7b892
JG		 1246 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1247}
1248
da2fa9ba
ML		 1249static void mv_port_free_dma_mem(struct ata_port *ap)
1250{
1251 struct mv_host_priv *hpriv = ap->host->private_data;
1252 struct mv_port_priv *pp = ap->private_data;
eb73d558 1253 int tag;
da2fa9ba
ML		 1254
1255 if (pp->crqb) {
1256 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1257 pp->crqb = NULL;
1258 }
1259 if (pp->crpb) {
1260 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1261 pp->crpb = NULL;
1262 }
eb73d558
ML		 1263 /*
1264 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1265 * For later hardware, we have one unique sg_tbl per NCQ tag.
1266 */
1267 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1268 if (pp->sg_tbl[tag]) {
1269 if (tag == 0 || !IS_GEN_I(hpriv))
1270 dma_pool_free(hpriv->sg_tbl_pool,
1271 pp->sg_tbl[tag],
1272 pp->sg_tbl_dma[tag]);
1273 pp->sg_tbl[tag] = NULL;
1274 }
da2fa9ba
ML		 1275 }
1276}
1277
05b308e1
BR		 1278/**
1279 * mv_port_start - Port specific init/start routine.
1280 * @ap: ATA channel to manipulate
1281 *
1282 * Allocate and point to DMA memory, init port private memory,
1283 * zero indices.
1284 *
1285 * LOCKING:
1286 * Inherited from caller.
1287 */
31961943
BR		 1288static int mv_port_start(struct ata_port *ap)
1289{
cca3974e
JG		 1290 struct device *dev = ap->host->dev;
1291 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1292 struct mv_port_priv *pp;
dde20207 1293 int tag;
31961943 1294
24dc5f33 1295 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1296 if (!pp)
24dc5f33 1297 return -ENOMEM;
da2fa9ba 1298 ap->private_data = pp;
31961943 1299
da2fa9ba
ML		 1300 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1301 if (!pp->crqb)
1302 return -ENOMEM;
1303 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1304
da2fa9ba
ML		 1305 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1306 if (!pp->crpb)
1307 goto out_port_free_dma_mem;
1308 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1309
eb73d558
ML		 1310 /*
1311 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1312 * For later hardware, we need one unique sg_tbl per NCQ tag.
1313 */
1314 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1315 if (tag == 0 || !IS_GEN_I(hpriv)) {
1316 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1317 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1318 if (!pp->sg_tbl[tag])
1319 goto out_port_free_dma_mem;
1320 } else {
1321 pp->sg_tbl[tag] = pp->sg_tbl[0];
1322 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1323 }
1324 }
31961943 1325 return 0;
da2fa9ba
ML		 1326
1327out_port_free_dma_mem:
1328 mv_port_free_dma_mem(ap);
1329 return -ENOMEM;
31961943
BR		 1330}
1331
05b308e1
BR		 1332/**
1333 * mv_port_stop - Port specific cleanup/stop routine.
1334 * @ap: ATA channel to manipulate
1335 *
1336 * Stop DMA, cleanup port memory.
1337 *
1338 * LOCKING:
cca3974e 1339 * This routine uses the host lock to protect the DMA stop.
05b308e1 1340 */
31961943
BR		 1341static void mv_port_stop(struct ata_port *ap)
1342{
e12bef50 1343 mv_stop_edma(ap);
da2fa9ba 1344 mv_port_free_dma_mem(ap);
31961943
BR		 1345}
1346
05b308e1
BR		 1347/**
1348 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1349 * @qc: queued command whose SG list to source from
1350 *
1351 * Populate the SG list and mark the last entry.
1352 *
1353 * LOCKING:
1354 * Inherited from caller.
1355 */
6c08772e 1356static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1357{
1358 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1359 struct scatterlist *sg;
3be6cbd7 1360 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1361 unsigned int si;
31961943 1362
eb73d558 1363 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1364 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1365 dma_addr_t addr = sg_dma_address(sg);
1366 u32 sg_len = sg_dma_len(sg);
22374677 1367
4007b493
OJ		 1368 while (sg_len) {
1369 u32 offset = addr & 0xffff;
1370 u32 len = sg_len;
22374677 1371
4007b493
OJ		 1372 if ((offset + sg_len > 0x10000))
1373 len = 0x10000 - offset;
1374
1375 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1376 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1377 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1378
1379 sg_len -= len;
1380 addr += len;
1381
3be6cbd7 1382 last_sg = mv_sg;
4007b493 1383 mv_sg++;
4007b493 1384 }
31961943 1385 }
3be6cbd7
JG		 1386
1387 if (likely(last_sg))
1388 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1389}
1390
5796d1c4 1391static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1392{
559eedad 1393 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1394 (last ? CRQB_CMD_LAST : 0);
559eedad 1395 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1396}
1397
05b308e1
BR		 1398/**
1399 * mv_qc_prep - Host specific command preparation.
1400 * @qc: queued command to prepare
1401 *
1402 * This routine simply redirects to the general purpose routine
1403 * if command is not DMA. Else, it handles prep of the CRQB
1404 * (command request block), does some sanity checking, and calls
1405 * the SG load routine.
1406 *
1407 * LOCKING:
1408 * Inherited from caller.
1409 */
31961943
BR		 1410static void mv_qc_prep(struct ata_queued_cmd *qc)
1411{
1412 struct ata_port *ap = qc->ap;
1413 struct mv_port_priv *pp = ap->private_data;
e1469874 1414 __le16 *cw;
31961943
BR		 1415 struct ata_taskfile *tf;
1416 u16 flags = 0;
a6432436 1417 unsigned in_index;
31961943 1418
138bfdd0
ML		 1419 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1420 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1421 return;
20f733e7 1422
31961943
BR		 1423 /* Fill in command request block
1424 */
e4e7b892 1425 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1426 flags |= CRQB_FLAG_READ;
beec7dbc 1427 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1428 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1429 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1430
bdd4ddde 1431 /* get current queue index from software */
fcfb1f77 1432 in_index = pp->req_idx;
a6432436
ML		 1433
1434 pp->crqb[in_index].sg_addr =
eb73d558 1435 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1436 pp->crqb[in_index].sg_addr_hi =
eb73d558 1437 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1438 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1439
a6432436 1440 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1441 tf = &qc->tf;
1442
1443 /* Sadly, the CRQB cannot accomodate all registers--there are
1444 * only 11 bytes...so we must pick and choose required
1445 * registers based on the command. So, we drop feature and
1446 * hob_feature for [RW] DMA commands, but they are needed for
1447 * NCQ. NCQ will drop hob_nsect.
20f733e7 1448 */
31961943
BR		 1449 switch (tf->command) {
1450 case ATA_CMD_READ:
1451 case ATA_CMD_READ_EXT:
1452 case ATA_CMD_WRITE:
1453 case ATA_CMD_WRITE_EXT:
c15d85c8 1454 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1455 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1456 break;
31961943
BR		 1457 case ATA_CMD_FPDMA_READ:
1458 case ATA_CMD_FPDMA_WRITE:
8b260248 1459 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1460 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1461 break;
31961943
BR		 1462 default:
1463 /* The only other commands EDMA supports in non-queued and
1464 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1465 * of which are defined/used by Linux. If we get here, this
1466 * driver needs work.
1467 *
1468 * FIXME: modify libata to give qc_prep a return value and
1469 * return error here.
1470 */
1471 BUG_ON(tf->command);
1472 break;
1473 }
1474 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1475 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1476 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1477 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1478 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1479 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1480 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1481 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1482 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1483
e4e7b892
JG		 1484 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1485 return;
1486 mv_fill_sg(qc);
1487}
1488
1489/**
1490 * mv_qc_prep_iie - Host specific command preparation.
1491 * @qc: queued command to prepare
1492 *
1493 * This routine simply redirects to the general purpose routine
1494 * if command is not DMA. Else, it handles prep of the CRQB
1495 * (command request block), does some sanity checking, and calls
1496 * the SG load routine.
1497 *
1498 * LOCKING:
1499 * Inherited from caller.
1500 */
1501static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1502{
1503 struct ata_port *ap = qc->ap;
1504 struct mv_port_priv *pp = ap->private_data;
1505 struct mv_crqb_iie *crqb;
1506 struct ata_taskfile *tf;
a6432436 1507 unsigned in_index;
e4e7b892
JG		 1508 u32 flags = 0;
1509
138bfdd0
ML		 1510 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1511 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1512 return;
1513
e12bef50 1514 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1515 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1516 flags |= CRQB_FLAG_READ;
1517
beec7dbc 1518 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1519 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1520 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1521 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1522
bdd4ddde 1523 /* get current queue index from software */
fcfb1f77 1524 in_index = pp->req_idx;
a6432436
ML		 1525
1526 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1527 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1528 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1529 crqb->flags = cpu_to_le32(flags);
1530
1531 tf = &qc->tf;
1532 crqb->ata_cmd[0] = cpu_to_le32(
1533 (tf->command << 16) |
1534 (tf->feature << 24)
1535 );
1536 crqb->ata_cmd[1] = cpu_to_le32(
1537 (tf->lbal << 0) |
1538 (tf->lbam << 8) |
1539 (tf->lbah << 16) |
1540 (tf->device << 24)
1541 );
1542 crqb->ata_cmd[2] = cpu_to_le32(
1543 (tf->hob_lbal << 0) |
1544 (tf->hob_lbam << 8) |
1545 (tf->hob_lbah << 16) |
1546 (tf->hob_feature << 24)
1547 );
1548 crqb->ata_cmd[3] = cpu_to_le32(
1549 (tf->nsect << 0) |
1550 (tf->hob_nsect << 8)
1551 );
1552
1553 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1554 return;
31961943
BR		 1555 mv_fill_sg(qc);
1556}
1557
05b308e1
BR		 1558/**
1559 * mv_qc_issue - Initiate a command to the host
1560 * @qc: queued command to start
1561 *
1562 * This routine simply redirects to the general purpose routine
1563 * if command is not DMA. Else, it sanity checks our local
1564 * caches of the request producer/consumer indices then enables
1565 * DMA and bumps the request producer index.
1566 *
1567 * LOCKING:
1568 * Inherited from caller.
1569 */
9a3d9eb0 1570static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1571{
c5d3e45a
JG		 1572 struct ata_port *ap = qc->ap;
1573 void __iomem *port_mmio = mv_ap_base(ap);
1574 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1575 u32 in_index;
31961943 1576
138bfdd0
ML		 1577 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1578 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1579 /*
1580 * We're about to send a non-EDMA capable command to the
31961943
BR		 1581 * port. Turn off EDMA so there won't be problems accessing
1582 * shadow block, etc registers.
1583 */
b562468c 1584 mv_stop_edma(ap);
e49856d8 1585 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1586 return ata_sff_qc_issue(qc);
31961943
BR		 1587 }
1588
72109168 1589 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1590
fcfb1f77
ML		 1591 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1592 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1593
1594 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1595 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1596 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1597
1598 return 0;
1599}
1600
8f767f8a
ML		 1601static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1602{
1603 struct mv_port_priv *pp = ap->private_data;
1604 struct ata_queued_cmd *qc;
1605
1606 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1607 return NULL;
1608 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1609 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1610 qc = NULL;
1611 return qc;
1612}
1613
29d187bb
ML		 1614static void mv_pmp_error_handler(struct ata_port *ap)
1615{
1616 unsigned int pmp, pmp_map;
1617 struct mv_port_priv *pp = ap->private_data;
1618
1619 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1620 /*
1621 * Perform NCQ error analysis on failed PMPs
1622 * before we freeze the port entirely.
1623 *
1624 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1625 */
1626 pmp_map = pp->delayed_eh_pmp_map;
1627 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1628 for (pmp = 0; pmp_map != 0; pmp++) {
1629 unsigned int this_pmp = (1 << pmp);
1630 if (pmp_map & this_pmp) {
1631 struct ata_link *link = &ap->pmp_link[pmp];
1632 pmp_map &= ~this_pmp;
1633 ata_eh_analyze_ncq_error(link);
1634 }
1635 }
1636 ata_port_freeze(ap);
1637 }
1638 sata_pmp_error_handler(ap);
1639}
1640
4c299ca3
ML		 1641static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1642{
1643 void __iomem *port_mmio = mv_ap_base(ap);
1644
1645 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1646}
1647
4c299ca3
ML		 1648static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1649{
1650 struct ata_eh_info *ehi;
1651 unsigned int pmp;
1652
1653 /*
1654 * Initialize EH info for PMPs which saw device errors
1655 */
1656 ehi = &ap->link.eh_info;
1657 for (pmp = 0; pmp_map != 0; pmp++) {
1658 unsigned int this_pmp = (1 << pmp);
1659 if (pmp_map & this_pmp) {
1660 struct ata_link *link = &ap->pmp_link[pmp];
1661
1662 pmp_map &= ~this_pmp;
1663 ehi = &link->eh_info;
1664 ata_ehi_clear_desc(ehi);
1665 ata_ehi_push_desc(ehi, "dev err");
1666 ehi->err_mask |= AC_ERR_DEV;
1667 ehi->action |= ATA_EH_RESET;
1668 ata_link_abort(link);
1669 }
1670 }
1671}
1672
1673static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1674{
1675 struct mv_port_priv *pp = ap->private_data;
1676 int failed_links;
1677 unsigned int old_map, new_map;
1678
1679 /*
1680 * Device error during FBS+NCQ operation:
1681 *
1682 * Set a port flag to prevent further I/O being enqueued.
1683 * Leave the EDMA running to drain outstanding commands from this port.
1684 * Perform the post-mortem/EH only when all responses are complete.
1685 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1686 */
1687 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1688 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1689 pp->delayed_eh_pmp_map = 0;
1690 }
1691 old_map = pp->delayed_eh_pmp_map;
1692 new_map = old_map | mv_get_err_pmp_map(ap);
1693
1694 if (old_map != new_map) {
1695 pp->delayed_eh_pmp_map = new_map;
1696 mv_pmp_eh_prep(ap, new_map & ~old_map);
1697 }
c46938cc 1698 failed_links = hweight16(new_map);
4c299ca3
ML		 1699
1700 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1701 "failed_links=%d nr_active_links=%d\n",
1702 __func__, pp->delayed_eh_pmp_map,
1703 ap->qc_active, failed_links,
1704 ap->nr_active_links);
1705
1706 if (ap->nr_active_links <= failed_links) {
1707 mv_process_crpb_entries(ap, pp);
1708 mv_stop_edma(ap);
1709 mv_eh_freeze(ap);
1710 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1711 return 1; /* handled */
1712 }
1713 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1714 return 1; /* handled */
1715}
1716
1717static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1718{
1719 /*
1720 * Possible future enhancement:
1721 *
1722 * FBS+non-NCQ operation is not yet implemented.
1723 * See related notes in mv_edma_cfg().
1724 *
1725 * Device error during FBS+non-NCQ operation:
1726 *
1727 * We need to snapshot the shadow registers for each failed command.
1728 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1729 */
1730 return 0; /* not handled */
1731}
1732
1733static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1734{
1735 struct mv_port_priv *pp = ap->private_data;
1736
1737 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1738 return 0; /* EDMA was not active: not handled */
1739 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1740 return 0; /* FBS was not active: not handled */
1741
1742 if (!(edma_err_cause & EDMA_ERR_DEV))
1743 return 0; /* non DEV error: not handled */
1744 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1745 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1746 return 0; /* other problems: not handled */
1747
1748 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1749 /*
1750 * EDMA should NOT have self-disabled for this case.
1751 * If it did, then something is wrong elsewhere,
1752 * and we cannot handle it here.
1753 */
1754 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1755 ata_port_printk(ap, KERN_WARNING,
1756 "%s: err_cause=0x%x pp_flags=0x%x\n",
1757 __func__, edma_err_cause, pp->pp_flags);
1758 return 0; /* not handled */
1759 }
1760 return mv_handle_fbs_ncq_dev_err(ap);
1761 } else {
1762 /*
1763 * EDMA should have self-disabled for this case.
1764 * If it did not, then something is wrong elsewhere,
1765 * and we cannot handle it here.
1766 */
1767 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1768 ata_port_printk(ap, KERN_WARNING,
1769 "%s: err_cause=0x%x pp_flags=0x%x\n",
1770 __func__, edma_err_cause, pp->pp_flags);
1771 return 0; /* not handled */
1772 }
1773 return mv_handle_fbs_non_ncq_dev_err(ap);
1774 }
1775 return 0; /* not handled */
1776}
1777
a9010329 1778static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1779{
8f767f8a 1780 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1781 char *when = "idle";
8f767f8a 1782
8f767f8a 1783 ata_ehi_clear_desc(ehi);
a9010329
ML		 1784 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1785 when = "disabled";
1786 } else if (edma_was_enabled) {
1787 when = "EDMA enabled";
8f767f8a
ML		 1788 } else {
1789 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1790 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1791 when = "polling";
8f767f8a 1792 }
a9010329 1793 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1794 ehi->err_mask |= AC_ERR_OTHER;
1795 ehi->action |= ATA_EH_RESET;
1796 ata_port_freeze(ap);
1797}
1798
05b308e1
BR		 1799/**
1800 * mv_err_intr - Handle error interrupts on the port
1801 * @ap: ATA channel to manipulate
8d07379d 1802 * @qc: affected command (non-NCQ), or NULL
05b308e1 1803 *
8d07379d
ML		 1804 * Most cases require a full reset of the chip's state machine,
1805 * which also performs a COMRESET.
1806 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1807 *
1808 * LOCKING:
1809 * Inherited from caller.
1810 */
37b9046a 1811static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1812{
1813 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde
JG		 1814 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1815 struct mv_port_priv *pp = ap->private_data;
1816 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1817 unsigned int action = 0, err_mask = 0;
9af5c9c9 1818 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1819 struct ata_queued_cmd *qc;
1820 int abort = 0;
20f733e7 1821
8d07379d 1822 /*
37b9046a 1823 * Read and clear the SError and err_cause bits.
8d07379d 1824 */
37b9046a
ML		 1825 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1826 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1827
bdd4ddde 1828 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
8d07379d 1829 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1830
37b9046a
ML		 1831 ata_port_printk(ap, KERN_INFO, "%s: err_cause=%08x pp_flags=0x%x\n",
1832 __func__, edma_err_cause, pp->pp_flags);
bdd4ddde 1833
4c299ca3
ML		 1834 if (edma_err_cause & EDMA_ERR_DEV) {
1835 /*
1836 * Device errors during FIS-based switching operation
1837 * require special handling.
1838 */
1839 if (mv_handle_dev_err(ap, edma_err_cause))
1840 return;
1841 }
1842
37b9046a
ML		 1843 qc = mv_get_active_qc(ap);
1844 ata_ehi_clear_desc(ehi);
1845 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1846 edma_err_cause, pp->pp_flags);
bdd4ddde 1847 /*
352fab70 1848 * All generations share these EDMA error cause bits:
bdd4ddde 1849 */
37b9046a 1850 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1851 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1852 action |= ATA_EH_RESET;
1853 ata_ehi_push_desc(ehi, "dev error");
1854 }
bdd4ddde 1855 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1856 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1857 EDMA_ERR_INTRL_PAR)) {
1858 err_mask |= AC_ERR_ATA_BUS;
cf480626 1859 action |= ATA_EH_RESET;
b64bbc39 1860 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1861 }
1862 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1863 ata_ehi_hotplugged(ehi);
1864 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1865 "dev disconnect" : "dev connect");
cf480626 1866 action |= ATA_EH_RESET;
bdd4ddde
JG		 1867 }
1868
352fab70
ML		 1869 /*
1870 * Gen-I has a different SELF_DIS bit,
1871 * different FREEZE bits, and no SERR bit:
1872 */
ee9ccdf7 1873 if (IS_GEN_I(hpriv)) {
bdd4ddde 1874 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1875 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1876 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1877 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1878 }
1879 } else {
1880 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1881 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1882 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1883 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1884 }
bdd4ddde 1885 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1886 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1887 err_mask |= AC_ERR_ATA_BUS;
cf480626 1888 action |= ATA_EH_RESET;
bdd4ddde 1889 }
afb0edd9 1890 }
20f733e7 1891
bdd4ddde
JG		 1892 if (!err_mask) {
1893 err_mask = AC_ERR_OTHER;
cf480626 1894 action |= ATA_EH_RESET;
bdd4ddde
JG		 1895 }
1896
1897 ehi->serror |= serr;
1898 ehi->action |= action;
1899
1900 if (qc)
1901 qc->err_mask |= err_mask;
1902 else
1903 ehi->err_mask |= err_mask;
1904
37b9046a
ML		 1905 if (err_mask == AC_ERR_DEV) {
1906 /*
1907 * Cannot do ata_port_freeze() here,
1908 * because it would kill PIO access,
1909 * which is needed for further diagnosis.
1910 */
1911 mv_eh_freeze(ap);
1912 abort = 1;
1913 } else if (edma_err_cause & eh_freeze_mask) {
1914 /*
1915 * Note to self: ata_port_freeze() calls ata_port_abort()
1916 */
bdd4ddde 1917 ata_port_freeze(ap);
37b9046a
ML		 1918 } else {
1919 abort = 1;
1920 }
1921
1922 if (abort) {
1923 if (qc)
1924 ata_link_abort(qc->dev->link);
1925 else
1926 ata_port_abort(ap);
1927 }
bdd4ddde
JG		 1928}
1929
fcfb1f77
ML		 1930static void mv_process_crpb_response(struct ata_port *ap,
1931 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1932{
1933 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1934
1935 if (qc) {
1936 u8 ata_status;
1937 u16 edma_status = le16_to_cpu(response->flags);
1938 /*
1939 * edma_status from a response queue entry:
1940 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1941 * MSB is saved ATA status from command completion.
1942 */
1943 if (!ncq_enabled) {
1944 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1945 if (err_cause) {
1946 /*
1947 * Error will be seen/handled by mv_err_intr().
1948 * So do nothing at all here.
1949 */
1950 return;
1951 }
1952 }
1953 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 1954 if (!ac_err_mask(ata_status))
1955 ata_qc_complete(qc);
1956 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 1957 } else {
1958 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1959 __func__, tag);
1960 }
1961}
1962
1963static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1964{
1965 void __iomem *port_mmio = mv_ap_base(ap);
1966 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1967 u32 in_index;
bdd4ddde 1968 bool work_done = false;
fcfb1f77 1969 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1970
fcfb1f77 1971 /* Get the hardware queue position index */
bdd4ddde
JG		 1972 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1973 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1974
fcfb1f77
ML		 1975 /* Process new responses from since the last time we looked */
1976 while (in_index != pp->resp_idx) {
6c1153e0 1977 unsigned int tag;
fcfb1f77 1978 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1979
fcfb1f77 1980 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1981
fcfb1f77
ML		 1982 if (IS_GEN_I(hpriv)) {
1983 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1984 tag = ap->link.active_tag;
fcfb1f77
ML		 1985 } else {
1986 /* Gen II/IIE: get command tag from CRPB entry */
1987 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1988 }
fcfb1f77 1989 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 1990 work_done = true;
bdd4ddde
JG		 1991 }
1992
352fab70 1993 /* Update the software queue position index in hardware */
bdd4ddde
JG		 1994 if (work_done)
1995 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 1996 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 1997 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 1998}
1999
a9010329
ML		 2000static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2001{
2002 struct mv_port_priv *pp;
2003 int edma_was_enabled;
2004
2005 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2006 mv_unexpected_intr(ap, 0);
2007 return;
2008 }
2009 /*
2010 * Grab a snapshot of the EDMA_EN flag setting,
2011 * so that we have a consistent view for this port,
2012 * even if something we call of our routines changes it.
2013 */
2014 pp = ap->private_data;
2015 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2016 /*
2017 * Process completed CRPB response(s) before other events.
2018 */
2019 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2020 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2021 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2022 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2023 }
2024 /*
2025 * Handle chip-reported errors, or continue on to handle PIO.
2026 */
2027 if (unlikely(port_cause & ERR_IRQ)) {
2028 mv_err_intr(ap);
2029 } else if (!edma_was_enabled) {
2030 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2031 if (qc)
2032 ata_sff_host_intr(ap, qc);
2033 else
2034 mv_unexpected_intr(ap, edma_was_enabled);
2035 }
2036}
2037
05b308e1
BR		 2038/**
2039 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2040 * @host: host specific structure
7368f919 2041 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2042 *
2043 * LOCKING:
2044 * Inherited from caller.
2045 */
7368f919 2046static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2047{
f351b2d6 2048 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2049 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2050 unsigned int handled = 0, port;
20f733e7 2051
a3718c1f 2052 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2053 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2054 unsigned int p, shift, hardport, port_cause;
2055
a3718c1f 2056 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2057 /*
eabd5eb1
ML		 2058 * Each hc within the host has its own hc_irq_cause register,
2059 * where the interrupting ports bits get ack'd.
a3718c1f 2060 */
eabd5eb1
ML		 2061 if (hardport == 0) { /* first port on this hc ? */
2062 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2063 u32 port_mask, ack_irqs;
2064 /*
2065 * Skip this entire hc if nothing pending for any ports
2066 */
2067 if (!hc_cause) {
2068 port += MV_PORTS_PER_HC - 1;
2069 continue;
2070 }
2071 /*
2072 * We don't need/want to read the hc_irq_cause register,
2073 * because doing so hurts performance, and
2074 * main_irq_cause already gives us everything we need.
2075 *
2076 * But we do have to *write* to the hc_irq_cause to ack
2077 * the ports that we are handling this time through.
2078 *
2079 * This requires that we create a bitmap for those
2080 * ports which interrupted us, and use that bitmap
2081 * to ack (only) those ports via hc_irq_cause.
2082 */
2083 ack_irqs = 0;
2084 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2085 if ((port + p) >= hpriv->n_ports)
2086 break;
2087 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2088 if (hc_cause & port_mask)
2089 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2090 }
a3718c1f 2091 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2092 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2093 handled = 1;
2094 }
8f767f8a 2095 /*
a9010329 2096 * Handle interrupts signalled for this port:
8f767f8a 2097 */
a9010329
ML		 2098 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2099 if (port_cause)
2100 mv_port_intr(ap, port_cause);
20f733e7 2101 }
a3718c1f 2102 return handled;
20f733e7
BR		 2103}
2104
a3718c1f 2105static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2106{
02a121da 2107 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2108 struct ata_port *ap;
2109 struct ata_queued_cmd *qc;
2110 struct ata_eh_info *ehi;
2111 unsigned int i, err_mask, printed = 0;
2112 u32 err_cause;
2113
02a121da 2114 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2115
2116 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2117 err_cause);
2118
2119 DPRINTK("All regs @ PCI error\n");
2120 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2121
02a121da 2122 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2123
2124 for (i = 0; i < host->n_ports; i++) {
2125 ap = host->ports[i];
936fd732 2126 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2127 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2128 ata_ehi_clear_desc(ehi);
2129 if (!printed++)
2130 ata_ehi_push_desc(ehi,
2131 "PCI err cause 0x%08x", err_cause);
2132 err_mask = AC_ERR_HOST_BUS;
cf480626 2133 ehi->action = ATA_EH_RESET;
9af5c9c9 2134 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2135 if (qc)
2136 qc->err_mask |= err_mask;
2137 else
2138 ehi->err_mask |= err_mask;
2139
2140 ata_port_freeze(ap);
2141 }
2142 }
a3718c1f 2143 return 1; /* handled */
bdd4ddde
JG		 2144}
2145
05b308e1 2146/**
c5d3e45a 2147 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2148 * @irq: unused
2149 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2150 *
2151 * Read the read only register to determine if any host
2152 * controllers have pending interrupts. If so, call lower level
2153 * routine to handle. Also check for PCI errors which are only
2154 * reported here.
2155 *
8b260248 2156 * LOCKING:
cca3974e 2157 * This routine holds the host lock while processing pending
05b308e1
BR		 2158 * interrupts.
2159 */
7d12e780 2160static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2161{
cca3974e 2162 struct ata_host *host = dev_instance;
f351b2d6 2163 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2164 unsigned int handled = 0;
7368f919 2165 u32 main_irq_cause, main_irq_mask;
20f733e7 2166
646a4da5 2167 spin_lock(&host->lock);
7368f919
ML		 2168 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2169 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 2170 /*
2171 * Deal with cases where we either have nothing pending, or have read
2172 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2173 */
7368f919
ML		 2174 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2175 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 2176 handled = mv_pci_error(host, hpriv->base);
2177 else
7368f919 2178 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 2179 }
cca3974e 2180 spin_unlock(&host->lock);
20f733e7
BR		 2181 return IRQ_RETVAL(handled);
2182}
2183
c9d39130
JG		 2184static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2185{
2186 unsigned int ofs;
2187
2188 switch (sc_reg_in) {
2189 case SCR_STATUS:
2190 case SCR_ERROR:
2191 case SCR_CONTROL:
2192 ofs = sc_reg_in * sizeof(u32);
2193 break;
2194 default:
2195 ofs = 0xffffffffU;
2196 break;
2197 }
2198 return ofs;
2199}
2200
da3dbb17 2201static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 2202{
f351b2d6
SB		 2203 struct mv_host_priv *hpriv = ap->host->private_data;
2204 void __iomem *mmio = hpriv->base;
0d5ff566 2205 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2206 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2207
da3dbb17
TH		 2208 if (ofs != 0xffffffffU) {
2209 *val = readl(addr + ofs);
2210 return 0;
2211 } else
2212 return -EINVAL;
c9d39130
JG		 2213}
2214
da3dbb17 2215static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 2216{
f351b2d6
SB		 2217 struct mv_host_priv *hpriv = ap->host->private_data;
2218 void __iomem *mmio = hpriv->base;
0d5ff566 2219 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2220 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2221
da3dbb17 2222 if (ofs != 0xffffffffU) {
0d5ff566 2223 writelfl(val, addr + ofs);
da3dbb17
TH		 2224 return 0;
2225 } else
2226 return -EINVAL;
c9d39130
JG		 2227}
2228
7bb3c529 2229static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2230{
7bb3c529 2231 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2232 int early_5080;
2233
44c10138 2234 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2235
2236 if (!early_5080) {
2237 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2238 tmp |= (1 << 0);
2239 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2240 }
2241
7bb3c529 2242 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2243}
2244
2245static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2246{
8e7decdb 2247 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2248}
2249
47c2b677 2250static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2251 void __iomem *mmio)
2252{
c9d39130
JG		 2253 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2254 u32 tmp;
2255
2256 tmp = readl(phy_mmio + MV5_PHY_MODE);
2257
2258 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2259 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2260}
2261
47c2b677 2262static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2263{
522479fb
JG		 2264 u32 tmp;
2265
8e7decdb 2266 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2267
2268 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2269
2270 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2271 tmp |= ~(1 << 0);
2272 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2273}
2274
2a47ce06
JG		 2275static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2276 unsigned int port)
bca1c4eb 2277{
c9d39130
JG		 2278 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2279 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2280 u32 tmp;
2281 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2282
2283 if (fix_apm_sq) {
8e7decdb 2284 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2285 tmp |= (1 << 19);
8e7decdb 2286 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2287
8e7decdb 2288 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2289 tmp &= ~0x3;
2290 tmp |= 0x1;
8e7decdb 2291 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2292 }
2293
2294 tmp = readl(phy_mmio + MV5_PHY_MODE);
2295 tmp &= ~mask;
2296 tmp |= hpriv->signal[port].pre;
2297 tmp |= hpriv->signal[port].amps;
2298 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2299}
2300
c9d39130
JG		 2301
2302#undef ZERO
2303#define ZERO(reg) writel(0, port_mmio + (reg))
2304static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2305 unsigned int port)
2306{
2307 void __iomem *port_mmio = mv_port_base(mmio, port);
2308
e12bef50 2309 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2310
2311 ZERO(0x028); /* command */
2312 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2313 ZERO(0x004); /* timer */
2314 ZERO(0x008); /* irq err cause */
2315 ZERO(0x00c); /* irq err mask */
2316 ZERO(0x010); /* rq bah */
2317 ZERO(0x014); /* rq inp */
2318 ZERO(0x018); /* rq outp */
2319 ZERO(0x01c); /* respq bah */
2320 ZERO(0x024); /* respq outp */
2321 ZERO(0x020); /* respq inp */
2322 ZERO(0x02c); /* test control */
8e7decdb 2323 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2324}
2325#undef ZERO
2326
2327#define ZERO(reg) writel(0, hc_mmio + (reg))
2328static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2329 unsigned int hc)
47c2b677 2330{
c9d39130
JG		 2331 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2332 u32 tmp;
2333
2334 ZERO(0x00c);
2335 ZERO(0x010);
2336 ZERO(0x014);
2337 ZERO(0x018);
2338
2339 tmp = readl(hc_mmio + 0x20);
2340 tmp &= 0x1c1c1c1c;
2341 tmp |= 0x03030303;
2342 writel(tmp, hc_mmio + 0x20);
2343}
2344#undef ZERO
2345
2346static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2347 unsigned int n_hc)
2348{
2349 unsigned int hc, port;
2350
2351 for (hc = 0; hc < n_hc; hc++) {
2352 for (port = 0; port < MV_PORTS_PER_HC; port++)
2353 mv5_reset_hc_port(hpriv, mmio,
2354 (hc * MV_PORTS_PER_HC) + port);
2355
2356 mv5_reset_one_hc(hpriv, mmio, hc);
2357 }
2358
2359 return 0;
47c2b677
JG		 2360}
2361
101ffae2
JG		 2362#undef ZERO
2363#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2364static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2365{
02a121da 2366 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2367 u32 tmp;
2368
8e7decdb 2369 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2370 tmp &= 0xff00ffff;
8e7decdb 2371 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2372
2373 ZERO(MV_PCI_DISC_TIMER);
2374 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2375 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
7368f919 2376 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2377 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2378 ZERO(hpriv->irq_cause_ofs);
2379 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2380 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2381 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2382 ZERO(MV_PCI_ERR_ATTRIBUTE);
2383 ZERO(MV_PCI_ERR_COMMAND);
2384}
2385#undef ZERO
2386
2387static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2388{
2389 u32 tmp;
2390
2391 mv5_reset_flash(hpriv, mmio);
2392
8e7decdb 2393 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2394 tmp &= 0x3;
2395 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2396 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2397}
2398
2399/**
2400 * mv6_reset_hc - Perform the 6xxx global soft reset
2401 * @mmio: base address of the HBA
2402 *
2403 * This routine only applies to 6xxx parts.
2404 *
2405 * LOCKING:
2406 * Inherited from caller.
2407 */
c9d39130
JG		 2408static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2409 unsigned int n_hc)
101ffae2
JG		 2410{
2411 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2412 int i, rc = 0;
2413 u32 t;
2414
2415 /* Following procedure defined in PCI "main command and status
2416 * register" table.
2417 */
2418 t = readl(reg);
2419 writel(t | STOP_PCI_MASTER, reg);
2420
2421 for (i = 0; i < 1000; i++) {
2422 udelay(1);
2423 t = readl(reg);
2dcb407e 2424 if (PCI_MASTER_EMPTY & t)
101ffae2 2425 break;
101ffae2
JG		 2426 }
2427 if (!(PCI_MASTER_EMPTY & t)) {
2428 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2429 rc = 1;
2430 goto done;
2431 }
2432
2433 /* set reset */
2434 i = 5;
2435 do {
2436 writel(t | GLOB_SFT_RST, reg);
2437 t = readl(reg);
2438 udelay(1);
2439 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2440
2441 if (!(GLOB_SFT_RST & t)) {
2442 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2443 rc = 1;
2444 goto done;
2445 }
2446
2447 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2448 i = 5;
2449 do {
2450 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2451 t = readl(reg);
2452 udelay(1);
2453 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2454
2455 if (GLOB_SFT_RST & t) {
2456 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2457 rc = 1;
2458 }
2459done:
2460 return rc;
2461}
2462
47c2b677 2463static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2464 void __iomem *mmio)
2465{
2466 void __iomem *port_mmio;
2467 u32 tmp;
2468
8e7decdb 2469 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2470 if ((tmp & (1 << 0)) == 0) {
47c2b677 2471 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2472 hpriv->signal[idx].pre = 0x1 << 5;
2473 return;
2474 }
2475
2476 port_mmio = mv_port_base(mmio, idx);
2477 tmp = readl(port_mmio + PHY_MODE2);
2478
2479 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2480 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2481}
2482
47c2b677 2483static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2484{
8e7decdb 2485 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2486}
2487
c9d39130 2488static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2489 unsigned int port)
bca1c4eb 2490{
c9d39130
JG		 2491 void __iomem *port_mmio = mv_port_base(mmio, port);
2492
bca1c4eb 2493 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2494 int fix_phy_mode2 =
2495 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2496 int fix_phy_mode4 =
47c2b677
JG		 2497 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2498 u32 m2, tmp;
2499
2500 if (fix_phy_mode2) {
2501 m2 = readl(port_mmio + PHY_MODE2);
2502 m2 &= ~(1 << 16);
2503 m2 |= (1 << 31);
2504 writel(m2, port_mmio + PHY_MODE2);
2505
2506 udelay(200);
2507
2508 m2 = readl(port_mmio + PHY_MODE2);
2509 m2 &= ~((1 << 16) | (1 << 31));
2510 writel(m2, port_mmio + PHY_MODE2);
2511
2512 udelay(200);
2513 }
2514
2515 /* who knows what this magic does */
2516 tmp = readl(port_mmio + PHY_MODE3);
2517 tmp &= ~0x7F800000;
2518 tmp |= 0x2A800000;
2519 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2520
2521 if (fix_phy_mode4) {
47c2b677 2522 u32 m4;
bca1c4eb
JG		 2523
2524 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2525
2526 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2527 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2528
e12bef50 2529 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2530 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2531
2532 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2533
2534 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2535 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2536 }
2537
2538 /* Revert values of pre-emphasis and signal amps to the saved ones */
2539 m2 = readl(port_mmio + PHY_MODE2);
2540
2541 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2542 m2 |= hpriv->signal[port].amps;
2543 m2 |= hpriv->signal[port].pre;
47c2b677 2544 m2 &= ~(1 << 16);
bca1c4eb 2545
e4e7b892
JG		 2546 /* according to mvSata 3.6.1, some IIE values are fixed */
2547 if (IS_GEN_IIE(hpriv)) {
2548 m2 &= ~0xC30FF01F;
2549 m2 |= 0x0000900F;
2550 }
2551
bca1c4eb
JG		 2552 writel(m2, port_mmio + PHY_MODE2);
2553}
2554
f351b2d6
SB		 2555/* TODO: use the generic LED interface to configure the SATA Presence */
2556/* & Acitivy LEDs on the board */
2557static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2558 void __iomem *mmio)
2559{
2560 return;
2561}
2562
2563static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2564 void __iomem *mmio)
2565{
2566 void __iomem *port_mmio;
2567 u32 tmp;
2568
2569 port_mmio = mv_port_base(mmio, idx);
2570 tmp = readl(port_mmio + PHY_MODE2);
2571
2572 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2573 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2574}
2575
2576#undef ZERO
2577#define ZERO(reg) writel(0, port_mmio + (reg))
2578static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2579 void __iomem *mmio, unsigned int port)
2580{
2581 void __iomem *port_mmio = mv_port_base(mmio, port);
2582
e12bef50 2583 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2584
2585 ZERO(0x028); /* command */
2586 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2587 ZERO(0x004); /* timer */
2588 ZERO(0x008); /* irq err cause */
2589 ZERO(0x00c); /* irq err mask */
2590 ZERO(0x010); /* rq bah */
2591 ZERO(0x014); /* rq inp */
2592 ZERO(0x018); /* rq outp */
2593 ZERO(0x01c); /* respq bah */
2594 ZERO(0x024); /* respq outp */
2595 ZERO(0x020); /* respq inp */
2596 ZERO(0x02c); /* test control */
8e7decdb 2597 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2598}
2599
2600#undef ZERO
2601
2602#define ZERO(reg) writel(0, hc_mmio + (reg))
2603static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2604 void __iomem *mmio)
2605{
2606 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2607
2608 ZERO(0x00c);
2609 ZERO(0x010);
2610 ZERO(0x014);
2611
2612}
2613
2614#undef ZERO
2615
2616static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2617 void __iomem *mmio, unsigned int n_hc)
2618{
2619 unsigned int port;
2620
2621 for (port = 0; port < hpriv->n_ports; port++)
2622 mv_soc_reset_hc_port(hpriv, mmio, port);
2623
2624 mv_soc_reset_one_hc(hpriv, mmio);
2625
2626 return 0;
2627}
2628
2629static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2630 void __iomem *mmio)
2631{
2632 return;
2633}
2634
2635static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2636{
2637 return;
2638}
2639
8e7decdb 2640static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2641{
8e7decdb 2642 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2643
8e7decdb 2644 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2645 if (want_gen2i)
8e7decdb
ML		 2646 ifcfg |= (1 << 7); /* enable gen2i speed */
2647 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2648}
2649
e12bef50 2650static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2651 unsigned int port_no)
2652{
2653 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2654
8e7decdb
ML		 2655 /*
2656 * The datasheet warns against setting EDMA_RESET when EDMA is active
2657 * (but doesn't say what the problem might be). So we first try
2658 * to disable the EDMA engine before doing the EDMA_RESET operation.
2659 */
0d8be5cb 2660 mv_stop_edma_engine(port_mmio);
8e7decdb 2661 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2662
b67a1064 2663 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2664 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2665 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2666 }
b67a1064 2667 /*
8e7decdb 2668 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2669 * link, and physical layers. It resets all SATA interface registers
2670 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2671 */
8e7decdb 2672 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2673 udelay(25); /* allow reset propagation */
c9d39130
JG		 2674 writelfl(0, port_mmio + EDMA_CMD_OFS);
2675
2676 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2677
ee9ccdf7 2678 if (IS_GEN_I(hpriv))
c9d39130
JG		 2679 mdelay(1);
2680}
2681
e49856d8 2682static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2683{
e49856d8
ML		 2684 if (sata_pmp_supported(ap)) {
2685 void __iomem *port_mmio = mv_ap_base(ap);
2686 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2687 int old = reg & 0xf;
22374677 2688
e49856d8
ML		 2689 if (old != pmp) {
2690 reg = (reg & ~0xf) | pmp;
2691 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2692 }
22374677 2693 }
20f733e7
BR		 2694}
2695
e49856d8
ML		 2696static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2697 unsigned long deadline)
22374677 2698{
e49856d8
ML		 2699 mv_pmp_select(link->ap, sata_srst_pmp(link));
2700 return sata_std_hardreset(link, class, deadline);
2701}
bdd4ddde 2702
e49856d8
ML		 2703static int mv_softreset(struct ata_link *link, unsigned int *class,
2704 unsigned long deadline)
2705{
2706 mv_pmp_select(link->ap, sata_srst_pmp(link));
2707 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2708}
2709
cc0680a5 2710static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2711 unsigned long deadline)
31961943 2712{
cc0680a5 2713 struct ata_port *ap = link->ap;
bdd4ddde 2714 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2715 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2716 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2717 int rc, attempts = 0, extra = 0;
2718 u32 sstatus;
2719 bool online;
31961943 2720
e12bef50 2721 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2722 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2723
0d8be5cb
ML		 2724 /* Workaround for errata FEr SATA#10 (part 2) */
2725 do {
17c5aab5
ML		 2726 const unsigned long *timing =
2727 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2728
17c5aab5
ML		 2729 rc = sata_link_hardreset(link, timing, deadline + extra,
2730 &online, NULL);
9dcffd99 2731 rc = online ? -EAGAIN : rc;
17c5aab5 2732 if (rc)
0d8be5cb 2733 return rc;
0d8be5cb
ML		 2734 sata_scr_read(link, SCR_STATUS, &sstatus);
2735 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2736 /* Force 1.5gb/s link speed and try again */
8e7decdb 2737 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2738 if (time_after(jiffies + HZ, deadline))
2739 extra = HZ; /* only extend it once, max */
2740 }
2741 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2742
17c5aab5 2743 return rc;
bdd4ddde
JG		 2744}
2745
bdd4ddde
JG		 2746static void mv_eh_freeze(struct ata_port *ap)
2747{
f351b2d6 2748 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2749 unsigned int shift, hardport, port = ap->port_no;
7368f919 2750 u32 main_irq_mask;
bdd4ddde
JG		 2751
2752 /* FIXME: handle coalescing completion events properly */
2753
1cfd19ae
ML		 2754 mv_stop_edma(ap);
2755 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2756
bdd4ddde 2757 /* disable assertion of portN err, done events */
7368f919
ML		 2758 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2759 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2760 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2761}
2762
2763static void mv_eh_thaw(struct ata_port *ap)
2764{
f351b2d6 2765 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2766 unsigned int shift, hardport, port = ap->port_no;
2767 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2768 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2769 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2770
2771 /* FIXME: handle coalescing completion events properly */
2772
1cfd19ae 2773 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2774
bdd4ddde
JG		 2775 /* clear EDMA errors on this port */
2776 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2777
2778 /* clear pending irq events */
2779 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2780 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2781 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2782
2783 /* enable assertion of portN err, done events */
7368f919
ML		 2784 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2785 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2786 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2787}
2788
05b308e1
BR		 2789/**
2790 * mv_port_init - Perform some early initialization on a single port.
2791 * @port: libata data structure storing shadow register addresses
2792 * @port_mmio: base address of the port
2793 *
2794 * Initialize shadow register mmio addresses, clear outstanding
2795 * interrupts on the port, and unmask interrupts for the future
2796 * start of the port.
2797 *
2798 * LOCKING:
2799 * Inherited from caller.
2800 */
31961943 2801static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2802{
0d5ff566 2803 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2804 unsigned serr_ofs;
2805
8b260248 2806 /* PIO related setup
31961943
BR		 2807 */
2808 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2809 port->error_addr =
31961943
BR		 2810 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2811 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2812 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2813 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2814 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2815 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2816 port->status_addr =
31961943
BR		 2817 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2818 /* special case: control/altstatus doesn't have ATA_REG_ address */
2819 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2820
2821 /* unused: */
8d9db2d2 2822 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2823
31961943
BR		 2824 /* Clear any currently outstanding port interrupt conditions */
2825 serr_ofs = mv_scr_offset(SCR_ERROR);
2826 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2827 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2828
646a4da5
ML		 2829 /* unmask all non-transient EDMA error interrupts */
2830 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2831
8b260248 2832 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2833 readl(port_mmio + EDMA_CFG_OFS),
2834 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2835 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2836}
2837
616d4a98
ML		 2838static unsigned int mv_in_pcix_mode(struct ata_host *host)
2839{
2840 struct mv_host_priv *hpriv = host->private_data;
2841 void __iomem *mmio = hpriv->base;
2842 u32 reg;
2843
2844 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2845 return 0; /* not PCI-X capable */
2846 reg = readl(mmio + MV_PCI_MODE_OFS);
2847 if ((reg & MV_PCI_MODE_MASK) == 0)
2848 return 0; /* conventional PCI mode */
2849 return 1; /* chip is in PCI-X mode */
2850}
2851
2852static int mv_pci_cut_through_okay(struct ata_host *host)
2853{
2854 struct mv_host_priv *hpriv = host->private_data;
2855 void __iomem *mmio = hpriv->base;
2856 u32 reg;
2857
2858 if (!mv_in_pcix_mode(host)) {
2859 reg = readl(mmio + PCI_COMMAND_OFS);
2860 if (reg & PCI_COMMAND_MRDTRIG)
2861 return 0; /* not okay */
2862 }
2863 return 1; /* okay */
2864}
2865
4447d351 2866static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2867{
4447d351
TH		 2868 struct pci_dev *pdev = to_pci_dev(host->dev);
2869 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2870 u32 hp_flags = hpriv->hp_flags;
2871
5796d1c4 2872 switch (board_idx) {
47c2b677
JG		 2873 case chip_5080:
2874 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2875 hp_flags |= MV_HP_GEN_I;
47c2b677 2876
44c10138 2877 switch (pdev->revision) {
47c2b677
JG		 2878 case 0x1:
2879 hp_flags |= MV_HP_ERRATA_50XXB0;
2880 break;
2881 case 0x3:
2882 hp_flags |= MV_HP_ERRATA_50XXB2;
2883 break;
2884 default:
2885 dev_printk(KERN_WARNING, &pdev->dev,
2886 "Applying 50XXB2 workarounds to unknown rev\n");
2887 hp_flags |= MV_HP_ERRATA_50XXB2;
2888 break;
2889 }
2890 break;
2891
bca1c4eb
JG		 2892 case chip_504x:
2893 case chip_508x:
47c2b677 2894 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2895 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2896
44c10138 2897 switch (pdev->revision) {
47c2b677
JG		 2898 case 0x0:
2899 hp_flags |= MV_HP_ERRATA_50XXB0;
2900 break;
2901 case 0x3:
2902 hp_flags |= MV_HP_ERRATA_50XXB2;
2903 break;
2904 default:
2905 dev_printk(KERN_WARNING, &pdev->dev,
2906 "Applying B2 workarounds to unknown rev\n");
2907 hp_flags |= MV_HP_ERRATA_50XXB2;
2908 break;
bca1c4eb
JG		 2909 }
2910 break;
2911
2912 case chip_604x:
2913 case chip_608x:
47c2b677 2914 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2915 hp_flags |= MV_HP_GEN_II;
47c2b677 2916
44c10138 2917 switch (pdev->revision) {
47c2b677
JG		 2918 case 0x7:
2919 hp_flags |= MV_HP_ERRATA_60X1B2;
2920 break;
2921 case 0x9:
2922 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2923 break;
2924 default:
2925 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2926 "Applying B2 workarounds to unknown rev\n");
2927 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2928 break;
2929 }
2930 break;
2931
e4e7b892 2932 case chip_7042:
616d4a98 2933 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2934 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2935 (pdev->device == 0x2300 || pdev->device == 0x2310))
2936 {
4e520033
ML		 2937 /*
2938 * Highpoint RocketRAID PCIe 23xx series cards:
2939 *
2940 * Unconfigured drives are treated as "Legacy"
2941 * by the BIOS, and it overwrites sector 8 with
2942 * a "Lgcy" metadata block prior to Linux boot.
2943 *
2944 * Configured drives (RAID or JBOD) leave sector 8
2945 * alone, but instead overwrite a high numbered
2946 * sector for the RAID metadata. This sector can
2947 * be determined exactly, by truncating the physical
2948 * drive capacity to a nice even GB value.
2949 *
2950 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2951 *
2952 * Warn the user, lest they think we're just buggy.
2953 */
2954 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2955 " BIOS CORRUPTS DATA on all attached drives,"
2956 " regardless of if/how they are configured."
2957 " BEWARE!\n");
2958 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2959 " use sectors 8-9 on \"Legacy\" drives,"
2960 " and avoid the final two gigabytes on"
2961 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2962 }
8e7decdb 2963 /* drop through */
e4e7b892
JG		 2964 case chip_6042:
2965 hpriv->ops = &mv6xxx_ops;
e4e7b892 2966 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2967 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2968 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2969
44c10138 2970 switch (pdev->revision) {
e4e7b892
JG		 2971 case 0x0:
2972 hp_flags |= MV_HP_ERRATA_XX42A0;
2973 break;
2974 case 0x1:
2975 hp_flags |= MV_HP_ERRATA_60X1C0;
2976 break;
2977 default:
2978 dev_printk(KERN_WARNING, &pdev->dev,
2979 "Applying 60X1C0 workarounds to unknown rev\n");
2980 hp_flags |= MV_HP_ERRATA_60X1C0;
2981 break;
2982 }
2983 break;
f351b2d6
SB		 2984 case chip_soc:
2985 hpriv->ops = &mv_soc_ops;
2986 hp_flags |= MV_HP_ERRATA_60X1C0;
2987 break;
e4e7b892 2988
bca1c4eb 2989 default:
f351b2d6 2990 dev_printk(KERN_ERR, host->dev,
5796d1c4 2991 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2992 return 1;
2993 }
2994
2995 hpriv->hp_flags = hp_flags;
02a121da
ML		 2996 if (hp_flags & MV_HP_PCIE) {
2997 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2998 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2999 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3000 } else {
3001 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3002 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3003 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3004 }
bca1c4eb
JG		 3005
3006 return 0;
3007}
3008
05b308e1 3009/**
47c2b677 3010 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3011 * @host: ATA host to initialize
3012 * @board_idx: controller index
05b308e1
BR		 3013 *
3014 * If possible, do an early global reset of the host. Then do
3015 * our port init and clear/unmask all/relevant host interrupts.
3016 *
3017 * LOCKING:
3018 * Inherited from caller.
3019 */
4447d351 3020static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3021{
3022 int rc = 0, n_hc, port, hc;
4447d351 3023 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3024 void __iomem *mmio = hpriv->base;
47c2b677 3025
4447d351 3026 rc = mv_chip_id(host, board_idx);
bca1c4eb 3027 if (rc)
352fab70 3028 goto done;
f351b2d6
SB		 3029
3030 if (HAS_PCI(host)) {
7368f919
ML		 3031 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3032 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3033 } else {
7368f919
ML		 3034 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3035 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3036 }
352fab70
ML		 3037
3038 /* global interrupt mask: 0 == mask everything */
7368f919 3039 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 3040
4447d351 3041 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3042
4447d351 3043 for (port = 0; port < host->n_ports; port++)
47c2b677 3044 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3045
c9d39130 3046 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3047 if (rc)
20f733e7 3048 goto done;
20f733e7 3049
522479fb 3050 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3051 hpriv->ops->reset_bus(host, mmio);
47c2b677 3052 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3053
4447d351 3054 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3055 struct ata_port *ap = host->ports[port];
2a47ce06 3056 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3057
3058 mv_port_init(&ap->ioaddr, port_mmio);
3059
7bb3c529 3060#ifdef CONFIG_PCI
f351b2d6
SB		 3061 if (HAS_PCI(host)) {
3062 unsigned int offset = port_mmio - mmio;
3063 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3064 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3065 }
7bb3c529 3066#endif
20f733e7
BR		 3067 }
3068
3069 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3070 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3071
3072 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3073 "(before clear)=0x%08x\n", hc,
3074 readl(hc_mmio + HC_CFG_OFS),
3075 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3076
3077 /* Clear any currently outstanding hc interrupt conditions */
3078 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3079 }
3080
f351b2d6
SB		 3081 if (HAS_PCI(host)) {
3082 /* Clear any currently outstanding host interrupt conditions */
3083 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3084
f351b2d6
SB		 3085 /* and unmask interrupt generation for host regs */
3086 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3087 if (IS_GEN_I(hpriv))
3088 writelfl(~HC_MAIN_MASKED_IRQS_5,
7368f919 3089 hpriv->main_irq_mask_addr);
f351b2d6
SB		 3090 else
3091 writelfl(~HC_MAIN_MASKED_IRQS,
7368f919 3092 hpriv->main_irq_mask_addr);
f351b2d6
SB		 3093
3094 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
3095 "PCI int cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 3096 readl(hpriv->main_irq_cause_addr),
3097 readl(hpriv->main_irq_mask_addr),
f351b2d6
SB		 3098 readl(mmio + hpriv->irq_cause_ofs),
3099 readl(mmio + hpriv->irq_mask_ofs));
3100 } else {
3101 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
7368f919 3102 hpriv->main_irq_mask_addr);
f351b2d6 3103 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 3104 readl(hpriv->main_irq_cause_addr),
3105 readl(hpriv->main_irq_mask_addr));
f351b2d6
SB		 3106 }
3107done:
3108 return rc;
3109}
fb621e2f 3110
fbf14e2f
BB		 3111static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3112{
3113 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3114 MV_CRQB_Q_SZ, 0);
3115 if (!hpriv->crqb_pool)
3116 return -ENOMEM;
3117
3118 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3119 MV_CRPB_Q_SZ, 0);
3120 if (!hpriv->crpb_pool)
3121 return -ENOMEM;
3122
3123 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3124 MV_SG_TBL_SZ, 0);
3125 if (!hpriv->sg_tbl_pool)
3126 return -ENOMEM;
3127
3128 return 0;
3129}
3130
15a32632
LB		 3131static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3132 struct mbus_dram_target_info *dram)
3133{
3134 int i;
3135
3136 for (i = 0; i < 4; i++) {
3137 writel(0, hpriv->base + WINDOW_CTRL(i));
3138 writel(0, hpriv->base + WINDOW_BASE(i));
3139 }
3140
3141 for (i = 0; i < dram->num_cs; i++) {
3142 struct mbus_dram_window *cs = dram->cs + i;
3143
3144 writel(((cs->size - 1) & 0xffff0000) |
3145 (cs->mbus_attr << 8) |
3146 (dram->mbus_dram_target_id << 4) | 1,
3147 hpriv->base + WINDOW_CTRL(i));
3148 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3149 }
3150}
3151
f351b2d6
SB		 3152/**
3153 * mv_platform_probe - handle a positive probe of an soc Marvell
3154 * host
3155 * @pdev: platform device found
3156 *
3157 * LOCKING:
3158 * Inherited from caller.
3159 */
3160static int mv_platform_probe(struct platform_device *pdev)
3161{
3162 static int printed_version;
3163 const struct mv_sata_platform_data *mv_platform_data;
3164 const struct ata_port_info *ppi[] =
3165 { &mv_port_info[chip_soc], NULL };
3166 struct ata_host *host;
3167 struct mv_host_priv *hpriv;
3168 struct resource *res;
3169 int n_ports, rc;
20f733e7 3170
f351b2d6
SB		 3171 if (!printed_version++)
3172 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3173
f351b2d6
SB		 3174 /*
3175 * Simple resource validation ..
3176 */
3177 if (unlikely(pdev->num_resources != 2)) {
3178 dev_err(&pdev->dev, "invalid number of resources\n");
3179 return -EINVAL;
3180 }
3181
3182 /*
3183 * Get the register base first
3184 */
3185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3186 if (res == NULL)
3187 return -EINVAL;
3188
3189 /* allocate host */
3190 mv_platform_data = pdev->dev.platform_data;
3191 n_ports = mv_platform_data->n_ports;
3192
3193 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3194 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3195
3196 if (!host || !hpriv)
3197 return -ENOMEM;
3198 host->private_data = hpriv;
3199 hpriv->n_ports = n_ports;
3200
3201 host->iomap = NULL;
f1cb0ea1
SB		 3202 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3203 res->end - res->start + 1);
f351b2d6
SB		 3204 hpriv->base -= MV_SATAHC0_REG_BASE;
3205
15a32632
LB		 3206 /*
3207 * (Re-)program MBUS remapping windows if we are asked to.
3208 */
3209 if (mv_platform_data->dram != NULL)
3210 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3211
fbf14e2f
BB		 3212 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3213 if (rc)
3214 return rc;
3215
f351b2d6
SB		 3216 /* initialize adapter */
3217 rc = mv_init_host(host, chip_soc);
3218 if (rc)
3219 return rc;
3220
3221 dev_printk(KERN_INFO, &pdev->dev,
3222 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3223 host->n_ports);
3224
3225 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3226 IRQF_SHARED, &mv6_sht);
3227}
3228
3229/*
3230 *
3231 * mv_platform_remove - unplug a platform interface
3232 * @pdev: platform device
3233 *
3234 * A platform bus SATA device has been unplugged. Perform the needed
3235 * cleanup. Also called on module unload for any active devices.
3236 */
3237static int __devexit mv_platform_remove(struct platform_device *pdev)
3238{
3239 struct device *dev = &pdev->dev;
3240 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3241
3242 ata_host_detach(host);
f351b2d6 3243 return 0;
20f733e7
BR		 3244}
3245
f351b2d6
SB		 3246static struct platform_driver mv_platform_driver = {
3247 .probe = mv_platform_probe,
3248 .remove = __devexit_p(mv_platform_remove),
3249 .driver = {
3250 .name = DRV_NAME,
3251 .owner = THIS_MODULE,
3252 },
3253};
3254
3255
7bb3c529 3256#ifdef CONFIG_PCI
f351b2d6
SB		 3257static int mv_pci_init_one(struct pci_dev *pdev,
3258 const struct pci_device_id *ent);
3259
7bb3c529
SB		 3260
3261static struct pci_driver mv_pci_driver = {
3262 .name = DRV_NAME,
3263 .id_table = mv_pci_tbl,
f351b2d6 3264 .probe = mv_pci_init_one,
7bb3c529
SB		 3265 .remove = ata_pci_remove_one,
3266};
3267
3268/*
3269 * module options
3270 */
3271static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3272
3273
3274/* move to PCI layer or libata core? */
3275static int pci_go_64(struct pci_dev *pdev)
3276{
3277 int rc;
3278
3279 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3280 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3281 if (rc) {
3282 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3283 if (rc) {
3284 dev_printk(KERN_ERR, &pdev->dev,
3285 "64-bit DMA enable failed\n");
3286 return rc;
3287 }
3288 }
3289 } else {
3290 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3291 if (rc) {
3292 dev_printk(KERN_ERR, &pdev->dev,
3293 "32-bit DMA enable failed\n");
3294 return rc;
3295 }
3296 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3297 if (rc) {
3298 dev_printk(KERN_ERR, &pdev->dev,
3299 "32-bit consistent DMA enable failed\n");
3300 return rc;
3301 }
3302 }
3303
3304 return rc;
3305}
3306
05b308e1
BR		 3307/**
3308 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3309 * @host: ATA host to print info about
05b308e1
BR		 3310 *
3311 * FIXME: complete this.
3312 *
3313 * LOCKING:
3314 * Inherited from caller.
3315 */
4447d351 3316static void mv_print_info(struct ata_host *host)
31961943 3317{
4447d351
TH		 3318 struct pci_dev *pdev = to_pci_dev(host->dev);
3319 struct mv_host_priv *hpriv = host->private_data;
44c10138 3320 u8 scc;
c1e4fe71 3321 const char *scc_s, *gen;
31961943
BR		 3322
3323 /* Use this to determine the HW stepping of the chip so we know
3324 * what errata to workaround
3325 */
31961943
BR		 3326 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3327 if (scc == 0)
3328 scc_s = "SCSI";
3329 else if (scc == 0x01)
3330 scc_s = "RAID";
3331 else
c1e4fe71
JG		 3332 scc_s = "?";
3333
3334 if (IS_GEN_I(hpriv))
3335 gen = "I";
3336 else if (IS_GEN_II(hpriv))
3337 gen = "II";
3338 else if (IS_GEN_IIE(hpriv))
3339 gen = "IIE";
3340 else
3341 gen = "?";
31961943 3342
a9524a76 3343 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3344 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3345 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3346 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3347}
3348
05b308e1 3349/**
f351b2d6 3350 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3351 * @pdev: PCI device found
3352 * @ent: PCI device ID entry for the matched host
3353 *
3354 * LOCKING:
3355 * Inherited from caller.
3356 */
f351b2d6
SB		 3357static int mv_pci_init_one(struct pci_dev *pdev,
3358 const struct pci_device_id *ent)
20f733e7 3359{
2dcb407e 3360 static int printed_version;
20f733e7 3361 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3362 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3363 struct ata_host *host;
3364 struct mv_host_priv *hpriv;
3365 int n_ports, rc;
20f733e7 3366
a9524a76
JG		 3367 if (!printed_version++)
3368 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3369
4447d351
TH		 3370 /* allocate host */
3371 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3372
3373 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3374 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3375 if (!host || !hpriv)
3376 return -ENOMEM;
3377 host->private_data = hpriv;
f351b2d6 3378 hpriv->n_ports = n_ports;
4447d351
TH		 3379
3380 /* acquire resources */
24dc5f33
TH		 3381 rc = pcim_enable_device(pdev);
3382 if (rc)
20f733e7 3383 return rc;
20f733e7 3384
0d5ff566
TH		 3385 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3386 if (rc == -EBUSY)
24dc5f33 3387 pcim_pin_device(pdev);
0d5ff566 3388 if (rc)
24dc5f33 3389 return rc;
4447d351 3390 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3391 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3392
d88184fb
JG		 3393 rc = pci_go_64(pdev);
3394 if (rc)
3395 return rc;
3396
da2fa9ba
ML		 3397 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3398 if (rc)
3399 return rc;
3400
20f733e7 3401 /* initialize adapter */
4447d351 3402 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3403 if (rc)
3404 return rc;
20f733e7 3405
31961943 3406 /* Enable interrupts */
6a59dcf8 3407 if (msi && pci_enable_msi(pdev))
31961943 3408 pci_intx(pdev, 1);
20f733e7 3409
31961943 3410 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3411 mv_print_info(host);
20f733e7 3412
4447d351 3413 pci_set_master(pdev);
ea8b4db9 3414 pci_try_set_mwi(pdev);
4447d351 3415 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3416 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3417}
7bb3c529 3418#endif
20f733e7 3419
f351b2d6
SB		 3420static int mv_platform_probe(struct platform_device *pdev);
3421static int __devexit mv_platform_remove(struct platform_device *pdev);
3422
20f733e7
BR		 3423static int __init mv_init(void)
3424{
7bb3c529
SB		 3425 int rc = -ENODEV;
3426#ifdef CONFIG_PCI
3427 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3428 if (rc < 0)
3429 return rc;
3430#endif
3431 rc = platform_driver_register(&mv_platform_driver);
3432
3433#ifdef CONFIG_PCI
3434 if (rc < 0)
3435 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3436#endif
3437 return rc;
20f733e7
BR		 3438}
3439
3440static void __exit mv_exit(void)
3441{
7bb3c529 3442#ifdef CONFIG_PCI
20f733e7 3443 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3444#endif
f351b2d6 3445 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3446}
3447
3448MODULE_AUTHOR("Brett Russ");
3449MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3450MODULE_LICENSE("GPL");
3451MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3452MODULE_VERSION(DRV_VERSION);
17c5aab5 3453MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3454
7bb3c529 3455#ifdef CONFIG_PCI
ddef9bb3
JG		 3456module_param(msi, int, 0444);
3457MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3458#endif
ddef9bb3 3459
20f733e7
BR		 3460module_init(mv_init);
3461module_exit(mv_exit);
Linux kernel - Deliverables
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