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libata-sff: reorder SFF/BMDMA functions
[deliverable/linux.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
40f21b11 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7 7 *
40f21b11
ML		 8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
20f733e7
BR		 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
4a05e209 28/*
85afb934
ML		 29 * sata_mv TODO list:
30 *
85afb934
ML		 31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
2b748a0a 33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
85afb934
ML		 34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
4a05e209 42
65ad7fef
ML		 43/*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
20f733e7
BR		 52#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/pci.h>
55#include <linux/init.h>
56#include <linux/blkdev.h>
57#include <linux/delay.h>
58#include <linux/interrupt.h>
8d8b6004 59#include <linux/dmapool.h>
20f733e7 60#include <linux/dma-mapping.h>
a9524a76 61#include <linux/device.h>
c77a2f4e 62#include <linux/clk.h>
f351b2d6
SB		 63#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
15a32632 65#include <linux/mbus.h>
c46938cc 66#include <linux/bitops.h>
5a0e3ad6 67#include <linux/gfp.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
cae5a29d 74#define DRV_VERSION "1.28"
20f733e7 75
40f21b11
ML		 76/*
77 * module options
78 */
79
80static int msi;
81#ifdef CONFIG_PCI
82module_param(msi, int, S_IRUGO);
83MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84#endif
85
2b748a0a
ML		 86static int irq_coalescing_io_count;
87module_param(irq_coalescing_io_count, int, S_IRUGO);
88MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
90
91static int irq_coalescing_usecs;
92module_param(irq_coalescing_usecs, int, S_IRUGO);
93MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
95
20f733e7
BR		 96enum {
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104
2b748a0a
ML		 105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109
20f733e7 110 MV_PCI_REG_BASE = 0,
615ab953 111
2b748a0a
ML		 112 /*
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
115 *
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 */
cae5a29d
ML		 119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
2b748a0a
ML		 121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122
cae5a29d
ML		 123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
2b748a0a
ML		 125
126 /*
127 * Registers for the (unused here) transaction coalescing feature:
128 */
cae5a29d
ML		 129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
2b748a0a 131
cae5a29d
ML		 132 SATAHC0_REG_BASE = 0x20000,
133 FLASH_CTL = 0x1046c,
134 GPIO_PORT_CTL = 0x104f0,
135 RESET_CFG = 0x180d8,
20f733e7
BR		 136
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141
31961943
BR		 142 MV_MAX_Q_DEPTH = 32,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 */
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 151 MV_MAX_SG_CT = 256,
31961943 152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 153
352fab70 154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 155 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 159
160 /* Host Flags */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
7bb3c529 162
c5d3e45a 163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91b1a84c 164 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
ad3aef51 165
91b1a84c 166 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 167
40f21b11
ML		 168 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
169 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
91b1a84c
ML		 170
171 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 172
31961943
BR		 173 CRQB_FLAG_READ = (1 << 0),
174 CRQB_TAG_SHIFT = 1,
c5d3e45a 175 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 176 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 177 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 178 CRQB_CMD_ADDR_SHIFT = 8,
179 CRQB_CMD_CS = (0x2 << 11),
180 CRQB_CMD_LAST = (1 << 15),
181
182 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 183 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
184 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 185
186 EPRD_FLAG_END_OF_TBL = (1 << 31),
187
20f733e7
BR		 188 /* PCI interface registers */
189
cae5a29d
ML		 190 MV_PCI_COMMAND = 0xc00,
191 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
192 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 193
cae5a29d 194 PCI_MAIN_CMD_STS = 0xd30,
20f733e7
BR		 195 STOP_PCI_MASTER = (1 << 2),
196 PCI_MASTER_EMPTY = (1 << 3),
197 GLOB_SFT_RST = (1 << 4),
198
cae5a29d 199 MV_PCI_MODE = 0xd00,
8e7decdb
ML		 200 MV_PCI_MODE_MASK = 0x30,
201
522479fb
JG		 202 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
203 MV_PCI_DISC_TIMER = 0xd04,
204 MV_PCI_MSI_TRIGGER = 0xc38,
205 MV_PCI_SERR_MASK = 0xc28,
cae5a29d 206 MV_PCI_XBAR_TMOUT = 0x1d04,
522479fb
JG		 207 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
208 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
209 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
210 MV_PCI_ERR_COMMAND = 0x1d50,
211
cae5a29d
ML		 212 PCI_IRQ_CAUSE = 0x1d58,
213 PCI_IRQ_MASK = 0x1d5c,
20f733e7
BR		 214 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
215
cae5a29d
ML		 216 PCIE_IRQ_CAUSE = 0x1900,
217 PCIE_IRQ_MASK = 0x1910,
646a4da5 218 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 219
7368f919 220 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
cae5a29d
ML		 221 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
222 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
223 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
224 SOC_HC_MAIN_IRQ_MASK = 0x20024,
40f21b11
ML		 225 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
226 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
20f733e7
BR		 227 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
228 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
2b748a0a
ML		 229 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
230 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
20f733e7 231 PCI_ERR = (1 << 18),
40f21b11
ML		 232 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
233 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
234 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
235 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
236 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
20f733e7
BR		 237 GPIO_INT = (1 << 22),
238 SELF_INT = (1 << 23),
239 TWSI_INT = (1 << 24),
240 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 241 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 242 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 243
244 /* SATAHC registers */
cae5a29d 245 HC_CFG = 0x00,
20f733e7 246
cae5a29d 247 HC_IRQ_CAUSE = 0x14,
352fab70
ML		 248 DMA_IRQ = (1 << 0), /* shift by port # */
249 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 250 DEV_IRQ = (1 << 8), /* shift by port # */
251
2b748a0a
ML		 252 /*
253 * Per-HC (Host-Controller) interrupt coalescing feature.
254 * This is present on all chip generations.
255 *
256 * Coalescing defers the interrupt until either the IO_THRESHOLD
257 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258 */
cae5a29d
ML		 259 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
260 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
2b748a0a 261
cae5a29d 262 SOC_LED_CTRL = 0x2c,
000b344f
ML		 263 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
264 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
265 /* with dev activity LED */
266
20f733e7 267 /* Shadow block registers */
cae5a29d
ML		 268 SHD_BLK = 0x100,
269 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
20f733e7
BR		 270
271 /* SATA registers */
cae5a29d
ML		 272 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
273 SATA_ACTIVE = 0x350,
274 FIS_IRQ_CAUSE = 0x364,
275 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
17c5aab5 276
cae5a29d 277 LTMODE = 0x30c, /* requires read-after-write */
17c5aab5
ML		 278 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
279
cae5a29d 280 PHY_MODE2 = 0x330,
47c2b677 281 PHY_MODE3 = 0x310,
cae5a29d
ML		 282
283 PHY_MODE4 = 0x314, /* requires read-after-write */
ba069e37
ML		 284 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
285 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
286 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
287 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
288
cae5a29d
ML		 289 SATA_IFCTL = 0x344,
290 SATA_TESTCTL = 0x348,
291 SATA_IFSTAT = 0x34c,
292 VENDOR_UNIQUE_FIS = 0x35c,
17c5aab5 293
cae5a29d 294 FISCFG = 0x360,
8e7decdb
ML		 295 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
296 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 297
29b7e43c
MM		 298 PHY_MODE9_GEN2 = 0x398,
299 PHY_MODE9_GEN1 = 0x39c,
300 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
301
c9d39130 302 MV5_PHY_MODE = 0x74,
cae5a29d
ML		 303 MV5_LTMODE = 0x30,
304 MV5_PHY_CTL = 0x0C,
305 SATA_IFCFG = 0x050,
bca1c4eb
JG		 306
307 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 308
309 /* Port registers */
cae5a29d 310 EDMA_CFG = 0,
0c58912e
ML		 311 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
312 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
313 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
314 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
315 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 316 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
317 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7 318
cae5a29d
ML		 319 EDMA_ERR_IRQ_CAUSE = 0x8,
320 EDMA_ERR_IRQ_MASK = 0xc,
6c1153e0
JG		 321 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
322 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
323 EDMA_ERR_DEV = (1 << 2), /* device error */
324 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
325 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
326 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 327 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
328 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 329 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 330 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 331 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
332 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
333 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
334 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 335
6c1153e0 336 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 337 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
338 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
339 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
340 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
341
6c1153e0 342 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 343
6c1153e0 344 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 345 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
346 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
347 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
348 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
349 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
350
6c1153e0 351 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 352
6c1153e0 353 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 354 EDMA_ERR_OVERRUN_5 = (1 << 5),
355 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 356
357 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
358 EDMA_ERR_LNK_CTRL_RX_1 |
359 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 360 EDMA_ERR_LNK_CTRL_TX,
646a4da5 361
bdd4ddde
JG		 362 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
363 EDMA_ERR_PRD_PAR |
364 EDMA_ERR_DEV_DCON |
365 EDMA_ERR_DEV_CON |
366 EDMA_ERR_SERR |
367 EDMA_ERR_SELF_DIS |
6c1153e0 368 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 369 EDMA_ERR_CRPB_PAR |
370 EDMA_ERR_INTRL_PAR |
371 EDMA_ERR_IORDY |
372 EDMA_ERR_LNK_CTRL_RX_2 |
373 EDMA_ERR_LNK_DATA_RX |
374 EDMA_ERR_LNK_DATA_TX |
375 EDMA_ERR_TRANS_PROTO,
e12bef50 376
bdd4ddde
JG		 377 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
378 EDMA_ERR_PRD_PAR |
379 EDMA_ERR_DEV_DCON |
380 EDMA_ERR_DEV_CON |
381 EDMA_ERR_OVERRUN_5 |
382 EDMA_ERR_UNDERRUN_5 |
383 EDMA_ERR_SELF_DIS_5 |
6c1153e0 384 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 385 EDMA_ERR_CRPB_PAR |
386 EDMA_ERR_INTRL_PAR |
387 EDMA_ERR_IORDY,
20f733e7 388
cae5a29d
ML		 389 EDMA_REQ_Q_BASE_HI = 0x10,
390 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
31961943 391
cae5a29d 392 EDMA_REQ_Q_OUT_PTR = 0x18,
31961943
BR		 393 EDMA_REQ_Q_PTR_SHIFT = 5,
394
cae5a29d
ML		 395 EDMA_RSP_Q_BASE_HI = 0x1c,
396 EDMA_RSP_Q_IN_PTR = 0x20,
397 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
31961943
BR		 398 EDMA_RSP_Q_PTR_SHIFT = 3,
399
cae5a29d 400 EDMA_CMD = 0x28, /* EDMA command register */
0ea9e179
JG		 401 EDMA_EN = (1 << 0), /* enable EDMA */
402 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 403 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
404
cae5a29d 405 EDMA_STATUS = 0x30, /* EDMA engine status */
8e7decdb
ML		 406 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
407 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 408
cae5a29d
ML		 409 EDMA_IORDY_TMOUT = 0x34,
410 EDMA_ARB_CFG = 0x38,
8e7decdb 411
cae5a29d
ML		 412 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
413 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
da14265e 414
cae5a29d
ML		 415 BMDMA_CMD = 0x224, /* bmdma command register */
416 BMDMA_STATUS = 0x228, /* bmdma status register */
417 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
418 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
da14265e 419
31961943
BR		 420 /* Host private flags (hp_flags) */
421 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 422 MV_HP_ERRATA_50XXB0 = (1 << 1),
423 MV_HP_ERRATA_50XXB2 = (1 << 2),
424 MV_HP_ERRATA_60X1B2 = (1 << 3),
425 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 426 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
427 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
428 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 429 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 430 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 431 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
000b344f 432 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
20f733e7 433
31961943 434 /* Port private flags (pp_flags) */
0ea9e179 435 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 436 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 437 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 438 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
d16ab3f6 439 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
20f733e7
BR		 440};
441
ee9ccdf7
JG		 442#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
443#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 444#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 445#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 446#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 447
15a32632
LB		 448#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
449#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
450
095fec88 451enum {
baf14aa1
JG		 452 /* DMA boundary 0xffff is required by the s/g splitting
453 * we need on /length/ in mv_fill-sg().
454 */
455 MV_DMA_BOUNDARY = 0xffffU,
095fec88 456
0ea9e179
JG		 457 /* mask of register bits containing lower 32 bits
458 * of EDMA request queue DMA address
459 */
095fec88
JG		 460 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
461
0ea9e179 462 /* ditto, for response queue */
095fec88
JG		 463 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464};
465
522479fb
JG		 466enum chip_type {
467 chip_504x,
468 chip_508x,
469 chip_5080,
470 chip_604x,
471 chip_608x,
e4e7b892
JG		 472 chip_6042,
473 chip_7042,
f351b2d6 474 chip_soc,
522479fb
JG		 475};
476
31961943
BR		 477/* Command ReQuest Block: 32B */
478struct mv_crqb {
e1469874
ML		 479 __le32 sg_addr;
480 __le32 sg_addr_hi;
481 __le16 ctrl_flags;
482 __le16 ata_cmd[11];
31961943 483};
20f733e7 484
e4e7b892 485struct mv_crqb_iie {
e1469874
ML		 486 __le32 addr;
487 __le32 addr_hi;
488 __le32 flags;
489 __le32 len;
490 __le32 ata_cmd[4];
e4e7b892
JG		 491};
492
31961943
BR		 493/* Command ResPonse Block: 8B */
494struct mv_crpb {
e1469874
ML		 495 __le16 id;
496 __le16 flags;
497 __le32 tmstmp;
20f733e7
BR		 498};
499
31961943
BR		 500/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
501struct mv_sg {
e1469874
ML		 502 __le32 addr;
503 __le32 flags_size;
504 __le32 addr_hi;
505 __le32 reserved;
31961943 506};
20f733e7 507
08da1759
ML		 508/*
509 * We keep a local cache of a few frequently accessed port
510 * registers here, to avoid having to read them (very slow)
511 * when switching between EDMA and non-EDMA modes.
512 */
513struct mv_cached_regs {
514 u32 fiscfg;
515 u32 ltmode;
516 u32 haltcond;
c01e8a23 517 u32 unknown_rsvd;
08da1759
ML		 518};
519
31961943
BR		 520struct mv_port_priv {
521 struct mv_crqb *crqb;
522 dma_addr_t crqb_dma;
523 struct mv_crpb *crpb;
524 dma_addr_t crpb_dma;
eb73d558
ML		 525 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
526 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 527
528 unsigned int req_idx;
529 unsigned int resp_idx;
530
31961943 531 u32 pp_flags;
08da1759 532 struct mv_cached_regs cached;
29d187bb 533 unsigned int delayed_eh_pmp_map;
31961943
BR		 534};
535
bca1c4eb
JG		 536struct mv_port_signal {
537 u32 amps;
538 u32 pre;
539};
540
02a121da
ML		 541struct mv_host_priv {
542 u32 hp_flags;
1bfeff03 543 unsigned int board_idx;
96e2c487 544 u32 main_irq_mask;
02a121da
ML		 545 struct mv_port_signal signal[8];
546 const struct mv_hw_ops *ops;
f351b2d6
SB		 547 int n_ports;
548 void __iomem *base;
7368f919
ML		 549 void __iomem *main_irq_cause_addr;
550 void __iomem *main_irq_mask_addr;
cae5a29d
ML		 551 u32 irq_cause_offset;
552 u32 irq_mask_offset;
02a121da 553 u32 unmask_all_irqs;
c77a2f4e
SB		 554
555#if defined(CONFIG_HAVE_CLK)
556 struct clk *clk;
557#endif
da2fa9ba
ML		 558 /*
559 * These consistent DMA memory pools give us guaranteed
560 * alignment for hardware-accessed data structures,
561 * and less memory waste in accomplishing the alignment.
562 */
563 struct dma_pool *crqb_pool;
564 struct dma_pool *crpb_pool;
565 struct dma_pool *sg_tbl_pool;
02a121da
ML		 566};
567
47c2b677 568struct mv_hw_ops {
2a47ce06
JG		 569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
570 unsigned int port);
47c2b677
JG		 571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
573 void __iomem *mmio);
c9d39130
JG		 574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
575 unsigned int n_hc);
522479fb 576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 578};
579
82ef04fb
TH		 580static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
581static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 584static int mv_port_start(struct ata_port *ap);
585static void mv_port_stop(struct ata_port *ap);
3e4a1391 586static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 587static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 588static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 589static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 590static int mv_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline);
bdd4ddde
JG		 592static void mv_eh_freeze(struct ata_port *ap);
593static void mv_eh_thaw(struct ata_port *ap);
f273827e 594static void mv6_dev_config(struct ata_device *dev);
20f733e7 595
2a47ce06
JG		 596static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
597 unsigned int port);
47c2b677
JG		 598static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
600 void __iomem *mmio);
c9d39130
JG		 601static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
602 unsigned int n_hc);
522479fb 603static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 604static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 605
2a47ce06
JG		 606static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port);
47c2b677
JG		 608static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
c9d39130
JG		 611static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
612 unsigned int n_hc);
522479fb 613static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 614static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
615 void __iomem *mmio);
616static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
617 void __iomem *mmio);
618static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619 void __iomem *mmio, unsigned int n_hc);
620static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
621 void __iomem *mmio);
622static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
29b7e43c
MM		 623static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624 void __iomem *mmio, unsigned int port);
7bb3c529 625static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 626static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 627 unsigned int port_no);
e12bef50 628static int mv_stop_edma(struct ata_port *ap);
b562468c 629static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 630static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 631
e49856d8
ML		 632static void mv_pmp_select(struct ata_port *ap, int pmp);
633static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
634 unsigned long deadline);
635static int mv_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
29d187bb 637static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 638static void mv_process_crpb_entries(struct ata_port *ap,
639 struct mv_port_priv *pp);
47c2b677 640
da14265e
ML		 641static void mv_sff_irq_clear(struct ata_port *ap);
642static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644static void mv_bmdma_start(struct ata_queued_cmd *qc);
645static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646static u8 mv_bmdma_status(struct ata_port *ap);
d16ab3f6 647static u8 mv_sff_check_status(struct ata_port *ap);
da14265e 648
eb73d558
ML		 649/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650 * because we have to allow room for worst case splitting of
651 * PRDs for 64K boundaries in mv_fill_sg().
652 */
c5d3e45a 653static struct scsi_host_template mv5_sht = {
68d1d07b 654 ATA_BASE_SHT(DRV_NAME),
baf14aa1 655 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 656 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 657};
658
659static struct scsi_host_template mv6_sht = {
68d1d07b 660 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 661 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 662 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 663 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 664};
665
029cfd6b
TH		 666static struct ata_port_operations mv5_ops = {
667 .inherits = &ata_sff_port_ops,
c9d39130 668
c96f1732
AC		 669 .lost_interrupt = ATA_OP_NULL,
670
3e4a1391 671 .qc_defer = mv_qc_defer,
c9d39130
JG		 672 .qc_prep = mv_qc_prep,
673 .qc_issue = mv_qc_issue,
c9d39130 674
bdd4ddde
JG		 675 .freeze = mv_eh_freeze,
676 .thaw = mv_eh_thaw,
a1efdaba 677 .hardreset = mv_hardreset,
a1efdaba 678 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 679 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 680
c9d39130
JG		 681 .scr_read = mv5_scr_read,
682 .scr_write = mv5_scr_write,
683
684 .port_start = mv_port_start,
685 .port_stop = mv_port_stop,
c9d39130
JG		 686};
687
029cfd6b
TH		 688static struct ata_port_operations mv6_ops = {
689 .inherits = &mv5_ops,
f273827e 690 .dev_config = mv6_dev_config,
20f733e7
BR		 691 .scr_read = mv_scr_read,
692 .scr_write = mv_scr_write,
693
e49856d8
ML		 694 .pmp_hardreset = mv_pmp_hardreset,
695 .pmp_softreset = mv_softreset,
696 .softreset = mv_softreset,
29d187bb 697 .error_handler = mv_pmp_error_handler,
da14265e 698
40f21b11 699 .sff_check_status = mv_sff_check_status,
da14265e
ML		 700 .sff_irq_clear = mv_sff_irq_clear,
701 .check_atapi_dma = mv_check_atapi_dma,
702 .bmdma_setup = mv_bmdma_setup,
703 .bmdma_start = mv_bmdma_start,
704 .bmdma_stop = mv_bmdma_stop,
705 .bmdma_status = mv_bmdma_status,
20f733e7
BR		 706};
707
029cfd6b
TH		 708static struct ata_port_operations mv_iie_ops = {
709 .inherits = &mv6_ops,
710 .dev_config = ATA_OP_NULL,
e4e7b892 711 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 712};
713
98ac62de 714static const struct ata_port_info mv_port_info[] = {
20f733e7 715 { /* chip_504x */
91b1a84c 716 .flags = MV_GEN_I_FLAGS,
c361acbc 717 .pio_mask = ATA_PIO4,
bf6263a8 718 .udma_mask = ATA_UDMA6,
c9d39130 719 .port_ops = &mv5_ops,
20f733e7
BR		 720 },
721 { /* chip_508x */
91b1a84c 722 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 723 .pio_mask = ATA_PIO4,
bf6263a8 724 .udma_mask = ATA_UDMA6,
c9d39130 725 .port_ops = &mv5_ops,
20f733e7 726 },
47c2b677 727 { /* chip_5080 */
91b1a84c 728 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 729 .pio_mask = ATA_PIO4,
bf6263a8 730 .udma_mask = ATA_UDMA6,
c9d39130 731 .port_ops = &mv5_ops,
47c2b677 732 },
20f733e7 733 { /* chip_604x */
91b1a84c 734 .flags = MV_GEN_II_FLAGS,
c361acbc 735 .pio_mask = ATA_PIO4,
bf6263a8 736 .udma_mask = ATA_UDMA6,
c9d39130 737 .port_ops = &mv6_ops,
20f733e7
BR		 738 },
739 { /* chip_608x */
91b1a84c 740 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 741 .pio_mask = ATA_PIO4,
bf6263a8 742 .udma_mask = ATA_UDMA6,
c9d39130 743 .port_ops = &mv6_ops,
20f733e7 744 },
e4e7b892 745 { /* chip_6042 */
91b1a84c 746 .flags = MV_GEN_IIE_FLAGS,
c361acbc 747 .pio_mask = ATA_PIO4,
bf6263a8 748 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 749 .port_ops = &mv_iie_ops,
750 },
751 { /* chip_7042 */
91b1a84c 752 .flags = MV_GEN_IIE_FLAGS,
c361acbc 753 .pio_mask = ATA_PIO4,
bf6263a8 754 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 755 .port_ops = &mv_iie_ops,
756 },
f351b2d6 757 { /* chip_soc */
91b1a84c 758 .flags = MV_GEN_IIE_FLAGS,
c361acbc 759 .pio_mask = ATA_PIO4,
17c5aab5
ML		 760 .udma_mask = ATA_UDMA6,
761 .port_ops = &mv_iie_ops,
f351b2d6 762 },
20f733e7
BR		 763};
764
3b7d697d 765static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 766 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
767 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
768 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
769 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 770 /* RocketRAID 1720/174x have different identifiers */
771 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 772 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
773 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 774
775 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
776 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
777 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
778 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
779 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
780
781 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
782
d9f9c6bc
FA		 783 /* Adaptec 1430SA */
784 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
785
02a121da 786 /* Marvell 7042 support */
6a3d586d
MT		 787 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
788
02a121da
ML		 789 /* Highpoint RocketRAID PCIe series */
790 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
791 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
792
2d2744fc 793 { } /* terminate list */
20f733e7
BR		 794};
795
47c2b677
JG		 796static const struct mv_hw_ops mv5xxx_ops = {
797 .phy_errata = mv5_phy_errata,
798 .enable_leds = mv5_enable_leds,
799 .read_preamp = mv5_read_preamp,
800 .reset_hc = mv5_reset_hc,
522479fb
JG		 801 .reset_flash = mv5_reset_flash,
802 .reset_bus = mv5_reset_bus,
47c2b677
JG		 803};
804
805static const struct mv_hw_ops mv6xxx_ops = {
806 .phy_errata = mv6_phy_errata,
807 .enable_leds = mv6_enable_leds,
808 .read_preamp = mv6_read_preamp,
809 .reset_hc = mv6_reset_hc,
522479fb
JG		 810 .reset_flash = mv6_reset_flash,
811 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 812};
813
f351b2d6
SB		 814static const struct mv_hw_ops mv_soc_ops = {
815 .phy_errata = mv6_phy_errata,
816 .enable_leds = mv_soc_enable_leds,
817 .read_preamp = mv_soc_read_preamp,
818 .reset_hc = mv_soc_reset_hc,
819 .reset_flash = mv_soc_reset_flash,
820 .reset_bus = mv_soc_reset_bus,
821};
822
29b7e43c
MM		 823static const struct mv_hw_ops mv_soc_65n_ops = {
824 .phy_errata = mv_soc_65n_phy_errata,
825 .enable_leds = mv_soc_enable_leds,
826 .reset_hc = mv_soc_reset_hc,
827 .reset_flash = mv_soc_reset_flash,
828 .reset_bus = mv_soc_reset_bus,
829};
830
20f733e7
BR		 831/*
832 * Functions
833 */
834
835static inline void writelfl(unsigned long data, void __iomem *addr)
836{
837 writel(data, addr);
838 (void) readl(addr); /* flush to avoid PCI posted write */
839}
840
c9d39130
JG		 841static inline unsigned int mv_hc_from_port(unsigned int port)
842{
843 return port >> MV_PORT_HC_SHIFT;
844}
845
846static inline unsigned int mv_hardport_from_port(unsigned int port)
847{
848 return port & MV_PORT_MASK;
849}
850
1cfd19ae
ML		 851/*
852 * Consolidate some rather tricky bit shift calculations.
853 * This is hot-path stuff, so not a function.
854 * Simple code, with two return values, so macro rather than inline.
855 *
856 * port is the sole input, in range 0..7.
7368f919
ML		 857 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
858 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 859 *
860 * Note that port and hardport may be the same variable in some cases.
861 */
862#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
863{ \
864 shift = mv_hc_from_port(port) * HC_SHIFT; \
865 hardport = mv_hardport_from_port(port); \
866 shift += hardport * 2; \
867}
868
352fab70
ML		 869static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
870{
cae5a29d 871 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
352fab70
ML		 872}
873
c9d39130
JG		 874static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
875 unsigned int port)
876{
877 return mv_hc_base(base, mv_hc_from_port(port));
878}
879
20f733e7
BR		 880static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
881{
c9d39130 882 return mv_hc_base_from_port(base, port) +
8b260248 883 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 884 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 885}
886
e12bef50
ML		 887static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
888{
889 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
890 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
891
892 return hc_mmio + ofs;
893}
894
f351b2d6
SB		 895static inline void __iomem *mv_host_base(struct ata_host *host)
896{
897 struct mv_host_priv *hpriv = host->private_data;
898 return hpriv->base;
899}
900
20f733e7
BR		 901static inline void __iomem *mv_ap_base(struct ata_port *ap)
902{
f351b2d6 903 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 904}
905
cca3974e 906static inline int mv_get_hc_count(unsigned long port_flags)
31961943 907{
cca3974e 908 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 909}
910
08da1759
ML		 911/**
912 * mv_save_cached_regs - (re-)initialize cached port registers
913 * @ap: the port whose registers we are caching
914 *
915 * Initialize the local cache of port registers,
916 * so that reading them over and over again can
917 * be avoided on the hotter paths of this driver.
918 * This saves a few microseconds each time we switch
919 * to/from EDMA mode to perform (eg.) a drive cache flush.
920 */
921static void mv_save_cached_regs(struct ata_port *ap)
922{
923 void __iomem *port_mmio = mv_ap_base(ap);
924 struct mv_port_priv *pp = ap->private_data;
925
cae5a29d
ML		 926 pp->cached.fiscfg = readl(port_mmio + FISCFG);
927 pp->cached.ltmode = readl(port_mmio + LTMODE);
928 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
929 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
08da1759
ML		 930}
931
932/**
933 * mv_write_cached_reg - write to a cached port register
934 * @addr: hardware address of the register
935 * @old: pointer to cached value of the register
936 * @new: new value for the register
937 *
938 * Write a new value to a cached register,
939 * but only if the value is different from before.
940 */
941static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
942{
943 if (new != *old) {
12f3b6d7 944 unsigned long laddr;
08da1759 945 *old = new;
12f3b6d7
ML		 946 /*
947 * Workaround for 88SX60x1-B2 FEr SATA#13:
948 * Read-after-write is needed to prevent generating 64-bit
949 * write cycles on the PCI bus for SATA interface registers
950 * at offsets ending in 0x4 or 0xc.
951 *
952 * Looks like a lot of fuss, but it avoids an unnecessary
953 * +1 usec read-after-write delay for unaffected registers.
954 */
955 laddr = (long)addr & 0xffff;
956 if (laddr >= 0x300 && laddr <= 0x33c) {
957 laddr &= 0x000f;
958 if (laddr == 0x4 || laddr == 0xc) {
959 writelfl(new, addr); /* read after write */
960 return;
961 }
962 }
963 writel(new, addr); /* unaffected by the errata */
08da1759
ML		 964 }
965}
966
c5d3e45a
JG		 967static void mv_set_edma_ptrs(void __iomem *port_mmio,
968 struct mv_host_priv *hpriv,
969 struct mv_port_priv *pp)
970{
bdd4ddde
JG		 971 u32 index;
972
c5d3e45a
JG		 973 /*
974 * initialize request queue
975 */
fcfb1f77
ML		 976 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
977 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 978
c5d3e45a 979 WARN_ON(pp->crqb_dma & 0x3ff);
cae5a29d 980 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
bdd4ddde 981 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
cae5a29d
ML		 982 port_mmio + EDMA_REQ_Q_IN_PTR);
983 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
c5d3e45a
JG		 984
985 /*
986 * initialize response queue
987 */
fcfb1f77
ML		 988 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
989 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 990
c5d3e45a 991 WARN_ON(pp->crpb_dma & 0xff);
cae5a29d
ML		 992 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
993 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
bdd4ddde 994 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
cae5a29d 995 port_mmio + EDMA_RSP_Q_OUT_PTR);
c5d3e45a
JG		 996}
997
2b748a0a
ML		 998static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
999{
1000 /*
1001 * When writing to the main_irq_mask in hardware,
1002 * we must ensure exclusivity between the interrupt coalescing bits
1003 * and the corresponding individual port DONE_IRQ bits.
1004 *
1005 * Note that this register is really an "IRQ enable" register,
1006 * not an "IRQ mask" register as Marvell's naming might suggest.
1007 */
1008 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1009 mask &= ~DONE_IRQ_0_3;
1010 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1011 mask &= ~DONE_IRQ_4_7;
1012 writelfl(mask, hpriv->main_irq_mask_addr);
1013}
1014
c4de573b
ML		 1015static void mv_set_main_irq_mask(struct ata_host *host,
1016 u32 disable_bits, u32 enable_bits)
1017{
1018 struct mv_host_priv *hpriv = host->private_data;
1019 u32 old_mask, new_mask;
1020
96e2c487 1021 old_mask = hpriv->main_irq_mask;
c4de573b 1022 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 1023 if (new_mask != old_mask) {
1024 hpriv->main_irq_mask = new_mask;
2b748a0a 1025 mv_write_main_irq_mask(new_mask, hpriv);
96e2c487 1026 }
c4de573b
ML		 1027}
1028
1029static void mv_enable_port_irqs(struct ata_port *ap,
1030 unsigned int port_bits)
1031{
1032 unsigned int shift, hardport, port = ap->port_no;
1033 u32 disable_bits, enable_bits;
1034
1035 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1036
1037 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1038 enable_bits = port_bits << shift;
1039 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1040}
1041
00b81235
ML		 1042static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1043 void __iomem *port_mmio,
1044 unsigned int port_irqs)
1045{
1046 struct mv_host_priv *hpriv = ap->host->private_data;
1047 int hardport = mv_hardport_from_port(ap->port_no);
1048 void __iomem *hc_mmio = mv_hc_base_from_port(
1049 mv_host_base(ap->host), ap->port_no);
1050 u32 hc_irq_cause;
1051
1052 /* clear EDMA event indicators, if any */
cae5a29d 1053 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
00b81235
ML		 1054
1055 /* clear pending irq events */
1056 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 1057 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
00b81235
ML		 1058
1059 /* clear FIS IRQ Cause */
1060 if (IS_GEN_IIE(hpriv))
cae5a29d 1061 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
00b81235
ML		 1062
1063 mv_enable_port_irqs(ap, port_irqs);
1064}
1065
2b748a0a
ML		 1066static void mv_set_irq_coalescing(struct ata_host *host,
1067 unsigned int count, unsigned int usecs)
1068{
1069 struct mv_host_priv *hpriv = host->private_data;
1070 void __iomem *mmio = hpriv->base, *hc_mmio;
1071 u32 coal_enable = 0;
1072 unsigned long flags;
6abf4678 1073 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
2b748a0a
ML		 1074 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1075 ALL_PORTS_COAL_DONE;
1076
1077 /* Disable IRQ coalescing if either threshold is zero */
1078 if (!usecs || !count) {
1079 clks = count = 0;
1080 } else {
1081 /* Respect maximum limits of the hardware */
1082 clks = usecs * COAL_CLOCKS_PER_USEC;
1083 if (clks > MAX_COAL_TIME_THRESHOLD)
1084 clks = MAX_COAL_TIME_THRESHOLD;
1085 if (count > MAX_COAL_IO_COUNT)
1086 count = MAX_COAL_IO_COUNT;
1087 }
1088
1089 spin_lock_irqsave(&host->lock, flags);
6abf4678 1090 mv_set_main_irq_mask(host, coal_disable, 0);
2b748a0a 1091
6abf4678 1092 if (is_dual_hc && !IS_GEN_I(hpriv)) {
2b748a0a 1093 /*
6abf4678
ML		 1094 * GEN_II/GEN_IIE with dual host controllers:
1095 * one set of global thresholds for the entire chip.
2b748a0a 1096 */
cae5a29d
ML		 1097 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1098 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
2b748a0a 1099 /* clear leftover coal IRQ bit */
cae5a29d 1100 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
6abf4678
ML		 1101 if (count)
1102 coal_enable = ALL_PORTS_COAL_DONE;
1103 clks = count = 0; /* force clearing of regular regs below */
2b748a0a 1104 }
6abf4678 1105
2b748a0a
ML		 1106 /*
1107 * All chips: independent thresholds for each HC on the chip.
1108 */
1109 hc_mmio = mv_hc_base_from_port(mmio, 0);
cae5a29d
ML		 1110 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1111 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1112 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1113 if (count)
1114 coal_enable |= PORTS_0_3_COAL_DONE;
1115 if (is_dual_hc) {
2b748a0a 1116 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
cae5a29d
ML		 1117 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1118 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1119 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1120 if (count)
1121 coal_enable |= PORTS_4_7_COAL_DONE;
2b748a0a 1122 }
2b748a0a 1123
6abf4678 1124 mv_set_main_irq_mask(host, 0, coal_enable);
2b748a0a
ML		 1125 spin_unlock_irqrestore(&host->lock, flags);
1126}
1127
05b308e1 1128/**
00b81235 1129 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 1130 * @base: port base address
1131 * @pp: port private data
1132 *
beec7dbc
TH		 1133 * Verify the local cache of the eDMA state is accurate with a
1134 * WARN_ON.
05b308e1
BR		 1135 *
1136 * LOCKING:
1137 * Inherited from caller.
1138 */
00b81235 1139static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 1140 struct mv_port_priv *pp, u8 protocol)
20f733e7 1141{
72109168
ML		 1142 int want_ncq = (protocol == ATA_PROT_NCQ);
1143
1144 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1145 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1146 if (want_ncq != using_ncq)
b562468c 1147 mv_stop_edma(ap);
72109168 1148 }
c5d3e45a 1149 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 1150 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 1151
00b81235 1152 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 1153
f630d562 1154 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 1155 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 1156
cae5a29d 1157 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
afb0edd9
BR		 1158 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1159 }
20f733e7
BR		 1160}
1161
9b2c4e0b
ML		 1162static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1163{
1164 void __iomem *port_mmio = mv_ap_base(ap);
1165 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1166 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1167 int i;
1168
1169 /*
1170 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 1171 * No idea what a good "timeout" value might be, but measurements
1172 * indicate that it often requires hundreds of microseconds
1173 * with two drives in-use. So we use the 15msec value above
1174 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 1175 */
1176 for (i = 0; i < timeout; ++i) {
cae5a29d 1177 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
9b2c4e0b
ML		 1178 if ((edma_stat & empty_idle) == empty_idle)
1179 break;
1180 udelay(per_loop);
1181 }
1182 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1183}
1184
05b308e1 1185/**
e12bef50 1186 * mv_stop_edma_engine - Disable eDMA engine
b562468c 1187 * @port_mmio: io base address
05b308e1
BR		 1188 *
1189 * LOCKING:
1190 * Inherited from caller.
1191 */
b562468c 1192static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 1193{
b562468c 1194 int i;
31961943 1195
b562468c 1196 /* Disable eDMA. The disable bit auto clears. */
cae5a29d 1197 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
8b260248 1198
b562468c
ML		 1199 /* Wait for the chip to confirm eDMA is off. */
1200 for (i = 10000; i > 0; i--) {
cae5a29d 1201 u32 reg = readl(port_mmio + EDMA_CMD);
4537deb5 1202 if (!(reg & EDMA_EN))
b562468c
ML		 1203 return 0;
1204 udelay(10);
31961943 1205 }
b562468c 1206 return -EIO;
20f733e7
BR		 1207}
1208
e12bef50 1209static int mv_stop_edma(struct ata_port *ap)
0ea9e179 1210{
b562468c
ML		 1211 void __iomem *port_mmio = mv_ap_base(ap);
1212 struct mv_port_priv *pp = ap->private_data;
66e57a2c 1213 int err = 0;
0ea9e179 1214
b562468c
ML		 1215 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1216 return 0;
1217 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 1218 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 1219 if (mv_stop_edma_engine(port_mmio)) {
1220 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
66e57a2c 1221 err = -EIO;
b562468c 1222 }
66e57a2c
ML		 1223 mv_edma_cfg(ap, 0, 0);
1224 return err;
0ea9e179
JG		 1225}
1226
8a70f8dc 1227#ifdef ATA_DEBUG
31961943 1228static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 1229{
31961943
BR		 1230 int b, w;
1231 for (b = 0; b < bytes; ) {
1232 DPRINTK("%p: ", start + b);
1233 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1234 printk("%08x ", readl(start + b));
31961943
BR		 1235 b += sizeof(u32);
1236 }
1237 printk("\n");
1238 }
31961943 1239}
8a70f8dc
JG		 1240#endif
1241
31961943
BR		 1242static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1243{
1244#ifdef ATA_DEBUG
1245 int b, w;
1246 u32 dw;
1247 for (b = 0; b < bytes; ) {
1248 DPRINTK("%02x: ", b);
1249 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1250 (void) pci_read_config_dword(pdev, b, &dw);
1251 printk("%08x ", dw);
31961943
BR		 1252 b += sizeof(u32);
1253 }
1254 printk("\n");
1255 }
1256#endif
1257}
1258static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1259 struct pci_dev *pdev)
1260{
1261#ifdef ATA_DEBUG
8b260248 1262 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1263 port >> MV_PORT_HC_SHIFT);
1264 void __iomem *port_base;
1265 int start_port, num_ports, p, start_hc, num_hcs, hc;
1266
1267 if (0 > port) {
1268 start_hc = start_port = 0;
1269 num_ports = 8; /* shld be benign for 4 port devs */
1270 num_hcs = 2;
1271 } else {
1272 start_hc = port >> MV_PORT_HC_SHIFT;
1273 start_port = port;
1274 num_ports = num_hcs = 1;
1275 }
8b260248 1276 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1277 num_ports > 1 ? num_ports - 1 : start_port);
1278
1279 if (NULL != pdev) {
1280 DPRINTK("PCI config space regs:\n");
1281 mv_dump_pci_cfg(pdev, 0x68);
1282 }
1283 DPRINTK("PCI regs:\n");
1284 mv_dump_mem(mmio_base+0xc00, 0x3c);
1285 mv_dump_mem(mmio_base+0xd00, 0x34);
1286 mv_dump_mem(mmio_base+0xf00, 0x4);
1287 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1288 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1289 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1290 DPRINTK("HC regs (HC %i):\n", hc);
1291 mv_dump_mem(hc_base, 0x1c);
1292 }
1293 for (p = start_port; p < start_port + num_ports; p++) {
1294 port_base = mv_port_base(mmio_base, p);
2dcb407e 1295 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1296 mv_dump_mem(port_base, 0x54);
2dcb407e 1297 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1298 mv_dump_mem(port_base+0x300, 0x60);
1299 }
1300#endif
20f733e7
BR		 1301}
1302
1303static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1304{
1305 unsigned int ofs;
1306
1307 switch (sc_reg_in) {
1308 case SCR_STATUS:
1309 case SCR_CONTROL:
1310 case SCR_ERROR:
cae5a29d 1311 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
20f733e7
BR		 1312 break;
1313 case SCR_ACTIVE:
cae5a29d 1314 ofs = SATA_ACTIVE; /* active is not with the others */
20f733e7
BR		 1315 break;
1316 default:
1317 ofs = 0xffffffffU;
1318 break;
1319 }
1320 return ofs;
1321}
1322
82ef04fb 1323static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1324{
1325 unsigned int ofs = mv_scr_offset(sc_reg_in);
1326
da3dbb17 1327 if (ofs != 0xffffffffU) {
82ef04fb 1328 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1329 return 0;
1330 } else
1331 return -EINVAL;
20f733e7
BR		 1332}
1333
82ef04fb 1334static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1335{
1336 unsigned int ofs = mv_scr_offset(sc_reg_in);
1337
da3dbb17 1338 if (ofs != 0xffffffffU) {
20091773
ML		 1339 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1340 if (sc_reg_in == SCR_CONTROL) {
1341 /*
1342 * Workaround for 88SX60x1 FEr SATA#26:
1343 *
1344 * COMRESETs have to take care not to accidently
1345 * put the drive to sleep when writing SCR_CONTROL.
1346 * Setting bits 12..15 prevents this problem.
1347 *
1348 * So if we see an outbound COMMRESET, set those bits.
1349 * Ditto for the followup write that clears the reset.
1350 *
1351 * The proprietary driver does this for
1352 * all chip versions, and so do we.
1353 */
1354 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1355 val |= 0xf000;
1356 }
1357 writelfl(val, addr);
da3dbb17
TH		 1358 return 0;
1359 } else
1360 return -EINVAL;
20f733e7
BR		 1361}
1362
f273827e
ML		 1363static void mv6_dev_config(struct ata_device *adev)
1364{
1365 /*
e49856d8
ML		 1366 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1367 *
1368 * Gen-II does not support NCQ over a port multiplier
1369 * (no FIS-based switching).
f273827e 1370 */
e49856d8 1371 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1372 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1373 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1374 ata_dev_printk(adev, KERN_INFO,
1375 "NCQ disabled for command-based switching\n");
352fab70 1376 }
e49856d8 1377 }
f273827e
ML		 1378}
1379
3e4a1391
ML		 1380static int mv_qc_defer(struct ata_queued_cmd *qc)
1381{
1382 struct ata_link *link = qc->dev->link;
1383 struct ata_port *ap = link->ap;
1384 struct mv_port_priv *pp = ap->private_data;
1385
29d187bb
ML		 1386 /*
1387 * Don't allow new commands if we're in a delayed EH state
1388 * for NCQ and/or FIS-based switching.
1389 */
1390 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1391 return ATA_DEFER_PORT;
159a7ff7
GG		 1392
1393 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1394 * can run concurrently.
1395 * set excl_link when we want to send a PIO command in DMA mode
1396 * or a non-NCQ command in NCQ mode.
1397 * When we receive a command from that link, and there are no
1398 * outstanding commands, mark a flag to clear excl_link and let
1399 * the command go through.
1400 */
1401 if (unlikely(ap->excl_link)) {
1402 if (link == ap->excl_link) {
1403 if (ap->nr_active_links)
1404 return ATA_DEFER_PORT;
1405 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1406 return 0;
1407 } else
1408 return ATA_DEFER_PORT;
1409 }
1410
3e4a1391
ML		 1411 /*
1412 * If the port is completely idle, then allow the new qc.
1413 */
1414 if (ap->nr_active_links == 0)
1415 return 0;
1416
4bdee6c5
TH		 1417 /*
1418 * The port is operating in host queuing mode (EDMA) with NCQ
1419 * enabled, allow multiple NCQ commands. EDMA also allows
1420 * queueing multiple DMA commands but libata core currently
1421 * doesn't allow it.
1422 */
1423 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
159a7ff7
GG		 1424 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1425 if (ata_is_ncq(qc->tf.protocol))
1426 return 0;
1427 else {
1428 ap->excl_link = link;
1429 return ATA_DEFER_PORT;
1430 }
1431 }
4bdee6c5 1432
3e4a1391
ML		 1433 return ATA_DEFER_PORT;
1434}
1435
08da1759 1436static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
e49856d8 1437{
08da1759
ML		 1438 struct mv_port_priv *pp = ap->private_data;
1439 void __iomem *port_mmio;
00f42eab 1440
08da1759
ML		 1441 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1442 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1443 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
00f42eab 1444
08da1759
ML		 1445 ltmode = *old_ltmode & ~LTMODE_BIT8;
1446 haltcond = *old_haltcond | EDMA_ERR_DEV;
00f42eab
ML		 1447
1448 if (want_fbs) {
08da1759
ML		 1449 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1450 ltmode = *old_ltmode | LTMODE_BIT8;
4c299ca3 1451 if (want_ncq)
08da1759 1452 haltcond &= ~EDMA_ERR_DEV;
4c299ca3 1453 else
08da1759
ML		 1454 fiscfg |= FISCFG_WAIT_DEV_ERR;
1455 } else {
1456 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
e49856d8 1457 }
00f42eab 1458
08da1759 1459 port_mmio = mv_ap_base(ap);
cae5a29d
ML		 1460 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1461 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1462 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
f273827e
ML		 1463}
1464
dd2890f6
ML		 1465static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1466{
1467 struct mv_host_priv *hpriv = ap->host->private_data;
1468 u32 old, new;
1469
1470 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
cae5a29d 1471 old = readl(hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1472 if (want_ncq)
1473 new = old | (1 << 22);
1474 else
1475 new = old & ~(1 << 22);
1476 if (new != old)
cae5a29d 1477 writel(new, hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1478}
1479
c01e8a23 1480/**
40f21b11
ML		 1481 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1482 * @ap: Port being initialized
c01e8a23
ML		 1483 *
1484 * There are two DMA modes on these chips: basic DMA, and EDMA.
1485 *
1486 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1487 * of basic DMA on the GEN_IIE versions of the chips.
1488 *
1489 * This bit survives EDMA resets, and must be set for basic DMA
1490 * to function, and should be cleared when EDMA is active.
1491 */
1492static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1493{
1494 struct mv_port_priv *pp = ap->private_data;
1495 u32 new, *old = &pp->cached.unknown_rsvd;
1496
1497 if (enable_bmdma)
1498 new = *old | 1;
1499 else
1500 new = *old & ~1;
cae5a29d 1501 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
c01e8a23
ML		 1502}
1503
000b344f
ML		 1504/*
1505 * SOC chips have an issue whereby the HDD LEDs don't always blink
1506 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1507 * of the SOC takes care of it, generating a steady blink rate when
1508 * any drive on the chip is active.
1509 *
1510 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1511 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1512 *
1513 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1514 * LED operation works then, and provides better (more accurate) feedback.
1515 *
1516 * Note that this code assumes that an SOC never has more than one HC onboard.
1517 */
1518static void mv_soc_led_blink_enable(struct ata_port *ap)
1519{
1520 struct ata_host *host = ap->host;
1521 struct mv_host_priv *hpriv = host->private_data;
1522 void __iomem *hc_mmio;
1523 u32 led_ctrl;
1524
1525 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1526 return;
1527 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1528 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1529 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1530 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1531}
1532
1533static void mv_soc_led_blink_disable(struct ata_port *ap)
1534{
1535 struct ata_host *host = ap->host;
1536 struct mv_host_priv *hpriv = host->private_data;
1537 void __iomem *hc_mmio;
1538 u32 led_ctrl;
1539 unsigned int port;
1540
1541 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1542 return;
1543
1544 /* disable led-blink only if no ports are using NCQ */
1545 for (port = 0; port < hpriv->n_ports; port++) {
1546 struct ata_port *this_ap = host->ports[port];
1547 struct mv_port_priv *pp = this_ap->private_data;
1548
1549 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1550 return;
1551 }
1552
1553 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1554 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1555 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1556 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1557}
1558
00b81235 1559static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1560{
0c58912e 1561 u32 cfg;
e12bef50
ML		 1562 struct mv_port_priv *pp = ap->private_data;
1563 struct mv_host_priv *hpriv = ap->host->private_data;
1564 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1565
1566 /* set up non-NCQ EDMA configuration */
0c58912e 1567 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
d16ab3f6
ML		 1568 pp->pp_flags &=
1569 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
e4e7b892 1570
0c58912e 1571 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1572 cfg |= (1 << 8); /* enab config burst size mask */
1573
dd2890f6 1574 else if (IS_GEN_II(hpriv)) {
e4e7b892 1575 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1576 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1577
dd2890f6 1578 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1579 int want_fbs = sata_pmp_attached(ap);
1580 /*
1581 * Possible future enhancement:
1582 *
1583 * The chip can use FBS with non-NCQ, if we allow it,
1584 * But first we need to have the error handling in place
1585 * for this mode (datasheet section 7.3.15.4.2.3).
1586 * So disallow non-NCQ FBS for now.
1587 */
1588 want_fbs &= want_ncq;
1589
08da1759 1590 mv_config_fbs(ap, want_ncq, want_fbs);
00f42eab
ML		 1591
1592 if (want_fbs) {
1593 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1594 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1595 }
1596
e728eabe 1597 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1598 if (want_edma) {
1599 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1600 if (!IS_SOC(hpriv))
1601 cfg |= (1 << 18); /* enab early completion */
1602 }
616d4a98
ML		 1603 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1604 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
c01e8a23 1605 mv_bmdma_enable_iie(ap, !want_edma);
000b344f
ML		 1606
1607 if (IS_SOC(hpriv)) {
1608 if (want_ncq)
1609 mv_soc_led_blink_enable(ap);
1610 else
1611 mv_soc_led_blink_disable(ap);
1612 }
e4e7b892
JG		 1613 }
1614
72109168
ML		 1615 if (want_ncq) {
1616 cfg |= EDMA_CFG_NCQ;
1617 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1618 }
72109168 1619
cae5a29d 1620 writelfl(cfg, port_mmio + EDMA_CFG);
e4e7b892
JG		 1621}
1622
da2fa9ba
ML		 1623static void mv_port_free_dma_mem(struct ata_port *ap)
1624{
1625 struct mv_host_priv *hpriv = ap->host->private_data;
1626 struct mv_port_priv *pp = ap->private_data;
eb73d558 1627 int tag;
da2fa9ba
ML		 1628
1629 if (pp->crqb) {
1630 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1631 pp->crqb = NULL;
1632 }
1633 if (pp->crpb) {
1634 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1635 pp->crpb = NULL;
1636 }
eb73d558
ML		 1637 /*
1638 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1639 * For later hardware, we have one unique sg_tbl per NCQ tag.
1640 */
1641 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1642 if (pp->sg_tbl[tag]) {
1643 if (tag == 0 || !IS_GEN_I(hpriv))
1644 dma_pool_free(hpriv->sg_tbl_pool,
1645 pp->sg_tbl[tag],
1646 pp->sg_tbl_dma[tag]);
1647 pp->sg_tbl[tag] = NULL;
1648 }
da2fa9ba
ML		 1649 }
1650}
1651
05b308e1
BR		 1652/**
1653 * mv_port_start - Port specific init/start routine.
1654 * @ap: ATA channel to manipulate
1655 *
1656 * Allocate and point to DMA memory, init port private memory,
1657 * zero indices.
1658 *
1659 * LOCKING:
1660 * Inherited from caller.
1661 */
31961943
BR		 1662static int mv_port_start(struct ata_port *ap)
1663{
cca3974e
JG		 1664 struct device *dev = ap->host->dev;
1665 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1666 struct mv_port_priv *pp;
933cb8e5 1667 unsigned long flags;
dde20207 1668 int tag;
31961943 1669
24dc5f33 1670 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1671 if (!pp)
24dc5f33 1672 return -ENOMEM;
da2fa9ba 1673 ap->private_data = pp;
31961943 1674
da2fa9ba
ML		 1675 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1676 if (!pp->crqb)
1677 return -ENOMEM;
1678 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1679
da2fa9ba
ML		 1680 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1681 if (!pp->crpb)
1682 goto out_port_free_dma_mem;
1683 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1684
3bd0a70e
ML		 1685 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1686 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1687 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1688 /*
1689 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1690 * For later hardware, we need one unique sg_tbl per NCQ tag.
1691 */
1692 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1693 if (tag == 0 || !IS_GEN_I(hpriv)) {
1694 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1695 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1696 if (!pp->sg_tbl[tag])
1697 goto out_port_free_dma_mem;
1698 } else {
1699 pp->sg_tbl[tag] = pp->sg_tbl[0];
1700 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1701 }
1702 }
933cb8e5
ML		 1703
1704 spin_lock_irqsave(ap->lock, flags);
08da1759 1705 mv_save_cached_regs(ap);
66e57a2c 1706 mv_edma_cfg(ap, 0, 0);
933cb8e5
ML		 1707 spin_unlock_irqrestore(ap->lock, flags);
1708
31961943 1709 return 0;
da2fa9ba
ML		 1710
1711out_port_free_dma_mem:
1712 mv_port_free_dma_mem(ap);
1713 return -ENOMEM;
31961943
BR		 1714}
1715
05b308e1
BR		 1716/**
1717 * mv_port_stop - Port specific cleanup/stop routine.
1718 * @ap: ATA channel to manipulate
1719 *
1720 * Stop DMA, cleanup port memory.
1721 *
1722 * LOCKING:
cca3974e 1723 * This routine uses the host lock to protect the DMA stop.
05b308e1 1724 */
31961943
BR		 1725static void mv_port_stop(struct ata_port *ap)
1726{
933cb8e5
ML		 1727 unsigned long flags;
1728
1729 spin_lock_irqsave(ap->lock, flags);
e12bef50 1730 mv_stop_edma(ap);
88e675e1 1731 mv_enable_port_irqs(ap, 0);
933cb8e5 1732 spin_unlock_irqrestore(ap->lock, flags);
da2fa9ba 1733 mv_port_free_dma_mem(ap);
31961943
BR		 1734}
1735
05b308e1
BR		 1736/**
1737 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1738 * @qc: queued command whose SG list to source from
1739 *
1740 * Populate the SG list and mark the last entry.
1741 *
1742 * LOCKING:
1743 * Inherited from caller.
1744 */
6c08772e 1745static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1746{
1747 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1748 struct scatterlist *sg;
3be6cbd7 1749 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1750 unsigned int si;
31961943 1751
eb73d558 1752 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1753 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1754 dma_addr_t addr = sg_dma_address(sg);
1755 u32 sg_len = sg_dma_len(sg);
22374677 1756
4007b493
OJ		 1757 while (sg_len) {
1758 u32 offset = addr & 0xffff;
1759 u32 len = sg_len;
22374677 1760
32cd11a6 1761 if (offset + len > 0x10000)
4007b493
OJ		 1762 len = 0x10000 - offset;
1763
1764 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1765 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1766 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1767 mv_sg->reserved = 0;
4007b493
OJ		 1768
1769 sg_len -= len;
1770 addr += len;
1771
3be6cbd7 1772 last_sg = mv_sg;
4007b493 1773 mv_sg++;
4007b493 1774 }
31961943 1775 }
3be6cbd7
JG		 1776
1777 if (likely(last_sg))
1778 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1779 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1780}
1781
5796d1c4 1782static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1783{
559eedad 1784 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1785 (last ? CRQB_CMD_LAST : 0);
559eedad 1786 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1787}
1788
da14265e
ML		 1789/**
1790 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1791 * @ap: Port associated with this ATA transaction.
1792 *
1793 * We need this only for ATAPI bmdma transactions,
1794 * as otherwise we experience spurious interrupts
1795 * after libata-sff handles the bmdma interrupts.
1796 */
1797static void mv_sff_irq_clear(struct ata_port *ap)
1798{
1799 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1800}
1801
1802/**
1803 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1804 * @qc: queued command to check for chipset/DMA compatibility.
1805 *
1806 * The bmdma engines cannot handle speculative data sizes
1807 * (bytecount under/over flow). So only allow DMA for
1808 * data transfer commands with known data sizes.
1809 *
1810 * LOCKING:
1811 * Inherited from caller.
1812 */
1813static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1814{
1815 struct scsi_cmnd *scmd = qc->scsicmd;
1816
1817 if (scmd) {
1818 switch (scmd->cmnd[0]) {
1819 case READ_6:
1820 case READ_10:
1821 case READ_12:
1822 case WRITE_6:
1823 case WRITE_10:
1824 case WRITE_12:
1825 case GPCMD_READ_CD:
1826 case GPCMD_SEND_DVD_STRUCTURE:
1827 case GPCMD_SEND_CUE_SHEET:
1828 return 0; /* DMA is safe */
1829 }
1830 }
1831 return -EOPNOTSUPP; /* use PIO instead */
1832}
1833
1834/**
1835 * mv_bmdma_setup - Set up BMDMA transaction
1836 * @qc: queued command to prepare DMA for.
1837 *
1838 * LOCKING:
1839 * Inherited from caller.
1840 */
1841static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1842{
1843 struct ata_port *ap = qc->ap;
1844 void __iomem *port_mmio = mv_ap_base(ap);
1845 struct mv_port_priv *pp = ap->private_data;
1846
1847 mv_fill_sg(qc);
1848
1849 /* clear all DMA cmd bits */
cae5a29d 1850 writel(0, port_mmio + BMDMA_CMD);
da14265e
ML		 1851
1852 /* load PRD table addr. */
1853 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
cae5a29d 1854 port_mmio + BMDMA_PRD_HIGH);
da14265e 1855 writelfl(pp->sg_tbl_dma[qc->tag],
cae5a29d 1856 port_mmio + BMDMA_PRD_LOW);
da14265e
ML		 1857
1858 /* issue r/w command */
1859 ap->ops->sff_exec_command(ap, &qc->tf);
1860}
1861
1862/**
1863 * mv_bmdma_start - Start a BMDMA transaction
1864 * @qc: queued command to start DMA on.
1865 *
1866 * LOCKING:
1867 * Inherited from caller.
1868 */
1869static void mv_bmdma_start(struct ata_queued_cmd *qc)
1870{
1871 struct ata_port *ap = qc->ap;
1872 void __iomem *port_mmio = mv_ap_base(ap);
1873 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1874 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1875
1876 /* start host DMA transaction */
cae5a29d 1877 writelfl(cmd, port_mmio + BMDMA_CMD);
da14265e
ML		 1878}
1879
1880/**
1881 * mv_bmdma_stop - Stop BMDMA transfer
1882 * @qc: queued command to stop DMA on.
1883 *
1884 * Clears the ATA_DMA_START flag in the bmdma control register
1885 *
1886 * LOCKING:
1887 * Inherited from caller.
1888 */
1889static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1890{
1891 struct ata_port *ap = qc->ap;
1892 void __iomem *port_mmio = mv_ap_base(ap);
1893 u32 cmd;
1894
1895 /* clear start/stop bit */
cae5a29d 1896 cmd = readl(port_mmio + BMDMA_CMD);
da14265e 1897 cmd &= ~ATA_DMA_START;
cae5a29d 1898 writelfl(cmd, port_mmio + BMDMA_CMD);
da14265e
ML		 1899
1900 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1901 ata_sff_dma_pause(ap);
1902}
1903
1904/**
1905 * mv_bmdma_status - Read BMDMA status
1906 * @ap: port for which to retrieve DMA status.
1907 *
1908 * Read and return equivalent of the sff BMDMA status register.
1909 *
1910 * LOCKING:
1911 * Inherited from caller.
1912 */
1913static u8 mv_bmdma_status(struct ata_port *ap)
1914{
1915 void __iomem *port_mmio = mv_ap_base(ap);
1916 u32 reg, status;
1917
1918 /*
1919 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1920 * and the ATA_DMA_INTR bit doesn't exist.
1921 */
cae5a29d 1922 reg = readl(port_mmio + BMDMA_STATUS);
da14265e
ML		 1923 if (reg & ATA_DMA_ACTIVE)
1924 status = ATA_DMA_ACTIVE;
1925 else
1926 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1927 return status;
1928}
1929
299b3f8d
ML		 1930static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1931{
1932 struct ata_taskfile *tf = &qc->tf;
1933 /*
1934 * Workaround for 88SX60x1 FEr SATA#24.
1935 *
1936 * Chip may corrupt WRITEs if multi_count >= 4kB.
1937 * Note that READs are unaffected.
1938 *
1939 * It's not clear if this errata really means "4K bytes",
1940 * or if it always happens for multi_count > 7
1941 * regardless of device sector_size.
1942 *
1943 * So, for safety, any write with multi_count > 7
1944 * gets converted here into a regular PIO write instead:
1945 */
1946 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1947 if (qc->dev->multi_count > 7) {
1948 switch (tf->command) {
1949 case ATA_CMD_WRITE_MULTI:
1950 tf->command = ATA_CMD_PIO_WRITE;
1951 break;
1952 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1953 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1954 /* fall through */
1955 case ATA_CMD_WRITE_MULTI_EXT:
1956 tf->command = ATA_CMD_PIO_WRITE_EXT;
1957 break;
1958 }
1959 }
1960 }
1961}
1962
05b308e1
BR		 1963/**
1964 * mv_qc_prep - Host specific command preparation.
1965 * @qc: queued command to prepare
1966 *
1967 * This routine simply redirects to the general purpose routine
1968 * if command is not DMA. Else, it handles prep of the CRQB
1969 * (command request block), does some sanity checking, and calls
1970 * the SG load routine.
1971 *
1972 * LOCKING:
1973 * Inherited from caller.
1974 */
31961943
BR		 1975static void mv_qc_prep(struct ata_queued_cmd *qc)
1976{
1977 struct ata_port *ap = qc->ap;
1978 struct mv_port_priv *pp = ap->private_data;
e1469874 1979 __le16 *cw;
8d2b450d 1980 struct ata_taskfile *tf = &qc->tf;
31961943 1981 u16 flags = 0;
a6432436 1982 unsigned in_index;
31961943 1983
299b3f8d
ML		 1984 switch (tf->protocol) {
1985 case ATA_PROT_DMA:
1986 case ATA_PROT_NCQ:
1987 break; /* continue below */
1988 case ATA_PROT_PIO:
1989 mv_rw_multi_errata_sata24(qc);
31961943 1990 return;
299b3f8d
ML		 1991 default:
1992 return;
1993 }
20f733e7 1994
31961943
BR		 1995 /* Fill in command request block
1996 */
8d2b450d 1997 if (!(tf->flags & ATA_TFLAG_WRITE))
31961943 1998 flags |= CRQB_FLAG_READ;
beec7dbc 1999 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 2000 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 2001 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 2002
bdd4ddde 2003 /* get current queue index from software */
fcfb1f77 2004 in_index = pp->req_idx;
a6432436
ML		 2005
2006 pp->crqb[in_index].sg_addr =
eb73d558 2007 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 2008 pp->crqb[in_index].sg_addr_hi =
eb73d558 2009 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 2010 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 2011
a6432436 2012 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 2013
2014 /* Sadly, the CRQB cannot accomodate all registers--there are
2015 * only 11 bytes...so we must pick and choose required
2016 * registers based on the command. So, we drop feature and
2017 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 2018 * NCQ. NCQ will drop hob_nsect, which is not needed there
2019 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 2020 */
31961943
BR		 2021 switch (tf->command) {
2022 case ATA_CMD_READ:
2023 case ATA_CMD_READ_EXT:
2024 case ATA_CMD_WRITE:
2025 case ATA_CMD_WRITE_EXT:
c15d85c8 2026 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 2027 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2028 break;
31961943
BR		 2029 case ATA_CMD_FPDMA_READ:
2030 case ATA_CMD_FPDMA_WRITE:
8b260248 2031 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 2032 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2033 break;
31961943
BR		 2034 default:
2035 /* The only other commands EDMA supports in non-queued and
2036 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2037 * of which are defined/used by Linux. If we get here, this
2038 * driver needs work.
2039 *
2040 * FIXME: modify libata to give qc_prep a return value and
2041 * return error here.
2042 */
2043 BUG_ON(tf->command);
2044 break;
2045 }
2046 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2047 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2048 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2049 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2050 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2051 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2052 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2053 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2054 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2055
e4e7b892
JG		 2056 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2057 return;
2058 mv_fill_sg(qc);
2059}
2060
2061/**
2062 * mv_qc_prep_iie - Host specific command preparation.
2063 * @qc: queued command to prepare
2064 *
2065 * This routine simply redirects to the general purpose routine
2066 * if command is not DMA. Else, it handles prep of the CRQB
2067 * (command request block), does some sanity checking, and calls
2068 * the SG load routine.
2069 *
2070 * LOCKING:
2071 * Inherited from caller.
2072 */
2073static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2074{
2075 struct ata_port *ap = qc->ap;
2076 struct mv_port_priv *pp = ap->private_data;
2077 struct mv_crqb_iie *crqb;
8d2b450d 2078 struct ata_taskfile *tf = &qc->tf;
a6432436 2079 unsigned in_index;
e4e7b892
JG		 2080 u32 flags = 0;
2081
8d2b450d
ML		 2082 if ((tf->protocol != ATA_PROT_DMA) &&
2083 (tf->protocol != ATA_PROT_NCQ))
e4e7b892
JG		 2084 return;
2085
e12bef50 2086 /* Fill in Gen IIE command request block */
8d2b450d 2087 if (!(tf->flags & ATA_TFLAG_WRITE))
e4e7b892
JG		 2088 flags |= CRQB_FLAG_READ;
2089
beec7dbc 2090 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 2091 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 2092 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 2093 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 2094
bdd4ddde 2095 /* get current queue index from software */
fcfb1f77 2096 in_index = pp->req_idx;
a6432436
ML		 2097
2098 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 2099 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2100 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 2101 crqb->flags = cpu_to_le32(flags);
2102
e4e7b892
JG		 2103 crqb->ata_cmd[0] = cpu_to_le32(
2104 (tf->command << 16) |
2105 (tf->feature << 24)
2106 );
2107 crqb->ata_cmd[1] = cpu_to_le32(
2108 (tf->lbal << 0) |
2109 (tf->lbam << 8) |
2110 (tf->lbah << 16) |
2111 (tf->device << 24)
2112 );
2113 crqb->ata_cmd[2] = cpu_to_le32(
2114 (tf->hob_lbal << 0) |
2115 (tf->hob_lbam << 8) |
2116 (tf->hob_lbah << 16) |
2117 (tf->hob_feature << 24)
2118 );
2119 crqb->ata_cmd[3] = cpu_to_le32(
2120 (tf->nsect << 0) |
2121 (tf->hob_nsect << 8)
2122 );
2123
2124 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 2125 return;
31961943
BR		 2126 mv_fill_sg(qc);
2127}
2128
d16ab3f6
ML		 2129/**
2130 * mv_sff_check_status - fetch device status, if valid
2131 * @ap: ATA port to fetch status from
2132 *
2133 * When using command issue via mv_qc_issue_fis(),
2134 * the initial ATA_BUSY state does not show up in the
2135 * ATA status (shadow) register. This can confuse libata!
2136 *
2137 * So we have a hook here to fake ATA_BUSY for that situation,
2138 * until the first time a BUSY, DRQ, or ERR bit is seen.
2139 *
2140 * The rest of the time, it simply returns the ATA status register.
2141 */
2142static u8 mv_sff_check_status(struct ata_port *ap)
2143{
2144 u8 stat = ioread8(ap->ioaddr.status_addr);
2145 struct mv_port_priv *pp = ap->private_data;
2146
2147 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2148 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2149 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2150 else
2151 stat = ATA_BUSY;
2152 }
2153 return stat;
2154}
2155
70f8b79c
ML		 2156/**
2157 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2158 * @fis: fis to be sent
2159 * @nwords: number of 32-bit words in the fis
2160 */
2161static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2162{
2163 void __iomem *port_mmio = mv_ap_base(ap);
2164 u32 ifctl, old_ifctl, ifstat;
2165 int i, timeout = 200, final_word = nwords - 1;
2166
2167 /* Initiate FIS transmission mode */
cae5a29d 2168 old_ifctl = readl(port_mmio + SATA_IFCTL);
70f8b79c 2169 ifctl = 0x100 | (old_ifctl & 0xf);
cae5a29d 2170 writelfl(ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2171
2172 /* Send all words of the FIS except for the final word */
2173 for (i = 0; i < final_word; ++i)
cae5a29d 2174 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2175
2176 /* Flag end-of-transmission, and then send the final word */
cae5a29d
ML		 2177 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2178 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2179
2180 /*
2181 * Wait for FIS transmission to complete.
2182 * This typically takes just a single iteration.
2183 */
2184 do {
cae5a29d 2185 ifstat = readl(port_mmio + SATA_IFSTAT);
70f8b79c
ML		 2186 } while (!(ifstat & 0x1000) && --timeout);
2187
2188 /* Restore original port configuration */
cae5a29d 2189 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2190
2191 /* See if it worked */
2192 if ((ifstat & 0x3000) != 0x1000) {
2193 ata_port_printk(ap, KERN_WARNING,
2194 "%s transmission error, ifstat=%08x\n",
2195 __func__, ifstat);
2196 return AC_ERR_OTHER;
2197 }
2198 return 0;
2199}
2200
2201/**
2202 * mv_qc_issue_fis - Issue a command directly as a FIS
2203 * @qc: queued command to start
2204 *
2205 * Note that the ATA shadow registers are not updated
2206 * after command issue, so the device will appear "READY"
2207 * if polled, even while it is BUSY processing the command.
2208 *
2209 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2210 *
2211 * Note: we don't get updated shadow regs on *completion*
2212 * of non-data commands. So avoid sending them via this function,
2213 * as they will appear to have completed immediately.
2214 *
2215 * GEN_IIE has special registers that we could get the result tf from,
2216 * but earlier chipsets do not. For now, we ignore those registers.
2217 */
2218static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2219{
2220 struct ata_port *ap = qc->ap;
2221 struct mv_port_priv *pp = ap->private_data;
2222 struct ata_link *link = qc->dev->link;
2223 u32 fis[5];
2224 int err = 0;
2225
2226 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
4c4a90fd 2227 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
70f8b79c
ML		 2228 if (err)
2229 return err;
2230
2231 switch (qc->tf.protocol) {
2232 case ATAPI_PROT_PIO:
2233 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2234 /* fall through */
2235 case ATAPI_PROT_NODATA:
2236 ap->hsm_task_state = HSM_ST_FIRST;
2237 break;
2238 case ATA_PROT_PIO:
2239 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2240 if (qc->tf.flags & ATA_TFLAG_WRITE)
2241 ap->hsm_task_state = HSM_ST_FIRST;
2242 else
2243 ap->hsm_task_state = HSM_ST;
2244 break;
2245 default:
2246 ap->hsm_task_state = HSM_ST_LAST;
2247 break;
2248 }
2249
2250 if (qc->tf.flags & ATA_TFLAG_POLLING)
2251 ata_pio_queue_task(ap, qc, 0);
2252 return 0;
2253}
2254
05b308e1
BR		 2255/**
2256 * mv_qc_issue - Initiate a command to the host
2257 * @qc: queued command to start
2258 *
2259 * This routine simply redirects to the general purpose routine
2260 * if command is not DMA. Else, it sanity checks our local
2261 * caches of the request producer/consumer indices then enables
2262 * DMA and bumps the request producer index.
2263 *
2264 * LOCKING:
2265 * Inherited from caller.
2266 */
9a3d9eb0 2267static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 2268{
f48765cc 2269 static int limit_warnings = 10;
c5d3e45a
JG		 2270 struct ata_port *ap = qc->ap;
2271 void __iomem *port_mmio = mv_ap_base(ap);
2272 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 2273 u32 in_index;
42ed893d 2274 unsigned int port_irqs;
f48765cc 2275
d16ab3f6
ML		 2276 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2277
f48765cc
ML		 2278 switch (qc->tf.protocol) {
2279 case ATA_PROT_DMA:
2280 case ATA_PROT_NCQ:
2281 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2282 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2283 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2284
2285 /* Write the request in pointer to kick the EDMA to life */
2286 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
cae5a29d 2287 port_mmio + EDMA_REQ_Q_IN_PTR);
f48765cc 2288 return 0;
31961943 2289
f48765cc 2290 case ATA_PROT_PIO:
c6112bd8
ML		 2291 /*
2292 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2293 *
2294 * Someday, we might implement special polling workarounds
2295 * for these, but it all seems rather unnecessary since we
2296 * normally use only DMA for commands which transfer more
2297 * than a single block of data.
2298 *
2299 * Much of the time, this could just work regardless.
2300 * So for now, just log the incident, and allow the attempt.
2301 */
c7843e8f 2302 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 2303 --limit_warnings;
2304 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2305 ": attempting PIO w/multiple DRQ: "
2306 "this may fail due to h/w errata\n");
2307 }
f48765cc 2308 /* drop through */
42ed893d 2309 case ATA_PROT_NODATA:
f48765cc 2310 case ATAPI_PROT_PIO:
42ed893d
ML		 2311 case ATAPI_PROT_NODATA:
2312 if (ap->flags & ATA_FLAG_PIO_POLLING)
2313 qc->tf.flags |= ATA_TFLAG_POLLING;
2314 break;
31961943 2315 }
42ed893d
ML		 2316
2317 if (qc->tf.flags & ATA_TFLAG_POLLING)
2318 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2319 else
2320 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2321
2322 /*
2323 * We're about to send a non-EDMA capable command to the
2324 * port. Turn off EDMA so there won't be problems accessing
2325 * shadow block, etc registers.
2326 */
2327 mv_stop_edma(ap);
2328 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2329 mv_pmp_select(ap, qc->dev->link->pmp);
70f8b79c
ML		 2330
2331 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2332 struct mv_host_priv *hpriv = ap->host->private_data;
2333 /*
2334 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
40f21b11 2335 *
70f8b79c
ML		 2336 * After any NCQ error, the READ_LOG_EXT command
2337 * from libata-eh *must* use mv_qc_issue_fis().
2338 * Otherwise it might fail, due to chip errata.
2339 *
2340 * Rather than special-case it, we'll just *always*
2341 * use this method here for READ_LOG_EXT, making for
2342 * easier testing.
2343 */
2344 if (IS_GEN_II(hpriv))
2345 return mv_qc_issue_fis(qc);
2346 }
42ed893d 2347 return ata_sff_qc_issue(qc);
31961943
BR		 2348}
2349
8f767f8a
ML		 2350static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2351{
2352 struct mv_port_priv *pp = ap->private_data;
2353 struct ata_queued_cmd *qc;
2354
2355 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2356 return NULL;
2357 qc = ata_qc_from_tag(ap, ap->link.active_tag);
3e4ec344
TH		 2358 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2359 return qc;
2360 return NULL;
8f767f8a
ML		 2361}
2362
29d187bb
ML		 2363static void mv_pmp_error_handler(struct ata_port *ap)
2364{
2365 unsigned int pmp, pmp_map;
2366 struct mv_port_priv *pp = ap->private_data;
2367
2368 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2369 /*
2370 * Perform NCQ error analysis on failed PMPs
2371 * before we freeze the port entirely.
2372 *
2373 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2374 */
2375 pmp_map = pp->delayed_eh_pmp_map;
2376 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2377 for (pmp = 0; pmp_map != 0; pmp++) {
2378 unsigned int this_pmp = (1 << pmp);
2379 if (pmp_map & this_pmp) {
2380 struct ata_link *link = &ap->pmp_link[pmp];
2381 pmp_map &= ~this_pmp;
2382 ata_eh_analyze_ncq_error(link);
2383 }
2384 }
2385 ata_port_freeze(ap);
2386 }
2387 sata_pmp_error_handler(ap);
2388}
2389
4c299ca3
ML		 2390static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2391{
2392 void __iomem *port_mmio = mv_ap_base(ap);
2393
cae5a29d 2394 return readl(port_mmio + SATA_TESTCTL) >> 16;
4c299ca3
ML		 2395}
2396
4c299ca3
ML		 2397static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2398{
2399 struct ata_eh_info *ehi;
2400 unsigned int pmp;
2401
2402 /*
2403 * Initialize EH info for PMPs which saw device errors
2404 */
2405 ehi = &ap->link.eh_info;
2406 for (pmp = 0; pmp_map != 0; pmp++) {
2407 unsigned int this_pmp = (1 << pmp);
2408 if (pmp_map & this_pmp) {
2409 struct ata_link *link = &ap->pmp_link[pmp];
2410
2411 pmp_map &= ~this_pmp;
2412 ehi = &link->eh_info;
2413 ata_ehi_clear_desc(ehi);
2414 ata_ehi_push_desc(ehi, "dev err");
2415 ehi->err_mask |= AC_ERR_DEV;
2416 ehi->action |= ATA_EH_RESET;
2417 ata_link_abort(link);
2418 }
2419 }
2420}
2421
06aaca3f
ML		 2422static int mv_req_q_empty(struct ata_port *ap)
2423{
2424 void __iomem *port_mmio = mv_ap_base(ap);
2425 u32 in_ptr, out_ptr;
2426
cae5a29d 2427 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
06aaca3f 2428 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
cae5a29d 2429 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
06aaca3f
ML		 2430 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2431 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2432}
2433
4c299ca3
ML		 2434static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2435{
2436 struct mv_port_priv *pp = ap->private_data;
2437 int failed_links;
2438 unsigned int old_map, new_map;
2439
2440 /*
2441 * Device error during FBS+NCQ operation:
2442 *
2443 * Set a port flag to prevent further I/O being enqueued.
2444 * Leave the EDMA running to drain outstanding commands from this port.
2445 * Perform the post-mortem/EH only when all responses are complete.
2446 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2447 */
2448 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2449 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2450 pp->delayed_eh_pmp_map = 0;
2451 }
2452 old_map = pp->delayed_eh_pmp_map;
2453 new_map = old_map | mv_get_err_pmp_map(ap);
2454
2455 if (old_map != new_map) {
2456 pp->delayed_eh_pmp_map = new_map;
2457 mv_pmp_eh_prep(ap, new_map & ~old_map);
2458 }
c46938cc 2459 failed_links = hweight16(new_map);
4c299ca3
ML		 2460
2461 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2462 "failed_links=%d nr_active_links=%d\n",
2463 __func__, pp->delayed_eh_pmp_map,
2464 ap->qc_active, failed_links,
2465 ap->nr_active_links);
2466
06aaca3f 2467 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 2468 mv_process_crpb_entries(ap, pp);
2469 mv_stop_edma(ap);
2470 mv_eh_freeze(ap);
2471 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2472 return 1; /* handled */
2473 }
2474 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2475 return 1; /* handled */
2476}
2477
2478static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2479{
2480 /*
2481 * Possible future enhancement:
2482 *
2483 * FBS+non-NCQ operation is not yet implemented.
2484 * See related notes in mv_edma_cfg().
2485 *
2486 * Device error during FBS+non-NCQ operation:
2487 *
2488 * We need to snapshot the shadow registers for each failed command.
2489 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2490 */
2491 return 0; /* not handled */
2492}
2493
2494static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2495{
2496 struct mv_port_priv *pp = ap->private_data;
2497
2498 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2499 return 0; /* EDMA was not active: not handled */
2500 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2501 return 0; /* FBS was not active: not handled */
2502
2503 if (!(edma_err_cause & EDMA_ERR_DEV))
2504 return 0; /* non DEV error: not handled */
2505 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2506 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2507 return 0; /* other problems: not handled */
2508
2509 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2510 /*
2511 * EDMA should NOT have self-disabled for this case.
2512 * If it did, then something is wrong elsewhere,
2513 * and we cannot handle it here.
2514 */
2515 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2516 ata_port_printk(ap, KERN_WARNING,
2517 "%s: err_cause=0x%x pp_flags=0x%x\n",
2518 __func__, edma_err_cause, pp->pp_flags);
2519 return 0; /* not handled */
2520 }
2521 return mv_handle_fbs_ncq_dev_err(ap);
2522 } else {
2523 /*
2524 * EDMA should have self-disabled for this case.
2525 * If it did not, then something is wrong elsewhere,
2526 * and we cannot handle it here.
2527 */
2528 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2529 ata_port_printk(ap, KERN_WARNING,
2530 "%s: err_cause=0x%x pp_flags=0x%x\n",
2531 __func__, edma_err_cause, pp->pp_flags);
2532 return 0; /* not handled */
2533 }
2534 return mv_handle_fbs_non_ncq_dev_err(ap);
2535 }
2536 return 0; /* not handled */
2537}
2538
a9010329 2539static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2540{
8f767f8a 2541 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2542 char *when = "idle";
8f767f8a 2543
8f767f8a 2544 ata_ehi_clear_desc(ehi);
3e4ec344 2545 if (edma_was_enabled) {
a9010329 2546 when = "EDMA enabled";
8f767f8a
ML		 2547 } else {
2548 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2549 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2550 when = "polling";
8f767f8a 2551 }
a9010329 2552 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2553 ehi->err_mask |= AC_ERR_OTHER;
2554 ehi->action |= ATA_EH_RESET;
2555 ata_port_freeze(ap);
2556}
2557
05b308e1
BR		 2558/**
2559 * mv_err_intr - Handle error interrupts on the port
2560 * @ap: ATA channel to manipulate
2561 *
8d07379d
ML		 2562 * Most cases require a full reset of the chip's state machine,
2563 * which also performs a COMRESET.
2564 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2565 *
2566 * LOCKING:
2567 * Inherited from caller.
2568 */
37b9046a 2569static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2570{
2571 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2572 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2573 u32 fis_cause = 0;
bdd4ddde
JG		 2574 struct mv_port_priv *pp = ap->private_data;
2575 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2576 unsigned int action = 0, err_mask = 0;
9af5c9c9 2577 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2578 struct ata_queued_cmd *qc;
2579 int abort = 0;
20f733e7 2580
8d07379d 2581 /*
37b9046a 2582 * Read and clear the SError and err_cause bits.
e4006077
ML		 2583 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2584 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2585 */
37b9046a
ML		 2586 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2587 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2588
cae5a29d 2589 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
e4006077 2590 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
cae5a29d
ML		 2591 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2592 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
e4006077 2593 }
cae5a29d 2594 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde 2595
4c299ca3
ML		 2596 if (edma_err_cause & EDMA_ERR_DEV) {
2597 /*
2598 * Device errors during FIS-based switching operation
2599 * require special handling.
2600 */
2601 if (mv_handle_dev_err(ap, edma_err_cause))
2602 return;
2603 }
2604
37b9046a
ML		 2605 qc = mv_get_active_qc(ap);
2606 ata_ehi_clear_desc(ehi);
2607 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2608 edma_err_cause, pp->pp_flags);
e4006077 2609
c443c500 2610 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2611 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
cae5a29d 2612 if (fis_cause & FIS_IRQ_CAUSE_AN) {
c443c500
ML		 2613 u32 ec = edma_err_cause &
2614 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2615 sata_async_notification(ap);
2616 if (!ec)
2617 return; /* Just an AN; no need for the nukes */
2618 ata_ehi_push_desc(ehi, "SDB notify");
2619 }
2620 }
bdd4ddde 2621 /*
352fab70 2622 * All generations share these EDMA error cause bits:
bdd4ddde 2623 */
37b9046a 2624 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2625 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2626 action |= ATA_EH_RESET;
2627 ata_ehi_push_desc(ehi, "dev error");
2628 }
bdd4ddde 2629 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2630 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2631 EDMA_ERR_INTRL_PAR)) {
2632 err_mask |= AC_ERR_ATA_BUS;
cf480626 2633 action |= ATA_EH_RESET;
b64bbc39 2634 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2635 }
2636 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2637 ata_ehi_hotplugged(ehi);
2638 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2639 "dev disconnect" : "dev connect");
cf480626 2640 action |= ATA_EH_RESET;
bdd4ddde
JG		 2641 }
2642
352fab70
ML		 2643 /*
2644 * Gen-I has a different SELF_DIS bit,
2645 * different FREEZE bits, and no SERR bit:
2646 */
ee9ccdf7 2647 if (IS_GEN_I(hpriv)) {
bdd4ddde 2648 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2649 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2650 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2651 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2652 }
2653 } else {
2654 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2655 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2656 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2657 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2658 }
bdd4ddde 2659 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2660 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2661 err_mask |= AC_ERR_ATA_BUS;
cf480626 2662 action |= ATA_EH_RESET;
bdd4ddde 2663 }
afb0edd9 2664 }
20f733e7 2665
bdd4ddde
JG		 2666 if (!err_mask) {
2667 err_mask = AC_ERR_OTHER;
cf480626 2668 action |= ATA_EH_RESET;
bdd4ddde
JG		 2669 }
2670
2671 ehi->serror |= serr;
2672 ehi->action |= action;
2673
2674 if (qc)
2675 qc->err_mask |= err_mask;
2676 else
2677 ehi->err_mask |= err_mask;
2678
37b9046a
ML		 2679 if (err_mask == AC_ERR_DEV) {
2680 /*
2681 * Cannot do ata_port_freeze() here,
2682 * because it would kill PIO access,
2683 * which is needed for further diagnosis.
2684 */
2685 mv_eh_freeze(ap);
2686 abort = 1;
2687 } else if (edma_err_cause & eh_freeze_mask) {
2688 /*
2689 * Note to self: ata_port_freeze() calls ata_port_abort()
2690 */
bdd4ddde 2691 ata_port_freeze(ap);
37b9046a
ML		 2692 } else {
2693 abort = 1;
2694 }
2695
2696 if (abort) {
2697 if (qc)
2698 ata_link_abort(qc->dev->link);
2699 else
2700 ata_port_abort(ap);
2701 }
bdd4ddde
JG		 2702}
2703
fcfb1f77
ML		 2704static void mv_process_crpb_response(struct ata_port *ap,
2705 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2706{
2707 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2708
2709 if (qc) {
2710 u8 ata_status;
2711 u16 edma_status = le16_to_cpu(response->flags);
2712 /*
2713 * edma_status from a response queue entry:
cae5a29d 2714 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
fcfb1f77
ML		 2715 * MSB is saved ATA status from command completion.
2716 */
2717 if (!ncq_enabled) {
2718 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2719 if (err_cause) {
2720 /*
2721 * Error will be seen/handled by mv_err_intr().
2722 * So do nothing at all here.
2723 */
2724 return;
2725 }
2726 }
2727 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2728 if (!ac_err_mask(ata_status))
2729 ata_qc_complete(qc);
2730 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2731 } else {
2732 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2733 __func__, tag);
2734 }
2735}
2736
2737static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2738{
2739 void __iomem *port_mmio = mv_ap_base(ap);
2740 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2741 u32 in_index;
bdd4ddde 2742 bool work_done = false;
fcfb1f77 2743 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2744
fcfb1f77 2745 /* Get the hardware queue position index */
cae5a29d 2746 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
bdd4ddde
JG		 2747 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2748
fcfb1f77
ML		 2749 /* Process new responses from since the last time we looked */
2750 while (in_index != pp->resp_idx) {
6c1153e0 2751 unsigned int tag;
fcfb1f77 2752 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2753
fcfb1f77 2754 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2755
fcfb1f77
ML		 2756 if (IS_GEN_I(hpriv)) {
2757 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2758 tag = ap->link.active_tag;
fcfb1f77
ML		 2759 } else {
2760 /* Gen II/IIE: get command tag from CRPB entry */
2761 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2762 }
fcfb1f77 2763 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2764 work_done = true;
bdd4ddde
JG		 2765 }
2766
352fab70 2767 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2768 if (work_done)
2769 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2770 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
cae5a29d 2771 port_mmio + EDMA_RSP_Q_OUT_PTR);
20f733e7
BR		 2772}
2773
a9010329
ML		 2774static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2775{
2776 struct mv_port_priv *pp;
2777 int edma_was_enabled;
2778
a9010329
ML		 2779 /*
2780 * Grab a snapshot of the EDMA_EN flag setting,
2781 * so that we have a consistent view for this port,
2782 * even if something we call of our routines changes it.
2783 */
2784 pp = ap->private_data;
2785 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2786 /*
2787 * Process completed CRPB response(s) before other events.
2788 */
2789 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2790 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2791 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2792 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2793 }
2794 /*
2795 * Handle chip-reported errors, or continue on to handle PIO.
2796 */
2797 if (unlikely(port_cause & ERR_IRQ)) {
2798 mv_err_intr(ap);
2799 } else if (!edma_was_enabled) {
2800 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2801 if (qc)
2802 ata_sff_host_intr(ap, qc);
2803 else
2804 mv_unexpected_intr(ap, edma_was_enabled);
2805 }
2806}
2807
05b308e1
BR		 2808/**
2809 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2810 * @host: host specific structure
7368f919 2811 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2812 *
2813 * LOCKING:
2814 * Inherited from caller.
2815 */
7368f919 2816static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2817{
f351b2d6 2818 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2819 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2820 unsigned int handled = 0, port;
20f733e7 2821
2b748a0a
ML		 2822 /* If asserted, clear the "all ports" IRQ coalescing bit */
2823 if (main_irq_cause & ALL_PORTS_COAL_DONE)
cae5a29d 2824 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2b748a0a 2825
a3718c1f 2826 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2827 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2828 unsigned int p, shift, hardport, port_cause;
2829
a3718c1f 2830 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2831 /*
eabd5eb1
ML		 2832 * Each hc within the host has its own hc_irq_cause register,
2833 * where the interrupting ports bits get ack'd.
a3718c1f 2834 */
eabd5eb1
ML		 2835 if (hardport == 0) { /* first port on this hc ? */
2836 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2837 u32 port_mask, ack_irqs;
2838 /*
2839 * Skip this entire hc if nothing pending for any ports
2840 */
2841 if (!hc_cause) {
2842 port += MV_PORTS_PER_HC - 1;
2843 continue;
2844 }
2845 /*
2846 * We don't need/want to read the hc_irq_cause register,
2847 * because doing so hurts performance, and
2848 * main_irq_cause already gives us everything we need.
2849 *
2850 * But we do have to *write* to the hc_irq_cause to ack
2851 * the ports that we are handling this time through.
2852 *
2853 * This requires that we create a bitmap for those
2854 * ports which interrupted us, and use that bitmap
2855 * to ack (only) those ports via hc_irq_cause.
2856 */
2857 ack_irqs = 0;
2b748a0a
ML		 2858 if (hc_cause & PORTS_0_3_COAL_DONE)
2859 ack_irqs = HC_COAL_IRQ;
eabd5eb1
ML		 2860 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2861 if ((port + p) >= hpriv->n_ports)
2862 break;
2863 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2864 if (hc_cause & port_mask)
2865 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2866 }
a3718c1f 2867 hc_mmio = mv_hc_base_from_port(mmio, port);
cae5a29d 2868 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
a3718c1f
ML		 2869 handled = 1;
2870 }
8f767f8a 2871 /*
a9010329 2872 * Handle interrupts signalled for this port:
8f767f8a 2873 */
a9010329
ML		 2874 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2875 if (port_cause)
2876 mv_port_intr(ap, port_cause);
20f733e7 2877 }
a3718c1f 2878 return handled;
20f733e7
BR		 2879}
2880
a3718c1f 2881static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2882{
02a121da 2883 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2884 struct ata_port *ap;
2885 struct ata_queued_cmd *qc;
2886 struct ata_eh_info *ehi;
2887 unsigned int i, err_mask, printed = 0;
2888 u32 err_cause;
2889
cae5a29d 2890 err_cause = readl(mmio + hpriv->irq_cause_offset);
bdd4ddde
JG		 2891
2892 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2893 err_cause);
2894
2895 DPRINTK("All regs @ PCI error\n");
2896 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2897
cae5a29d 2898 writelfl(0, mmio + hpriv->irq_cause_offset);
bdd4ddde
JG		 2899
2900 for (i = 0; i < host->n_ports; i++) {
2901 ap = host->ports[i];
936fd732 2902 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2903 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2904 ata_ehi_clear_desc(ehi);
2905 if (!printed++)
2906 ata_ehi_push_desc(ehi,
2907 "PCI err cause 0x%08x", err_cause);
2908 err_mask = AC_ERR_HOST_BUS;
cf480626 2909 ehi->action = ATA_EH_RESET;
9af5c9c9 2910 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2911 if (qc)
2912 qc->err_mask |= err_mask;
2913 else
2914 ehi->err_mask |= err_mask;
2915
2916 ata_port_freeze(ap);
2917 }
2918 }
a3718c1f 2919 return 1; /* handled */
bdd4ddde
JG		 2920}
2921
05b308e1 2922/**
c5d3e45a 2923 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2924 * @irq: unused
2925 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2926 *
2927 * Read the read only register to determine if any host
2928 * controllers have pending interrupts. If so, call lower level
2929 * routine to handle. Also check for PCI errors which are only
2930 * reported here.
2931 *
8b260248 2932 * LOCKING:
cca3974e 2933 * This routine holds the host lock while processing pending
05b308e1
BR		 2934 * interrupts.
2935 */
7d12e780 2936static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2937{
cca3974e 2938 struct ata_host *host = dev_instance;
f351b2d6 2939 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2940 unsigned int handled = 0;
6d3c30ef 2941 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2942 u32 main_irq_cause, pending_irqs;
20f733e7 2943
646a4da5 2944 spin_lock(&host->lock);
6d3c30ef
ML		 2945
2946 /* for MSI: block new interrupts while in here */
2947 if (using_msi)
2b748a0a 2948 mv_write_main_irq_mask(0, hpriv);
6d3c30ef 2949
7368f919 2950 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2951 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2952 /*
2953 * Deal with cases where we either have nothing pending, or have read
2954 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2955 */
a44253d2 2956 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2957 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2958 handled = mv_pci_error(host, hpriv->base);
2959 else
a44253d2 2960 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2961 }
6d3c30ef
ML		 2962
2963 /* for MSI: unmask; interrupt cause bits will retrigger now */
2964 if (using_msi)
2b748a0a 2965 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
6d3c30ef 2966
9d51af7b
ML		 2967 spin_unlock(&host->lock);
2968
20f733e7
BR		 2969 return IRQ_RETVAL(handled);
2970}
2971
c9d39130
JG		 2972static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2973{
2974 unsigned int ofs;
2975
2976 switch (sc_reg_in) {
2977 case SCR_STATUS:
2978 case SCR_ERROR:
2979 case SCR_CONTROL:
2980 ofs = sc_reg_in * sizeof(u32);
2981 break;
2982 default:
2983 ofs = 0xffffffffU;
2984 break;
2985 }
2986 return ofs;
2987}
2988
82ef04fb 2989static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 2990{
82ef04fb 2991 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2992 void __iomem *mmio = hpriv->base;
82ef04fb 2993 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2994 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2995
da3dbb17
TH		 2996 if (ofs != 0xffffffffU) {
2997 *val = readl(addr + ofs);
2998 return 0;
2999 } else
3000 return -EINVAL;
c9d39130
JG		 3001}
3002
82ef04fb 3003static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 3004{
82ef04fb 3005 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 3006 void __iomem *mmio = hpriv->base;
82ef04fb 3007 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 3008 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3009
da3dbb17 3010 if (ofs != 0xffffffffU) {
0d5ff566 3011 writelfl(val, addr + ofs);
da3dbb17
TH		 3012 return 0;
3013 } else
3014 return -EINVAL;
c9d39130
JG		 3015}
3016
7bb3c529 3017static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 3018{
7bb3c529 3019 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 3020 int early_5080;
3021
44c10138 3022 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 3023
3024 if (!early_5080) {
3025 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3026 tmp |= (1 << 0);
3027 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3028 }
3029
7bb3c529 3030 mv_reset_pci_bus(host, mmio);
522479fb
JG		 3031}
3032
3033static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3034{
cae5a29d 3035 writel(0x0fcfffff, mmio + FLASH_CTL);
522479fb
JG		 3036}
3037
47c2b677 3038static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3039 void __iomem *mmio)
3040{
c9d39130
JG		 3041 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3042 u32 tmp;
3043
3044 tmp = readl(phy_mmio + MV5_PHY_MODE);
3045
3046 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3047 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 3048}
3049
47c2b677 3050static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3051{
522479fb
JG		 3052 u32 tmp;
3053
cae5a29d 3054 writel(0, mmio + GPIO_PORT_CTL);
522479fb
JG		 3055
3056 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3057
3058 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3059 tmp |= ~(1 << 0);
3060 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 3061}
3062
2a47ce06
JG		 3063static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3064 unsigned int port)
bca1c4eb 3065{
c9d39130
JG		 3066 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3067 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3068 u32 tmp;
3069 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3070
3071 if (fix_apm_sq) {
cae5a29d 3072 tmp = readl(phy_mmio + MV5_LTMODE);
c9d39130 3073 tmp |= (1 << 19);
cae5a29d 3074 writel(tmp, phy_mmio + MV5_LTMODE);
c9d39130 3075
cae5a29d 3076 tmp = readl(phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3077 tmp &= ~0x3;
3078 tmp |= 0x1;
cae5a29d 3079 writel(tmp, phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3080 }
3081
3082 tmp = readl(phy_mmio + MV5_PHY_MODE);
3083 tmp &= ~mask;
3084 tmp |= hpriv->signal[port].pre;
3085 tmp |= hpriv->signal[port].amps;
3086 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 3087}
3088
c9d39130
JG		 3089
3090#undef ZERO
3091#define ZERO(reg) writel(0, port_mmio + (reg))
3092static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3093 unsigned int port)
3094{
3095 void __iomem *port_mmio = mv_port_base(mmio, port);
3096
e12bef50 3097 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 3098
3099 ZERO(0x028); /* command */
cae5a29d 3100 writel(0x11f, port_mmio + EDMA_CFG);
c9d39130
JG		 3101 ZERO(0x004); /* timer */
3102 ZERO(0x008); /* irq err cause */
3103 ZERO(0x00c); /* irq err mask */
3104 ZERO(0x010); /* rq bah */
3105 ZERO(0x014); /* rq inp */
3106 ZERO(0x018); /* rq outp */
3107 ZERO(0x01c); /* respq bah */
3108 ZERO(0x024); /* respq outp */
3109 ZERO(0x020); /* respq inp */
3110 ZERO(0x02c); /* test control */
cae5a29d 3111 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
c9d39130
JG		 3112}
3113#undef ZERO
3114
3115#define ZERO(reg) writel(0, hc_mmio + (reg))
3116static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3117 unsigned int hc)
47c2b677 3118{
c9d39130
JG		 3119 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3120 u32 tmp;
3121
3122 ZERO(0x00c);
3123 ZERO(0x010);
3124 ZERO(0x014);
3125 ZERO(0x018);
3126
3127 tmp = readl(hc_mmio + 0x20);
3128 tmp &= 0x1c1c1c1c;
3129 tmp |= 0x03030303;
3130 writel(tmp, hc_mmio + 0x20);
3131}
3132#undef ZERO
3133
3134static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3135 unsigned int n_hc)
3136{
3137 unsigned int hc, port;
3138
3139 for (hc = 0; hc < n_hc; hc++) {
3140 for (port = 0; port < MV_PORTS_PER_HC; port++)
3141 mv5_reset_hc_port(hpriv, mmio,
3142 (hc * MV_PORTS_PER_HC) + port);
3143
3144 mv5_reset_one_hc(hpriv, mmio, hc);
3145 }
3146
3147 return 0;
47c2b677
JG		 3148}
3149
101ffae2
JG		 3150#undef ZERO
3151#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 3152static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 3153{
02a121da 3154 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 3155 u32 tmp;
3156
cae5a29d 3157 tmp = readl(mmio + MV_PCI_MODE);
101ffae2 3158 tmp &= 0xff00ffff;
cae5a29d 3159 writel(tmp, mmio + MV_PCI_MODE);
101ffae2
JG		 3160
3161 ZERO(MV_PCI_DISC_TIMER);
3162 ZERO(MV_PCI_MSI_TRIGGER);
cae5a29d 3163 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
101ffae2 3164 ZERO(MV_PCI_SERR_MASK);
cae5a29d
ML		 3165 ZERO(hpriv->irq_cause_offset);
3166 ZERO(hpriv->irq_mask_offset);
101ffae2
JG		 3167 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3168 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3169 ZERO(MV_PCI_ERR_ATTRIBUTE);
3170 ZERO(MV_PCI_ERR_COMMAND);
3171}
3172#undef ZERO
3173
3174static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3175{
3176 u32 tmp;
3177
3178 mv5_reset_flash(hpriv, mmio);
3179
cae5a29d 3180 tmp = readl(mmio + GPIO_PORT_CTL);
101ffae2
JG		 3181 tmp &= 0x3;
3182 tmp |= (1 << 5) | (1 << 6);
cae5a29d 3183 writel(tmp, mmio + GPIO_PORT_CTL);
101ffae2
JG		 3184}
3185
3186/**
3187 * mv6_reset_hc - Perform the 6xxx global soft reset
3188 * @mmio: base address of the HBA
3189 *
3190 * This routine only applies to 6xxx parts.
3191 *
3192 * LOCKING:
3193 * Inherited from caller.
3194 */
c9d39130
JG		 3195static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3196 unsigned int n_hc)
101ffae2 3197{
cae5a29d 3198 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
101ffae2
JG		 3199 int i, rc = 0;
3200 u32 t;
3201
3202 /* Following procedure defined in PCI "main command and status
3203 * register" table.
3204 */
3205 t = readl(reg);
3206 writel(t | STOP_PCI_MASTER, reg);
3207
3208 for (i = 0; i < 1000; i++) {
3209 udelay(1);
3210 t = readl(reg);
2dcb407e 3211 if (PCI_MASTER_EMPTY & t)
101ffae2 3212 break;
101ffae2
JG		 3213 }
3214 if (!(PCI_MASTER_EMPTY & t)) {
3215 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3216 rc = 1;
3217 goto done;
3218 }
3219
3220 /* set reset */
3221 i = 5;
3222 do {
3223 writel(t | GLOB_SFT_RST, reg);
3224 t = readl(reg);
3225 udelay(1);
3226 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3227
3228 if (!(GLOB_SFT_RST & t)) {
3229 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3230 rc = 1;
3231 goto done;
3232 }
3233
3234 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3235 i = 5;
3236 do {
3237 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3238 t = readl(reg);
3239 udelay(1);
3240 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3241
3242 if (GLOB_SFT_RST & t) {
3243 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3244 rc = 1;
3245 }
3246done:
3247 return rc;
3248}
3249
47c2b677 3250static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3251 void __iomem *mmio)
3252{
3253 void __iomem *port_mmio;
3254 u32 tmp;
3255
cae5a29d 3256 tmp = readl(mmio + RESET_CFG);
ba3fe8fb 3257 if ((tmp & (1 << 0)) == 0) {
47c2b677 3258 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 3259 hpriv->signal[idx].pre = 0x1 << 5;
3260 return;
3261 }
3262
3263 port_mmio = mv_port_base(mmio, idx);
3264 tmp = readl(port_mmio + PHY_MODE2);
3265
3266 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3267 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3268}
3269
47c2b677 3270static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3271{
cae5a29d 3272 writel(0x00000060, mmio + GPIO_PORT_CTL);
ba3fe8fb
JG		 3273}
3274
c9d39130 3275static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 3276 unsigned int port)
bca1c4eb 3277{
c9d39130
JG		 3278 void __iomem *port_mmio = mv_port_base(mmio, port);
3279
bca1c4eb 3280 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 3281 int fix_phy_mode2 =
3282 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 3283 int fix_phy_mode4 =
47c2b677 3284 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 3285 u32 m2, m3;
47c2b677
JG		 3286
3287 if (fix_phy_mode2) {
3288 m2 = readl(port_mmio + PHY_MODE2);
3289 m2 &= ~(1 << 16);
3290 m2 |= (1 << 31);
3291 writel(m2, port_mmio + PHY_MODE2);
3292
3293 udelay(200);
3294
3295 m2 = readl(port_mmio + PHY_MODE2);
3296 m2 &= ~((1 << 16) | (1 << 31));
3297 writel(m2, port_mmio + PHY_MODE2);
3298
3299 udelay(200);
3300 }
3301
8c30a8b9
ML		 3302 /*
3303 * Gen-II/IIe PHY_MODE3 errata RM#2:
3304 * Achieves better receiver noise performance than the h/w default:
3305 */
3306 m3 = readl(port_mmio + PHY_MODE3);
3307 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 3308
0388a8c0
ML		 3309 /* Guideline 88F5182 (GL# SATA-S11) */
3310 if (IS_SOC(hpriv))
3311 m3 &= ~0x1c;
3312
bca1c4eb 3313 if (fix_phy_mode4) {
ba069e37
ML		 3314 u32 m4 = readl(port_mmio + PHY_MODE4);
3315 /*
3316 * Enforce reserved-bit restrictions on GenIIe devices only.
3317 * For earlier chipsets, force only the internal config field
3318 * (workaround for errata FEr SATA#10 part 1).
3319 */
8c30a8b9 3320 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 3321 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3322 else
3323 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 3324 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 3325 }
b406c7a6
ML		 3326 /*
3327 * Workaround for 60x1-B2 errata SATA#13:
3328 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3329 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
ba68460b 3330 * Or ensure we use writelfl() when writing PHY_MODE4.
b406c7a6
ML		 3331 */
3332 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 3333
3334 /* Revert values of pre-emphasis and signal amps to the saved ones */
3335 m2 = readl(port_mmio + PHY_MODE2);
3336
3337 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 3338 m2 |= hpriv->signal[port].amps;
3339 m2 |= hpriv->signal[port].pre;
47c2b677 3340 m2 &= ~(1 << 16);
bca1c4eb 3341
e4e7b892
JG		 3342 /* according to mvSata 3.6.1, some IIE values are fixed */
3343 if (IS_GEN_IIE(hpriv)) {
3344 m2 &= ~0xC30FF01F;
3345 m2 |= 0x0000900F;
3346 }
3347
bca1c4eb
JG		 3348 writel(m2, port_mmio + PHY_MODE2);
3349}
3350
f351b2d6
SB		 3351/* TODO: use the generic LED interface to configure the SATA Presence */
3352/* & Acitivy LEDs on the board */
3353static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3354 void __iomem *mmio)
3355{
3356 return;
3357}
3358
3359static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3360 void __iomem *mmio)
3361{
3362 void __iomem *port_mmio;
3363 u32 tmp;
3364
3365 port_mmio = mv_port_base(mmio, idx);
3366 tmp = readl(port_mmio + PHY_MODE2);
3367
3368 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3369 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3370}
3371
3372#undef ZERO
3373#define ZERO(reg) writel(0, port_mmio + (reg))
3374static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3375 void __iomem *mmio, unsigned int port)
3376{
3377 void __iomem *port_mmio = mv_port_base(mmio, port);
3378
e12bef50 3379 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 3380
3381 ZERO(0x028); /* command */
cae5a29d 3382 writel(0x101f, port_mmio + EDMA_CFG);
f351b2d6
SB		 3383 ZERO(0x004); /* timer */
3384 ZERO(0x008); /* irq err cause */
3385 ZERO(0x00c); /* irq err mask */
3386 ZERO(0x010); /* rq bah */
3387 ZERO(0x014); /* rq inp */
3388 ZERO(0x018); /* rq outp */
3389 ZERO(0x01c); /* respq bah */
3390 ZERO(0x024); /* respq outp */
3391 ZERO(0x020); /* respq inp */
3392 ZERO(0x02c); /* test control */
d7b0c143 3393 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
f351b2d6
SB		 3394}
3395
3396#undef ZERO
3397
3398#define ZERO(reg) writel(0, hc_mmio + (reg))
3399static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3400 void __iomem *mmio)
3401{
3402 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3403
3404 ZERO(0x00c);
3405 ZERO(0x010);
3406 ZERO(0x014);
3407
3408}
3409
3410#undef ZERO
3411
3412static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3413 void __iomem *mmio, unsigned int n_hc)
3414{
3415 unsigned int port;
3416
3417 for (port = 0; port < hpriv->n_ports; port++)
3418 mv_soc_reset_hc_port(hpriv, mmio, port);
3419
3420 mv_soc_reset_one_hc(hpriv, mmio);
3421
3422 return 0;
3423}
3424
3425static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3426 void __iomem *mmio)
3427{
3428 return;
3429}
3430
3431static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3432{
3433 return;
3434}
3435
29b7e43c
MM		 3436static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3437 void __iomem *mmio, unsigned int port)
3438{
3439 void __iomem *port_mmio = mv_port_base(mmio, port);
3440 u32 reg;
3441
3442 reg = readl(port_mmio + PHY_MODE3);
3443 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3444 reg |= (0x1 << 27);
3445 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3446 reg |= (0x1 << 29);
3447 writel(reg, port_mmio + PHY_MODE3);
3448
3449 reg = readl(port_mmio + PHY_MODE4);
3450 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3451 reg |= (0x1 << 16);
3452 writel(reg, port_mmio + PHY_MODE4);
3453
3454 reg = readl(port_mmio + PHY_MODE9_GEN2);
3455 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3456 reg |= 0x8;
3457 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3458 writel(reg, port_mmio + PHY_MODE9_GEN2);
3459
3460 reg = readl(port_mmio + PHY_MODE9_GEN1);
3461 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3462 reg |= 0x8;
3463 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3464 writel(reg, port_mmio + PHY_MODE9_GEN1);
3465}
3466
3467/**
3468 * soc_is_65 - check if the soc is 65 nano device
3469 *
3470 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3471 * register, this register should contain non-zero value and it exists only
3472 * in the 65 nano devices, when reading it from older devices we get 0.
3473 */
3474static bool soc_is_65n(struct mv_host_priv *hpriv)
3475{
3476 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3477
3478 if (readl(port0_mmio + PHYCFG_OFS))
3479 return true;
3480 return false;
3481}
3482
8e7decdb 3483static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 3484{
cae5a29d 3485 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
b67a1064 3486
8e7decdb 3487 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 3488 if (want_gen2i)
8e7decdb 3489 ifcfg |= (1 << 7); /* enable gen2i speed */
cae5a29d 3490 writelfl(ifcfg, port_mmio + SATA_IFCFG);
b67a1064
ML		 3491}
3492
e12bef50 3493static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 3494 unsigned int port_no)
3495{
3496 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3497
8e7decdb
ML		 3498 /*
3499 * The datasheet warns against setting EDMA_RESET when EDMA is active
3500 * (but doesn't say what the problem might be). So we first try
3501 * to disable the EDMA engine before doing the EDMA_RESET operation.
3502 */
0d8be5cb 3503 mv_stop_edma_engine(port_mmio);
cae5a29d 3504 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
c9d39130 3505
b67a1064 3506 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 3507 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3508 mv_setup_ifcfg(port_mmio, 1);
c9d39130 3509 }
b67a1064 3510 /*
8e7decdb 3511 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064 3512 * link, and physical layers. It resets all SATA interface registers
cae5a29d 3513 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
c9d39130 3514 */
cae5a29d 3515 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
b67a1064 3516 udelay(25); /* allow reset propagation */
cae5a29d 3517 writelfl(0, port_mmio + EDMA_CMD);
c9d39130
JG		 3518
3519 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3520
ee9ccdf7 3521 if (IS_GEN_I(hpriv))
c9d39130
JG		 3522 mdelay(1);
3523}
3524
e49856d8 3525static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 3526{
e49856d8
ML		 3527 if (sata_pmp_supported(ap)) {
3528 void __iomem *port_mmio = mv_ap_base(ap);
cae5a29d 3529 u32 reg = readl(port_mmio + SATA_IFCTL);
e49856d8 3530 int old = reg & 0xf;
22374677 3531
e49856d8
ML		 3532 if (old != pmp) {
3533 reg = (reg & ~0xf) | pmp;
cae5a29d 3534 writelfl(reg, port_mmio + SATA_IFCTL);
e49856d8 3535 }
22374677 3536 }
20f733e7
BR		 3537}
3538
e49856d8
ML		 3539static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3540 unsigned long deadline)
22374677 3541{
e49856d8
ML		 3542 mv_pmp_select(link->ap, sata_srst_pmp(link));
3543 return sata_std_hardreset(link, class, deadline);
3544}
bdd4ddde 3545
e49856d8
ML		 3546static int mv_softreset(struct ata_link *link, unsigned int *class,
3547 unsigned long deadline)
3548{
3549 mv_pmp_select(link->ap, sata_srst_pmp(link));
3550 return ata_sff_softreset(link, class, deadline);
22374677
JG		 3551}
3552
cc0680a5 3553static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 3554 unsigned long deadline)
31961943 3555{
cc0680a5 3556 struct ata_port *ap = link->ap;
bdd4ddde 3557 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 3558 struct mv_port_priv *pp = ap->private_data;
f351b2d6 3559 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 3560 int rc, attempts = 0, extra = 0;
3561 u32 sstatus;
3562 bool online;
31961943 3563
e12bef50 3564 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 3565 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
d16ab3f6
ML		 3566 pp->pp_flags &=
3567 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
bdd4ddde 3568
0d8be5cb
ML		 3569 /* Workaround for errata FEr SATA#10 (part 2) */
3570 do {
17c5aab5
ML		 3571 const unsigned long *timing =
3572 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 3573
17c5aab5
ML		 3574 rc = sata_link_hardreset(link, timing, deadline + extra,
3575 &online, NULL);
9dcffd99 3576 rc = online ? -EAGAIN : rc;
17c5aab5 3577 if (rc)
0d8be5cb 3578 return rc;
0d8be5cb
ML		 3579 sata_scr_read(link, SCR_STATUS, &sstatus);
3580 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3581 /* Force 1.5gb/s link speed and try again */
8e7decdb 3582 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 3583 if (time_after(jiffies + HZ, deadline))
3584 extra = HZ; /* only extend it once, max */
3585 }
3586 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
08da1759 3587 mv_save_cached_regs(ap);
66e57a2c 3588 mv_edma_cfg(ap, 0, 0);
bdd4ddde 3589
17c5aab5 3590 return rc;
bdd4ddde
JG		 3591}
3592
bdd4ddde
JG		 3593static void mv_eh_freeze(struct ata_port *ap)
3594{
1cfd19ae 3595 mv_stop_edma(ap);
c4de573b 3596 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3597}
3598
3599static void mv_eh_thaw(struct ata_port *ap)
3600{
f351b2d6 3601 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3602 unsigned int port = ap->port_no;
3603 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3604 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3605 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3606 u32 hc_irq_cause;
bdd4ddde 3607
bdd4ddde 3608 /* clear EDMA errors on this port */
cae5a29d 3609 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde
JG		 3610
3611 /* clear pending irq events */
cae6edc3 3612 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 3613 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
bdd4ddde 3614
88e675e1 3615 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3616}
3617
05b308e1
BR		 3618/**
3619 * mv_port_init - Perform some early initialization on a single port.
3620 * @port: libata data structure storing shadow register addresses
3621 * @port_mmio: base address of the port
3622 *
3623 * Initialize shadow register mmio addresses, clear outstanding
3624 * interrupts on the port, and unmask interrupts for the future
3625 * start of the port.
3626 *
3627 * LOCKING:
3628 * Inherited from caller.
3629 */
31961943 3630static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3631{
cae5a29d 3632 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
31961943 3633
8b260248 3634 /* PIO related setup
31961943
BR		 3635 */
3636 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3637 port->error_addr =
31961943
BR		 3638 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3639 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3640 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3641 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3642 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3643 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3644 port->status_addr =
31961943
BR		 3645 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3646 /* special case: control/altstatus doesn't have ATA_REG_ address */
cae5a29d 3647 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
31961943 3648
31961943 3649 /* Clear any currently outstanding port interrupt conditions */
cae5a29d
ML		 3650 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3651 writelfl(readl(serr), serr);
3652 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
31961943 3653
646a4da5 3654 /* unmask all non-transient EDMA error interrupts */
cae5a29d 3655 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
20f733e7 3656
8b260248 3657 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
cae5a29d
ML		 3658 readl(port_mmio + EDMA_CFG),
3659 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3660 readl(port_mmio + EDMA_ERR_IRQ_MASK));
20f733e7
BR		 3661}
3662
616d4a98
ML		 3663static unsigned int mv_in_pcix_mode(struct ata_host *host)
3664{
3665 struct mv_host_priv *hpriv = host->private_data;
3666 void __iomem *mmio = hpriv->base;
3667 u32 reg;
3668
1f398472 3669 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98 3670 return 0; /* not PCI-X capable */
cae5a29d 3671 reg = readl(mmio + MV_PCI_MODE);
616d4a98
ML		 3672 if ((reg & MV_PCI_MODE_MASK) == 0)
3673 return 0; /* conventional PCI mode */
3674 return 1; /* chip is in PCI-X mode */
3675}
3676
3677static int mv_pci_cut_through_okay(struct ata_host *host)
3678{
3679 struct mv_host_priv *hpriv = host->private_data;
3680 void __iomem *mmio = hpriv->base;
3681 u32 reg;
3682
3683 if (!mv_in_pcix_mode(host)) {
cae5a29d
ML		 3684 reg = readl(mmio + MV_PCI_COMMAND);
3685 if (reg & MV_PCI_COMMAND_MRDTRIG)
616d4a98
ML		 3686 return 0; /* not okay */
3687 }
3688 return 1; /* okay */
3689}
3690
65ad7fef
ML		 3691static void mv_60x1b2_errata_pci7(struct ata_host *host)
3692{
3693 struct mv_host_priv *hpriv = host->private_data;
3694 void __iomem *mmio = hpriv->base;
3695
3696 /* workaround for 60x1-B2 errata PCI#7 */
3697 if (mv_in_pcix_mode(host)) {
cae5a29d
ML		 3698 u32 reg = readl(mmio + MV_PCI_COMMAND);
3699 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
65ad7fef
ML		 3700 }
3701}
3702
4447d351 3703static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3704{
4447d351
TH		 3705 struct pci_dev *pdev = to_pci_dev(host->dev);
3706 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3707 u32 hp_flags = hpriv->hp_flags;
3708
5796d1c4 3709 switch (board_idx) {
47c2b677
JG		 3710 case chip_5080:
3711 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3712 hp_flags |= MV_HP_GEN_I;
47c2b677 3713
44c10138 3714 switch (pdev->revision) {
47c2b677
JG		 3715 case 0x1:
3716 hp_flags |= MV_HP_ERRATA_50XXB0;
3717 break;
3718 case 0x3:
3719 hp_flags |= MV_HP_ERRATA_50XXB2;
3720 break;
3721 default:
3722 dev_printk(KERN_WARNING, &pdev->dev,
3723 "Applying 50XXB2 workarounds to unknown rev\n");
3724 hp_flags |= MV_HP_ERRATA_50XXB2;
3725 break;
3726 }
3727 break;
3728
bca1c4eb
JG		 3729 case chip_504x:
3730 case chip_508x:
47c2b677 3731 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3732 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3733
44c10138 3734 switch (pdev->revision) {
47c2b677
JG		 3735 case 0x0:
3736 hp_flags |= MV_HP_ERRATA_50XXB0;
3737 break;
3738 case 0x3:
3739 hp_flags |= MV_HP_ERRATA_50XXB2;
3740 break;
3741 default:
3742 dev_printk(KERN_WARNING, &pdev->dev,
3743 "Applying B2 workarounds to unknown rev\n");
3744 hp_flags |= MV_HP_ERRATA_50XXB2;
3745 break;
bca1c4eb
JG		 3746 }
3747 break;
3748
3749 case chip_604x:
3750 case chip_608x:
47c2b677 3751 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3752 hp_flags |= MV_HP_GEN_II;
47c2b677 3753
44c10138 3754 switch (pdev->revision) {
47c2b677 3755 case 0x7:
65ad7fef 3756 mv_60x1b2_errata_pci7(host);
47c2b677
JG		 3757 hp_flags |= MV_HP_ERRATA_60X1B2;
3758 break;
3759 case 0x9:
3760 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3761 break;
3762 default:
3763 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 3764 "Applying B2 workarounds to unknown rev\n");
3765 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3766 break;
3767 }
3768 break;
3769
e4e7b892 3770 case chip_7042:
616d4a98 3771 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3772 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3773 (pdev->device == 0x2300 || pdev->device == 0x2310))
3774 {
4e520033
ML		 3775 /*
3776 * Highpoint RocketRAID PCIe 23xx series cards:
3777 *
3778 * Unconfigured drives are treated as "Legacy"
3779 * by the BIOS, and it overwrites sector 8 with
3780 * a "Lgcy" metadata block prior to Linux boot.
3781 *
3782 * Configured drives (RAID or JBOD) leave sector 8
3783 * alone, but instead overwrite a high numbered
3784 * sector for the RAID metadata. This sector can
3785 * be determined exactly, by truncating the physical
3786 * drive capacity to a nice even GB value.
3787 *
3788 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3789 *
3790 * Warn the user, lest they think we're just buggy.
3791 */
3792 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3793 " BIOS CORRUPTS DATA on all attached drives,"
3794 " regardless of if/how they are configured."
3795 " BEWARE!\n");
3796 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3797 " use sectors 8-9 on \"Legacy\" drives,"
3798 " and avoid the final two gigabytes on"
3799 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3800 }
8e7decdb 3801 /* drop through */
e4e7b892
JG		 3802 case chip_6042:
3803 hpriv->ops = &mv6xxx_ops;
e4e7b892 3804 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3805 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3806 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3807
44c10138 3808 switch (pdev->revision) {
5cf73bfb 3809 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3810 hp_flags |= MV_HP_ERRATA_60X1C0;
3811 break;
3812 default:
3813 dev_printk(KERN_WARNING, &pdev->dev,
3814 "Applying 60X1C0 workarounds to unknown rev\n");
3815 hp_flags |= MV_HP_ERRATA_60X1C0;
3816 break;
3817 }
3818 break;
f351b2d6 3819 case chip_soc:
29b7e43c
MM		 3820 if (soc_is_65n(hpriv))
3821 hpriv->ops = &mv_soc_65n_ops;
3822 else
3823 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3824 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3825 MV_HP_ERRATA_60X1C0;
f351b2d6 3826 break;
e4e7b892 3827
bca1c4eb 3828 default:
f351b2d6 3829 dev_printk(KERN_ERR, host->dev,
5796d1c4 3830 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3831 return 1;
3832 }
3833
3834 hpriv->hp_flags = hp_flags;
02a121da 3835 if (hp_flags & MV_HP_PCIE) {
cae5a29d
ML		 3836 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3837 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
02a121da
ML		 3838 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3839 } else {
cae5a29d
ML		 3840 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3841 hpriv->irq_mask_offset = PCI_IRQ_MASK;
02a121da
ML		 3842 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3843 }
bca1c4eb
JG		 3844
3845 return 0;
3846}
3847
05b308e1 3848/**
47c2b677 3849 * mv_init_host - Perform some early initialization of the host.
4447d351 3850 * @host: ATA host to initialize
05b308e1
BR		 3851 *
3852 * If possible, do an early global reset of the host. Then do
3853 * our port init and clear/unmask all/relevant host interrupts.
3854 *
3855 * LOCKING:
3856 * Inherited from caller.
3857 */
1bfeff03 3858static int mv_init_host(struct ata_host *host)
20f733e7
BR		 3859{
3860 int rc = 0, n_hc, port, hc;
4447d351 3861 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3862 void __iomem *mmio = hpriv->base;
47c2b677 3863
1bfeff03 3864 rc = mv_chip_id(host, hpriv->board_idx);
bca1c4eb 3865 if (rc)
352fab70 3866 goto done;
f351b2d6 3867
1f398472 3868 if (IS_SOC(hpriv)) {
cae5a29d
ML		 3869 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3870 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
1f398472 3871 } else {
cae5a29d
ML		 3872 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3873 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
f351b2d6 3874 }
352fab70 3875
5d0fb2e7
TR		 3876 /* initialize shadow irq mask with register's value */
3877 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3878
352fab70 3879 /* global interrupt mask: 0 == mask everything */
c4de573b 3880 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3881
4447d351 3882 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3883
4447d351 3884 for (port = 0; port < host->n_ports; port++)
29b7e43c
MM		 3885 if (hpriv->ops->read_preamp)
3886 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3887
c9d39130 3888 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3889 if (rc)
20f733e7 3890 goto done;
20f733e7 3891
522479fb 3892 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3893 hpriv->ops->reset_bus(host, mmio);
47c2b677 3894 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3895
4447d351 3896 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3897 struct ata_port *ap = host->ports[port];
2a47ce06 3898 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3899
3900 mv_port_init(&ap->ioaddr, port_mmio);
20f733e7
BR		 3901 }
3902
3903 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3904 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3905
3906 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3907 "(before clear)=0x%08x\n", hc,
cae5a29d
ML		 3908 readl(hc_mmio + HC_CFG),
3909 readl(hc_mmio + HC_IRQ_CAUSE));
31961943
BR		 3910
3911 /* Clear any currently outstanding hc interrupt conditions */
cae5a29d 3912 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
20f733e7
BR		 3913 }
3914
44c65d16
ML		 3915 if (!IS_SOC(hpriv)) {
3916 /* Clear any currently outstanding host interrupt conditions */
cae5a29d 3917 writelfl(0, mmio + hpriv->irq_cause_offset);
31961943 3918
44c65d16 3919 /* and unmask interrupt generation for host regs */
cae5a29d 3920 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
44c65d16 3921 }
51de32d2 3922
6be96ac1
ML		 3923 /*
3924 * enable only global host interrupts for now.
3925 * The per-port interrupts get done later as ports are set up.
3926 */
3927 mv_set_main_irq_mask(host, 0, PCI_ERR);
2b748a0a
ML		 3928 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3929 irq_coalescing_usecs);
f351b2d6
SB		 3930done:
3931 return rc;
3932}
fb621e2f 3933
fbf14e2f
BB		 3934static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3935{
3936 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3937 MV_CRQB_Q_SZ, 0);
3938 if (!hpriv->crqb_pool)
3939 return -ENOMEM;
3940
3941 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3942 MV_CRPB_Q_SZ, 0);
3943 if (!hpriv->crpb_pool)
3944 return -ENOMEM;
3945
3946 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3947 MV_SG_TBL_SZ, 0);
3948 if (!hpriv->sg_tbl_pool)
3949 return -ENOMEM;
3950
3951 return 0;
3952}
3953
15a32632
LB		 3954static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3955 struct mbus_dram_target_info *dram)
3956{
3957 int i;
3958
3959 for (i = 0; i < 4; i++) {
3960 writel(0, hpriv->base + WINDOW_CTRL(i));
3961 writel(0, hpriv->base + WINDOW_BASE(i));
3962 }
3963
3964 for (i = 0; i < dram->num_cs; i++) {
3965 struct mbus_dram_window *cs = dram->cs + i;
3966
3967 writel(((cs->size - 1) & 0xffff0000) |
3968 (cs->mbus_attr << 8) |
3969 (dram->mbus_dram_target_id << 4) | 1,
3970 hpriv->base + WINDOW_CTRL(i));
3971 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3972 }
3973}
3974
f351b2d6
SB		 3975/**
3976 * mv_platform_probe - handle a positive probe of an soc Marvell
3977 * host
3978 * @pdev: platform device found
3979 *
3980 * LOCKING:
3981 * Inherited from caller.
3982 */
3983static int mv_platform_probe(struct platform_device *pdev)
3984{
3985 static int printed_version;
3986 const struct mv_sata_platform_data *mv_platform_data;
3987 const struct ata_port_info *ppi[] =
3988 { &mv_port_info[chip_soc], NULL };
3989 struct ata_host *host;
3990 struct mv_host_priv *hpriv;
3991 struct resource *res;
3992 int n_ports, rc;
20f733e7 3993
f351b2d6
SB		 3994 if (!printed_version++)
3995 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3996
f351b2d6
SB		 3997 /*
3998 * Simple resource validation ..
3999 */
4000 if (unlikely(pdev->num_resources != 2)) {
4001 dev_err(&pdev->dev, "invalid number of resources\n");
4002 return -EINVAL;
4003 }
4004
4005 /*
4006 * Get the register base first
4007 */
4008 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4009 if (res == NULL)
4010 return -EINVAL;
4011
4012 /* allocate host */
4013 mv_platform_data = pdev->dev.platform_data;
4014 n_ports = mv_platform_data->n_ports;
4015
4016 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4017 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4018
4019 if (!host || !hpriv)
4020 return -ENOMEM;
4021 host->private_data = hpriv;
4022 hpriv->n_ports = n_ports;
1bfeff03 4023 hpriv->board_idx = chip_soc;
f351b2d6
SB		 4024
4025 host->iomap = NULL;
f1cb0ea1 4026 hpriv->base = devm_ioremap(&pdev->dev, res->start,
041b5eac 4027 resource_size(res));
cae5a29d 4028 hpriv->base -= SATAHC0_REG_BASE;
f351b2d6 4029
c77a2f4e
SB		 4030#if defined(CONFIG_HAVE_CLK)
4031 hpriv->clk = clk_get(&pdev->dev, NULL);
4032 if (IS_ERR(hpriv->clk))
4033 dev_notice(&pdev->dev, "cannot get clkdev\n");
4034 else
4035 clk_enable(hpriv->clk);
4036#endif
4037
15a32632
LB		 4038 /*
4039 * (Re-)program MBUS remapping windows if we are asked to.
4040 */
4041 if (mv_platform_data->dram != NULL)
4042 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4043
fbf14e2f
BB		 4044 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4045 if (rc)
c77a2f4e 4046 goto err;
fbf14e2f 4047
f351b2d6 4048 /* initialize adapter */
1bfeff03 4049 rc = mv_init_host(host);
f351b2d6 4050 if (rc)
c77a2f4e 4051 goto err;
f351b2d6
SB		 4052
4053 dev_printk(KERN_INFO, &pdev->dev,
4054 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4055 host->n_ports);
4056
4057 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4058 IRQF_SHARED, &mv6_sht);
c77a2f4e
SB		 4059err:
4060#if defined(CONFIG_HAVE_CLK)
4061 if (!IS_ERR(hpriv->clk)) {
4062 clk_disable(hpriv->clk);
4063 clk_put(hpriv->clk);
4064 }
4065#endif
4066
4067 return rc;
f351b2d6
SB		 4068}
4069
4070/*
4071 *
4072 * mv_platform_remove - unplug a platform interface
4073 * @pdev: platform device
4074 *
4075 * A platform bus SATA device has been unplugged. Perform the needed
4076 * cleanup. Also called on module unload for any active devices.
4077 */
4078static int __devexit mv_platform_remove(struct platform_device *pdev)
4079{
4080 struct device *dev = &pdev->dev;
4081 struct ata_host *host = dev_get_drvdata(dev);
c77a2f4e
SB		 4082#if defined(CONFIG_HAVE_CLK)
4083 struct mv_host_priv *hpriv = host->private_data;
4084#endif
f351b2d6 4085 ata_host_detach(host);
c77a2f4e
SB		 4086
4087#if defined(CONFIG_HAVE_CLK)
4088 if (!IS_ERR(hpriv->clk)) {
4089 clk_disable(hpriv->clk);
4090 clk_put(hpriv->clk);
4091 }
4092#endif
f351b2d6 4093 return 0;
20f733e7
BR		 4094}
4095
6481f2b5
SB		 4096#ifdef CONFIG_PM
4097static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4098{
4099 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4100 if (host)
4101 return ata_host_suspend(host, state);
4102 else
4103 return 0;
4104}
4105
4106static int mv_platform_resume(struct platform_device *pdev)
4107{
4108 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4109 int ret;
4110
4111 if (host) {
4112 struct mv_host_priv *hpriv = host->private_data;
4113 const struct mv_sata_platform_data *mv_platform_data = \
4114 pdev->dev.platform_data;
4115 /*
4116 * (Re-)program MBUS remapping windows if we are asked to.
4117 */
4118 if (mv_platform_data->dram != NULL)
4119 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4120
4121 /* initialize adapter */
1bfeff03 4122 ret = mv_init_host(host);
6481f2b5
SB		 4123 if (ret) {
4124 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4125 return ret;
4126 }
4127 ata_host_resume(host);
4128 }
4129
4130 return 0;
4131}
4132#else
4133#define mv_platform_suspend NULL
4134#define mv_platform_resume NULL
4135#endif
4136
f351b2d6
SB		 4137static struct platform_driver mv_platform_driver = {
4138 .probe = mv_platform_probe,
4139 .remove = __devexit_p(mv_platform_remove),
6481f2b5
SB		 4140 .suspend = mv_platform_suspend,
4141 .resume = mv_platform_resume,
f351b2d6
SB		 4142 .driver = {
4143 .name = DRV_NAME,
4144 .owner = THIS_MODULE,
4145 },
4146};
4147
4148
7bb3c529 4149#ifdef CONFIG_PCI
f351b2d6
SB		 4150static int mv_pci_init_one(struct pci_dev *pdev,
4151 const struct pci_device_id *ent);
b2dec48c
SB		 4152#ifdef CONFIG_PM
4153static int mv_pci_device_resume(struct pci_dev *pdev);
4154#endif
f351b2d6 4155
7bb3c529
SB		 4156
4157static struct pci_driver mv_pci_driver = {
4158 .name = DRV_NAME,
4159 .id_table = mv_pci_tbl,
f351b2d6 4160 .probe = mv_pci_init_one,
7bb3c529 4161 .remove = ata_pci_remove_one,
b2dec48c
SB		 4162#ifdef CONFIG_PM
4163 .suspend = ata_pci_device_suspend,
4164 .resume = mv_pci_device_resume,
4165#endif
4166
7bb3c529
SB		 4167};
4168
7bb3c529
SB		 4169/* move to PCI layer or libata core? */
4170static int pci_go_64(struct pci_dev *pdev)
4171{
4172 int rc;
4173
6a35528a
YH		 4174 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4175 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
7bb3c529 4176 if (rc) {
284901a9 4177 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529
SB		 4178 if (rc) {
4179 dev_printk(KERN_ERR, &pdev->dev,
4180 "64-bit DMA enable failed\n");
4181 return rc;
4182 }
4183 }
4184 } else {
284901a9 4185 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529
SB		 4186 if (rc) {
4187 dev_printk(KERN_ERR, &pdev->dev,
4188 "32-bit DMA enable failed\n");
4189 return rc;
4190 }
284901a9 4191 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529
SB		 4192 if (rc) {
4193 dev_printk(KERN_ERR, &pdev->dev,
4194 "32-bit consistent DMA enable failed\n");
4195 return rc;
4196 }
4197 }
4198
4199 return rc;
4200}
4201
05b308e1
BR		 4202/**
4203 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 4204 * @host: ATA host to print info about
05b308e1
BR		 4205 *
4206 * FIXME: complete this.
4207 *
4208 * LOCKING:
4209 * Inherited from caller.
4210 */
4447d351 4211static void mv_print_info(struct ata_host *host)
31961943 4212{
4447d351
TH		 4213 struct pci_dev *pdev = to_pci_dev(host->dev);
4214 struct mv_host_priv *hpriv = host->private_data;
44c10138 4215 u8 scc;
c1e4fe71 4216 const char *scc_s, *gen;
31961943
BR		 4217
4218 /* Use this to determine the HW stepping of the chip so we know
4219 * what errata to workaround
4220 */
31961943
BR		 4221 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4222 if (scc == 0)
4223 scc_s = "SCSI";
4224 else if (scc == 0x01)
4225 scc_s = "RAID";
4226 else
c1e4fe71
JG		 4227 scc_s = "?";
4228
4229 if (IS_GEN_I(hpriv))
4230 gen = "I";
4231 else if (IS_GEN_II(hpriv))
4232 gen = "II";
4233 else if (IS_GEN_IIE(hpriv))
4234 gen = "IIE";
4235 else
4236 gen = "?";
31961943 4237
a9524a76 4238 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 4239 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4240 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 4241 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4242}
4243
05b308e1 4244/**
f351b2d6 4245 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 4246 * @pdev: PCI device found
4247 * @ent: PCI device ID entry for the matched host
4248 *
4249 * LOCKING:
4250 * Inherited from caller.
4251 */
f351b2d6
SB		 4252static int mv_pci_init_one(struct pci_dev *pdev,
4253 const struct pci_device_id *ent)
20f733e7 4254{
2dcb407e 4255 static int printed_version;
20f733e7 4256 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 4257 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4258 struct ata_host *host;
4259 struct mv_host_priv *hpriv;
c4bc7d73 4260 int n_ports, port, rc;
20f733e7 4261
a9524a76
JG		 4262 if (!printed_version++)
4263 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 4264
4447d351
TH		 4265 /* allocate host */
4266 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4267
4268 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4269 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4270 if (!host || !hpriv)
4271 return -ENOMEM;
4272 host->private_data = hpriv;
f351b2d6 4273 hpriv->n_ports = n_ports;
1bfeff03 4274 hpriv->board_idx = board_idx;
4447d351
TH		 4275
4276 /* acquire resources */
24dc5f33
TH		 4277 rc = pcim_enable_device(pdev);
4278 if (rc)
20f733e7 4279 return rc;
20f733e7 4280
0d5ff566
TH		 4281 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4282 if (rc == -EBUSY)
24dc5f33 4283 pcim_pin_device(pdev);
0d5ff566 4284 if (rc)
24dc5f33 4285 return rc;
4447d351 4286 host->iomap = pcim_iomap_table(pdev);
f351b2d6 4287 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 4288
d88184fb
JG		 4289 rc = pci_go_64(pdev);
4290 if (rc)
4291 return rc;
4292
da2fa9ba
ML		 4293 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4294 if (rc)
4295 return rc;
4296
c4bc7d73
SB		 4297 for (port = 0; port < host->n_ports; port++) {
4298 struct ata_port *ap = host->ports[port];
4299 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4300 unsigned int offset = port_mmio - hpriv->base;
4301
4302 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4303 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4304 }
4305
20f733e7 4306 /* initialize adapter */
1bfeff03 4307 rc = mv_init_host(host);
24dc5f33
TH		 4308 if (rc)
4309 return rc;
20f733e7 4310
6d3c30ef
ML		 4311 /* Enable message-switched interrupts, if requested */
4312 if (msi && pci_enable_msi(pdev) == 0)
4313 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 4314
31961943 4315 mv_dump_pci_cfg(pdev, 0x68);
4447d351 4316 mv_print_info(host);
20f733e7 4317
4447d351 4318 pci_set_master(pdev);
ea8b4db9 4319 pci_try_set_mwi(pdev);
4447d351 4320 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 4321 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 4322}
b2dec48c
SB		 4323
4324#ifdef CONFIG_PM
4325static int mv_pci_device_resume(struct pci_dev *pdev)
4326{
4327 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4328 int rc;
4329
4330 rc = ata_pci_device_do_resume(pdev);
4331 if (rc)
4332 return rc;
4333
4334 /* initialize adapter */
4335 rc = mv_init_host(host);
4336 if (rc)
4337 return rc;
4338
4339 ata_host_resume(host);
4340
4341 return 0;
4342}
4343#endif
7bb3c529 4344#endif
20f733e7 4345
f351b2d6
SB		 4346static int mv_platform_probe(struct platform_device *pdev);
4347static int __devexit mv_platform_remove(struct platform_device *pdev);
4348
20f733e7
BR		 4349static int __init mv_init(void)
4350{
7bb3c529
SB		 4351 int rc = -ENODEV;
4352#ifdef CONFIG_PCI
4353 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 4354 if (rc < 0)
4355 return rc;
4356#endif
4357 rc = platform_driver_register(&mv_platform_driver);
4358
4359#ifdef CONFIG_PCI
4360 if (rc < 0)
4361 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 4362#endif
4363 return rc;
20f733e7
BR		 4364}
4365
4366static void __exit mv_exit(void)
4367{
7bb3c529 4368#ifdef CONFIG_PCI
20f733e7 4369 pci_unregister_driver(&mv_pci_driver);
7bb3c529 4370#endif
f351b2d6 4371 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 4372}
4373
4374MODULE_AUTHOR("Brett Russ");
4375MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4376MODULE_LICENSE("GPL");
4377MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4378MODULE_VERSION(DRV_VERSION);
17c5aab5 4379MODULE_ALIAS("platform:" DRV_NAME);
20f733e7
BR		 4380
4381module_init(mv_init);
4382module_exit(mv_exit);
Linux kernel - Deliverables
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