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1da177e4 LT |
1 | /* |
2 | * sata_nv.c - NVIDIA nForce SATA | |
3 | * | |
4 | * Copyright 2004 NVIDIA Corp. All rights reserved. | |
5 | * Copyright 2004 Andrew Chew | |
6 | * | |
aa7e16d6 JG |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, write to | |
20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
1da177e4 | 21 | * |
af36d7f0 JG |
22 | * |
23 | * libata documentation is available via 'make {ps|pdf}docs', | |
24 | * as Documentation/DocBook/libata.* | |
25 | * | |
26 | * No hardware documentation available outside of NVIDIA. | |
27 | * This driver programs the NVIDIA SATA controller in a similar | |
28 | * fashion as with other PCI IDE BMDMA controllers, with a few | |
29 | * NV-specific details such as register offsets, SATA phy location, | |
30 | * hotplug info, etc. | |
31 | * | |
fbbb262d RH |
32 | * CK804/MCP04 controllers support an alternate programming interface |
33 | * similar to the ADMA specification (with some modifications). | |
34 | * This allows the use of NCQ. Non-DMA-mapped ATA commands are still | |
35 | * sent through the legacy interface. | |
36 | * | |
1da177e4 LT |
37 | */ |
38 | ||
1da177e4 LT |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/blkdev.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/interrupt.h> | |
a9524a76 | 46 | #include <linux/device.h> |
1da177e4 | 47 | #include <scsi/scsi_host.h> |
fbbb262d | 48 | #include <scsi/scsi_device.h> |
1da177e4 LT |
49 | #include <linux/libata.h> |
50 | ||
51 | #define DRV_NAME "sata_nv" | |
2a3103ce | 52 | #define DRV_VERSION "3.5" |
fbbb262d RH |
53 | |
54 | #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL | |
1da177e4 | 55 | |
10ad05df | 56 | enum { |
0d5ff566 TH |
57 | NV_MMIO_BAR = 5, |
58 | ||
10ad05df JG |
59 | NV_PORTS = 2, |
60 | NV_PIO_MASK = 0x1f, | |
61 | NV_MWDMA_MASK = 0x07, | |
62 | NV_UDMA_MASK = 0x7f, | |
63 | NV_PORT0_SCR_REG_OFFSET = 0x00, | |
64 | NV_PORT1_SCR_REG_OFFSET = 0x40, | |
1da177e4 | 65 | |
27e4b274 | 66 | /* INT_STATUS/ENABLE */ |
10ad05df | 67 | NV_INT_STATUS = 0x10, |
10ad05df | 68 | NV_INT_ENABLE = 0x11, |
27e4b274 | 69 | NV_INT_STATUS_CK804 = 0x440, |
10ad05df | 70 | NV_INT_ENABLE_CK804 = 0x441, |
1da177e4 | 71 | |
27e4b274 TH |
72 | /* INT_STATUS/ENABLE bits */ |
73 | NV_INT_DEV = 0x01, | |
74 | NV_INT_PM = 0x02, | |
75 | NV_INT_ADDED = 0x04, | |
76 | NV_INT_REMOVED = 0x08, | |
77 | ||
78 | NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */ | |
79 | ||
39f87582 | 80 | NV_INT_ALL = 0x0f, |
5a44efff TH |
81 | NV_INT_MASK = NV_INT_DEV | |
82 | NV_INT_ADDED | NV_INT_REMOVED, | |
39f87582 | 83 | |
27e4b274 | 84 | /* INT_CONFIG */ |
10ad05df JG |
85 | NV_INT_CONFIG = 0x12, |
86 | NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI | |
1da177e4 | 87 | |
10ad05df JG |
88 | // For PCI config register 20 |
89 | NV_MCP_SATA_CFG_20 = 0x50, | |
90 | NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04, | |
fbbb262d RH |
91 | NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17), |
92 | NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16), | |
93 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14), | |
94 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12), | |
95 | ||
96 | NV_ADMA_MAX_CPBS = 32, | |
97 | NV_ADMA_CPB_SZ = 128, | |
98 | NV_ADMA_APRD_SZ = 16, | |
99 | NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) / | |
100 | NV_ADMA_APRD_SZ, | |
101 | NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5, | |
102 | NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ, | |
103 | NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS * | |
104 | (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ), | |
105 | ||
106 | /* BAR5 offset to ADMA general registers */ | |
107 | NV_ADMA_GEN = 0x400, | |
108 | NV_ADMA_GEN_CTL = 0x00, | |
109 | NV_ADMA_NOTIFIER_CLEAR = 0x30, | |
110 | ||
111 | /* BAR5 offset to ADMA ports */ | |
112 | NV_ADMA_PORT = 0x480, | |
113 | ||
114 | /* size of ADMA port register space */ | |
115 | NV_ADMA_PORT_SIZE = 0x100, | |
116 | ||
117 | /* ADMA port registers */ | |
118 | NV_ADMA_CTL = 0x40, | |
119 | NV_ADMA_CPB_COUNT = 0x42, | |
120 | NV_ADMA_NEXT_CPB_IDX = 0x43, | |
121 | NV_ADMA_STAT = 0x44, | |
122 | NV_ADMA_CPB_BASE_LOW = 0x48, | |
123 | NV_ADMA_CPB_BASE_HIGH = 0x4C, | |
124 | NV_ADMA_APPEND = 0x50, | |
125 | NV_ADMA_NOTIFIER = 0x68, | |
126 | NV_ADMA_NOTIFIER_ERROR = 0x6C, | |
127 | ||
128 | /* NV_ADMA_CTL register bits */ | |
129 | NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0), | |
130 | NV_ADMA_CTL_CHANNEL_RESET = (1 << 5), | |
131 | NV_ADMA_CTL_GO = (1 << 7), | |
132 | NV_ADMA_CTL_AIEN = (1 << 8), | |
133 | NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11), | |
134 | NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12), | |
135 | ||
136 | /* CPB response flag bits */ | |
137 | NV_CPB_RESP_DONE = (1 << 0), | |
138 | NV_CPB_RESP_ATA_ERR = (1 << 3), | |
139 | NV_CPB_RESP_CMD_ERR = (1 << 4), | |
140 | NV_CPB_RESP_CPB_ERR = (1 << 7), | |
141 | ||
142 | /* CPB control flag bits */ | |
143 | NV_CPB_CTL_CPB_VALID = (1 << 0), | |
144 | NV_CPB_CTL_QUEUE = (1 << 1), | |
145 | NV_CPB_CTL_APRD_VALID = (1 << 2), | |
146 | NV_CPB_CTL_IEN = (1 << 3), | |
147 | NV_CPB_CTL_FPDMA = (1 << 4), | |
148 | ||
149 | /* APRD flags */ | |
150 | NV_APRD_WRITE = (1 << 1), | |
151 | NV_APRD_END = (1 << 2), | |
152 | NV_APRD_CONT = (1 << 3), | |
153 | ||
154 | /* NV_ADMA_STAT flags */ | |
155 | NV_ADMA_STAT_TIMEOUT = (1 << 0), | |
156 | NV_ADMA_STAT_HOTUNPLUG = (1 << 1), | |
157 | NV_ADMA_STAT_HOTPLUG = (1 << 2), | |
158 | NV_ADMA_STAT_CPBERR = (1 << 4), | |
159 | NV_ADMA_STAT_SERROR = (1 << 5), | |
160 | NV_ADMA_STAT_CMD_COMPLETE = (1 << 6), | |
161 | NV_ADMA_STAT_IDLE = (1 << 8), | |
162 | NV_ADMA_STAT_LEGACY = (1 << 9), | |
163 | NV_ADMA_STAT_STOPPED = (1 << 10), | |
164 | NV_ADMA_STAT_DONE = (1 << 12), | |
165 | NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR | | |
166 | NV_ADMA_STAT_TIMEOUT, | |
167 | ||
168 | /* port flags */ | |
169 | NV_ADMA_PORT_REGISTER_MODE = (1 << 0), | |
2dec7555 | 170 | NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1), |
fbbb262d RH |
171 | |
172 | }; | |
173 | ||
174 | /* ADMA Physical Region Descriptor - one SG segment */ | |
175 | struct nv_adma_prd { | |
176 | __le64 addr; | |
177 | __le32 len; | |
178 | u8 flags; | |
179 | u8 packet_len; | |
180 | __le16 reserved; | |
181 | }; | |
182 | ||
183 | enum nv_adma_regbits { | |
184 | CMDEND = (1 << 15), /* end of command list */ | |
185 | WNB = (1 << 14), /* wait-not-BSY */ | |
186 | IGN = (1 << 13), /* ignore this entry */ | |
187 | CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */ | |
188 | DA2 = (1 << (2 + 8)), | |
189 | DA1 = (1 << (1 + 8)), | |
190 | DA0 = (1 << (0 + 8)), | |
191 | }; | |
192 | ||
193 | /* ADMA Command Parameter Block | |
194 | The first 5 SG segments are stored inside the Command Parameter Block itself. | |
195 | If there are more than 5 segments the remainder are stored in a separate | |
196 | memory area indicated by next_aprd. */ | |
197 | struct nv_adma_cpb { | |
198 | u8 resp_flags; /* 0 */ | |
199 | u8 reserved1; /* 1 */ | |
200 | u8 ctl_flags; /* 2 */ | |
201 | /* len is length of taskfile in 64 bit words */ | |
202 | u8 len; /* 3 */ | |
203 | u8 tag; /* 4 */ | |
204 | u8 next_cpb_idx; /* 5 */ | |
205 | __le16 reserved2; /* 6-7 */ | |
206 | __le16 tf[12]; /* 8-31 */ | |
207 | struct nv_adma_prd aprd[5]; /* 32-111 */ | |
208 | __le64 next_aprd; /* 112-119 */ | |
209 | __le64 reserved3; /* 120-127 */ | |
10ad05df | 210 | }; |
1da177e4 | 211 | |
fbbb262d RH |
212 | |
213 | struct nv_adma_port_priv { | |
214 | struct nv_adma_cpb *cpb; | |
215 | dma_addr_t cpb_dma; | |
216 | struct nv_adma_prd *aprd; | |
217 | dma_addr_t aprd_dma; | |
cdf56bcf RH |
218 | void __iomem * ctl_block; |
219 | void __iomem * gen_block; | |
220 | void __iomem * notifier_clear_block; | |
fbbb262d | 221 | u8 flags; |
5e5c74a5 | 222 | int last_issue_ncq; |
fbbb262d RH |
223 | }; |
224 | ||
cdf56bcf RH |
225 | struct nv_host_priv { |
226 | unsigned long type; | |
227 | }; | |
228 | ||
fbbb262d RH |
229 | #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT))))) |
230 | ||
1da177e4 | 231 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
438ac6d5 | 232 | #ifdef CONFIG_PM |
cdf56bcf | 233 | static int nv_pci_device_resume(struct pci_dev *pdev); |
438ac6d5 | 234 | #endif |
cca3974e | 235 | static void nv_ck804_host_stop(struct ata_host *host); |
7d12e780 DH |
236 | static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance); |
237 | static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance); | |
238 | static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance); | |
da3dbb17 TH |
239 | static int nv_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val); |
240 | static int nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 241 | |
39f87582 TH |
242 | static void nv_nf2_freeze(struct ata_port *ap); |
243 | static void nv_nf2_thaw(struct ata_port *ap); | |
244 | static void nv_ck804_freeze(struct ata_port *ap); | |
245 | static void nv_ck804_thaw(struct ata_port *ap); | |
246 | static void nv_error_handler(struct ata_port *ap); | |
fbbb262d | 247 | static int nv_adma_slave_config(struct scsi_device *sdev); |
2dec7555 | 248 | static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc); |
fbbb262d RH |
249 | static void nv_adma_qc_prep(struct ata_queued_cmd *qc); |
250 | static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc); | |
251 | static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance); | |
252 | static void nv_adma_irq_clear(struct ata_port *ap); | |
253 | static int nv_adma_port_start(struct ata_port *ap); | |
254 | static void nv_adma_port_stop(struct ata_port *ap); | |
438ac6d5 | 255 | #ifdef CONFIG_PM |
cdf56bcf RH |
256 | static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg); |
257 | static int nv_adma_port_resume(struct ata_port *ap); | |
438ac6d5 | 258 | #endif |
53014e25 RH |
259 | static void nv_adma_freeze(struct ata_port *ap); |
260 | static void nv_adma_thaw(struct ata_port *ap); | |
fbbb262d RH |
261 | static void nv_adma_error_handler(struct ata_port *ap); |
262 | static void nv_adma_host_stop(struct ata_host *host); | |
f5ecac2d | 263 | static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc); |
f2fb344b | 264 | static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
39f87582 | 265 | |
1da177e4 LT |
266 | enum nv_host_type |
267 | { | |
268 | GENERIC, | |
269 | NFORCE2, | |
27e4b274 | 270 | NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ |
fbbb262d RH |
271 | CK804, |
272 | ADMA | |
1da177e4 LT |
273 | }; |
274 | ||
3b7d697d | 275 | static const struct pci_device_id nv_pci_tbl[] = { |
54bb3a94 JG |
276 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 }, |
277 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 }, | |
278 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 }, | |
279 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 }, | |
280 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 }, | |
281 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 }, | |
282 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 }, | |
283 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC }, | |
284 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC }, | |
285 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC }, | |
286 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC }, | |
287 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC }, | |
288 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC }, | |
289 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC }, | |
2d2744fc JG |
290 | |
291 | { } /* terminate list */ | |
1da177e4 LT |
292 | }; |
293 | ||
1da177e4 LT |
294 | static struct pci_driver nv_pci_driver = { |
295 | .name = DRV_NAME, | |
296 | .id_table = nv_pci_tbl, | |
297 | .probe = nv_init_one, | |
438ac6d5 | 298 | #ifdef CONFIG_PM |
cdf56bcf RH |
299 | .suspend = ata_pci_device_suspend, |
300 | .resume = nv_pci_device_resume, | |
438ac6d5 | 301 | #endif |
1daf9ce7 | 302 | .remove = ata_pci_remove_one, |
1da177e4 LT |
303 | }; |
304 | ||
193515d5 | 305 | static struct scsi_host_template nv_sht = { |
1da177e4 LT |
306 | .module = THIS_MODULE, |
307 | .name = DRV_NAME, | |
308 | .ioctl = ata_scsi_ioctl, | |
309 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
310 | .can_queue = ATA_DEF_QUEUE, |
311 | .this_id = ATA_SHT_THIS_ID, | |
312 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
313 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
314 | .emulated = ATA_SHT_EMULATED, | |
315 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
316 | .proc_name = DRV_NAME, | |
317 | .dma_boundary = ATA_DMA_BOUNDARY, | |
318 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 319 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 320 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
321 | }; |
322 | ||
fbbb262d RH |
323 | static struct scsi_host_template nv_adma_sht = { |
324 | .module = THIS_MODULE, | |
325 | .name = DRV_NAME, | |
326 | .ioctl = ata_scsi_ioctl, | |
327 | .queuecommand = ata_scsi_queuecmd, | |
1e0b5ab8 | 328 | .change_queue_depth = ata_scsi_change_queue_depth, |
fbbb262d RH |
329 | .can_queue = NV_ADMA_MAX_CPBS, |
330 | .this_id = ATA_SHT_THIS_ID, | |
331 | .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN, | |
fbbb262d RH |
332 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
333 | .emulated = ATA_SHT_EMULATED, | |
334 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
335 | .proc_name = DRV_NAME, | |
336 | .dma_boundary = NV_ADMA_DMA_BOUNDARY, | |
337 | .slave_configure = nv_adma_slave_config, | |
338 | .slave_destroy = ata_scsi_slave_destroy, | |
339 | .bios_param = ata_std_bios_param, | |
340 | }; | |
341 | ||
ada364e8 | 342 | static const struct ata_port_operations nv_generic_ops = { |
1da177e4 LT |
343 | .tf_load = ata_tf_load, |
344 | .tf_read = ata_tf_read, | |
345 | .exec_command = ata_exec_command, | |
346 | .check_status = ata_check_status, | |
347 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
348 | .bmdma_setup = ata_bmdma_setup, |
349 | .bmdma_start = ata_bmdma_start, | |
350 | .bmdma_stop = ata_bmdma_stop, | |
351 | .bmdma_status = ata_bmdma_status, | |
352 | .qc_prep = ata_qc_prep, | |
353 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
354 | .freeze = ata_bmdma_freeze, |
355 | .thaw = ata_bmdma_thaw, | |
356 | .error_handler = nv_error_handler, | |
357 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
0d5ff566 | 358 | .data_xfer = ata_data_xfer, |
1da177e4 | 359 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 360 | .irq_on = ata_irq_on, |
1da177e4 LT |
361 | .scr_read = nv_scr_read, |
362 | .scr_write = nv_scr_write, | |
363 | .port_start = ata_port_start, | |
1da177e4 LT |
364 | }; |
365 | ||
ada364e8 | 366 | static const struct ata_port_operations nv_nf2_ops = { |
ada364e8 TH |
367 | .tf_load = ata_tf_load, |
368 | .tf_read = ata_tf_read, | |
369 | .exec_command = ata_exec_command, | |
370 | .check_status = ata_check_status, | |
371 | .dev_select = ata_std_dev_select, | |
ada364e8 TH |
372 | .bmdma_setup = ata_bmdma_setup, |
373 | .bmdma_start = ata_bmdma_start, | |
374 | .bmdma_stop = ata_bmdma_stop, | |
375 | .bmdma_status = ata_bmdma_status, | |
376 | .qc_prep = ata_qc_prep, | |
377 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
378 | .freeze = nv_nf2_freeze, |
379 | .thaw = nv_nf2_thaw, | |
380 | .error_handler = nv_error_handler, | |
381 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
0d5ff566 | 382 | .data_xfer = ata_data_xfer, |
ada364e8 | 383 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 384 | .irq_on = ata_irq_on, |
ada364e8 TH |
385 | .scr_read = nv_scr_read, |
386 | .scr_write = nv_scr_write, | |
387 | .port_start = ata_port_start, | |
ada364e8 TH |
388 | }; |
389 | ||
390 | static const struct ata_port_operations nv_ck804_ops = { | |
ada364e8 TH |
391 | .tf_load = ata_tf_load, |
392 | .tf_read = ata_tf_read, | |
393 | .exec_command = ata_exec_command, | |
394 | .check_status = ata_check_status, | |
395 | .dev_select = ata_std_dev_select, | |
ada364e8 TH |
396 | .bmdma_setup = ata_bmdma_setup, |
397 | .bmdma_start = ata_bmdma_start, | |
398 | .bmdma_stop = ata_bmdma_stop, | |
399 | .bmdma_status = ata_bmdma_status, | |
400 | .qc_prep = ata_qc_prep, | |
401 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
402 | .freeze = nv_ck804_freeze, |
403 | .thaw = nv_ck804_thaw, | |
404 | .error_handler = nv_error_handler, | |
405 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
0d5ff566 | 406 | .data_xfer = ata_data_xfer, |
ada364e8 | 407 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 408 | .irq_on = ata_irq_on, |
ada364e8 TH |
409 | .scr_read = nv_scr_read, |
410 | .scr_write = nv_scr_write, | |
411 | .port_start = ata_port_start, | |
ada364e8 TH |
412 | .host_stop = nv_ck804_host_stop, |
413 | }; | |
414 | ||
fbbb262d | 415 | static const struct ata_port_operations nv_adma_ops = { |
fbbb262d | 416 | .tf_load = ata_tf_load, |
f2fb344b | 417 | .tf_read = nv_adma_tf_read, |
2dec7555 | 418 | .check_atapi_dma = nv_adma_check_atapi_dma, |
fbbb262d RH |
419 | .exec_command = ata_exec_command, |
420 | .check_status = ata_check_status, | |
421 | .dev_select = ata_std_dev_select, | |
f5ecac2d RH |
422 | .bmdma_setup = ata_bmdma_setup, |
423 | .bmdma_start = ata_bmdma_start, | |
424 | .bmdma_stop = ata_bmdma_stop, | |
425 | .bmdma_status = ata_bmdma_status, | |
fbbb262d RH |
426 | .qc_prep = nv_adma_qc_prep, |
427 | .qc_issue = nv_adma_qc_issue, | |
53014e25 RH |
428 | .freeze = nv_adma_freeze, |
429 | .thaw = nv_adma_thaw, | |
fbbb262d | 430 | .error_handler = nv_adma_error_handler, |
f5ecac2d | 431 | .post_internal_cmd = nv_adma_post_internal_cmd, |
0d5ff566 | 432 | .data_xfer = ata_data_xfer, |
fbbb262d | 433 | .irq_clear = nv_adma_irq_clear, |
246ce3b6 | 434 | .irq_on = ata_irq_on, |
fbbb262d RH |
435 | .scr_read = nv_scr_read, |
436 | .scr_write = nv_scr_write, | |
437 | .port_start = nv_adma_port_start, | |
438 | .port_stop = nv_adma_port_stop, | |
438ac6d5 | 439 | #ifdef CONFIG_PM |
cdf56bcf RH |
440 | .port_suspend = nv_adma_port_suspend, |
441 | .port_resume = nv_adma_port_resume, | |
438ac6d5 | 442 | #endif |
fbbb262d RH |
443 | .host_stop = nv_adma_host_stop, |
444 | }; | |
445 | ||
1626aeb8 | 446 | static const struct ata_port_info nv_port_info[] = { |
ada364e8 TH |
447 | /* generic */ |
448 | { | |
449 | .sht = &nv_sht, | |
0c88758b TH |
450 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
451 | .link_flags = ATA_LFLAG_HRST_TO_RESUME, | |
ada364e8 TH |
452 | .pio_mask = NV_PIO_MASK, |
453 | .mwdma_mask = NV_MWDMA_MASK, | |
454 | .udma_mask = NV_UDMA_MASK, | |
455 | .port_ops = &nv_generic_ops, | |
9a829ccf | 456 | .irq_handler = nv_generic_interrupt, |
ada364e8 TH |
457 | }, |
458 | /* nforce2/3 */ | |
459 | { | |
460 | .sht = &nv_sht, | |
0c88758b TH |
461 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
462 | .link_flags = ATA_LFLAG_HRST_TO_RESUME, | |
ada364e8 TH |
463 | .pio_mask = NV_PIO_MASK, |
464 | .mwdma_mask = NV_MWDMA_MASK, | |
465 | .udma_mask = NV_UDMA_MASK, | |
466 | .port_ops = &nv_nf2_ops, | |
9a829ccf | 467 | .irq_handler = nv_nf2_interrupt, |
ada364e8 TH |
468 | }, |
469 | /* ck804 */ | |
470 | { | |
471 | .sht = &nv_sht, | |
0c88758b TH |
472 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
473 | .link_flags = ATA_LFLAG_HRST_TO_RESUME, | |
ada364e8 TH |
474 | .pio_mask = NV_PIO_MASK, |
475 | .mwdma_mask = NV_MWDMA_MASK, | |
476 | .udma_mask = NV_UDMA_MASK, | |
477 | .port_ops = &nv_ck804_ops, | |
9a829ccf | 478 | .irq_handler = nv_ck804_interrupt, |
ada364e8 | 479 | }, |
fbbb262d RH |
480 | /* ADMA */ |
481 | { | |
482 | .sht = &nv_adma_sht, | |
483 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
484 | ATA_FLAG_MMIO | ATA_FLAG_NCQ, | |
0c88758b | 485 | .link_flags = ATA_LFLAG_HRST_TO_RESUME, |
fbbb262d RH |
486 | .pio_mask = NV_PIO_MASK, |
487 | .mwdma_mask = NV_MWDMA_MASK, | |
488 | .udma_mask = NV_UDMA_MASK, | |
489 | .port_ops = &nv_adma_ops, | |
9a829ccf | 490 | .irq_handler = nv_adma_interrupt, |
fbbb262d | 491 | }, |
1da177e4 LT |
492 | }; |
493 | ||
494 | MODULE_AUTHOR("NVIDIA"); | |
495 | MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller"); | |
496 | MODULE_LICENSE("GPL"); | |
497 | MODULE_DEVICE_TABLE(pci, nv_pci_tbl); | |
498 | MODULE_VERSION(DRV_VERSION); | |
499 | ||
fbbb262d RH |
500 | static int adma_enabled = 1; |
501 | ||
2dec7555 RH |
502 | static void nv_adma_register_mode(struct ata_port *ap) |
503 | { | |
2dec7555 | 504 | struct nv_adma_port_priv *pp = ap->private_data; |
cdf56bcf | 505 | void __iomem *mmio = pp->ctl_block; |
a2cfe81a RH |
506 | u16 tmp, status; |
507 | int count = 0; | |
2dec7555 RH |
508 | |
509 | if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) | |
510 | return; | |
511 | ||
a2cfe81a RH |
512 | status = readw(mmio + NV_ADMA_STAT); |
513 | while(!(status & NV_ADMA_STAT_IDLE) && count < 20) { | |
514 | ndelay(50); | |
515 | status = readw(mmio + NV_ADMA_STAT); | |
516 | count++; | |
517 | } | |
518 | if(count == 20) | |
519 | ata_port_printk(ap, KERN_WARNING, | |
520 | "timeout waiting for ADMA IDLE, stat=0x%hx\n", | |
521 | status); | |
522 | ||
2dec7555 RH |
523 | tmp = readw(mmio + NV_ADMA_CTL); |
524 | writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); | |
525 | ||
a2cfe81a RH |
526 | count = 0; |
527 | status = readw(mmio + NV_ADMA_STAT); | |
528 | while(!(status & NV_ADMA_STAT_LEGACY) && count < 20) { | |
529 | ndelay(50); | |
530 | status = readw(mmio + NV_ADMA_STAT); | |
531 | count++; | |
532 | } | |
533 | if(count == 20) | |
534 | ata_port_printk(ap, KERN_WARNING, | |
535 | "timeout waiting for ADMA LEGACY, stat=0x%hx\n", | |
536 | status); | |
537 | ||
2dec7555 RH |
538 | pp->flags |= NV_ADMA_PORT_REGISTER_MODE; |
539 | } | |
540 | ||
541 | static void nv_adma_mode(struct ata_port *ap) | |
542 | { | |
2dec7555 | 543 | struct nv_adma_port_priv *pp = ap->private_data; |
cdf56bcf | 544 | void __iomem *mmio = pp->ctl_block; |
a2cfe81a RH |
545 | u16 tmp, status; |
546 | int count = 0; | |
2dec7555 RH |
547 | |
548 | if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) | |
549 | return; | |
f20b16ff | 550 | |
2dec7555 RH |
551 | WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE); |
552 | ||
553 | tmp = readw(mmio + NV_ADMA_CTL); | |
554 | writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); | |
555 | ||
a2cfe81a RH |
556 | status = readw(mmio + NV_ADMA_STAT); |
557 | while(((status & NV_ADMA_STAT_LEGACY) || | |
558 | !(status & NV_ADMA_STAT_IDLE)) && count < 20) { | |
559 | ndelay(50); | |
560 | status = readw(mmio + NV_ADMA_STAT); | |
561 | count++; | |
562 | } | |
563 | if(count == 20) | |
564 | ata_port_printk(ap, KERN_WARNING, | |
565 | "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n", | |
566 | status); | |
567 | ||
2dec7555 RH |
568 | pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE; |
569 | } | |
570 | ||
fbbb262d RH |
571 | static int nv_adma_slave_config(struct scsi_device *sdev) |
572 | { | |
573 | struct ata_port *ap = ata_shost_to_port(sdev->host); | |
2dec7555 RH |
574 | struct nv_adma_port_priv *pp = ap->private_data; |
575 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
fbbb262d RH |
576 | u64 bounce_limit; |
577 | unsigned long segment_boundary; | |
578 | unsigned short sg_tablesize; | |
579 | int rc; | |
2dec7555 RH |
580 | int adma_enable; |
581 | u32 current_reg, new_reg, config_mask; | |
fbbb262d RH |
582 | |
583 | rc = ata_scsi_slave_config(sdev); | |
584 | ||
585 | if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun) | |
586 | /* Not a proper libata device, ignore */ | |
587 | return rc; | |
588 | ||
9af5c9c9 | 589 | if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) { |
fbbb262d RH |
590 | /* |
591 | * NVIDIA reports that ADMA mode does not support ATAPI commands. | |
592 | * Therefore ATAPI commands are sent through the legacy interface. | |
593 | * However, the legacy interface only supports 32-bit DMA. | |
594 | * Restrict DMA parameters as required by the legacy interface | |
595 | * when an ATAPI device is connected. | |
596 | */ | |
597 | bounce_limit = ATA_DMA_MASK; | |
598 | segment_boundary = ATA_DMA_BOUNDARY; | |
599 | /* Subtract 1 since an extra entry may be needed for padding, see | |
600 | libata-scsi.c */ | |
601 | sg_tablesize = LIBATA_MAX_PRD - 1; | |
f20b16ff | 602 | |
2dec7555 RH |
603 | /* Since the legacy DMA engine is in use, we need to disable ADMA |
604 | on the port. */ | |
605 | adma_enable = 0; | |
606 | nv_adma_register_mode(ap); | |
fbbb262d RH |
607 | } |
608 | else { | |
609 | bounce_limit = *ap->dev->dma_mask; | |
610 | segment_boundary = NV_ADMA_DMA_BOUNDARY; | |
611 | sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN; | |
2dec7555 | 612 | adma_enable = 1; |
fbbb262d | 613 | } |
f20b16ff | 614 | |
2dec7555 RH |
615 | pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, ¤t_reg); |
616 | ||
617 | if(ap->port_no == 1) | |
618 | config_mask = NV_MCP_SATA_CFG_20_PORT1_EN | | |
619 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN; | |
620 | else | |
621 | config_mask = NV_MCP_SATA_CFG_20_PORT0_EN | | |
622 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN; | |
f20b16ff | 623 | |
2dec7555 RH |
624 | if(adma_enable) { |
625 | new_reg = current_reg | config_mask; | |
626 | pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE; | |
627 | } | |
628 | else { | |
629 | new_reg = current_reg & ~config_mask; | |
630 | pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE; | |
631 | } | |
f20b16ff | 632 | |
2dec7555 RH |
633 | if(current_reg != new_reg) |
634 | pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg); | |
f20b16ff | 635 | |
fbbb262d RH |
636 | blk_queue_bounce_limit(sdev->request_queue, bounce_limit); |
637 | blk_queue_segment_boundary(sdev->request_queue, segment_boundary); | |
638 | blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize); | |
639 | ata_port_printk(ap, KERN_INFO, | |
640 | "bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n", | |
641 | (unsigned long long)bounce_limit, segment_boundary, sg_tablesize); | |
642 | return rc; | |
643 | } | |
644 | ||
2dec7555 RH |
645 | static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc) |
646 | { | |
647 | struct nv_adma_port_priv *pp = qc->ap->private_data; | |
648 | return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE); | |
649 | } | |
650 | ||
f2fb344b RH |
651 | static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
652 | { | |
653 | /* Since commands where a result TF is requested are not | |
654 | executed in ADMA mode, the only time this function will be called | |
655 | in ADMA mode will be if a command fails. In this case we | |
656 | don't care about going into register mode with ADMA commands | |
657 | pending, as the commands will all shortly be aborted anyway. */ | |
658 | nv_adma_register_mode(ap); | |
659 | ||
660 | ata_tf_read(ap, tf); | |
661 | } | |
662 | ||
2dec7555 | 663 | static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb) |
fbbb262d RH |
664 | { |
665 | unsigned int idx = 0; | |
666 | ||
ac3d6b86 RH |
667 | if(tf->flags & ATA_TFLAG_ISADDR) { |
668 | if (tf->flags & ATA_TFLAG_LBA48) { | |
669 | cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB); | |
670 | cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect); | |
671 | cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal); | |
672 | cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam); | |
673 | cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah); | |
674 | cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature); | |
675 | } else | |
676 | cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB); | |
a84471fe | 677 | |
ac3d6b86 RH |
678 | cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect); |
679 | cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal); | |
680 | cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam); | |
681 | cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah); | |
fbbb262d | 682 | } |
a84471fe | 683 | |
ac3d6b86 RH |
684 | if(tf->flags & ATA_TFLAG_DEVICE) |
685 | cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device); | |
fbbb262d RH |
686 | |
687 | cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND); | |
a84471fe | 688 | |
ac3d6b86 RH |
689 | while(idx < 12) |
690 | cpb[idx++] = cpu_to_le16(IGN); | |
fbbb262d RH |
691 | |
692 | return idx; | |
693 | } | |
694 | ||
5bd28a4b | 695 | static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err) |
fbbb262d RH |
696 | { |
697 | struct nv_adma_port_priv *pp = ap->private_data; | |
2dec7555 | 698 | u8 flags = pp->cpb[cpb_num].resp_flags; |
fbbb262d RH |
699 | |
700 | VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags); | |
701 | ||
5bd28a4b RH |
702 | if (unlikely((force_err || |
703 | flags & (NV_CPB_RESP_ATA_ERR | | |
704 | NV_CPB_RESP_CMD_ERR | | |
705 | NV_CPB_RESP_CPB_ERR)))) { | |
9af5c9c9 | 706 | struct ata_eh_info *ehi = &ap->link.eh_info; |
5bd28a4b RH |
707 | int freeze = 0; |
708 | ||
709 | ata_ehi_clear_desc(ehi); | |
b64bbc39 | 710 | __ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags ); |
5bd28a4b | 711 | if (flags & NV_CPB_RESP_ATA_ERR) { |
b64bbc39 | 712 | ata_ehi_push_desc(ehi, "ATA error"); |
5bd28a4b RH |
713 | ehi->err_mask |= AC_ERR_DEV; |
714 | } else if (flags & NV_CPB_RESP_CMD_ERR) { | |
b64bbc39 | 715 | ata_ehi_push_desc(ehi, "CMD error"); |
5bd28a4b RH |
716 | ehi->err_mask |= AC_ERR_DEV; |
717 | } else if (flags & NV_CPB_RESP_CPB_ERR) { | |
b64bbc39 | 718 | ata_ehi_push_desc(ehi, "CPB error"); |
5bd28a4b RH |
719 | ehi->err_mask |= AC_ERR_SYSTEM; |
720 | freeze = 1; | |
721 | } else { | |
722 | /* notifier error, but no error in CPB flags? */ | |
b64bbc39 | 723 | ata_ehi_push_desc(ehi, "unknown"); |
5bd28a4b RH |
724 | ehi->err_mask |= AC_ERR_OTHER; |
725 | freeze = 1; | |
726 | } | |
727 | /* Kill all commands. EH will determine what actually failed. */ | |
728 | if (freeze) | |
729 | ata_port_freeze(ap); | |
730 | else | |
731 | ata_port_abort(ap); | |
732 | return 1; | |
fbbb262d | 733 | } |
5bd28a4b | 734 | |
f2fb344b | 735 | if (likely(flags & NV_CPB_RESP_DONE)) { |
fbbb262d | 736 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num); |
5bd28a4b RH |
737 | VPRINTK("CPB flags done, flags=0x%x\n", flags); |
738 | if (likely(qc)) { | |
f2fb344b | 739 | DPRINTK("Completing qc from tag %d\n",cpb_num); |
fbbb262d | 740 | ata_qc_complete(qc); |
2a54cf76 | 741 | } else { |
9af5c9c9 | 742 | struct ata_eh_info *ehi = &ap->link.eh_info; |
2a54cf76 RH |
743 | /* Notifier bits set without a command may indicate the drive |
744 | is misbehaving. Raise host state machine violation on this | |
745 | condition. */ | |
746 | ata_port_printk(ap, KERN_ERR, "notifier for tag %d with no command?\n", | |
747 | cpb_num); | |
748 | ehi->err_mask |= AC_ERR_HSM; | |
749 | ehi->action |= ATA_EH_SOFTRESET; | |
750 | ata_port_freeze(ap); | |
751 | return 1; | |
fbbb262d RH |
752 | } |
753 | } | |
5bd28a4b | 754 | return 0; |
fbbb262d RH |
755 | } |
756 | ||
2dec7555 RH |
757 | static int nv_host_intr(struct ata_port *ap, u8 irq_stat) |
758 | { | |
9af5c9c9 | 759 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); |
2dec7555 RH |
760 | |
761 | /* freeze if hotplugged */ | |
762 | if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) { | |
763 | ata_port_freeze(ap); | |
764 | return 1; | |
765 | } | |
766 | ||
767 | /* bail out if not our interrupt */ | |
768 | if (!(irq_stat & NV_INT_DEV)) | |
769 | return 0; | |
770 | ||
771 | /* DEV interrupt w/ no active qc? */ | |
772 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { | |
773 | ata_check_status(ap); | |
774 | return 1; | |
775 | } | |
776 | ||
777 | /* handle interrupt */ | |
f740d168 | 778 | return ata_host_intr(ap, qc); |
2dec7555 RH |
779 | } |
780 | ||
fbbb262d RH |
781 | static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance) |
782 | { | |
783 | struct ata_host *host = dev_instance; | |
784 | int i, handled = 0; | |
2dec7555 | 785 | u32 notifier_clears[2]; |
fbbb262d RH |
786 | |
787 | spin_lock(&host->lock); | |
788 | ||
789 | for (i = 0; i < host->n_ports; i++) { | |
790 | struct ata_port *ap = host->ports[i]; | |
2dec7555 | 791 | notifier_clears[i] = 0; |
fbbb262d RH |
792 | |
793 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { | |
794 | struct nv_adma_port_priv *pp = ap->private_data; | |
cdf56bcf | 795 | void __iomem *mmio = pp->ctl_block; |
fbbb262d RH |
796 | u16 status; |
797 | u32 gen_ctl; | |
fbbb262d | 798 | u32 notifier, notifier_error; |
a617c09f | 799 | |
53014e25 RH |
800 | /* if ADMA is disabled, use standard ata interrupt handler */ |
801 | if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) { | |
802 | u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804) | |
803 | >> (NV_INT_PORT_SHIFT * i); | |
804 | handled += nv_host_intr(ap, irq_stat); | |
805 | continue; | |
806 | } | |
fbbb262d | 807 | |
53014e25 | 808 | /* if in ATA register mode, check for standard interrupts */ |
fbbb262d | 809 | if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) { |
0d5ff566 | 810 | u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804) |
2dec7555 | 811 | >> (NV_INT_PORT_SHIFT * i); |
9af5c9c9 | 812 | if(ata_tag_valid(ap->link.active_tag)) |
f740d168 RH |
813 | /** NV_INT_DEV indication seems unreliable at times |
814 | at least in ADMA mode. Force it on always when a | |
815 | command is active, to prevent losing interrupts. */ | |
816 | irq_stat |= NV_INT_DEV; | |
2dec7555 | 817 | handled += nv_host_intr(ap, irq_stat); |
fbbb262d RH |
818 | } |
819 | ||
820 | notifier = readl(mmio + NV_ADMA_NOTIFIER); | |
821 | notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); | |
2dec7555 | 822 | notifier_clears[i] = notifier | notifier_error; |
fbbb262d | 823 | |
cdf56bcf | 824 | gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); |
fbbb262d | 825 | |
fbbb262d RH |
826 | if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier && |
827 | !notifier_error) | |
828 | /* Nothing to do */ | |
829 | continue; | |
830 | ||
831 | status = readw(mmio + NV_ADMA_STAT); | |
832 | ||
833 | /* Clear status. Ensure the controller sees the clearing before we start | |
834 | looking at any of the CPB statuses, so that any CPB completions after | |
835 | this point in the handler will raise another interrupt. */ | |
836 | writew(status, mmio + NV_ADMA_STAT); | |
837 | readw(mmio + NV_ADMA_STAT); /* flush posted write */ | |
838 | rmb(); | |
839 | ||
5bd28a4b RH |
840 | handled++; /* irq handled if we got here */ |
841 | ||
842 | /* freeze if hotplugged or controller error */ | |
843 | if (unlikely(status & (NV_ADMA_STAT_HOTPLUG | | |
844 | NV_ADMA_STAT_HOTUNPLUG | | |
5278b50c RH |
845 | NV_ADMA_STAT_TIMEOUT | |
846 | NV_ADMA_STAT_SERROR))) { | |
9af5c9c9 | 847 | struct ata_eh_info *ehi = &ap->link.eh_info; |
5bd28a4b RH |
848 | |
849 | ata_ehi_clear_desc(ehi); | |
b64bbc39 | 850 | __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status ); |
5bd28a4b RH |
851 | if (status & NV_ADMA_STAT_TIMEOUT) { |
852 | ehi->err_mask |= AC_ERR_SYSTEM; | |
b64bbc39 | 853 | ata_ehi_push_desc(ehi, "timeout"); |
5bd28a4b RH |
854 | } else if (status & NV_ADMA_STAT_HOTPLUG) { |
855 | ata_ehi_hotplugged(ehi); | |
b64bbc39 | 856 | ata_ehi_push_desc(ehi, "hotplug"); |
5bd28a4b RH |
857 | } else if (status & NV_ADMA_STAT_HOTUNPLUG) { |
858 | ata_ehi_hotplugged(ehi); | |
b64bbc39 | 859 | ata_ehi_push_desc(ehi, "hot unplug"); |
5278b50c RH |
860 | } else if (status & NV_ADMA_STAT_SERROR) { |
861 | /* let libata analyze SError and figure out the cause */ | |
b64bbc39 TH |
862 | ata_ehi_push_desc(ehi, "SError"); |
863 | } else | |
864 | ata_ehi_push_desc(ehi, "unknown"); | |
fbbb262d | 865 | ata_port_freeze(ap); |
fbbb262d RH |
866 | continue; |
867 | } | |
868 | ||
5bd28a4b RH |
869 | if (status & (NV_ADMA_STAT_DONE | |
870 | NV_ADMA_STAT_CPBERR)) { | |
8ba5e4cb | 871 | u32 check_commands; |
721449bf | 872 | int pos, error = 0; |
8ba5e4cb | 873 | |
9af5c9c9 TH |
874 | if(ata_tag_valid(ap->link.active_tag)) |
875 | check_commands = 1 << ap->link.active_tag; | |
8ba5e4cb | 876 | else |
9af5c9c9 | 877 | check_commands = ap->link.sactive; |
8ba5e4cb | 878 | |
fbbb262d | 879 | /** Check CPBs for completed commands */ |
721449bf RH |
880 | while ((pos = ffs(check_commands)) && !error) { |
881 | pos--; | |
882 | error = nv_adma_check_cpb(ap, pos, | |
883 | notifier_error & (1 << pos) ); | |
884 | check_commands &= ~(1 << pos ); | |
fbbb262d RH |
885 | } |
886 | } | |
fbbb262d RH |
887 | } |
888 | } | |
f20b16ff | 889 | |
2dec7555 RH |
890 | if(notifier_clears[0] || notifier_clears[1]) { |
891 | /* Note: Both notifier clear registers must be written | |
892 | if either is set, even if one is zero, according to NVIDIA. */ | |
cdf56bcf RH |
893 | struct nv_adma_port_priv *pp = host->ports[0]->private_data; |
894 | writel(notifier_clears[0], pp->notifier_clear_block); | |
895 | pp = host->ports[1]->private_data; | |
896 | writel(notifier_clears[1], pp->notifier_clear_block); | |
2dec7555 | 897 | } |
fbbb262d RH |
898 | |
899 | spin_unlock(&host->lock); | |
900 | ||
901 | return IRQ_RETVAL(handled); | |
902 | } | |
903 | ||
53014e25 RH |
904 | static void nv_adma_freeze(struct ata_port *ap) |
905 | { | |
906 | struct nv_adma_port_priv *pp = ap->private_data; | |
907 | void __iomem *mmio = pp->ctl_block; | |
908 | u16 tmp; | |
909 | ||
910 | nv_ck804_freeze(ap); | |
911 | ||
912 | if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) | |
913 | return; | |
914 | ||
915 | /* clear any outstanding CK804 notifications */ | |
916 | writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT), | |
917 | ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); | |
918 | ||
919 | /* Disable interrupt */ | |
920 | tmp = readw(mmio + NV_ADMA_CTL); | |
921 | writew( tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN), | |
922 | mmio + NV_ADMA_CTL); | |
923 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | |
924 | } | |
925 | ||
926 | static void nv_adma_thaw(struct ata_port *ap) | |
927 | { | |
928 | struct nv_adma_port_priv *pp = ap->private_data; | |
929 | void __iomem *mmio = pp->ctl_block; | |
930 | u16 tmp; | |
931 | ||
932 | nv_ck804_thaw(ap); | |
933 | ||
934 | if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) | |
935 | return; | |
936 | ||
937 | /* Enable interrupt */ | |
938 | tmp = readw(mmio + NV_ADMA_CTL); | |
939 | writew( tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN), | |
940 | mmio + NV_ADMA_CTL); | |
941 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | |
942 | } | |
943 | ||
fbbb262d RH |
944 | static void nv_adma_irq_clear(struct ata_port *ap) |
945 | { | |
cdf56bcf RH |
946 | struct nv_adma_port_priv *pp = ap->private_data; |
947 | void __iomem *mmio = pp->ctl_block; | |
53014e25 | 948 | u32 notifier_clears[2]; |
fbbb262d | 949 | |
53014e25 RH |
950 | if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) { |
951 | ata_bmdma_irq_clear(ap); | |
952 | return; | |
953 | } | |
954 | ||
955 | /* clear any outstanding CK804 notifications */ | |
956 | writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT), | |
957 | ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); | |
fbbb262d | 958 | |
53014e25 RH |
959 | /* clear ADMA status */ |
960 | writew(0xffff, mmio + NV_ADMA_STAT); | |
a617c09f | 961 | |
53014e25 RH |
962 | /* clear notifiers - note both ports need to be written with |
963 | something even though we are only clearing on one */ | |
964 | if (ap->port_no == 0) { | |
965 | notifier_clears[0] = 0xFFFFFFFF; | |
966 | notifier_clears[1] = 0; | |
967 | } else { | |
968 | notifier_clears[0] = 0; | |
969 | notifier_clears[1] = 0xFFFFFFFF; | |
970 | } | |
971 | pp = ap->host->ports[0]->private_data; | |
972 | writel(notifier_clears[0], pp->notifier_clear_block); | |
973 | pp = ap->host->ports[1]->private_data; | |
974 | writel(notifier_clears[1], pp->notifier_clear_block); | |
fbbb262d RH |
975 | } |
976 | ||
f5ecac2d | 977 | static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc) |
fbbb262d | 978 | { |
f5ecac2d | 979 | struct nv_adma_port_priv *pp = qc->ap->private_data; |
fbbb262d | 980 | |
f5ecac2d RH |
981 | if(pp->flags & NV_ADMA_PORT_REGISTER_MODE) |
982 | ata_bmdma_post_internal_cmd(qc); | |
fbbb262d RH |
983 | } |
984 | ||
985 | static int nv_adma_port_start(struct ata_port *ap) | |
986 | { | |
987 | struct device *dev = ap->host->dev; | |
988 | struct nv_adma_port_priv *pp; | |
989 | int rc; | |
990 | void *mem; | |
991 | dma_addr_t mem_dma; | |
cdf56bcf | 992 | void __iomem *mmio; |
fbbb262d RH |
993 | u16 tmp; |
994 | ||
995 | VPRINTK("ENTER\n"); | |
996 | ||
997 | rc = ata_port_start(ap); | |
998 | if (rc) | |
999 | return rc; | |
1000 | ||
24dc5f33 TH |
1001 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
1002 | if (!pp) | |
1003 | return -ENOMEM; | |
fbbb262d | 1004 | |
0d5ff566 | 1005 | mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT + |
cdf56bcf RH |
1006 | ap->port_no * NV_ADMA_PORT_SIZE; |
1007 | pp->ctl_block = mmio; | |
0d5ff566 | 1008 | pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN; |
cdf56bcf RH |
1009 | pp->notifier_clear_block = pp->gen_block + |
1010 | NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no); | |
1011 | ||
24dc5f33 TH |
1012 | mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ, |
1013 | &mem_dma, GFP_KERNEL); | |
1014 | if (!mem) | |
1015 | return -ENOMEM; | |
fbbb262d RH |
1016 | memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ); |
1017 | ||
1018 | /* | |
1019 | * First item in chunk of DMA memory: | |
1020 | * 128-byte command parameter block (CPB) | |
1021 | * one for each command tag | |
1022 | */ | |
1023 | pp->cpb = mem; | |
1024 | pp->cpb_dma = mem_dma; | |
1025 | ||
1026 | writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW); | |
1027 | writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH); | |
1028 | ||
1029 | mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ; | |
1030 | mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ; | |
1031 | ||
1032 | /* | |
1033 | * Second item: block of ADMA_SGTBL_LEN s/g entries | |
1034 | */ | |
1035 | pp->aprd = mem; | |
1036 | pp->aprd_dma = mem_dma; | |
1037 | ||
1038 | ap->private_data = pp; | |
1039 | ||
1040 | /* clear any outstanding interrupt conditions */ | |
1041 | writew(0xffff, mmio + NV_ADMA_STAT); | |
1042 | ||
1043 | /* initialize port variables */ | |
1044 | pp->flags = NV_ADMA_PORT_REGISTER_MODE; | |
1045 | ||
1046 | /* clear CPB fetch count */ | |
1047 | writew(0, mmio + NV_ADMA_CPB_COUNT); | |
1048 | ||
cdf56bcf | 1049 | /* clear GO for register mode, enable interrupt */ |
fbbb262d | 1050 | tmp = readw(mmio + NV_ADMA_CTL); |
5ce0cf6f RH |
1051 | writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | |
1052 | NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); | |
fbbb262d RH |
1053 | |
1054 | tmp = readw(mmio + NV_ADMA_CTL); | |
1055 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | |
5ce0cf6f | 1056 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
fbbb262d RH |
1057 | udelay(1); |
1058 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | |
5ce0cf6f | 1059 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
fbbb262d RH |
1060 | |
1061 | return 0; | |
fbbb262d RH |
1062 | } |
1063 | ||
1064 | static void nv_adma_port_stop(struct ata_port *ap) | |
1065 | { | |
fbbb262d | 1066 | struct nv_adma_port_priv *pp = ap->private_data; |
cdf56bcf | 1067 | void __iomem *mmio = pp->ctl_block; |
fbbb262d RH |
1068 | |
1069 | VPRINTK("ENTER\n"); | |
fbbb262d | 1070 | writew(0, mmio + NV_ADMA_CTL); |
fbbb262d RH |
1071 | } |
1072 | ||
438ac6d5 | 1073 | #ifdef CONFIG_PM |
cdf56bcf RH |
1074 | static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1075 | { | |
1076 | struct nv_adma_port_priv *pp = ap->private_data; | |
1077 | void __iomem *mmio = pp->ctl_block; | |
1078 | ||
1079 | /* Go to register mode - clears GO */ | |
1080 | nv_adma_register_mode(ap); | |
1081 | ||
1082 | /* clear CPB fetch count */ | |
1083 | writew(0, mmio + NV_ADMA_CPB_COUNT); | |
1084 | ||
1085 | /* disable interrupt, shut down port */ | |
1086 | writew(0, mmio + NV_ADMA_CTL); | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | static int nv_adma_port_resume(struct ata_port *ap) | |
1092 | { | |
1093 | struct nv_adma_port_priv *pp = ap->private_data; | |
1094 | void __iomem *mmio = pp->ctl_block; | |
1095 | u16 tmp; | |
1096 | ||
1097 | /* set CPB block location */ | |
1098 | writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW); | |
1099 | writel((pp->cpb_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH); | |
1100 | ||
1101 | /* clear any outstanding interrupt conditions */ | |
1102 | writew(0xffff, mmio + NV_ADMA_STAT); | |
1103 | ||
1104 | /* initialize port variables */ | |
1105 | pp->flags |= NV_ADMA_PORT_REGISTER_MODE; | |
1106 | ||
1107 | /* clear CPB fetch count */ | |
1108 | writew(0, mmio + NV_ADMA_CPB_COUNT); | |
1109 | ||
1110 | /* clear GO for register mode, enable interrupt */ | |
1111 | tmp = readw(mmio + NV_ADMA_CTL); | |
5ce0cf6f RH |
1112 | writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | |
1113 | NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); | |
cdf56bcf RH |
1114 | |
1115 | tmp = readw(mmio + NV_ADMA_CTL); | |
1116 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | |
5ce0cf6f | 1117 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
cdf56bcf RH |
1118 | udelay(1); |
1119 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | |
5ce0cf6f | 1120 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
cdf56bcf RH |
1121 | |
1122 | return 0; | |
1123 | } | |
438ac6d5 | 1124 | #endif |
fbbb262d | 1125 | |
9a829ccf | 1126 | static void nv_adma_setup_port(struct ata_port *ap) |
fbbb262d | 1127 | { |
9a829ccf TH |
1128 | void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; |
1129 | struct ata_ioports *ioport = &ap->ioaddr; | |
fbbb262d RH |
1130 | |
1131 | VPRINTK("ENTER\n"); | |
1132 | ||
9a829ccf | 1133 | mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE; |
fbbb262d | 1134 | |
0d5ff566 TH |
1135 | ioport->cmd_addr = mmio; |
1136 | ioport->data_addr = mmio + (ATA_REG_DATA * 4); | |
fbbb262d | 1137 | ioport->error_addr = |
0d5ff566 TH |
1138 | ioport->feature_addr = mmio + (ATA_REG_ERR * 4); |
1139 | ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4); | |
1140 | ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4); | |
1141 | ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4); | |
1142 | ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4); | |
1143 | ioport->device_addr = mmio + (ATA_REG_DEVICE * 4); | |
fbbb262d | 1144 | ioport->status_addr = |
0d5ff566 | 1145 | ioport->command_addr = mmio + (ATA_REG_STATUS * 4); |
fbbb262d | 1146 | ioport->altstatus_addr = |
0d5ff566 | 1147 | ioport->ctl_addr = mmio + 0x20; |
fbbb262d RH |
1148 | } |
1149 | ||
9a829ccf | 1150 | static int nv_adma_host_init(struct ata_host *host) |
fbbb262d | 1151 | { |
9a829ccf | 1152 | struct pci_dev *pdev = to_pci_dev(host->dev); |
fbbb262d RH |
1153 | unsigned int i; |
1154 | u32 tmp32; | |
1155 | ||
1156 | VPRINTK("ENTER\n"); | |
1157 | ||
1158 | /* enable ADMA on the ports */ | |
1159 | pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); | |
1160 | tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN | | |
1161 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN | | |
1162 | NV_MCP_SATA_CFG_20_PORT1_EN | | |
1163 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN; | |
1164 | ||
1165 | pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); | |
1166 | ||
9a829ccf TH |
1167 | for (i = 0; i < host->n_ports; i++) |
1168 | nv_adma_setup_port(host->ports[i]); | |
fbbb262d | 1169 | |
fbbb262d RH |
1170 | return 0; |
1171 | } | |
1172 | ||
1173 | static void nv_adma_fill_aprd(struct ata_queued_cmd *qc, | |
1174 | struct scatterlist *sg, | |
1175 | int idx, | |
1176 | struct nv_adma_prd *aprd) | |
1177 | { | |
41949ed5 | 1178 | u8 flags = 0; |
fbbb262d RH |
1179 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1180 | flags |= NV_APRD_WRITE; | |
1181 | if (idx == qc->n_elem - 1) | |
1182 | flags |= NV_APRD_END; | |
1183 | else if (idx != 4) | |
1184 | flags |= NV_APRD_CONT; | |
1185 | ||
1186 | aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg))); | |
1187 | aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */ | |
2dec7555 | 1188 | aprd->flags = flags; |
41949ed5 | 1189 | aprd->packet_len = 0; |
fbbb262d RH |
1190 | } |
1191 | ||
1192 | static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb) | |
1193 | { | |
1194 | struct nv_adma_port_priv *pp = qc->ap->private_data; | |
1195 | unsigned int idx; | |
1196 | struct nv_adma_prd *aprd; | |
1197 | struct scatterlist *sg; | |
1198 | ||
1199 | VPRINTK("ENTER\n"); | |
1200 | ||
1201 | idx = 0; | |
1202 | ||
1203 | ata_for_each_sg(sg, qc) { | |
1204 | aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)]; | |
1205 | nv_adma_fill_aprd(qc, sg, idx, aprd); | |
1206 | idx++; | |
1207 | } | |
1208 | if (idx > 5) | |
1209 | cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag))); | |
41949ed5 RH |
1210 | else |
1211 | cpb->next_aprd = cpu_to_le64(0); | |
fbbb262d RH |
1212 | } |
1213 | ||
382a6652 RH |
1214 | static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc) |
1215 | { | |
1216 | struct nv_adma_port_priv *pp = qc->ap->private_data; | |
1217 | ||
1218 | /* ADMA engine can only be used for non-ATAPI DMA commands, | |
f2fb344b RH |
1219 | or interrupt-driven no-data commands, where a result taskfile |
1220 | is not required. */ | |
382a6652 | 1221 | if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) || |
f2fb344b RH |
1222 | (qc->tf.flags & ATA_TFLAG_POLLING) || |
1223 | (qc->flags & ATA_QCFLAG_RESULT_TF)) | |
382a6652 RH |
1224 | return 1; |
1225 | ||
1226 | if((qc->flags & ATA_QCFLAG_DMAMAP) || | |
1227 | (qc->tf.protocol == ATA_PROT_NODATA)) | |
1228 | return 0; | |
1229 | ||
1230 | return 1; | |
1231 | } | |
1232 | ||
fbbb262d RH |
1233 | static void nv_adma_qc_prep(struct ata_queued_cmd *qc) |
1234 | { | |
1235 | struct nv_adma_port_priv *pp = qc->ap->private_data; | |
1236 | struct nv_adma_cpb *cpb = &pp->cpb[qc->tag]; | |
1237 | u8 ctl_flags = NV_CPB_CTL_CPB_VALID | | |
fbbb262d RH |
1238 | NV_CPB_CTL_IEN; |
1239 | ||
382a6652 | 1240 | if (nv_adma_use_reg_mode(qc)) { |
2dec7555 | 1241 | nv_adma_register_mode(qc->ap); |
fbbb262d RH |
1242 | ata_qc_prep(qc); |
1243 | return; | |
1244 | } | |
1245 | ||
41949ed5 RH |
1246 | cpb->resp_flags = NV_CPB_RESP_DONE; |
1247 | wmb(); | |
1248 | cpb->ctl_flags = 0; | |
1249 | wmb(); | |
fbbb262d RH |
1250 | |
1251 | cpb->len = 3; | |
1252 | cpb->tag = qc->tag; | |
1253 | cpb->next_cpb_idx = 0; | |
1254 | ||
1255 | /* turn on NCQ flags for NCQ commands */ | |
1256 | if (qc->tf.protocol == ATA_PROT_NCQ) | |
1257 | ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA; | |
1258 | ||
cdf56bcf RH |
1259 | VPRINTK("qc->flags = 0x%lx\n", qc->flags); |
1260 | ||
fbbb262d RH |
1261 | nv_adma_tf_to_cpb(&qc->tf, cpb->tf); |
1262 | ||
382a6652 RH |
1263 | if(qc->flags & ATA_QCFLAG_DMAMAP) { |
1264 | nv_adma_fill_sg(qc, cpb); | |
1265 | ctl_flags |= NV_CPB_CTL_APRD_VALID; | |
1266 | } else | |
1267 | memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5); | |
fbbb262d RH |
1268 | |
1269 | /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are | |
1270 | finished filling in all of the contents */ | |
1271 | wmb(); | |
1272 | cpb->ctl_flags = ctl_flags; | |
41949ed5 RH |
1273 | wmb(); |
1274 | cpb->resp_flags = 0; | |
fbbb262d RH |
1275 | } |
1276 | ||
1277 | static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc) | |
1278 | { | |
2dec7555 | 1279 | struct nv_adma_port_priv *pp = qc->ap->private_data; |
cdf56bcf | 1280 | void __iomem *mmio = pp->ctl_block; |
5e5c74a5 | 1281 | int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ); |
fbbb262d RH |
1282 | |
1283 | VPRINTK("ENTER\n"); | |
1284 | ||
382a6652 | 1285 | if (nv_adma_use_reg_mode(qc)) { |
fbbb262d | 1286 | /* use ATA register mode */ |
382a6652 | 1287 | VPRINTK("using ATA register mode: 0x%lx\n", qc->flags); |
fbbb262d RH |
1288 | nv_adma_register_mode(qc->ap); |
1289 | return ata_qc_issue_prot(qc); | |
1290 | } else | |
1291 | nv_adma_mode(qc->ap); | |
1292 | ||
1293 | /* write append register, command tag in lower 8 bits | |
1294 | and (number of cpbs to append -1) in top 8 bits */ | |
1295 | wmb(); | |
5e5c74a5 RH |
1296 | |
1297 | if(curr_ncq != pp->last_issue_ncq) { | |
1298 | /* Seems to need some delay before switching between NCQ and non-NCQ | |
1299 | commands, else we get command timeouts and such. */ | |
1300 | udelay(20); | |
1301 | pp->last_issue_ncq = curr_ncq; | |
1302 | } | |
1303 | ||
fbbb262d RH |
1304 | writew(qc->tag, mmio + NV_ADMA_APPEND); |
1305 | ||
1306 | DPRINTK("Issued tag %u\n",qc->tag); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
7d12e780 | 1311 | static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance) |
1da177e4 | 1312 | { |
cca3974e | 1313 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1314 | unsigned int i; |
1315 | unsigned int handled = 0; | |
1316 | unsigned long flags; | |
1317 | ||
cca3974e | 1318 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 | 1319 | |
cca3974e | 1320 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 LT |
1321 | struct ata_port *ap; |
1322 | ||
cca3974e | 1323 | ap = host->ports[i]; |
c1389503 | 1324 | if (ap && |
029f5468 | 1325 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
1326 | struct ata_queued_cmd *qc; |
1327 | ||
9af5c9c9 | 1328 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
e50362ec | 1329 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 | 1330 | handled += ata_host_intr(ap, qc); |
b887030a AC |
1331 | else |
1332 | // No request pending? Clear interrupt status | |
1333 | // anyway, in case there's one pending. | |
1334 | ap->ops->check_status(ap); | |
1da177e4 LT |
1335 | } |
1336 | ||
1337 | } | |
1338 | ||
cca3974e | 1339 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1340 | |
1341 | return IRQ_RETVAL(handled); | |
1342 | } | |
1343 | ||
cca3974e | 1344 | static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat) |
ada364e8 TH |
1345 | { |
1346 | int i, handled = 0; | |
1347 | ||
cca3974e JG |
1348 | for (i = 0; i < host->n_ports; i++) { |
1349 | struct ata_port *ap = host->ports[i]; | |
ada364e8 TH |
1350 | |
1351 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) | |
1352 | handled += nv_host_intr(ap, irq_stat); | |
1353 | ||
1354 | irq_stat >>= NV_INT_PORT_SHIFT; | |
1355 | } | |
1356 | ||
1357 | return IRQ_RETVAL(handled); | |
1358 | } | |
1359 | ||
7d12e780 | 1360 | static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance) |
ada364e8 | 1361 | { |
cca3974e | 1362 | struct ata_host *host = dev_instance; |
ada364e8 TH |
1363 | u8 irq_stat; |
1364 | irqreturn_t ret; | |
1365 | ||
cca3974e | 1366 | spin_lock(&host->lock); |
0d5ff566 | 1367 | irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); |
cca3974e JG |
1368 | ret = nv_do_interrupt(host, irq_stat); |
1369 | spin_unlock(&host->lock); | |
ada364e8 TH |
1370 | |
1371 | return ret; | |
1372 | } | |
1373 | ||
7d12e780 | 1374 | static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance) |
ada364e8 | 1375 | { |
cca3974e | 1376 | struct ata_host *host = dev_instance; |
ada364e8 TH |
1377 | u8 irq_stat; |
1378 | irqreturn_t ret; | |
1379 | ||
cca3974e | 1380 | spin_lock(&host->lock); |
0d5ff566 | 1381 | irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); |
cca3974e JG |
1382 | ret = nv_do_interrupt(host, irq_stat); |
1383 | spin_unlock(&host->lock); | |
ada364e8 TH |
1384 | |
1385 | return ret; | |
1386 | } | |
1387 | ||
da3dbb17 | 1388 | static int nv_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 1389 | { |
1da177e4 | 1390 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 1391 | return -EINVAL; |
1da177e4 | 1392 | |
da3dbb17 TH |
1393 | *val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4)); |
1394 | return 0; | |
1da177e4 LT |
1395 | } |
1396 | ||
da3dbb17 | 1397 | static int nv_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 1398 | { |
1da177e4 | 1399 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 1400 | return -EINVAL; |
1da177e4 | 1401 | |
0d5ff566 | 1402 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 1403 | return 0; |
1da177e4 LT |
1404 | } |
1405 | ||
39f87582 TH |
1406 | static void nv_nf2_freeze(struct ata_port *ap) |
1407 | { | |
0d5ff566 | 1408 | void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
39f87582 TH |
1409 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1410 | u8 mask; | |
1411 | ||
0d5ff566 | 1412 | mask = ioread8(scr_addr + NV_INT_ENABLE); |
39f87582 | 1413 | mask &= ~(NV_INT_ALL << shift); |
0d5ff566 | 1414 | iowrite8(mask, scr_addr + NV_INT_ENABLE); |
39f87582 TH |
1415 | } |
1416 | ||
1417 | static void nv_nf2_thaw(struct ata_port *ap) | |
1418 | { | |
0d5ff566 | 1419 | void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
39f87582 TH |
1420 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1421 | u8 mask; | |
1422 | ||
0d5ff566 | 1423 | iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS); |
39f87582 | 1424 | |
0d5ff566 | 1425 | mask = ioread8(scr_addr + NV_INT_ENABLE); |
39f87582 | 1426 | mask |= (NV_INT_MASK << shift); |
0d5ff566 | 1427 | iowrite8(mask, scr_addr + NV_INT_ENABLE); |
39f87582 TH |
1428 | } |
1429 | ||
1430 | static void nv_ck804_freeze(struct ata_port *ap) | |
1431 | { | |
0d5ff566 | 1432 | void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; |
39f87582 TH |
1433 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1434 | u8 mask; | |
1435 | ||
1436 | mask = readb(mmio_base + NV_INT_ENABLE_CK804); | |
1437 | mask &= ~(NV_INT_ALL << shift); | |
1438 | writeb(mask, mmio_base + NV_INT_ENABLE_CK804); | |
1439 | } | |
1440 | ||
1441 | static void nv_ck804_thaw(struct ata_port *ap) | |
1442 | { | |
0d5ff566 | 1443 | void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; |
39f87582 TH |
1444 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
1445 | u8 mask; | |
1446 | ||
1447 | writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804); | |
1448 | ||
1449 | mask = readb(mmio_base + NV_INT_ENABLE_CK804); | |
1450 | mask |= (NV_INT_MASK << shift); | |
1451 | writeb(mask, mmio_base + NV_INT_ENABLE_CK804); | |
1452 | } | |
1453 | ||
cc0680a5 | 1454 | static int nv_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1455 | unsigned long deadline) |
39f87582 TH |
1456 | { |
1457 | unsigned int dummy; | |
1458 | ||
1459 | /* SATA hardreset fails to retrieve proper device signature on | |
1460 | * some controllers. Don't classify on hardreset. For more | |
1461 | * info, see http://bugme.osdl.org/show_bug.cgi?id=3352 | |
1462 | */ | |
cc0680a5 | 1463 | return sata_std_hardreset(link, &dummy, deadline); |
39f87582 TH |
1464 | } |
1465 | ||
1466 | static void nv_error_handler(struct ata_port *ap) | |
1467 | { | |
1468 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, | |
1469 | nv_hardreset, ata_std_postreset); | |
1470 | } | |
1471 | ||
fbbb262d RH |
1472 | static void nv_adma_error_handler(struct ata_port *ap) |
1473 | { | |
1474 | struct nv_adma_port_priv *pp = ap->private_data; | |
1475 | if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) { | |
cdf56bcf | 1476 | void __iomem *mmio = pp->ctl_block; |
fbbb262d RH |
1477 | int i; |
1478 | u16 tmp; | |
a84471fe | 1479 | |
9af5c9c9 | 1480 | if(ata_tag_valid(ap->link.active_tag) || ap->link.sactive) { |
2cb27853 RH |
1481 | u32 notifier = readl(mmio + NV_ADMA_NOTIFIER); |
1482 | u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); | |
1483 | u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); | |
1484 | u32 status = readw(mmio + NV_ADMA_STAT); | |
08af7414 RH |
1485 | u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT); |
1486 | u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX); | |
2cb27853 RH |
1487 | |
1488 | ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X " | |
08af7414 RH |
1489 | "notifier_error 0x%X gen_ctl 0x%X status 0x%X " |
1490 | "next cpb count 0x%X next cpb idx 0x%x\n", | |
1491 | notifier, notifier_error, gen_ctl, status, | |
1492 | cpb_count, next_cpb_idx); | |
2cb27853 RH |
1493 | |
1494 | for( i=0;i<NV_ADMA_MAX_CPBS;i++) { | |
1495 | struct nv_adma_cpb *cpb = &pp->cpb[i]; | |
9af5c9c9 TH |
1496 | if( (ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) || |
1497 | ap->link.sactive & (1 << i) ) | |
2cb27853 RH |
1498 | ata_port_printk(ap, KERN_ERR, |
1499 | "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n", | |
1500 | i, cpb->ctl_flags, cpb->resp_flags); | |
1501 | } | |
1502 | } | |
fbbb262d | 1503 | |
fbbb262d RH |
1504 | /* Push us back into port register mode for error handling. */ |
1505 | nv_adma_register_mode(ap); | |
1506 | ||
fbbb262d RH |
1507 | /* Mark all of the CPBs as invalid to prevent them from being executed */ |
1508 | for( i=0;i<NV_ADMA_MAX_CPBS;i++) | |
1509 | pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID; | |
1510 | ||
1511 | /* clear CPB fetch count */ | |
1512 | writew(0, mmio + NV_ADMA_CPB_COUNT); | |
1513 | ||
1514 | /* Reset channel */ | |
1515 | tmp = readw(mmio + NV_ADMA_CTL); | |
1516 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | |
5ce0cf6f | 1517 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
fbbb262d RH |
1518 | udelay(1); |
1519 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | |
5ce0cf6f | 1520 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
fbbb262d RH |
1521 | } |
1522 | ||
1523 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, | |
1524 | nv_hardreset, ata_std_postreset); | |
1525 | } | |
1526 | ||
1da177e4 LT |
1527 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
1528 | { | |
1529 | static int printed_version = 0; | |
1626aeb8 | 1530 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
9a829ccf | 1531 | struct ata_host *host; |
cdf56bcf | 1532 | struct nv_host_priv *hpriv; |
1da177e4 LT |
1533 | int rc; |
1534 | u32 bar; | |
0d5ff566 | 1535 | void __iomem *base; |
fbbb262d | 1536 | unsigned long type = ent->driver_data; |
1da177e4 LT |
1537 | |
1538 | // Make sure this is a SATA controller by counting the number of bars | |
1539 | // (NVIDIA SATA controllers will always have six bars). Otherwise, | |
1540 | // it's an IDE controller and we ignore it. | |
1541 | for (bar=0; bar<6; bar++) | |
1542 | if (pci_resource_start(pdev, bar) == 0) | |
1543 | return -ENODEV; | |
1544 | ||
cdf56bcf | 1545 | if (!printed_version++) |
a9524a76 | 1546 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1547 | |
24dc5f33 | 1548 | rc = pcim_enable_device(pdev); |
1da177e4 | 1549 | if (rc) |
24dc5f33 | 1550 | return rc; |
1da177e4 | 1551 | |
9a829ccf TH |
1552 | /* determine type and allocate host */ |
1553 | if (type >= CK804 && adma_enabled) { | |
fbbb262d RH |
1554 | dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n"); |
1555 | type = ADMA; | |
fbbb262d RH |
1556 | } |
1557 | ||
1626aeb8 | 1558 | ppi[0] = &nv_port_info[type]; |
d583bc18 | 1559 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
9a829ccf TH |
1560 | if (rc) |
1561 | return rc; | |
1da177e4 | 1562 | |
24dc5f33 | 1563 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
cdf56bcf | 1564 | if (!hpriv) |
24dc5f33 | 1565 | return -ENOMEM; |
9a829ccf TH |
1566 | hpriv->type = type; |
1567 | host->private_data = hpriv; | |
cdf56bcf | 1568 | |
9a829ccf TH |
1569 | /* set 64bit dma masks, may fail */ |
1570 | if (type == ADMA) { | |
1571 | if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) | |
1572 | pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1573 | } | |
1da177e4 | 1574 | |
9a829ccf TH |
1575 | /* request and iomap NV_MMIO_BAR */ |
1576 | rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME); | |
1577 | if (rc) | |
1578 | return rc; | |
1da177e4 | 1579 | |
9a829ccf TH |
1580 | /* configure SCR access */ |
1581 | base = host->iomap[NV_MMIO_BAR]; | |
1582 | host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET; | |
1583 | host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET; | |
1da177e4 | 1584 | |
ada364e8 | 1585 | /* enable SATA space for CK804 */ |
fbbb262d | 1586 | if (type >= CK804) { |
ada364e8 TH |
1587 | u8 regval; |
1588 | ||
1589 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
1590 | regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
1591 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
1592 | } | |
1593 | ||
9a829ccf | 1594 | /* init ADMA */ |
fbbb262d | 1595 | if (type == ADMA) { |
9a829ccf | 1596 | rc = nv_adma_host_init(host); |
fbbb262d | 1597 | if (rc) |
24dc5f33 | 1598 | return rc; |
fbbb262d RH |
1599 | } |
1600 | ||
9a829ccf TH |
1601 | pci_set_master(pdev); |
1602 | return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler, | |
1603 | IRQF_SHARED, ppi[0]->sht); | |
1da177e4 LT |
1604 | } |
1605 | ||
438ac6d5 | 1606 | #ifdef CONFIG_PM |
cdf56bcf RH |
1607 | static int nv_pci_device_resume(struct pci_dev *pdev) |
1608 | { | |
1609 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1610 | struct nv_host_priv *hpriv = host->private_data; | |
ce053fa8 | 1611 | int rc; |
cdf56bcf | 1612 | |
ce053fa8 RH |
1613 | rc = ata_pci_device_do_resume(pdev); |
1614 | if(rc) | |
1615 | return rc; | |
cdf56bcf RH |
1616 | |
1617 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
1618 | if(hpriv->type >= CK804) { | |
1619 | u8 regval; | |
1620 | ||
1621 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
1622 | regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
1623 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
1624 | } | |
1625 | if(hpriv->type == ADMA) { | |
1626 | u32 tmp32; | |
1627 | struct nv_adma_port_priv *pp; | |
1628 | /* enable/disable ADMA on the ports appropriately */ | |
1629 | pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); | |
1630 | ||
1631 | pp = host->ports[0]->private_data; | |
1632 | if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) | |
1633 | tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | | |
1634 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN); | |
1635 | else | |
1636 | tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN | | |
1637 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN); | |
1638 | pp = host->ports[1]->private_data; | |
1639 | if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) | |
1640 | tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN | | |
1641 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN); | |
1642 | else | |
1643 | tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN | | |
1644 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN); | |
1645 | ||
1646 | pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); | |
1647 | } | |
1648 | } | |
1649 | ||
1650 | ata_host_resume(host); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
438ac6d5 | 1654 | #endif |
cdf56bcf | 1655 | |
cca3974e | 1656 | static void nv_ck804_host_stop(struct ata_host *host) |
ada364e8 | 1657 | { |
cca3974e | 1658 | struct pci_dev *pdev = to_pci_dev(host->dev); |
ada364e8 TH |
1659 | u8 regval; |
1660 | ||
1661 | /* disable SATA space for CK804 */ | |
1662 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
1663 | regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
1664 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
ada364e8 TH |
1665 | } |
1666 | ||
fbbb262d RH |
1667 | static void nv_adma_host_stop(struct ata_host *host) |
1668 | { | |
1669 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
fbbb262d RH |
1670 | u32 tmp32; |
1671 | ||
fbbb262d RH |
1672 | /* disable ADMA on the ports */ |
1673 | pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); | |
1674 | tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | | |
1675 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN | | |
1676 | NV_MCP_SATA_CFG_20_PORT1_EN | | |
1677 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN); | |
1678 | ||
1679 | pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); | |
1680 | ||
1681 | nv_ck804_host_stop(host); | |
1682 | } | |
1683 | ||
1da177e4 LT |
1684 | static int __init nv_init(void) |
1685 | { | |
b7887196 | 1686 | return pci_register_driver(&nv_pci_driver); |
1da177e4 LT |
1687 | } |
1688 | ||
1689 | static void __exit nv_exit(void) | |
1690 | { | |
1691 | pci_unregister_driver(&nv_pci_driver); | |
1692 | } | |
1693 | ||
1694 | module_init(nv_init); | |
1695 | module_exit(nv_exit); | |
fbbb262d RH |
1696 | module_param_named(adma, adma_enabled, bool, 0444); |
1697 | MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)"); |