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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / ata / sata_promise.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5595ddf9 5 * Mikael Pettersson <mikpe@it.uu.se>
1da177e4
LT		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
1da177e4 11 *
af36d7f0
JG		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
1da177e4
LT		 31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
a9524a76 41#include <linux/device.h>
95006188 42#include <scsi/scsi.h>
1da177e4 43#include <scsi/scsi_host.h>
193515d5 44#include <scsi/scsi_cmnd.h>
1da177e4 45#include <linux/libata.h>
1da177e4
LT		 46#include "sata_promise.h"
47
48#define DRV_NAME "sata_promise"
c07a9c49 49#define DRV_VERSION "2.12"
1da177e4
LT		 50
51enum {
eca25dca 52 PDC_MAX_PORTS = 4,
0d5ff566 53 PDC_MMIO_BAR = 3,
b9ccd4a9 54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
0d5ff566 55
821d22cd
MP		 56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
ff7cddf5 59 PDC_PCI_CTL = 0x48, /* PCI control/status reg */
821d22cd
MP		 60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
63 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
64
65 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
95006188
MP		 66 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
67 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
68 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
69 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
70 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
71 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
72 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
73fd456b 73 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
1da177e4 74 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
1da177e4
LT		 75 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
76 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
821d22cd
MP		 77
78 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
ff7cddf5 79 PDC_SATA_ERROR = 0x04,
821d22cd 80 PDC_PHYMODE4 = 0x14,
ff7cddf5
MP		 81 PDC_LINK_LAYER_ERRORS = 0x6C,
82 PDC_FPDMA_CTLSTAT = 0xD8,
83 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
84 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
85
86 /* PDC_FPDMA_CTLSTAT bit definitions */
87 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
88 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
89 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
1da177e4 90
176efb05
MP		 91 /* PDC_GLOBAL_CTL bit definitions */
92 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
93 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
94 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
95 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
96 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
97 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
98 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
99 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
100 PDC_DRIVE_ERR = (1 << 21), /* drive error */
101 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
102 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
103 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
5796d1c4
JG		 104 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
105 PDC2_ATA_DMA_CNT_ERR,
106 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
107 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
108 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
109 PDC1_ERR_MASK | PDC2_ERR_MASK,
1da177e4
LT		 110
111 board_2037x = 0, /* FastTrak S150 TX2plus */
eca25dca
TH		 112 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
113 board_20319 = 2, /* FastTrak S150 TX4 */
114 board_20619 = 3, /* FastTrak TX4000 */
115 board_2057x = 4, /* SATAII150 Tx2plus */
d0e58031 116 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
eca25dca 117 board_40518 = 6, /* SATAII150 Tx4 */
1da177e4 118
6340f019 119 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
1da177e4 120
95006188
MP		 121 /* Sequence counter control registers bit definitions */
122 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
123
124 /* Feature register values */
125 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
126 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
127
128 /* Device/Head register values */
129 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
130
25b93d81
MP		 131 /* PDC_CTLSTAT bit definitions */
132 PDC_DMA_ENABLE = (1 << 7),
133 PDC_IRQ_DISABLE = (1 << 10),
1da177e4 134 PDC_RESET = (1 << 11), /* HDMA reset */
50630195 135
25b93d81 136 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
95006188 137 ATA_FLAG_MMIO |
3d0a59c0 138 ATA_FLAG_PIO_POLLING,
b2d1eee1 139
eca25dca
TH		 140 /* ap->flags bits */
141 PDC_FLAG_GEN_II = (1 << 24),
142 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
143 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
1da177e4
LT		 144};
145
1da177e4
LT		 146struct pdc_port_priv {
147 u8 *pkt;
148 dma_addr_t pkt_dma;
149};
150
82ef04fb
TH		 151static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
152static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
7715a6f9 153static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
eca25dca
TH		 154static int pdc_common_port_start(struct ata_port *ap);
155static int pdc_sata_port_start(struct ata_port *ap);
1da177e4 156static void pdc_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 157static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
158static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
95006188 159static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
724114a5 160static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
1da177e4 161static void pdc_irq_clear(struct ata_port *ap);
9363c382 162static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
25b93d81 163static void pdc_freeze(struct ata_port *ap);
c07a9c49 164static void pdc_sata_freeze(struct ata_port *ap);
25b93d81 165static void pdc_thaw(struct ata_port *ap);
c07a9c49 166static void pdc_sata_thaw(struct ata_port *ap);
cadef677
MP		 167static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
168 unsigned long deadline);
169static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
170 unsigned long deadline);
a1efdaba 171static void pdc_error_handler(struct ata_port *ap);
25b93d81 172static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
724114a5
MP		 173static int pdc_pata_cable_detect(struct ata_port *ap);
174static int pdc_sata_cable_detect(struct ata_port *ap);
374b1873 175
193515d5 176static struct scsi_host_template pdc_ata_sht = {
68d1d07b 177 ATA_BASE_SHT(DRV_NAME),
b9ccd4a9 178 .sg_tablesize = PDC_MAX_PRD,
1da177e4 179 .dma_boundary = ATA_DMA_BOUNDARY,
1da177e4
LT		 180};
181
029cfd6b
TH		 182static const struct ata_port_operations pdc_common_ops = {
183 .inherits = &ata_sff_port_ops,
184
5682ed33
TH		 185 .sff_tf_load = pdc_tf_load_mmio,
186 .sff_exec_command = pdc_exec_command_mmio,
95006188 187 .check_atapi_dma = pdc_check_atapi_dma,
95006188 188 .qc_prep = pdc_qc_prep,
9363c382 189 .qc_issue = pdc_qc_issue,
c96f1732 190
5682ed33 191 .sff_irq_clear = pdc_irq_clear,
c96f1732 192 .lost_interrupt = ATA_OP_NULL,
95006188 193
029cfd6b 194 .post_internal_cmd = pdc_post_internal_cmd,
a1efdaba 195 .error_handler = pdc_error_handler,
95006188
MP		 196};
197
029cfd6b
TH		 198static struct ata_port_operations pdc_sata_ops = {
199 .inherits = &pdc_common_ops,
200 .cable_detect = pdc_sata_cable_detect,
c07a9c49
MP		 201 .freeze = pdc_sata_freeze,
202 .thaw = pdc_sata_thaw,
1da177e4
LT		 203 .scr_read = pdc_sata_scr_read,
204 .scr_write = pdc_sata_scr_write,
eca25dca 205 .port_start = pdc_sata_port_start,
cadef677 206 .hardreset = pdc_sata_hardreset,
1da177e4
LT		 207};
208
0ae6654d
MP		 209/* First-generation chips need a more restrictive ->check_atapi_dma op,
210 and ->freeze/thaw that ignore the hotplug controls. */
029cfd6b
TH		 211static struct ata_port_operations pdc_old_sata_ops = {
212 .inherits = &pdc_sata_ops,
0ae6654d
MP		 213 .freeze = pdc_freeze,
214 .thaw = pdc_thaw,
029cfd6b
TH		 215 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
216};
2cba582a 217
029cfd6b
TH		 218static struct ata_port_operations pdc_pata_ops = {
219 .inherits = &pdc_common_ops,
220 .cable_detect = pdc_pata_cable_detect,
5387373b
MP		 221 .freeze = pdc_freeze,
222 .thaw = pdc_thaw,
eca25dca 223 .port_start = pdc_common_port_start,
cadef677 224 .softreset = pdc_pata_softreset,
2cba582a
JG		 225};
226
98ac62de 227static const struct ata_port_info pdc_port_info[] = {
5595ddf9 228 [board_2037x] =
1da177e4 229 {
eca25dca
TH		 230 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
231 PDC_FLAG_SATA_PATA,
14bdef98
EIB		 232 .pio_mask = ATA_PIO4,
233 .mwdma_mask = ATA_MWDMA2,
469248ab 234 .udma_mask = ATA_UDMA6,
95006188 235 .port_ops = &pdc_old_sata_ops,
1da177e4
LT		 236 },
237
5595ddf9 238 [board_2037x_pata] =
eca25dca
TH		 239 {
240 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 241 .pio_mask = ATA_PIO4,
242 .mwdma_mask = ATA_MWDMA2,
469248ab 243 .udma_mask = ATA_UDMA6,
eca25dca
TH		 244 .port_ops = &pdc_pata_ops,
245 },
246
5595ddf9 247 [board_20319] =
1da177e4 248 {
eca25dca
TH		 249 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
250 PDC_FLAG_4_PORTS,
14bdef98
EIB		 251 .pio_mask = ATA_PIO4,
252 .mwdma_mask = ATA_MWDMA2,
469248ab 253 .udma_mask = ATA_UDMA6,
95006188 254 .port_ops = &pdc_old_sata_ops,
1da177e4 255 },
f497ba73 256
5595ddf9 257 [board_20619] =
f497ba73 258 {
eca25dca
TH		 259 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
260 PDC_FLAG_4_PORTS,
14bdef98
EIB		 261 .pio_mask = ATA_PIO4,
262 .mwdma_mask = ATA_MWDMA2,
469248ab 263 .udma_mask = ATA_UDMA6,
2cba582a 264 .port_ops = &pdc_pata_ops,
f497ba73 265 },
5a46fe89 266
5595ddf9 267 [board_2057x] =
6340f019 268 {
eca25dca
TH		 269 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
270 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
14bdef98
EIB		 271 .pio_mask = ATA_PIO4,
272 .mwdma_mask = ATA_MWDMA2,
469248ab 273 .udma_mask = ATA_UDMA6,
6340f019
LK		 274 .port_ops = &pdc_sata_ops,
275 },
276
5595ddf9 277 [board_2057x_pata] =
eca25dca 278 {
bb312235 279 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
eca25dca 280 PDC_FLAG_GEN_II,
14bdef98
EIB		 281 .pio_mask = ATA_PIO4,
282 .mwdma_mask = ATA_MWDMA2,
469248ab 283 .udma_mask = ATA_UDMA6,
eca25dca
TH		 284 .port_ops = &pdc_pata_ops,
285 },
286
5595ddf9 287 [board_40518] =
6340f019 288 {
eca25dca
TH		 289 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
290 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
14bdef98
EIB		 291 .pio_mask = ATA_PIO4,
292 .mwdma_mask = ATA_MWDMA2,
469248ab 293 .udma_mask = ATA_UDMA6,
6340f019
LK		 294 .port_ops = &pdc_sata_ops,
295 },
1da177e4
LT		 296};
297
3b7d697d 298static const struct pci_device_id pdc_ata_pci_tbl[] = {
54bb3a94 299 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
54bb3a94
JG		 300 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
301 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
302 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
b2d1eee1
MP		 303 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
304 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
54bb3a94 305 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
d324d462 306 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
b2d1eee1 307 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
54bb3a94 308 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
54bb3a94
JG		 309
310 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
311 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
7f9992a2
MP		 312 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
313 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
b2d1eee1 314 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
54bb3a94
JG		 315 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
316
317 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
f497ba73 318
1da177e4
LT		 319 { } /* terminate list */
320};
321
1da177e4
LT		 322static struct pci_driver pdc_ata_pci_driver = {
323 .name = DRV_NAME,
324 .id_table = pdc_ata_pci_tbl,
325 .probe = pdc_ata_init_one,
326 .remove = ata_pci_remove_one,
327};
328
724114a5 329static int pdc_common_port_start(struct ata_port *ap)
1da177e4 330{
cca3974e 331 struct device *dev = ap->host->dev;
1da177e4
LT		 332 struct pdc_port_priv *pp;
333 int rc;
334
335 rc = ata_port_start(ap);
336 if (rc)
337 return rc;
338
24dc5f33
TH		 339 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
340 if (!pp)
341 return -ENOMEM;
1da177e4 342
24dc5f33
TH		 343 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
344 if (!pp->pkt)
345 return -ENOMEM;
1da177e4
LT		 346
347 ap->private_data = pp;
348
724114a5
MP		 349 return 0;
350}
351
352static int pdc_sata_port_start(struct ata_port *ap)
353{
724114a5
MP		 354 int rc;
355
356 rc = pdc_common_port_start(ap);
357 if (rc)
358 return rc;
359
599b7202 360 /* fix up PHYMODE4 align timing */
eca25dca 361 if (ap->flags & PDC_FLAG_GEN_II) {
821d22cd 362 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
599b7202
MP		 363 unsigned int tmp;
364
821d22cd 365 tmp = readl(sata_mmio + PDC_PHYMODE4);
599b7202 366 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
821d22cd 367 writel(tmp, sata_mmio + PDC_PHYMODE4);
599b7202
MP		 368 }
369
1da177e4 370 return 0;
1da177e4
LT		 371}
372
ff7cddf5
MP		 373static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
374{
375 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
376 u32 tmp;
377
378 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
379 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
380 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
381
382 /* It's not allowed to write to the entire FPDMA_CTLSTAT register
383 when NCQ is running. So do a byte-sized write to bits 10 and 11. */
384 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
385 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
386}
387
388static void pdc_fpdma_reset(struct ata_port *ap)
389{
390 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
391 u8 tmp;
392
393 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
394 tmp &= 0x7F;
395 tmp |= PDC_FPDMA_CTLSTAT_RESET;
396 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
397 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
398 udelay(100);
399 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
400 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
401 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
402
403 pdc_fpdma_clear_interrupt_flag(ap);
404}
405
406static void pdc_not_at_command_packet_phase(struct ata_port *ap)
407{
408 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
409 unsigned int i;
410 u32 tmp;
411
412 /* check not at ASIC packet command phase */
413 for (i = 0; i < 100; ++i) {
414 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
415 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
416 if ((tmp & 0xF) != 1)
417 break;
418 udelay(100);
419 }
420}
421
422static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
423{
424 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
425
426 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
427 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
428}
429
1da177e4
LT		 430static void pdc_reset_port(struct ata_port *ap)
431{
821d22cd 432 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
1da177e4
LT		 433 unsigned int i;
434 u32 tmp;
435
ff7cddf5
MP		 436 if (ap->flags & PDC_FLAG_GEN_II)
437 pdc_not_at_command_packet_phase(ap);
438
439 tmp = readl(ata_ctlstat_mmio);
440 tmp |= PDC_RESET;
441 writel(tmp, ata_ctlstat_mmio);
442
1da177e4 443 for (i = 11; i > 0; i--) {
821d22cd 444 tmp = readl(ata_ctlstat_mmio);
1da177e4
LT		 445 if (tmp & PDC_RESET)
446 break;
447
448 udelay(100);
449
450 tmp |= PDC_RESET;
821d22cd 451 writel(tmp, ata_ctlstat_mmio);
1da177e4
LT		 452 }
453
454 tmp &= ~PDC_RESET;
821d22cd
MP		 455 writel(tmp, ata_ctlstat_mmio);
456 readl(ata_ctlstat_mmio); /* flush */
ff7cddf5
MP		 457
458 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
459 pdc_fpdma_reset(ap);
460 pdc_clear_internal_debug_record_error_register(ap);
461 }
1da177e4
LT		 462}
463
724114a5 464static int pdc_pata_cable_detect(struct ata_port *ap)
2cba582a 465{
d3fb4e8d 466 u8 tmp;
821d22cd 467 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
d3fb4e8d 468
821d22cd 469 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
724114a5
MP		 470 if (tmp & 0x01)
471 return ATA_CBL_PATA40;
472 return ATA_CBL_PATA80;
473}
474
475static int pdc_sata_cable_detect(struct ata_port *ap)
476{
e2a9752a 477 return ATA_CBL_SATA;
d3fb4e8d 478}
2cba582a 479
82ef04fb
TH		 480static int pdc_sata_scr_read(struct ata_link *link,
481 unsigned int sc_reg, u32 *val)
1da177e4 482{
724114a5 483 if (sc_reg > SCR_CONTROL)
da3dbb17 484 return -EINVAL;
82ef04fb 485 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17 486 return 0;
1da177e4
LT		 487}
488
82ef04fb
TH		 489static int pdc_sata_scr_write(struct ata_link *link,
490 unsigned int sc_reg, u32 val)
1da177e4 491{
724114a5 492 if (sc_reg > SCR_CONTROL)
da3dbb17 493 return -EINVAL;
82ef04fb 494 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17 495 return 0;
1da177e4
LT		 496}
497
fba6edbd 498static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
95006188 499{
4113bb6b
MP		 500 struct ata_port *ap = qc->ap;
501 dma_addr_t sg_table = ap->prd_dma;
502 unsigned int cdb_len = qc->dev->cdb_len;
503 u8 *cdb = qc->cdb;
504 struct pdc_port_priv *pp = ap->private_data;
505 u8 *buf = pp->pkt;
826cd156 506 __le32 *buf32 = (__le32 *) buf;
46a67143 507 unsigned int dev_sel, feature;
95006188
MP		 508
509 /* set control bits (byte 0), zero delay seq id (byte 3),
510 * and seq id (byte 2)
511 */
fba6edbd 512 switch (qc->tf.protocol) {
0dc36888 513 case ATAPI_PROT_DMA:
fba6edbd
MP		 514 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
515 buf32[0] = cpu_to_le32(PDC_PKT_READ);
516 else
517 buf32[0] = 0;
518 break;
0dc36888 519 case ATAPI_PROT_NODATA:
fba6edbd
MP		 520 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
521 break;
522 default:
523 BUG();
524 break;
525 }
95006188
MP		 526 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
527 buf32[2] = 0; /* no next-packet */
528
4113bb6b 529 /* select drive */
46a67143 530 if (sata_scr_valid(&ap->link))
4113bb6b 531 dev_sel = PDC_DEVICE_SATA;
46a67143
TH		 532 else
533 dev_sel = qc->tf.device;
534
4113bb6b
MP		 535 buf[12] = (1 << 5) | ATA_REG_DEVICE;
536 buf[13] = dev_sel;
537 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
538 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
539
540 buf[16] = (1 << 5) | ATA_REG_NSECT;
46a67143 541 buf[17] = qc->tf.nsect;
4113bb6b 542 buf[18] = (1 << 5) | ATA_REG_LBAL;
46a67143 543 buf[19] = qc->tf.lbal;
4113bb6b
MP		 544
545 /* set feature and byte counter registers */
0dc36888 546 if (qc->tf.protocol != ATAPI_PROT_DMA)
4113bb6b 547 feature = PDC_FEATURE_ATAPI_PIO;
46a67143 548 else
4113bb6b 549 feature = PDC_FEATURE_ATAPI_DMA;
46a67143 550
4113bb6b
MP		 551 buf[20] = (1 << 5) | ATA_REG_FEATURE;
552 buf[21] = feature;
553 buf[22] = (1 << 5) | ATA_REG_BYTEL;
46a67143 554 buf[23] = qc->tf.lbam;
4113bb6b 555 buf[24] = (1 << 5) | ATA_REG_BYTEH;
46a67143 556 buf[25] = qc->tf.lbah;
4113bb6b
MP		 557
558 /* send ATAPI packet command 0xA0 */
559 buf[26] = (1 << 5) | ATA_REG_CMD;
46a67143 560 buf[27] = qc->tf.command;
4113bb6b
MP		 561
562 /* select drive and check DRQ */
563 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
564 buf[29] = dev_sel;
565
95006188
MP		 566 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
567 BUG_ON(cdb_len & ~0x1E);
568
4113bb6b
MP		 569 /* append the CDB as the final part */
570 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
571 memcpy(buf+31, cdb, cdb_len);
95006188
MP		 572}
573
b9ccd4a9
MP		 574/**
575 * pdc_fill_sg - Fill PCI IDE PRD table
576 * @qc: Metadata associated with taskfile to be transferred
577 *
578 * Fill PCI IDE PRD (scatter-gather) table with segments
579 * associated with the current disk command.
580 * Make sure hardware does not choke on it.
581 *
582 * LOCKING:
583 * spin_lock_irqsave(host lock)
584 *
585 */
586static void pdc_fill_sg(struct ata_queued_cmd *qc)
587{
588 struct ata_port *ap = qc->ap;
589 struct scatterlist *sg;
b9ccd4a9 590 const u32 SG_COUNT_ASIC_BUG = 41*4;
ff2aeb1e
TH		 591 unsigned int si, idx;
592 u32 len;
b9ccd4a9
MP		 593
594 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
595 return;
596
b9ccd4a9 597 idx = 0;
ff2aeb1e 598 for_each_sg(qc->sg, sg, qc->n_elem, si) {
b9ccd4a9 599 u32 addr, offset;
6903c0f7 600 u32 sg_len;
b9ccd4a9
MP		 601
602 /* determine if physical DMA addr spans 64K boundary.
603 * Note h/w doesn't support 64-bit, so we unconditionally
604 * truncate dma_addr_t to u32.
605 */
606 addr = (u32) sg_dma_address(sg);
607 sg_len = sg_dma_len(sg);
608
609 while (sg_len) {
610 offset = addr & 0xffff;
611 len = sg_len;
612 if ((offset + sg_len) > 0x10000)
613 len = 0x10000 - offset;
614
615 ap->prd[idx].addr = cpu_to_le32(addr);
616 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
617 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
618
619 idx++;
620 sg_len -= len;
621 addr += len;
622 }
623 }
624
ff2aeb1e 625 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
b9ccd4a9 626
ff2aeb1e
TH		 627 if (len > SG_COUNT_ASIC_BUG) {
628 u32 addr;
b9ccd4a9 629
ff2aeb1e 630 VPRINTK("Splitting last PRD.\n");
b9ccd4a9 631
ff2aeb1e
TH		 632 addr = le32_to_cpu(ap->prd[idx - 1].addr);
633 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
634 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
b9ccd4a9 635
ff2aeb1e
TH		 636 addr = addr + len - SG_COUNT_ASIC_BUG;
637 len = SG_COUNT_ASIC_BUG;
638 ap->prd[idx].addr = cpu_to_le32(addr);
639 ap->prd[idx].flags_len = cpu_to_le32(len);
640 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
b9ccd4a9 641
ff2aeb1e 642 idx++;
b9ccd4a9 643 }
ff2aeb1e
TH		 644
645 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
b9ccd4a9
MP		 646}
647
1da177e4
LT		 648static void pdc_qc_prep(struct ata_queued_cmd *qc)
649{
650 struct pdc_port_priv *pp = qc->ap->private_data;
651 unsigned int i;
652
653 VPRINTK("ENTER\n");
654
655 switch (qc->tf.protocol) {
656 case ATA_PROT_DMA:
b9ccd4a9 657 pdc_fill_sg(qc);
7715a6f9 658 /*FALLTHROUGH*/
1da177e4
LT		 659 case ATA_PROT_NODATA:
660 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
661 qc->dev->devno, pp->pkt);
1da177e4
LT		 662 if (qc->tf.flags & ATA_TFLAG_LBA48)
663 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
664 else
665 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
1da177e4
LT		 666 pdc_pkt_footer(&qc->tf, pp->pkt, i);
667 break;
0dc36888 668 case ATAPI_PROT_PIO:
b9ccd4a9 669 pdc_fill_sg(qc);
95006188 670 break;
0dc36888 671 case ATAPI_PROT_DMA:
b9ccd4a9 672 pdc_fill_sg(qc);
fba6edbd 673 /*FALLTHROUGH*/
0dc36888 674 case ATAPI_PROT_NODATA:
fba6edbd 675 pdc_atapi_pkt(qc);
95006188 676 break;
1da177e4
LT		 677 default:
678 break;
679 }
680}
681
c07a9c49
MP		 682static int pdc_is_sataii_tx4(unsigned long flags)
683{
684 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
685 return (flags & mask) == mask;
686}
687
688static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
689 int is_sataii_tx4)
690{
691 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
692 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
693}
694
695static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
696{
697 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
698}
699
700static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
701{
702 const struct ata_host *host = ap->host;
703 unsigned int nr_ports = pdc_sata_nr_ports(ap);
704 unsigned int i;
705
7715a6f9 706 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
c07a9c49
MP		 707 ;
708 BUG_ON(i >= nr_ports);
709 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
710}
711
25b93d81
MP		 712static void pdc_freeze(struct ata_port *ap)
713{
821d22cd 714 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 715 u32 tmp;
716
821d22cd 717 tmp = readl(ata_mmio + PDC_CTLSTAT);
25b93d81
MP		 718 tmp |= PDC_IRQ_DISABLE;
719 tmp &= ~PDC_DMA_ENABLE;
821d22cd
MP		 720 writel(tmp, ata_mmio + PDC_CTLSTAT);
721 readl(ata_mmio + PDC_CTLSTAT); /* flush */
25b93d81
MP		 722}
723
c07a9c49
MP		 724static void pdc_sata_freeze(struct ata_port *ap)
725{
726 struct ata_host *host = ap->host;
727 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
0ae6654d 728 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
c07a9c49
MP		 729 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
730 u32 hotplug_status;
731
732 /* Disable hotplug events on this port.
733 *
734 * Locking:
735 * 1) hotplug register accesses must be serialised via host->lock
736 * 2) ap->lock == &ap->host->lock
737 * 3) ->freeze() and ->thaw() are called with ap->lock held
738 */
739 hotplug_status = readl(host_mmio + hotplug_offset);
740 hotplug_status |= 0x11 << (ata_no + 16);
741 writel(hotplug_status, host_mmio + hotplug_offset);
742 readl(host_mmio + hotplug_offset); /* flush */
743
744 pdc_freeze(ap);
745}
746
25b93d81
MP		 747static void pdc_thaw(struct ata_port *ap)
748{
821d22cd 749 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 750 u32 tmp;
751
752 /* clear IRQ */
821d22cd 753 readl(ata_mmio + PDC_COMMAND);
25b93d81
MP		 754
755 /* turn IRQ back on */
821d22cd 756 tmp = readl(ata_mmio + PDC_CTLSTAT);
25b93d81 757 tmp &= ~PDC_IRQ_DISABLE;
821d22cd
MP		 758 writel(tmp, ata_mmio + PDC_CTLSTAT);
759 readl(ata_mmio + PDC_CTLSTAT); /* flush */
25b93d81
MP		 760}
761
c07a9c49
MP		 762static void pdc_sata_thaw(struct ata_port *ap)
763{
764 struct ata_host *host = ap->host;
765 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
0ae6654d 766 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
c07a9c49
MP		 767 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
768 u32 hotplug_status;
769
770 pdc_thaw(ap);
771
772 /* Enable hotplug events on this port.
773 * Locking: see pdc_sata_freeze().
774 */
775 hotplug_status = readl(host_mmio + hotplug_offset);
776 hotplug_status |= 0x11 << ata_no;
777 hotplug_status &= ~(0x11 << (ata_no + 16));
778 writel(hotplug_status, host_mmio + hotplug_offset);
779 readl(host_mmio + hotplug_offset); /* flush */
780}
781
cadef677
MP		 782static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
783 unsigned long deadline)
784{
785 pdc_reset_port(link->ap);
786 return ata_sff_softreset(link, class, deadline);
787}
788
ff7cddf5
MP		 789static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
790{
791 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
792 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
793
794 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
795 return (ata_mmio - host_mmio - 0x200) / 0x80;
796}
797
798static void pdc_hard_reset_port(struct ata_port *ap)
799{
800 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
801 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
802 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
803 u8 tmp;
804
805 spin_lock(&ap->host->lock);
806
807 tmp = readb(pcictl_b1_mmio);
808 tmp &= ~(0x10 << ata_no);
809 writeb(tmp, pcictl_b1_mmio);
810 readb(pcictl_b1_mmio); /* flush */
811 udelay(100);
812 tmp |= (0x10 << ata_no);
813 writeb(tmp, pcictl_b1_mmio);
814 readb(pcictl_b1_mmio); /* flush */
815
816 spin_unlock(&ap->host->lock);
817}
818
cadef677
MP		 819static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
820 unsigned long deadline)
821{
ff7cddf5
MP		 822 if (link->ap->flags & PDC_FLAG_GEN_II)
823 pdc_not_at_command_packet_phase(link->ap);
824 /* hotplug IRQs should have been masked by pdc_sata_freeze() */
825 pdc_hard_reset_port(link->ap);
cadef677 826 pdc_reset_port(link->ap);
ff7cddf5
MP		 827
828 /* sata_promise can't reliably acquire the first D2H Reg FIS
829 * after hardreset. Do non-waiting hardreset and request
830 * follow-up SRST.
831 */
832 return sata_std_hardreset(link, class, deadline);
cadef677
MP		 833}
834
a1efdaba 835static void pdc_error_handler(struct ata_port *ap)
25b93d81 836{
25b93d81
MP		 837 if (!(ap->pflags & ATA_PFLAG_FROZEN))
838 pdc_reset_port(ap);
839
a1efdaba 840 ata_std_error_handler(ap);
724114a5
MP		 841}
842
25b93d81
MP		 843static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
844{
845 struct ata_port *ap = qc->ap;
846
25b93d81 847 /* make DMA engine forget about the failed command */
a51d644a 848 if (qc->flags & ATA_QCFLAG_FAILED)
25b93d81
MP		 849 pdc_reset_port(ap);
850}
851
176efb05
MP		 852static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
853 u32 port_status, u32 err_mask)
854{
9af5c9c9 855 struct ata_eh_info *ehi = &ap->link.eh_info;
176efb05
MP		 856 unsigned int ac_err_mask = 0;
857
858 ata_ehi_clear_desc(ehi);
859 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
860 port_status &= err_mask;
861
862 if (port_status & PDC_DRIVE_ERR)
863 ac_err_mask |= AC_ERR_DEV;
864 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
865 ac_err_mask |= AC_ERR_HSM;
866 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
867 ac_err_mask |= AC_ERR_ATA_BUS;
868 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
869 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
870 ac_err_mask |= AC_ERR_HOST_BUS;
871
936fd732 872 if (sata_scr_valid(&ap->link)) {
da3dbb17
TH		 873 u32 serror;
874
82ef04fb 875 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
da3dbb17
TH		 876 ehi->serror |= serror;
877 }
ce2d3abc 878
176efb05 879 qc->err_mask |= ac_err_mask;
ce2d3abc
MP		 880
881 pdc_reset_port(ap);
8ffcfd9d
MP		 882
883 ata_port_abort(ap);
176efb05
MP		 884}
885
7715a6f9
MP		 886static unsigned int pdc_host_intr(struct ata_port *ap,
887 struct ata_queued_cmd *qc)
1da177e4 888{
a22e2eb0 889 unsigned int handled = 0;
821d22cd 890 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
176efb05
MP		 891 u32 port_status, err_mask;
892
893 err_mask = PDC_ERR_MASK;
eca25dca 894 if (ap->flags & PDC_FLAG_GEN_II)
176efb05
MP		 895 err_mask &= ~PDC1_ERR_MASK;
896 else
897 err_mask &= ~PDC2_ERR_MASK;
821d22cd 898 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
176efb05
MP		 899 if (unlikely(port_status & err_mask)) {
900 pdc_error_intr(ap, qc, port_status, err_mask);
901 return 1;
1da177e4
LT		 902 }
903
904 switch (qc->tf.protocol) {
905 case ATA_PROT_DMA:
906 case ATA_PROT_NODATA:
0dc36888
TH		 907 case ATAPI_PROT_DMA:
908 case ATAPI_PROT_NODATA:
a22e2eb0
AL		 909 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
910 ata_qc_complete(qc);
1da177e4
LT		 911 handled = 1;
912 break;
d0e58031 913 default:
ee500aab
AL		 914 ap->stats.idle_irq++;
915 break;
d0e58031 916 }
1da177e4 917
ee500aab 918 return handled;
1da177e4
LT		 919}
920
921static void pdc_irq_clear(struct ata_port *ap)
922{
821d22cd 923 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1da177e4 924
821d22cd 925 readl(ata_mmio + PDC_COMMAND);
1da177e4
LT		 926}
927
5796d1c4 928static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
1da177e4 929{
cca3974e 930 struct ata_host *host = dev_instance;
1da177e4
LT		 931 struct ata_port *ap;
932 u32 mask = 0;
933 unsigned int i, tmp;
934 unsigned int handled = 0;
821d22cd 935 void __iomem *host_mmio;
a77720ad
MP		 936 unsigned int hotplug_offset, ata_no;
937 u32 hotplug_status;
938 int is_sataii_tx4;
1da177e4
LT		 939
940 VPRINTK("ENTER\n");
941
0d5ff566 942 if (!host || !host->iomap[PDC_MMIO_BAR]) {
1da177e4
LT		 943 VPRINTK("QUICK EXIT\n");
944 return IRQ_NONE;
945 }
946
821d22cd 947 host_mmio = host->iomap[PDC_MMIO_BAR];
1da177e4 948
c07a9c49
MP		 949 spin_lock(&host->lock);
950
a77720ad 951 /* read and clear hotplug flags for all ports */
0ae6654d 952 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
a77720ad 953 hotplug_offset = PDC2_SATA_PLUG_CSR;
0ae6654d
MP		 954 hotplug_status = readl(host_mmio + hotplug_offset);
955 if (hotplug_status & 0xff)
956 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
957 hotplug_status &= 0xff; /* clear uninteresting bits */
958 } else
959 hotplug_status = 0;
a77720ad 960
1da177e4 961 /* reading should also clear interrupts */
821d22cd 962 mask = readl(host_mmio + PDC_INT_SEQMASK);
1da177e4 963
a77720ad 964 if (mask == 0xffffffff && hotplug_status == 0) {
1da177e4 965 VPRINTK("QUICK EXIT 2\n");
c07a9c49 966 goto done_irq;
1da177e4 967 }
6340f019 968
7715a6f9 969 mask &= 0xffff; /* only 16 SEQIDs possible */
a77720ad 970 if (mask == 0 && hotplug_status == 0) {
1da177e4 971 VPRINTK("QUICK EXIT 3\n");
6340f019 972 goto done_irq;
1da177e4
LT		 973 }
974
821d22cd 975 writel(mask, host_mmio + PDC_INT_SEQMASK);
1da177e4 976
a77720ad
MP		 977 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
978
cca3974e 979 for (i = 0; i < host->n_ports; i++) {
1da177e4 980 VPRINTK("port %u\n", i);
cca3974e 981 ap = host->ports[i];
a77720ad
MP		 982
983 /* check for a plug or unplug event */
984 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
985 tmp = hotplug_status & (0x11 << ata_no);
986 if (tmp && ap &&
987 !(ap->flags & ATA_FLAG_DISABLED)) {
9af5c9c9 988 struct ata_eh_info *ehi = &ap->link.eh_info;
a77720ad
MP		 989 ata_ehi_clear_desc(ehi);
990 ata_ehi_hotplugged(ehi);
991 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
992 ata_port_freeze(ap);
993 ++handled;
994 continue;
995 }
996
997 /* check for a packet interrupt */
1da177e4 998 tmp = mask & (1 << (i + 1));
c1389503 999 if (tmp && ap &&
029f5468 1000 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 1001 struct ata_queued_cmd *qc;
1002
9af5c9c9 1003 qc = ata_qc_from_tag(ap, ap->link.active_tag);
e50362ec 1004 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4
LT		 1005 handled += pdc_host_intr(ap, qc);
1006 }
1007 }
1008
1da177e4
LT		 1009 VPRINTK("EXIT\n");
1010
6340f019 1011done_irq:
cca3974e 1012 spin_unlock(&host->lock);
1da177e4
LT		 1013 return IRQ_RETVAL(handled);
1014}
1015
7715a6f9 1016static void pdc_packet_start(struct ata_queued_cmd *qc)
1da177e4
LT		 1017{
1018 struct ata_port *ap = qc->ap;
1019 struct pdc_port_priv *pp = ap->private_data;
821d22cd
MP		 1020 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1021 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1022 unsigned int port_no = ap->port_no;
1023 u8 seq = (u8) (port_no + 1);
1024
1025 VPRINTK("ENTER, ap %p\n", ap);
1026
821d22cd
MP		 1027 writel(0x00000001, host_mmio + (seq * 4));
1028 readl(host_mmio + (seq * 4)); /* flush */
1da177e4
LT		 1029
1030 pp->pkt[2] = seq;
1031 wmb(); /* flush PRD, pkt writes */
821d22cd
MP		 1032 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1033 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1da177e4
LT		 1034}
1035
9363c382 1036static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1037{
1038 switch (qc->tf.protocol) {
0dc36888 1039 case ATAPI_PROT_NODATA:
fba6edbd
MP		 1040 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1041 break;
1042 /*FALLTHROUGH*/
51b94d2a
TH		 1043 case ATA_PROT_NODATA:
1044 if (qc->tf.flags & ATA_TFLAG_POLLING)
1045 break;
1046 /*FALLTHROUGH*/
0dc36888 1047 case ATAPI_PROT_DMA:
1da177e4 1048 case ATA_PROT_DMA:
1da177e4
LT		 1049 pdc_packet_start(qc);
1050 return 0;
1da177e4
LT		 1051 default:
1052 break;
1053 }
9363c382 1054 return ata_sff_qc_issue(qc);
1da177e4
LT		 1055}
1056
057ace5e 1057static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4 1058{
0dc36888 1059 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
9363c382 1060 ata_sff_tf_load(ap, tf);
1da177e4
LT		 1061}
1062
5796d1c4
JG		 1063static void pdc_exec_command_mmio(struct ata_port *ap,
1064 const struct ata_taskfile *tf)
1da177e4 1065{
0dc36888 1066 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
9363c382 1067 ata_sff_exec_command(ap, tf);
1da177e4
LT		 1068}
1069
95006188
MP		 1070static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1071{
1072 u8 *scsicmd = qc->scsicmd->cmnd;
1073 int pio = 1; /* atapi dma off by default */
1074
1075 /* Whitelist commands that may use DMA. */
1076 switch (scsicmd[0]) {
1077 case WRITE_12:
1078 case WRITE_10:
1079 case WRITE_6:
1080 case READ_12:
1081 case READ_10:
1082 case READ_6:
1083 case 0xad: /* READ_DVD_STRUCTURE */
1084 case 0xbe: /* READ_CD */
1085 pio = 0;
1086 }
1087 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1088 if (scsicmd[0] == WRITE_10) {
5796d1c4
JG		 1089 unsigned int lba =
1090 (scsicmd[2] << 24) |
1091 (scsicmd[3] << 16) |
1092 (scsicmd[4] << 8) |
1093 scsicmd[5];
95006188
MP		 1094 if (lba >= 0xFFFF4FA2)
1095 pio = 1;
1096 }
1097 return pio;
1098}
1099
724114a5 1100static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
95006188 1101{
95006188 1102 /* First generation chips cannot use ATAPI DMA on SATA ports */
724114a5 1103 return 1;
95006188 1104}
1da177e4 1105
eca25dca
TH		 1106static void pdc_ata_setup_port(struct ata_port *ap,
1107 void __iomem *base, void __iomem *scr_addr)
1da177e4 1108{
eca25dca
TH		 1109 ap->ioaddr.cmd_addr = base;
1110 ap->ioaddr.data_addr = base;
1111 ap->ioaddr.feature_addr =
1112 ap->ioaddr.error_addr = base + 0x4;
1113 ap->ioaddr.nsect_addr = base + 0x8;
1114 ap->ioaddr.lbal_addr = base + 0xc;
1115 ap->ioaddr.lbam_addr = base + 0x10;
1116 ap->ioaddr.lbah_addr = base + 0x14;
1117 ap->ioaddr.device_addr = base + 0x18;
1118 ap->ioaddr.command_addr =
1119 ap->ioaddr.status_addr = base + 0x1c;
1120 ap->ioaddr.altstatus_addr =
1121 ap->ioaddr.ctl_addr = base + 0x38;
1122 ap->ioaddr.scr_addr = scr_addr;
1da177e4
LT		 1123}
1124
eca25dca 1125static void pdc_host_init(struct ata_host *host)
1da177e4 1126{
821d22cd 1127 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
eca25dca 1128 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
d324d462 1129 int hotplug_offset;
1da177e4
LT		 1130 u32 tmp;
1131
eca25dca 1132 if (is_gen2)
d324d462
MP		 1133 hotplug_offset = PDC2_SATA_PLUG_CSR;
1134 else
1135 hotplug_offset = PDC_SATA_PLUG_CSR;
1136
1da177e4
LT		 1137 /*
1138 * Except for the hotplug stuff, this is voodoo from the
1139 * Promise driver. Label this entire section
1140 * "TODO: figure out why we do this"
1141 */
1142
b2d1eee1 1143 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
821d22cd 1144 tmp = readl(host_mmio + PDC_FLASH_CTL);
b2d1eee1 1145 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
eca25dca 1146 if (!is_gen2)
b2d1eee1 1147 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
821d22cd 1148 writel(tmp, host_mmio + PDC_FLASH_CTL);
1da177e4
LT		 1149
1150 /* clear plug/unplug flags for all ports */
821d22cd
MP		 1151 tmp = readl(host_mmio + hotplug_offset);
1152 writel(tmp | 0xff, host_mmio + hotplug_offset);
1da177e4 1153
821d22cd 1154 tmp = readl(host_mmio + hotplug_offset);
0ae6654d
MP		 1155 if (is_gen2) /* unmask plug/unplug ints */
1156 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1157 else /* mask plug/unplug ints */
1158 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1da177e4 1159
b2d1eee1 1160 /* don't initialise TBG or SLEW on 2nd generation chips */
eca25dca 1161 if (is_gen2)
b2d1eee1
MP		 1162 return;
1163
1da177e4 1164 /* reduce TBG clock to 133 Mhz. */
821d22cd 1165 tmp = readl(host_mmio + PDC_TBG_MODE);
1da177e4
LT		 1166 tmp &= ~0x30000; /* clear bit 17, 16*/
1167 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
821d22cd 1168 writel(tmp, host_mmio + PDC_TBG_MODE);
1da177e4 1169
821d22cd 1170 readl(host_mmio + PDC_TBG_MODE); /* flush */
1da177e4
LT		 1171 msleep(10);
1172
1173 /* adjust slew rate control register. */
821d22cd 1174 tmp = readl(host_mmio + PDC_SLEW_CTL);
1da177e4
LT		 1175 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1176 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
821d22cd 1177 writel(tmp, host_mmio + PDC_SLEW_CTL);
1da177e4
LT		 1178}
1179
5796d1c4
JG		 1180static int pdc_ata_init_one(struct pci_dev *pdev,
1181 const struct pci_device_id *ent)
1da177e4
LT		 1182{
1183 static int printed_version;
eca25dca
TH		 1184 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1185 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1186 struct ata_host *host;
821d22cd 1187 void __iomem *host_mmio;
eca25dca 1188 int n_ports, i, rc;
5ac2fe57 1189 int is_sataii_tx4;
1da177e4
LT		 1190
1191 if (!printed_version++)
a9524a76 1192 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1193
eca25dca 1194 /* enable and acquire resources */
24dc5f33 1195 rc = pcim_enable_device(pdev);
1da177e4
LT		 1196 if (rc)
1197 return rc;
1198
0d5ff566
TH		 1199 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1200 if (rc == -EBUSY)
24dc5f33 1201 pcim_pin_device(pdev);
0d5ff566 1202 if (rc)
24dc5f33 1203 return rc;
821d22cd 1204 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1da177e4 1205
eca25dca
TH		 1206 /* determine port configuration and setup host */
1207 n_ports = 2;
1208 if (pi->flags & PDC_FLAG_4_PORTS)
1209 n_ports = 4;
1210 for (i = 0; i < n_ports; i++)
1211 ppi[i] = pi;
1da177e4 1212
eca25dca 1213 if (pi->flags & PDC_FLAG_SATA_PATA) {
821d22cd 1214 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
d0e58031 1215 if (!(tmp & 0x80))
eca25dca 1216 ppi[n_ports++] = pi + 1;
eca25dca 1217 }
1da177e4 1218
eca25dca
TH		 1219 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1220 if (!host) {
1221 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
24dc5f33 1222 return -ENOMEM;
1da177e4 1223 }
eca25dca 1224 host->iomap = pcim_iomap_table(pdev);
1da177e4 1225
d0e58031 1226 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
5ac2fe57 1227 for (i = 0; i < host->n_ports; i++) {
cbcdd875 1228 struct ata_port *ap = host->ports[i];
d0e58031 1229 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
821d22cd 1230 unsigned int ata_offset = 0x200 + ata_no * 0x80;
cbcdd875
TH		 1231 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1232
821d22cd 1233 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
cbcdd875
TH		 1234
1235 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
821d22cd 1236 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
5ac2fe57 1237 }
1da177e4
LT		 1238
1239 /* initialize adapter */
eca25dca 1240 pdc_host_init(host);
1da177e4 1241
eca25dca
TH		 1242 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1243 if (rc)
1244 return rc;
1245 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1246 if (rc)
1247 return rc;
1da177e4 1248
eca25dca
TH		 1249 /* start host, request IRQ and attach */
1250 pci_set_master(pdev);
1251 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1252 &pdc_ata_sht);
1da177e4
LT		 1253}
1254
1da177e4
LT		 1255static int __init pdc_ata_init(void)
1256{
b7887196 1257 return pci_register_driver(&pdc_ata_pci_driver);
1da177e4
LT		 1258}
1259
1da177e4
LT		 1260static void __exit pdc_ata_exit(void)
1261{
1262 pci_unregister_driver(&pdc_ata_pci_driver);
1263}
1264
1da177e4 1265MODULE_AUTHOR("Jeff Garzik");
f497ba73 1266MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1da177e4
LT		 1267MODULE_LICENSE("GPL");
1268MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1269MODULE_VERSION(DRV_VERSION);
1270
1271module_init(pdc_ata_init);
1272module_exit(pdc_ata_exit);
Linux kernel - Deliverables
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