Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5595ddf9 | 5 | * Mikael Pettersson <mikpe@it.uu.se> |
1da177e4 LT |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003-2004 Red Hat, Inc. | |
10 | * | |
1da177e4 | 11 | * |
af36d7f0 JG |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware information only available under NDA. | |
1da177e4 LT |
31 | * |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
a9524a76 | 41 | #include <linux/device.h> |
95006188 | 42 | #include <scsi/scsi.h> |
1da177e4 | 43 | #include <scsi/scsi_host.h> |
193515d5 | 44 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 45 | #include <linux/libata.h> |
1da177e4 LT |
46 | #include "sata_promise.h" |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
c07a9c49 | 49 | #define DRV_VERSION "2.12" |
1da177e4 LT |
50 | |
51 | enum { | |
eca25dca | 52 | PDC_MAX_PORTS = 4, |
0d5ff566 | 53 | PDC_MMIO_BAR = 3, |
b9ccd4a9 | 54 | PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ |
0d5ff566 | 55 | |
821d22cd MP |
56 | /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ |
57 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
58 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
59 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
60 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ | |
61 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ | |
62 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
63 | ||
64 | /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */ | |
95006188 MP |
65 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ |
66 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
67 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
68 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
69 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
70 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
71 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 72 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 | 73 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
1da177e4 LT |
74 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
75 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
821d22cd MP |
76 | |
77 | /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ | |
78 | PDC_PHYMODE4 = 0x14, | |
1da177e4 | 79 | |
176efb05 MP |
80 | /* PDC_GLOBAL_CTL bit definitions */ |
81 | PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ | |
82 | PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ | |
83 | PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ | |
84 | PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ | |
85 | PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ | |
86 | PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ | |
87 | PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ | |
88 | PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ | |
89 | PDC_DRIVE_ERR = (1 << 21), /* drive error */ | |
90 | PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ | |
91 | PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ | |
92 | PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, | |
5796d1c4 JG |
93 | PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | |
94 | PDC2_ATA_DMA_CNT_ERR, | |
95 | PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | | |
96 | PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | | |
97 | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | | |
98 | PDC1_ERR_MASK | PDC2_ERR_MASK, | |
1da177e4 LT |
99 | |
100 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
eca25dca TH |
101 | board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ |
102 | board_20319 = 2, /* FastTrak S150 TX4 */ | |
103 | board_20619 = 3, /* FastTrak TX4000 */ | |
104 | board_2057x = 4, /* SATAII150 Tx2plus */ | |
d0e58031 | 105 | board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ |
eca25dca | 106 | board_40518 = 6, /* SATAII150 Tx4 */ |
1da177e4 | 107 | |
6340f019 | 108 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 109 | |
95006188 MP |
110 | /* Sequence counter control registers bit definitions */ |
111 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
112 | ||
113 | /* Feature register values */ | |
114 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
115 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
116 | ||
117 | /* Device/Head register values */ | |
118 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
119 | ||
25b93d81 MP |
120 | /* PDC_CTLSTAT bit definitions */ |
121 | PDC_DMA_ENABLE = (1 << 7), | |
122 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 123 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 124 | |
25b93d81 | 125 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 126 | ATA_FLAG_MMIO | |
3d0a59c0 | 127 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 | 128 | |
eca25dca TH |
129 | /* ap->flags bits */ |
130 | PDC_FLAG_GEN_II = (1 << 24), | |
131 | PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ | |
132 | PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ | |
1da177e4 LT |
133 | }; |
134 | ||
1da177e4 LT |
135 | struct pdc_port_priv { |
136 | u8 *pkt; | |
137 | dma_addr_t pkt_dma; | |
138 | }; | |
139 | ||
82ef04fb TH |
140 | static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
141 | static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
7715a6f9 | 142 | static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
eca25dca TH |
143 | static int pdc_common_port_start(struct ata_port *ap); |
144 | static int pdc_sata_port_start(struct ata_port *ap); | |
1da177e4 | 145 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
146 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
147 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 | 148 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
724114a5 | 149 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); |
1da177e4 | 150 | static void pdc_irq_clear(struct ata_port *ap); |
9363c382 | 151 | static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc); |
25b93d81 | 152 | static void pdc_freeze(struct ata_port *ap); |
c07a9c49 | 153 | static void pdc_sata_freeze(struct ata_port *ap); |
25b93d81 | 154 | static void pdc_thaw(struct ata_port *ap); |
c07a9c49 | 155 | static void pdc_sata_thaw(struct ata_port *ap); |
cadef677 MP |
156 | static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, |
157 | unsigned long deadline); | |
158 | static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, | |
159 | unsigned long deadline); | |
a1efdaba | 160 | static void pdc_error_handler(struct ata_port *ap); |
25b93d81 | 161 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); |
724114a5 MP |
162 | static int pdc_pata_cable_detect(struct ata_port *ap); |
163 | static int pdc_sata_cable_detect(struct ata_port *ap); | |
374b1873 | 164 | |
193515d5 | 165 | static struct scsi_host_template pdc_ata_sht = { |
68d1d07b | 166 | ATA_BASE_SHT(DRV_NAME), |
b9ccd4a9 | 167 | .sg_tablesize = PDC_MAX_PRD, |
1da177e4 | 168 | .dma_boundary = ATA_DMA_BOUNDARY, |
1da177e4 LT |
169 | }; |
170 | ||
029cfd6b TH |
171 | static const struct ata_port_operations pdc_common_ops = { |
172 | .inherits = &ata_sff_port_ops, | |
173 | ||
5682ed33 TH |
174 | .sff_tf_load = pdc_tf_load_mmio, |
175 | .sff_exec_command = pdc_exec_command_mmio, | |
95006188 | 176 | .check_atapi_dma = pdc_check_atapi_dma, |
95006188 | 177 | .qc_prep = pdc_qc_prep, |
9363c382 | 178 | .qc_issue = pdc_qc_issue, |
5682ed33 | 179 | .sff_irq_clear = pdc_irq_clear, |
95006188 | 180 | |
029cfd6b | 181 | .post_internal_cmd = pdc_post_internal_cmd, |
a1efdaba | 182 | .error_handler = pdc_error_handler, |
95006188 MP |
183 | }; |
184 | ||
029cfd6b TH |
185 | static struct ata_port_operations pdc_sata_ops = { |
186 | .inherits = &pdc_common_ops, | |
187 | .cable_detect = pdc_sata_cable_detect, | |
c07a9c49 MP |
188 | .freeze = pdc_sata_freeze, |
189 | .thaw = pdc_sata_thaw, | |
1da177e4 LT |
190 | .scr_read = pdc_sata_scr_read, |
191 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 192 | .port_start = pdc_sata_port_start, |
cadef677 | 193 | .hardreset = pdc_sata_hardreset, |
1da177e4 LT |
194 | }; |
195 | ||
029cfd6b TH |
196 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ |
197 | static struct ata_port_operations pdc_old_sata_ops = { | |
198 | .inherits = &pdc_sata_ops, | |
199 | .check_atapi_dma = pdc_old_sata_check_atapi_dma, | |
200 | }; | |
2cba582a | 201 | |
029cfd6b TH |
202 | static struct ata_port_operations pdc_pata_ops = { |
203 | .inherits = &pdc_common_ops, | |
204 | .cable_detect = pdc_pata_cable_detect, | |
5387373b MP |
205 | .freeze = pdc_freeze, |
206 | .thaw = pdc_thaw, | |
eca25dca | 207 | .port_start = pdc_common_port_start, |
cadef677 | 208 | .softreset = pdc_pata_softreset, |
2cba582a JG |
209 | }; |
210 | ||
98ac62de | 211 | static const struct ata_port_info pdc_port_info[] = { |
5595ddf9 | 212 | [board_2037x] = |
1da177e4 | 213 | { |
eca25dca TH |
214 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
215 | PDC_FLAG_SATA_PATA, | |
1da177e4 LT |
216 | .pio_mask = 0x1f, /* pio0-4 */ |
217 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 218 | .udma_mask = ATA_UDMA6, |
95006188 | 219 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
220 | }, |
221 | ||
5595ddf9 | 222 | [board_2037x_pata] = |
eca25dca TH |
223 | { |
224 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, | |
225 | .pio_mask = 0x1f, /* pio0-4 */ | |
226 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 227 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
228 | .port_ops = &pdc_pata_ops, |
229 | }, | |
230 | ||
5595ddf9 | 231 | [board_20319] = |
1da177e4 | 232 | { |
eca25dca TH |
233 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
234 | PDC_FLAG_4_PORTS, | |
1da177e4 LT |
235 | .pio_mask = 0x1f, /* pio0-4 */ |
236 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 237 | .udma_mask = ATA_UDMA6, |
95006188 | 238 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 239 | }, |
f497ba73 | 240 | |
5595ddf9 | 241 | [board_20619] = |
f497ba73 | 242 | { |
eca25dca TH |
243 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
244 | PDC_FLAG_4_PORTS, | |
f497ba73 TL |
245 | .pio_mask = 0x1f, /* pio0-4 */ |
246 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 247 | .udma_mask = ATA_UDMA6, |
2cba582a | 248 | .port_ops = &pdc_pata_ops, |
f497ba73 | 249 | }, |
5a46fe89 | 250 | |
5595ddf9 | 251 | [board_2057x] = |
6340f019 | 252 | { |
eca25dca TH |
253 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
254 | PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, | |
6340f019 LK |
255 | .pio_mask = 0x1f, /* pio0-4 */ |
256 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 257 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
258 | .port_ops = &pdc_sata_ops, |
259 | }, | |
260 | ||
5595ddf9 | 261 | [board_2057x_pata] = |
eca25dca | 262 | { |
bb312235 | 263 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
eca25dca TH |
264 | PDC_FLAG_GEN_II, |
265 | .pio_mask = 0x1f, /* pio0-4 */ | |
266 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 267 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
268 | .port_ops = &pdc_pata_ops, |
269 | }, | |
270 | ||
5595ddf9 | 271 | [board_40518] = |
6340f019 | 272 | { |
eca25dca TH |
273 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
274 | PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, | |
6340f019 LK |
275 | .pio_mask = 0x1f, /* pio0-4 */ |
276 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 277 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
278 | .port_ops = &pdc_sata_ops, |
279 | }, | |
1da177e4 LT |
280 | }; |
281 | ||
3b7d697d | 282 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 283 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
284 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
285 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
286 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
287 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
288 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 289 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 290 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 291 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 292 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
293 | |
294 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
295 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
7f9992a2 MP |
296 | { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, |
297 | { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, | |
b2d1eee1 | 298 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
299 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
300 | ||
301 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 302 | |
1da177e4 LT |
303 | { } /* terminate list */ |
304 | }; | |
305 | ||
1da177e4 LT |
306 | static struct pci_driver pdc_ata_pci_driver = { |
307 | .name = DRV_NAME, | |
308 | .id_table = pdc_ata_pci_tbl, | |
309 | .probe = pdc_ata_init_one, | |
310 | .remove = ata_pci_remove_one, | |
311 | }; | |
312 | ||
724114a5 | 313 | static int pdc_common_port_start(struct ata_port *ap) |
1da177e4 | 314 | { |
cca3974e | 315 | struct device *dev = ap->host->dev; |
1da177e4 LT |
316 | struct pdc_port_priv *pp; |
317 | int rc; | |
318 | ||
319 | rc = ata_port_start(ap); | |
320 | if (rc) | |
321 | return rc; | |
322 | ||
24dc5f33 TH |
323 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
324 | if (!pp) | |
325 | return -ENOMEM; | |
1da177e4 | 326 | |
24dc5f33 TH |
327 | pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); |
328 | if (!pp->pkt) | |
329 | return -ENOMEM; | |
1da177e4 LT |
330 | |
331 | ap->private_data = pp; | |
332 | ||
724114a5 MP |
333 | return 0; |
334 | } | |
335 | ||
336 | static int pdc_sata_port_start(struct ata_port *ap) | |
337 | { | |
724114a5 MP |
338 | int rc; |
339 | ||
340 | rc = pdc_common_port_start(ap); | |
341 | if (rc) | |
342 | return rc; | |
343 | ||
599b7202 | 344 | /* fix up PHYMODE4 align timing */ |
eca25dca | 345 | if (ap->flags & PDC_FLAG_GEN_II) { |
821d22cd | 346 | void __iomem *sata_mmio = ap->ioaddr.scr_addr; |
599b7202 MP |
347 | unsigned int tmp; |
348 | ||
821d22cd | 349 | tmp = readl(sata_mmio + PDC_PHYMODE4); |
599b7202 | 350 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ |
821d22cd | 351 | writel(tmp, sata_mmio + PDC_PHYMODE4); |
599b7202 MP |
352 | } |
353 | ||
1da177e4 | 354 | return 0; |
1da177e4 LT |
355 | } |
356 | ||
1da177e4 LT |
357 | static void pdc_reset_port(struct ata_port *ap) |
358 | { | |
821d22cd | 359 | void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
360 | unsigned int i; |
361 | u32 tmp; | |
362 | ||
363 | for (i = 11; i > 0; i--) { | |
821d22cd | 364 | tmp = readl(ata_ctlstat_mmio); |
1da177e4 LT |
365 | if (tmp & PDC_RESET) |
366 | break; | |
367 | ||
368 | udelay(100); | |
369 | ||
370 | tmp |= PDC_RESET; | |
821d22cd | 371 | writel(tmp, ata_ctlstat_mmio); |
1da177e4 LT |
372 | } |
373 | ||
374 | tmp &= ~PDC_RESET; | |
821d22cd MP |
375 | writel(tmp, ata_ctlstat_mmio); |
376 | readl(ata_ctlstat_mmio); /* flush */ | |
1da177e4 LT |
377 | } |
378 | ||
724114a5 | 379 | static int pdc_pata_cable_detect(struct ata_port *ap) |
2cba582a | 380 | { |
d3fb4e8d | 381 | u8 tmp; |
821d22cd | 382 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
d3fb4e8d | 383 | |
821d22cd | 384 | tmp = readb(ata_mmio + PDC_CTLSTAT + 3); |
724114a5 MP |
385 | if (tmp & 0x01) |
386 | return ATA_CBL_PATA40; | |
387 | return ATA_CBL_PATA80; | |
388 | } | |
389 | ||
390 | static int pdc_sata_cable_detect(struct ata_port *ap) | |
391 | { | |
e2a9752a | 392 | return ATA_CBL_SATA; |
d3fb4e8d | 393 | } |
2cba582a | 394 | |
82ef04fb TH |
395 | static int pdc_sata_scr_read(struct ata_link *link, |
396 | unsigned int sc_reg, u32 *val) | |
1da177e4 | 397 | { |
724114a5 | 398 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 399 | return -EINVAL; |
82ef04fb | 400 | *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 401 | return 0; |
1da177e4 LT |
402 | } |
403 | ||
82ef04fb TH |
404 | static int pdc_sata_scr_write(struct ata_link *link, |
405 | unsigned int sc_reg, u32 val) | |
1da177e4 | 406 | { |
724114a5 | 407 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 408 | return -EINVAL; |
82ef04fb | 409 | writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 410 | return 0; |
1da177e4 LT |
411 | } |
412 | ||
fba6edbd | 413 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 414 | { |
4113bb6b MP |
415 | struct ata_port *ap = qc->ap; |
416 | dma_addr_t sg_table = ap->prd_dma; | |
417 | unsigned int cdb_len = qc->dev->cdb_len; | |
418 | u8 *cdb = qc->cdb; | |
419 | struct pdc_port_priv *pp = ap->private_data; | |
420 | u8 *buf = pp->pkt; | |
826cd156 | 421 | __le32 *buf32 = (__le32 *) buf; |
46a67143 | 422 | unsigned int dev_sel, feature; |
95006188 MP |
423 | |
424 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
425 | * and seq id (byte 2) | |
426 | */ | |
fba6edbd | 427 | switch (qc->tf.protocol) { |
0dc36888 | 428 | case ATAPI_PROT_DMA: |
fba6edbd MP |
429 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
430 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
431 | else | |
432 | buf32[0] = 0; | |
433 | break; | |
0dc36888 | 434 | case ATAPI_PROT_NODATA: |
fba6edbd MP |
435 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); |
436 | break; | |
437 | default: | |
438 | BUG(); | |
439 | break; | |
440 | } | |
95006188 MP |
441 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
442 | buf32[2] = 0; /* no next-packet */ | |
443 | ||
4113bb6b | 444 | /* select drive */ |
46a67143 | 445 | if (sata_scr_valid(&ap->link)) |
4113bb6b | 446 | dev_sel = PDC_DEVICE_SATA; |
46a67143 TH |
447 | else |
448 | dev_sel = qc->tf.device; | |
449 | ||
4113bb6b MP |
450 | buf[12] = (1 << 5) | ATA_REG_DEVICE; |
451 | buf[13] = dev_sel; | |
452 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
453 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
454 | ||
455 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
46a67143 | 456 | buf[17] = qc->tf.nsect; |
4113bb6b | 457 | buf[18] = (1 << 5) | ATA_REG_LBAL; |
46a67143 | 458 | buf[19] = qc->tf.lbal; |
4113bb6b MP |
459 | |
460 | /* set feature and byte counter registers */ | |
0dc36888 | 461 | if (qc->tf.protocol != ATAPI_PROT_DMA) |
4113bb6b | 462 | feature = PDC_FEATURE_ATAPI_PIO; |
46a67143 | 463 | else |
4113bb6b | 464 | feature = PDC_FEATURE_ATAPI_DMA; |
46a67143 | 465 | |
4113bb6b MP |
466 | buf[20] = (1 << 5) | ATA_REG_FEATURE; |
467 | buf[21] = feature; | |
468 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
46a67143 | 469 | buf[23] = qc->tf.lbam; |
4113bb6b | 470 | buf[24] = (1 << 5) | ATA_REG_BYTEH; |
46a67143 | 471 | buf[25] = qc->tf.lbah; |
4113bb6b MP |
472 | |
473 | /* send ATAPI packet command 0xA0 */ | |
474 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
46a67143 | 475 | buf[27] = qc->tf.command; |
4113bb6b MP |
476 | |
477 | /* select drive and check DRQ */ | |
478 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
479 | buf[29] = dev_sel; | |
480 | ||
95006188 MP |
481 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
482 | BUG_ON(cdb_len & ~0x1E); | |
483 | ||
4113bb6b MP |
484 | /* append the CDB as the final part */ |
485 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
486 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
487 | } |
488 | ||
b9ccd4a9 MP |
489 | /** |
490 | * pdc_fill_sg - Fill PCI IDE PRD table | |
491 | * @qc: Metadata associated with taskfile to be transferred | |
492 | * | |
493 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
494 | * associated with the current disk command. | |
495 | * Make sure hardware does not choke on it. | |
496 | * | |
497 | * LOCKING: | |
498 | * spin_lock_irqsave(host lock) | |
499 | * | |
500 | */ | |
501 | static void pdc_fill_sg(struct ata_queued_cmd *qc) | |
502 | { | |
503 | struct ata_port *ap = qc->ap; | |
504 | struct scatterlist *sg; | |
b9ccd4a9 | 505 | const u32 SG_COUNT_ASIC_BUG = 41*4; |
ff2aeb1e TH |
506 | unsigned int si, idx; |
507 | u32 len; | |
b9ccd4a9 MP |
508 | |
509 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
510 | return; | |
511 | ||
b9ccd4a9 | 512 | idx = 0; |
ff2aeb1e | 513 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
b9ccd4a9 | 514 | u32 addr, offset; |
6903c0f7 | 515 | u32 sg_len; |
b9ccd4a9 MP |
516 | |
517 | /* determine if physical DMA addr spans 64K boundary. | |
518 | * Note h/w doesn't support 64-bit, so we unconditionally | |
519 | * truncate dma_addr_t to u32. | |
520 | */ | |
521 | addr = (u32) sg_dma_address(sg); | |
522 | sg_len = sg_dma_len(sg); | |
523 | ||
524 | while (sg_len) { | |
525 | offset = addr & 0xffff; | |
526 | len = sg_len; | |
527 | if ((offset + sg_len) > 0x10000) | |
528 | len = 0x10000 - offset; | |
529 | ||
530 | ap->prd[idx].addr = cpu_to_le32(addr); | |
531 | ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff); | |
532 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); | |
533 | ||
534 | idx++; | |
535 | sg_len -= len; | |
536 | addr += len; | |
537 | } | |
538 | } | |
539 | ||
ff2aeb1e | 540 | len = le32_to_cpu(ap->prd[idx - 1].flags_len); |
b9ccd4a9 | 541 | |
ff2aeb1e TH |
542 | if (len > SG_COUNT_ASIC_BUG) { |
543 | u32 addr; | |
b9ccd4a9 | 544 | |
ff2aeb1e | 545 | VPRINTK("Splitting last PRD.\n"); |
b9ccd4a9 | 546 | |
ff2aeb1e TH |
547 | addr = le32_to_cpu(ap->prd[idx - 1].addr); |
548 | ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); | |
549 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG); | |
b9ccd4a9 | 550 | |
ff2aeb1e TH |
551 | addr = addr + len - SG_COUNT_ASIC_BUG; |
552 | len = SG_COUNT_ASIC_BUG; | |
553 | ap->prd[idx].addr = cpu_to_le32(addr); | |
554 | ap->prd[idx].flags_len = cpu_to_le32(len); | |
555 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); | |
b9ccd4a9 | 556 | |
ff2aeb1e | 557 | idx++; |
b9ccd4a9 | 558 | } |
ff2aeb1e TH |
559 | |
560 | ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
b9ccd4a9 MP |
561 | } |
562 | ||
1da177e4 LT |
563 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
564 | { | |
565 | struct pdc_port_priv *pp = qc->ap->private_data; | |
566 | unsigned int i; | |
567 | ||
568 | VPRINTK("ENTER\n"); | |
569 | ||
570 | switch (qc->tf.protocol) { | |
571 | case ATA_PROT_DMA: | |
b9ccd4a9 | 572 | pdc_fill_sg(qc); |
7715a6f9 | 573 | /*FALLTHROUGH*/ |
1da177e4 LT |
574 | case ATA_PROT_NODATA: |
575 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
576 | qc->dev->devno, pp->pkt); | |
1da177e4 LT |
577 | if (qc->tf.flags & ATA_TFLAG_LBA48) |
578 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
579 | else | |
580 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
1da177e4 LT |
581 | pdc_pkt_footer(&qc->tf, pp->pkt, i); |
582 | break; | |
0dc36888 | 583 | case ATAPI_PROT_PIO: |
b9ccd4a9 | 584 | pdc_fill_sg(qc); |
95006188 | 585 | break; |
0dc36888 | 586 | case ATAPI_PROT_DMA: |
b9ccd4a9 | 587 | pdc_fill_sg(qc); |
fba6edbd | 588 | /*FALLTHROUGH*/ |
0dc36888 | 589 | case ATAPI_PROT_NODATA: |
fba6edbd | 590 | pdc_atapi_pkt(qc); |
95006188 | 591 | break; |
1da177e4 LT |
592 | default: |
593 | break; | |
594 | } | |
595 | } | |
596 | ||
c07a9c49 MP |
597 | static int pdc_is_sataii_tx4(unsigned long flags) |
598 | { | |
599 | const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; | |
600 | return (flags & mask) == mask; | |
601 | } | |
602 | ||
603 | static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, | |
604 | int is_sataii_tx4) | |
605 | { | |
606 | static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; | |
607 | return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; | |
608 | } | |
609 | ||
610 | static unsigned int pdc_sata_nr_ports(const struct ata_port *ap) | |
611 | { | |
612 | return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2; | |
613 | } | |
614 | ||
615 | static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap) | |
616 | { | |
617 | const struct ata_host *host = ap->host; | |
618 | unsigned int nr_ports = pdc_sata_nr_ports(ap); | |
619 | unsigned int i; | |
620 | ||
7715a6f9 | 621 | for (i = 0; i < nr_ports && host->ports[i] != ap; ++i) |
c07a9c49 MP |
622 | ; |
623 | BUG_ON(i >= nr_ports); | |
624 | return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); | |
625 | } | |
626 | ||
627 | static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap) | |
628 | { | |
629 | return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR; | |
630 | } | |
631 | ||
25b93d81 MP |
632 | static void pdc_freeze(struct ata_port *ap) |
633 | { | |
821d22cd | 634 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
635 | u32 tmp; |
636 | ||
821d22cd | 637 | tmp = readl(ata_mmio + PDC_CTLSTAT); |
25b93d81 MP |
638 | tmp |= PDC_IRQ_DISABLE; |
639 | tmp &= ~PDC_DMA_ENABLE; | |
821d22cd MP |
640 | writel(tmp, ata_mmio + PDC_CTLSTAT); |
641 | readl(ata_mmio + PDC_CTLSTAT); /* flush */ | |
25b93d81 MP |
642 | } |
643 | ||
c07a9c49 MP |
644 | static void pdc_sata_freeze(struct ata_port *ap) |
645 | { | |
646 | struct ata_host *host = ap->host; | |
647 | void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; | |
648 | unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); | |
649 | unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); | |
650 | u32 hotplug_status; | |
651 | ||
652 | /* Disable hotplug events on this port. | |
653 | * | |
654 | * Locking: | |
655 | * 1) hotplug register accesses must be serialised via host->lock | |
656 | * 2) ap->lock == &ap->host->lock | |
657 | * 3) ->freeze() and ->thaw() are called with ap->lock held | |
658 | */ | |
659 | hotplug_status = readl(host_mmio + hotplug_offset); | |
660 | hotplug_status |= 0x11 << (ata_no + 16); | |
661 | writel(hotplug_status, host_mmio + hotplug_offset); | |
662 | readl(host_mmio + hotplug_offset); /* flush */ | |
663 | ||
664 | pdc_freeze(ap); | |
665 | } | |
666 | ||
25b93d81 MP |
667 | static void pdc_thaw(struct ata_port *ap) |
668 | { | |
821d22cd | 669 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
670 | u32 tmp; |
671 | ||
672 | /* clear IRQ */ | |
821d22cd | 673 | readl(ata_mmio + PDC_COMMAND); |
25b93d81 MP |
674 | |
675 | /* turn IRQ back on */ | |
821d22cd | 676 | tmp = readl(ata_mmio + PDC_CTLSTAT); |
25b93d81 | 677 | tmp &= ~PDC_IRQ_DISABLE; |
821d22cd MP |
678 | writel(tmp, ata_mmio + PDC_CTLSTAT); |
679 | readl(ata_mmio + PDC_CTLSTAT); /* flush */ | |
25b93d81 MP |
680 | } |
681 | ||
c07a9c49 MP |
682 | static void pdc_sata_thaw(struct ata_port *ap) |
683 | { | |
684 | struct ata_host *host = ap->host; | |
685 | void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; | |
686 | unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); | |
687 | unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); | |
688 | u32 hotplug_status; | |
689 | ||
690 | pdc_thaw(ap); | |
691 | ||
692 | /* Enable hotplug events on this port. | |
693 | * Locking: see pdc_sata_freeze(). | |
694 | */ | |
695 | hotplug_status = readl(host_mmio + hotplug_offset); | |
696 | hotplug_status |= 0x11 << ata_no; | |
697 | hotplug_status &= ~(0x11 << (ata_no + 16)); | |
698 | writel(hotplug_status, host_mmio + hotplug_offset); | |
699 | readl(host_mmio + hotplug_offset); /* flush */ | |
700 | } | |
701 | ||
cadef677 MP |
702 | static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, |
703 | unsigned long deadline) | |
704 | { | |
705 | pdc_reset_port(link->ap); | |
706 | return ata_sff_softreset(link, class, deadline); | |
707 | } | |
708 | ||
709 | static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, | |
710 | unsigned long deadline) | |
711 | { | |
712 | pdc_reset_port(link->ap); | |
713 | return sata_sff_hardreset(link, class, deadline); | |
714 | } | |
715 | ||
a1efdaba | 716 | static void pdc_error_handler(struct ata_port *ap) |
25b93d81 | 717 | { |
25b93d81 MP |
718 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) |
719 | pdc_reset_port(ap); | |
720 | ||
a1efdaba | 721 | ata_std_error_handler(ap); |
724114a5 MP |
722 | } |
723 | ||
25b93d81 MP |
724 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) |
725 | { | |
726 | struct ata_port *ap = qc->ap; | |
727 | ||
25b93d81 | 728 | /* make DMA engine forget about the failed command */ |
a51d644a | 729 | if (qc->flags & ATA_QCFLAG_FAILED) |
25b93d81 MP |
730 | pdc_reset_port(ap); |
731 | } | |
732 | ||
176efb05 MP |
733 | static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, |
734 | u32 port_status, u32 err_mask) | |
735 | { | |
9af5c9c9 | 736 | struct ata_eh_info *ehi = &ap->link.eh_info; |
176efb05 MP |
737 | unsigned int ac_err_mask = 0; |
738 | ||
739 | ata_ehi_clear_desc(ehi); | |
740 | ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); | |
741 | port_status &= err_mask; | |
742 | ||
743 | if (port_status & PDC_DRIVE_ERR) | |
744 | ac_err_mask |= AC_ERR_DEV; | |
745 | if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) | |
746 | ac_err_mask |= AC_ERR_HSM; | |
747 | if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) | |
748 | ac_err_mask |= AC_ERR_ATA_BUS; | |
749 | if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR | |
750 | | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) | |
751 | ac_err_mask |= AC_ERR_HOST_BUS; | |
752 | ||
936fd732 | 753 | if (sata_scr_valid(&ap->link)) { |
da3dbb17 TH |
754 | u32 serror; |
755 | ||
82ef04fb | 756 | pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror); |
da3dbb17 TH |
757 | ehi->serror |= serror; |
758 | } | |
ce2d3abc | 759 | |
176efb05 | 760 | qc->err_mask |= ac_err_mask; |
ce2d3abc MP |
761 | |
762 | pdc_reset_port(ap); | |
8ffcfd9d MP |
763 | |
764 | ata_port_abort(ap); | |
176efb05 MP |
765 | } |
766 | ||
7715a6f9 MP |
767 | static unsigned int pdc_host_intr(struct ata_port *ap, |
768 | struct ata_queued_cmd *qc) | |
1da177e4 | 769 | { |
a22e2eb0 | 770 | unsigned int handled = 0; |
821d22cd | 771 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
176efb05 MP |
772 | u32 port_status, err_mask; |
773 | ||
774 | err_mask = PDC_ERR_MASK; | |
eca25dca | 775 | if (ap->flags & PDC_FLAG_GEN_II) |
176efb05 MP |
776 | err_mask &= ~PDC1_ERR_MASK; |
777 | else | |
778 | err_mask &= ~PDC2_ERR_MASK; | |
821d22cd | 779 | port_status = readl(ata_mmio + PDC_GLOBAL_CTL); |
176efb05 MP |
780 | if (unlikely(port_status & err_mask)) { |
781 | pdc_error_intr(ap, qc, port_status, err_mask); | |
782 | return 1; | |
1da177e4 LT |
783 | } |
784 | ||
785 | switch (qc->tf.protocol) { | |
786 | case ATA_PROT_DMA: | |
787 | case ATA_PROT_NODATA: | |
0dc36888 TH |
788 | case ATAPI_PROT_DMA: |
789 | case ATAPI_PROT_NODATA: | |
a22e2eb0 AL |
790 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
791 | ata_qc_complete(qc); | |
1da177e4 LT |
792 | handled = 1; |
793 | break; | |
d0e58031 | 794 | default: |
ee500aab AL |
795 | ap->stats.idle_irq++; |
796 | break; | |
d0e58031 | 797 | } |
1da177e4 | 798 | |
ee500aab | 799 | return handled; |
1da177e4 LT |
800 | } |
801 | ||
802 | static void pdc_irq_clear(struct ata_port *ap) | |
803 | { | |
821d22cd | 804 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
1da177e4 | 805 | |
821d22cd | 806 | readl(ata_mmio + PDC_COMMAND); |
1da177e4 LT |
807 | } |
808 | ||
5796d1c4 | 809 | static irqreturn_t pdc_interrupt(int irq, void *dev_instance) |
1da177e4 | 810 | { |
cca3974e | 811 | struct ata_host *host = dev_instance; |
1da177e4 LT |
812 | struct ata_port *ap; |
813 | u32 mask = 0; | |
814 | unsigned int i, tmp; | |
815 | unsigned int handled = 0; | |
821d22cd | 816 | void __iomem *host_mmio; |
a77720ad MP |
817 | unsigned int hotplug_offset, ata_no; |
818 | u32 hotplug_status; | |
819 | int is_sataii_tx4; | |
1da177e4 LT |
820 | |
821 | VPRINTK("ENTER\n"); | |
822 | ||
0d5ff566 | 823 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
1da177e4 LT |
824 | VPRINTK("QUICK EXIT\n"); |
825 | return IRQ_NONE; | |
826 | } | |
827 | ||
821d22cd | 828 | host_mmio = host->iomap[PDC_MMIO_BAR]; |
1da177e4 | 829 | |
c07a9c49 MP |
830 | spin_lock(&host->lock); |
831 | ||
a77720ad MP |
832 | /* read and clear hotplug flags for all ports */ |
833 | if (host->ports[0]->flags & PDC_FLAG_GEN_II) | |
834 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
835 | else | |
836 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
821d22cd | 837 | hotplug_status = readl(host_mmio + hotplug_offset); |
a77720ad | 838 | if (hotplug_status & 0xff) |
821d22cd | 839 | writel(hotplug_status | 0xff, host_mmio + hotplug_offset); |
a77720ad MP |
840 | hotplug_status &= 0xff; /* clear uninteresting bits */ |
841 | ||
1da177e4 | 842 | /* reading should also clear interrupts */ |
821d22cd | 843 | mask = readl(host_mmio + PDC_INT_SEQMASK); |
1da177e4 | 844 | |
a77720ad | 845 | if (mask == 0xffffffff && hotplug_status == 0) { |
1da177e4 | 846 | VPRINTK("QUICK EXIT 2\n"); |
c07a9c49 | 847 | goto done_irq; |
1da177e4 | 848 | } |
6340f019 | 849 | |
7715a6f9 | 850 | mask &= 0xffff; /* only 16 SEQIDs possible */ |
a77720ad | 851 | if (mask == 0 && hotplug_status == 0) { |
1da177e4 | 852 | VPRINTK("QUICK EXIT 3\n"); |
6340f019 | 853 | goto done_irq; |
1da177e4 LT |
854 | } |
855 | ||
821d22cd | 856 | writel(mask, host_mmio + PDC_INT_SEQMASK); |
1da177e4 | 857 | |
a77720ad MP |
858 | is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); |
859 | ||
cca3974e | 860 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 861 | VPRINTK("port %u\n", i); |
cca3974e | 862 | ap = host->ports[i]; |
a77720ad MP |
863 | |
864 | /* check for a plug or unplug event */ | |
865 | ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); | |
866 | tmp = hotplug_status & (0x11 << ata_no); | |
867 | if (tmp && ap && | |
868 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
9af5c9c9 | 869 | struct ata_eh_info *ehi = &ap->link.eh_info; |
a77720ad MP |
870 | ata_ehi_clear_desc(ehi); |
871 | ata_ehi_hotplugged(ehi); | |
872 | ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); | |
873 | ata_port_freeze(ap); | |
874 | ++handled; | |
875 | continue; | |
876 | } | |
877 | ||
878 | /* check for a packet interrupt */ | |
1da177e4 | 879 | tmp = mask & (1 << (i + 1)); |
c1389503 | 880 | if (tmp && ap && |
029f5468 | 881 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
882 | struct ata_queued_cmd *qc; |
883 | ||
9af5c9c9 | 884 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
e50362ec | 885 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
886 | handled += pdc_host_intr(ap, qc); |
887 | } | |
888 | } | |
889 | ||
1da177e4 LT |
890 | VPRINTK("EXIT\n"); |
891 | ||
6340f019 | 892 | done_irq: |
cca3974e | 893 | spin_unlock(&host->lock); |
1da177e4 LT |
894 | return IRQ_RETVAL(handled); |
895 | } | |
896 | ||
7715a6f9 | 897 | static void pdc_packet_start(struct ata_queued_cmd *qc) |
1da177e4 LT |
898 | { |
899 | struct ata_port *ap = qc->ap; | |
900 | struct pdc_port_priv *pp = ap->private_data; | |
821d22cd MP |
901 | void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; |
902 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; | |
1da177e4 LT |
903 | unsigned int port_no = ap->port_no; |
904 | u8 seq = (u8) (port_no + 1); | |
905 | ||
906 | VPRINTK("ENTER, ap %p\n", ap); | |
907 | ||
821d22cd MP |
908 | writel(0x00000001, host_mmio + (seq * 4)); |
909 | readl(host_mmio + (seq * 4)); /* flush */ | |
1da177e4 LT |
910 | |
911 | pp->pkt[2] = seq; | |
912 | wmb(); /* flush PRD, pkt writes */ | |
821d22cd MP |
913 | writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT); |
914 | readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
915 | } |
916 | ||
9363c382 | 917 | static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
918 | { |
919 | switch (qc->tf.protocol) { | |
0dc36888 | 920 | case ATAPI_PROT_NODATA: |
fba6edbd MP |
921 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) |
922 | break; | |
923 | /*FALLTHROUGH*/ | |
51b94d2a TH |
924 | case ATA_PROT_NODATA: |
925 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
926 | break; | |
927 | /*FALLTHROUGH*/ | |
0dc36888 | 928 | case ATAPI_PROT_DMA: |
1da177e4 | 929 | case ATA_PROT_DMA: |
1da177e4 LT |
930 | pdc_packet_start(qc); |
931 | return 0; | |
1da177e4 LT |
932 | default: |
933 | break; | |
934 | } | |
9363c382 | 935 | return ata_sff_qc_issue(qc); |
1da177e4 LT |
936 | } |
937 | ||
057ace5e | 938 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 | 939 | { |
0dc36888 | 940 | WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); |
9363c382 | 941 | ata_sff_tf_load(ap, tf); |
1da177e4 LT |
942 | } |
943 | ||
5796d1c4 JG |
944 | static void pdc_exec_command_mmio(struct ata_port *ap, |
945 | const struct ata_taskfile *tf) | |
1da177e4 | 946 | { |
0dc36888 | 947 | WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); |
9363c382 | 948 | ata_sff_exec_command(ap, tf); |
1da177e4 LT |
949 | } |
950 | ||
95006188 MP |
951 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
952 | { | |
953 | u8 *scsicmd = qc->scsicmd->cmnd; | |
954 | int pio = 1; /* atapi dma off by default */ | |
955 | ||
956 | /* Whitelist commands that may use DMA. */ | |
957 | switch (scsicmd[0]) { | |
958 | case WRITE_12: | |
959 | case WRITE_10: | |
960 | case WRITE_6: | |
961 | case READ_12: | |
962 | case READ_10: | |
963 | case READ_6: | |
964 | case 0xad: /* READ_DVD_STRUCTURE */ | |
965 | case 0xbe: /* READ_CD */ | |
966 | pio = 0; | |
967 | } | |
968 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
969 | if (scsicmd[0] == WRITE_10) { | |
5796d1c4 JG |
970 | unsigned int lba = |
971 | (scsicmd[2] << 24) | | |
972 | (scsicmd[3] << 16) | | |
973 | (scsicmd[4] << 8) | | |
974 | scsicmd[5]; | |
95006188 MP |
975 | if (lba >= 0xFFFF4FA2) |
976 | pio = 1; | |
977 | } | |
978 | return pio; | |
979 | } | |
980 | ||
724114a5 | 981 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
95006188 | 982 | { |
95006188 | 983 | /* First generation chips cannot use ATAPI DMA on SATA ports */ |
724114a5 | 984 | return 1; |
95006188 | 985 | } |
1da177e4 | 986 | |
eca25dca TH |
987 | static void pdc_ata_setup_port(struct ata_port *ap, |
988 | void __iomem *base, void __iomem *scr_addr) | |
1da177e4 | 989 | { |
eca25dca TH |
990 | ap->ioaddr.cmd_addr = base; |
991 | ap->ioaddr.data_addr = base; | |
992 | ap->ioaddr.feature_addr = | |
993 | ap->ioaddr.error_addr = base + 0x4; | |
994 | ap->ioaddr.nsect_addr = base + 0x8; | |
995 | ap->ioaddr.lbal_addr = base + 0xc; | |
996 | ap->ioaddr.lbam_addr = base + 0x10; | |
997 | ap->ioaddr.lbah_addr = base + 0x14; | |
998 | ap->ioaddr.device_addr = base + 0x18; | |
999 | ap->ioaddr.command_addr = | |
1000 | ap->ioaddr.status_addr = base + 0x1c; | |
1001 | ap->ioaddr.altstatus_addr = | |
1002 | ap->ioaddr.ctl_addr = base + 0x38; | |
1003 | ap->ioaddr.scr_addr = scr_addr; | |
1da177e4 LT |
1004 | } |
1005 | ||
eca25dca | 1006 | static void pdc_host_init(struct ata_host *host) |
1da177e4 | 1007 | { |
821d22cd | 1008 | void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; |
eca25dca | 1009 | int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; |
d324d462 | 1010 | int hotplug_offset; |
1da177e4 LT |
1011 | u32 tmp; |
1012 | ||
eca25dca | 1013 | if (is_gen2) |
d324d462 MP |
1014 | hotplug_offset = PDC2_SATA_PLUG_CSR; |
1015 | else | |
1016 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
1017 | ||
1da177e4 LT |
1018 | /* |
1019 | * Except for the hotplug stuff, this is voodoo from the | |
1020 | * Promise driver. Label this entire section | |
1021 | * "TODO: figure out why we do this" | |
1022 | */ | |
1023 | ||
b2d1eee1 | 1024 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
821d22cd | 1025 | tmp = readl(host_mmio + PDC_FLASH_CTL); |
b2d1eee1 | 1026 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
eca25dca | 1027 | if (!is_gen2) |
b2d1eee1 | 1028 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ |
821d22cd | 1029 | writel(tmp, host_mmio + PDC_FLASH_CTL); |
1da177e4 LT |
1030 | |
1031 | /* clear plug/unplug flags for all ports */ | |
821d22cd MP |
1032 | tmp = readl(host_mmio + hotplug_offset); |
1033 | writel(tmp | 0xff, host_mmio + hotplug_offset); | |
1da177e4 | 1034 | |
a77720ad | 1035 | /* unmask plug/unplug ints */ |
821d22cd MP |
1036 | tmp = readl(host_mmio + hotplug_offset); |
1037 | writel(tmp & ~0xff0000, host_mmio + hotplug_offset); | |
1da177e4 | 1038 | |
b2d1eee1 | 1039 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
eca25dca | 1040 | if (is_gen2) |
b2d1eee1 MP |
1041 | return; |
1042 | ||
1da177e4 | 1043 | /* reduce TBG clock to 133 Mhz. */ |
821d22cd | 1044 | tmp = readl(host_mmio + PDC_TBG_MODE); |
1da177e4 LT |
1045 | tmp &= ~0x30000; /* clear bit 17, 16*/ |
1046 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
821d22cd | 1047 | writel(tmp, host_mmio + PDC_TBG_MODE); |
1da177e4 | 1048 | |
821d22cd | 1049 | readl(host_mmio + PDC_TBG_MODE); /* flush */ |
1da177e4 LT |
1050 | msleep(10); |
1051 | ||
1052 | /* adjust slew rate control register. */ | |
821d22cd | 1053 | tmp = readl(host_mmio + PDC_SLEW_CTL); |
1da177e4 LT |
1054 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ |
1055 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
821d22cd | 1056 | writel(tmp, host_mmio + PDC_SLEW_CTL); |
1da177e4 LT |
1057 | } |
1058 | ||
5796d1c4 JG |
1059 | static int pdc_ata_init_one(struct pci_dev *pdev, |
1060 | const struct pci_device_id *ent) | |
1da177e4 LT |
1061 | { |
1062 | static int printed_version; | |
eca25dca TH |
1063 | const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; |
1064 | const struct ata_port_info *ppi[PDC_MAX_PORTS]; | |
1065 | struct ata_host *host; | |
821d22cd | 1066 | void __iomem *host_mmio; |
eca25dca | 1067 | int n_ports, i, rc; |
5ac2fe57 | 1068 | int is_sataii_tx4; |
1da177e4 LT |
1069 | |
1070 | if (!printed_version++) | |
a9524a76 | 1071 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1072 | |
eca25dca | 1073 | /* enable and acquire resources */ |
24dc5f33 | 1074 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1075 | if (rc) |
1076 | return rc; | |
1077 | ||
0d5ff566 TH |
1078 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
1079 | if (rc == -EBUSY) | |
24dc5f33 | 1080 | pcim_pin_device(pdev); |
0d5ff566 | 1081 | if (rc) |
24dc5f33 | 1082 | return rc; |
821d22cd | 1083 | host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; |
1da177e4 | 1084 | |
eca25dca TH |
1085 | /* determine port configuration and setup host */ |
1086 | n_ports = 2; | |
1087 | if (pi->flags & PDC_FLAG_4_PORTS) | |
1088 | n_ports = 4; | |
1089 | for (i = 0; i < n_ports; i++) | |
1090 | ppi[i] = pi; | |
1da177e4 | 1091 | |
eca25dca | 1092 | if (pi->flags & PDC_FLAG_SATA_PATA) { |
821d22cd | 1093 | u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); |
d0e58031 | 1094 | if (!(tmp & 0x80)) |
eca25dca | 1095 | ppi[n_ports++] = pi + 1; |
eca25dca | 1096 | } |
1da177e4 | 1097 | |
eca25dca TH |
1098 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
1099 | if (!host) { | |
1100 | dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); | |
24dc5f33 | 1101 | return -ENOMEM; |
1da177e4 | 1102 | } |
eca25dca | 1103 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 | 1104 | |
d0e58031 | 1105 | is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); |
5ac2fe57 | 1106 | for (i = 0; i < host->n_ports; i++) { |
cbcdd875 | 1107 | struct ata_port *ap = host->ports[i]; |
d0e58031 | 1108 | unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); |
821d22cd | 1109 | unsigned int ata_offset = 0x200 + ata_no * 0x80; |
cbcdd875 TH |
1110 | unsigned int scr_offset = 0x400 + ata_no * 0x100; |
1111 | ||
821d22cd | 1112 | pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset); |
cbcdd875 TH |
1113 | |
1114 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); | |
821d22cd | 1115 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata"); |
5ac2fe57 | 1116 | } |
1da177e4 LT |
1117 | |
1118 | /* initialize adapter */ | |
eca25dca | 1119 | pdc_host_init(host); |
1da177e4 | 1120 | |
eca25dca TH |
1121 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1122 | if (rc) | |
1123 | return rc; | |
1124 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1125 | if (rc) | |
1126 | return rc; | |
1da177e4 | 1127 | |
eca25dca TH |
1128 | /* start host, request IRQ and attach */ |
1129 | pci_set_master(pdev); | |
1130 | return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, | |
1131 | &pdc_ata_sht); | |
1da177e4 LT |
1132 | } |
1133 | ||
1da177e4 LT |
1134 | static int __init pdc_ata_init(void) |
1135 | { | |
b7887196 | 1136 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1137 | } |
1138 | ||
1da177e4 LT |
1139 | static void __exit pdc_ata_exit(void) |
1140 | { | |
1141 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1142 | } | |
1143 | ||
1da177e4 | 1144 | MODULE_AUTHOR("Jeff Garzik"); |
f497ba73 | 1145 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1146 | MODULE_LICENSE("GPL"); |
1147 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1148 | MODULE_VERSION(DRV_VERSION); | |
1149 | ||
1150 | module_init(pdc_ata_init); | |
1151 | module_exit(pdc_ata_exit); |