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libata: fix spurious WARN_ON_ONCE() on port freeze
[deliverable/linux.git] / drivers / ata / sata_promise.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5595ddf9 5 * Mikael Pettersson <mikpe@it.uu.se>
1da177e4
LT		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
1da177e4 11 *
af36d7f0
JG		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
1da177e4
LT		 31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
a9524a76 41#include <linux/device.h>
95006188 42#include <scsi/scsi.h>
1da177e4 43#include <scsi/scsi_host.h>
193515d5 44#include <scsi/scsi_cmnd.h>
1da177e4 45#include <linux/libata.h>
1da177e4
LT		 46#include "sata_promise.h"
47
48#define DRV_NAME "sata_promise"
c07a9c49 49#define DRV_VERSION "2.12"
1da177e4
LT		 50
51enum {
eca25dca 52 PDC_MAX_PORTS = 4,
0d5ff566 53 PDC_MMIO_BAR = 3,
b9ccd4a9 54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
0d5ff566 55
821d22cd
MP		 56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
63
64 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
95006188
MP		 65 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
66 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
67 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
68 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
69 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
70 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
71 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
73fd456b 72 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
1da177e4 73 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
1da177e4
LT		 74 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
821d22cd
MP		 76
77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
78 PDC_PHYMODE4 = 0x14,
1da177e4 79
176efb05
MP		 80 /* PDC_GLOBAL_CTL bit definitions */
81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
82 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
83 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
84 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
85 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
86 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
87 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
88 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
89 PDC_DRIVE_ERR = (1 << 21), /* drive error */
90 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
91 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
92 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
5796d1c4
JG		 93 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
94 PDC2_ATA_DMA_CNT_ERR,
95 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
96 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
97 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
98 PDC1_ERR_MASK | PDC2_ERR_MASK,
1da177e4
LT		 99
100 board_2037x = 0, /* FastTrak S150 TX2plus */
eca25dca
TH		 101 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
102 board_20319 = 2, /* FastTrak S150 TX4 */
103 board_20619 = 3, /* FastTrak TX4000 */
104 board_2057x = 4, /* SATAII150 Tx2plus */
d0e58031 105 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
eca25dca 106 board_40518 = 6, /* SATAII150 Tx4 */
1da177e4 107
6340f019 108 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
1da177e4 109
95006188
MP		 110 /* Sequence counter control registers bit definitions */
111 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
112
113 /* Feature register values */
114 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
115 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
116
117 /* Device/Head register values */
118 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
119
25b93d81
MP		 120 /* PDC_CTLSTAT bit definitions */
121 PDC_DMA_ENABLE = (1 << 7),
122 PDC_IRQ_DISABLE = (1 << 10),
1da177e4 123 PDC_RESET = (1 << 11), /* HDMA reset */
50630195 124
25b93d81 125 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
95006188 126 ATA_FLAG_MMIO |
3d0a59c0 127 ATA_FLAG_PIO_POLLING,
b2d1eee1 128
eca25dca
TH		 129 /* ap->flags bits */
130 PDC_FLAG_GEN_II = (1 << 24),
131 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
132 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
1da177e4
LT		 133};
134
1da177e4
LT		 135struct pdc_port_priv {
136 u8 *pkt;
137 dma_addr_t pkt_dma;
138};
139
82ef04fb
TH		 140static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
141static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
7715a6f9 142static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
eca25dca
TH		 143static int pdc_common_port_start(struct ata_port *ap);
144static int pdc_sata_port_start(struct ata_port *ap);
1da177e4 145static void pdc_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 146static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
147static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
95006188 148static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
724114a5 149static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
1da177e4 150static void pdc_irq_clear(struct ata_port *ap);
9363c382 151static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
25b93d81 152static void pdc_freeze(struct ata_port *ap);
c07a9c49 153static void pdc_sata_freeze(struct ata_port *ap);
25b93d81 154static void pdc_thaw(struct ata_port *ap);
c07a9c49 155static void pdc_sata_thaw(struct ata_port *ap);
cadef677
MP		 156static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
157 unsigned long deadline);
158static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
159 unsigned long deadline);
a1efdaba 160static void pdc_error_handler(struct ata_port *ap);
25b93d81 161static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
724114a5
MP		 162static int pdc_pata_cable_detect(struct ata_port *ap);
163static int pdc_sata_cable_detect(struct ata_port *ap);
374b1873 164
193515d5 165static struct scsi_host_template pdc_ata_sht = {
68d1d07b 166 ATA_BASE_SHT(DRV_NAME),
b9ccd4a9 167 .sg_tablesize = PDC_MAX_PRD,
1da177e4 168 .dma_boundary = ATA_DMA_BOUNDARY,
1da177e4
LT		 169};
170
029cfd6b
TH		 171static const struct ata_port_operations pdc_common_ops = {
172 .inherits = &ata_sff_port_ops,
173
5682ed33
TH		 174 .sff_tf_load = pdc_tf_load_mmio,
175 .sff_exec_command = pdc_exec_command_mmio,
95006188 176 .check_atapi_dma = pdc_check_atapi_dma,
95006188 177 .qc_prep = pdc_qc_prep,
9363c382 178 .qc_issue = pdc_qc_issue,
c96f1732 179
5682ed33 180 .sff_irq_clear = pdc_irq_clear,
c96f1732 181 .lost_interrupt = ATA_OP_NULL,
95006188 182
029cfd6b 183 .post_internal_cmd = pdc_post_internal_cmd,
a1efdaba 184 .error_handler = pdc_error_handler,
95006188
MP		 185};
186
029cfd6b
TH		 187static struct ata_port_operations pdc_sata_ops = {
188 .inherits = &pdc_common_ops,
189 .cable_detect = pdc_sata_cable_detect,
c07a9c49
MP		 190 .freeze = pdc_sata_freeze,
191 .thaw = pdc_sata_thaw,
1da177e4
LT		 192 .scr_read = pdc_sata_scr_read,
193 .scr_write = pdc_sata_scr_write,
eca25dca 194 .port_start = pdc_sata_port_start,
cadef677 195 .hardreset = pdc_sata_hardreset,
1da177e4
LT		 196};
197
029cfd6b
TH		 198/* First-generation chips need a more restrictive ->check_atapi_dma op */
199static struct ata_port_operations pdc_old_sata_ops = {
200 .inherits = &pdc_sata_ops,
201 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
202};
2cba582a 203
029cfd6b
TH		 204static struct ata_port_operations pdc_pata_ops = {
205 .inherits = &pdc_common_ops,
206 .cable_detect = pdc_pata_cable_detect,
5387373b
MP		 207 .freeze = pdc_freeze,
208 .thaw = pdc_thaw,
eca25dca 209 .port_start = pdc_common_port_start,
cadef677 210 .softreset = pdc_pata_softreset,
2cba582a
JG		 211};
212
98ac62de 213static const struct ata_port_info pdc_port_info[] = {
5595ddf9 214 [board_2037x] =
1da177e4 215 {
eca25dca
TH		 216 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
217 PDC_FLAG_SATA_PATA,
14bdef98
EIB		 218 .pio_mask = ATA_PIO4,
219 .mwdma_mask = ATA_MWDMA2,
469248ab 220 .udma_mask = ATA_UDMA6,
95006188 221 .port_ops = &pdc_old_sata_ops,
1da177e4
LT		 222 },
223
5595ddf9 224 [board_2037x_pata] =
eca25dca
TH		 225 {
226 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 227 .pio_mask = ATA_PIO4,
228 .mwdma_mask = ATA_MWDMA2,
469248ab 229 .udma_mask = ATA_UDMA6,
eca25dca
TH		 230 .port_ops = &pdc_pata_ops,
231 },
232
5595ddf9 233 [board_20319] =
1da177e4 234 {
eca25dca
TH		 235 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
236 PDC_FLAG_4_PORTS,
14bdef98
EIB		 237 .pio_mask = ATA_PIO4,
238 .mwdma_mask = ATA_MWDMA2,
469248ab 239 .udma_mask = ATA_UDMA6,
95006188 240 .port_ops = &pdc_old_sata_ops,
1da177e4 241 },
f497ba73 242
5595ddf9 243 [board_20619] =
f497ba73 244 {
eca25dca
TH		 245 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
246 PDC_FLAG_4_PORTS,
14bdef98
EIB		 247 .pio_mask = ATA_PIO4,
248 .mwdma_mask = ATA_MWDMA2,
469248ab 249 .udma_mask = ATA_UDMA6,
2cba582a 250 .port_ops = &pdc_pata_ops,
f497ba73 251 },
5a46fe89 252
5595ddf9 253 [board_2057x] =
6340f019 254 {
eca25dca
TH		 255 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
256 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
14bdef98
EIB		 257 .pio_mask = ATA_PIO4,
258 .mwdma_mask = ATA_MWDMA2,
469248ab 259 .udma_mask = ATA_UDMA6,
6340f019
LK		 260 .port_ops = &pdc_sata_ops,
261 },
262
5595ddf9 263 [board_2057x_pata] =
eca25dca 264 {
bb312235 265 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
eca25dca 266 PDC_FLAG_GEN_II,
14bdef98
EIB		 267 .pio_mask = ATA_PIO4,
268 .mwdma_mask = ATA_MWDMA2,
469248ab 269 .udma_mask = ATA_UDMA6,
eca25dca
TH		 270 .port_ops = &pdc_pata_ops,
271 },
272
5595ddf9 273 [board_40518] =
6340f019 274 {
eca25dca
TH		 275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
276 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
14bdef98
EIB		 277 .pio_mask = ATA_PIO4,
278 .mwdma_mask = ATA_MWDMA2,
469248ab 279 .udma_mask = ATA_UDMA6,
6340f019
LK		 280 .port_ops = &pdc_sata_ops,
281 },
1da177e4
LT		 282};
283
3b7d697d 284static const struct pci_device_id pdc_ata_pci_tbl[] = {
54bb3a94 285 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
54bb3a94
JG		 286 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
b2d1eee1
MP		 289 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
290 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
54bb3a94 291 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
d324d462 292 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
b2d1eee1 293 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
54bb3a94 294 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
54bb3a94
JG		 295
296 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
297 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
7f9992a2
MP		 298 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
299 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
b2d1eee1 300 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
54bb3a94
JG		 301 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
302
303 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
f497ba73 304
1da177e4
LT		 305 { } /* terminate list */
306};
307
1da177e4
LT		 308static struct pci_driver pdc_ata_pci_driver = {
309 .name = DRV_NAME,
310 .id_table = pdc_ata_pci_tbl,
311 .probe = pdc_ata_init_one,
312 .remove = ata_pci_remove_one,
313};
314
724114a5 315static int pdc_common_port_start(struct ata_port *ap)
1da177e4 316{
cca3974e 317 struct device *dev = ap->host->dev;
1da177e4
LT		 318 struct pdc_port_priv *pp;
319 int rc;
320
321 rc = ata_port_start(ap);
322 if (rc)
323 return rc;
324
24dc5f33
TH		 325 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
326 if (!pp)
327 return -ENOMEM;
1da177e4 328
24dc5f33
TH		 329 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
330 if (!pp->pkt)
331 return -ENOMEM;
1da177e4
LT		 332
333 ap->private_data = pp;
334
724114a5
MP		 335 return 0;
336}
337
338static int pdc_sata_port_start(struct ata_port *ap)
339{
724114a5
MP		 340 int rc;
341
342 rc = pdc_common_port_start(ap);
343 if (rc)
344 return rc;
345
599b7202 346 /* fix up PHYMODE4 align timing */
eca25dca 347 if (ap->flags & PDC_FLAG_GEN_II) {
821d22cd 348 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
599b7202
MP		 349 unsigned int tmp;
350
821d22cd 351 tmp = readl(sata_mmio + PDC_PHYMODE4);
599b7202 352 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
821d22cd 353 writel(tmp, sata_mmio + PDC_PHYMODE4);
599b7202
MP		 354 }
355
1da177e4 356 return 0;
1da177e4
LT		 357}
358
1da177e4
LT		 359static void pdc_reset_port(struct ata_port *ap)
360{
821d22cd 361 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
1da177e4
LT		 362 unsigned int i;
363 u32 tmp;
364
365 for (i = 11; i > 0; i--) {
821d22cd 366 tmp = readl(ata_ctlstat_mmio);
1da177e4
LT		 367 if (tmp & PDC_RESET)
368 break;
369
370 udelay(100);
371
372 tmp |= PDC_RESET;
821d22cd 373 writel(tmp, ata_ctlstat_mmio);
1da177e4
LT		 374 }
375
376 tmp &= ~PDC_RESET;
821d22cd
MP		 377 writel(tmp, ata_ctlstat_mmio);
378 readl(ata_ctlstat_mmio); /* flush */
1da177e4
LT		 379}
380
724114a5 381static int pdc_pata_cable_detect(struct ata_port *ap)
2cba582a 382{
d3fb4e8d 383 u8 tmp;
821d22cd 384 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
d3fb4e8d 385
821d22cd 386 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
724114a5
MP		 387 if (tmp & 0x01)
388 return ATA_CBL_PATA40;
389 return ATA_CBL_PATA80;
390}
391
392static int pdc_sata_cable_detect(struct ata_port *ap)
393{
e2a9752a 394 return ATA_CBL_SATA;
d3fb4e8d 395}
2cba582a 396
82ef04fb
TH		 397static int pdc_sata_scr_read(struct ata_link *link,
398 unsigned int sc_reg, u32 *val)
1da177e4 399{
724114a5 400 if (sc_reg > SCR_CONTROL)
da3dbb17 401 return -EINVAL;
82ef04fb 402 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17 403 return 0;
1da177e4
LT		 404}
405
82ef04fb
TH		 406static int pdc_sata_scr_write(struct ata_link *link,
407 unsigned int sc_reg, u32 val)
1da177e4 408{
724114a5 409 if (sc_reg > SCR_CONTROL)
da3dbb17 410 return -EINVAL;
82ef04fb 411 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17 412 return 0;
1da177e4
LT		 413}
414
fba6edbd 415static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
95006188 416{
4113bb6b
MP		 417 struct ata_port *ap = qc->ap;
418 dma_addr_t sg_table = ap->prd_dma;
419 unsigned int cdb_len = qc->dev->cdb_len;
420 u8 *cdb = qc->cdb;
421 struct pdc_port_priv *pp = ap->private_data;
422 u8 *buf = pp->pkt;
826cd156 423 __le32 *buf32 = (__le32 *) buf;
46a67143 424 unsigned int dev_sel, feature;
95006188
MP		 425
426 /* set control bits (byte 0), zero delay seq id (byte 3),
427 * and seq id (byte 2)
428 */
fba6edbd 429 switch (qc->tf.protocol) {
0dc36888 430 case ATAPI_PROT_DMA:
fba6edbd
MP		 431 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
432 buf32[0] = cpu_to_le32(PDC_PKT_READ);
433 else
434 buf32[0] = 0;
435 break;
0dc36888 436 case ATAPI_PROT_NODATA:
fba6edbd
MP		 437 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
438 break;
439 default:
440 BUG();
441 break;
442 }
95006188
MP		 443 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
444 buf32[2] = 0; /* no next-packet */
445
4113bb6b 446 /* select drive */
46a67143 447 if (sata_scr_valid(&ap->link))
4113bb6b 448 dev_sel = PDC_DEVICE_SATA;
46a67143
TH		 449 else
450 dev_sel = qc->tf.device;
451
4113bb6b
MP		 452 buf[12] = (1 << 5) | ATA_REG_DEVICE;
453 buf[13] = dev_sel;
454 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
455 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
456
457 buf[16] = (1 << 5) | ATA_REG_NSECT;
46a67143 458 buf[17] = qc->tf.nsect;
4113bb6b 459 buf[18] = (1 << 5) | ATA_REG_LBAL;
46a67143 460 buf[19] = qc->tf.lbal;
4113bb6b
MP		 461
462 /* set feature and byte counter registers */
0dc36888 463 if (qc->tf.protocol != ATAPI_PROT_DMA)
4113bb6b 464 feature = PDC_FEATURE_ATAPI_PIO;
46a67143 465 else
4113bb6b 466 feature = PDC_FEATURE_ATAPI_DMA;
46a67143 467
4113bb6b
MP		 468 buf[20] = (1 << 5) | ATA_REG_FEATURE;
469 buf[21] = feature;
470 buf[22] = (1 << 5) | ATA_REG_BYTEL;
46a67143 471 buf[23] = qc->tf.lbam;
4113bb6b 472 buf[24] = (1 << 5) | ATA_REG_BYTEH;
46a67143 473 buf[25] = qc->tf.lbah;
4113bb6b
MP		 474
475 /* send ATAPI packet command 0xA0 */
476 buf[26] = (1 << 5) | ATA_REG_CMD;
46a67143 477 buf[27] = qc->tf.command;
4113bb6b
MP		 478
479 /* select drive and check DRQ */
480 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
481 buf[29] = dev_sel;
482
95006188
MP		 483 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
484 BUG_ON(cdb_len & ~0x1E);
485
4113bb6b
MP		 486 /* append the CDB as the final part */
487 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
488 memcpy(buf+31, cdb, cdb_len);
95006188
MP		 489}
490
b9ccd4a9
MP		 491/**
492 * pdc_fill_sg - Fill PCI IDE PRD table
493 * @qc: Metadata associated with taskfile to be transferred
494 *
495 * Fill PCI IDE PRD (scatter-gather) table with segments
496 * associated with the current disk command.
497 * Make sure hardware does not choke on it.
498 *
499 * LOCKING:
500 * spin_lock_irqsave(host lock)
501 *
502 */
503static void pdc_fill_sg(struct ata_queued_cmd *qc)
504{
505 struct ata_port *ap = qc->ap;
506 struct scatterlist *sg;
b9ccd4a9 507 const u32 SG_COUNT_ASIC_BUG = 41*4;
ff2aeb1e
TH		 508 unsigned int si, idx;
509 u32 len;
b9ccd4a9
MP		 510
511 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
512 return;
513
b9ccd4a9 514 idx = 0;
ff2aeb1e 515 for_each_sg(qc->sg, sg, qc->n_elem, si) {
b9ccd4a9 516 u32 addr, offset;
6903c0f7 517 u32 sg_len;
b9ccd4a9
MP		 518
519 /* determine if physical DMA addr spans 64K boundary.
520 * Note h/w doesn't support 64-bit, so we unconditionally
521 * truncate dma_addr_t to u32.
522 */
523 addr = (u32) sg_dma_address(sg);
524 sg_len = sg_dma_len(sg);
525
526 while (sg_len) {
527 offset = addr & 0xffff;
528 len = sg_len;
529 if ((offset + sg_len) > 0x10000)
530 len = 0x10000 - offset;
531
532 ap->prd[idx].addr = cpu_to_le32(addr);
533 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
534 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
535
536 idx++;
537 sg_len -= len;
538 addr += len;
539 }
540 }
541
ff2aeb1e 542 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
b9ccd4a9 543
ff2aeb1e
TH		 544 if (len > SG_COUNT_ASIC_BUG) {
545 u32 addr;
b9ccd4a9 546
ff2aeb1e 547 VPRINTK("Splitting last PRD.\n");
b9ccd4a9 548
ff2aeb1e
TH		 549 addr = le32_to_cpu(ap->prd[idx - 1].addr);
550 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
551 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
b9ccd4a9 552
ff2aeb1e
TH		 553 addr = addr + len - SG_COUNT_ASIC_BUG;
554 len = SG_COUNT_ASIC_BUG;
555 ap->prd[idx].addr = cpu_to_le32(addr);
556 ap->prd[idx].flags_len = cpu_to_le32(len);
557 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
b9ccd4a9 558
ff2aeb1e 559 idx++;
b9ccd4a9 560 }
ff2aeb1e
TH		 561
562 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
b9ccd4a9
MP		 563}
564
1da177e4
LT		 565static void pdc_qc_prep(struct ata_queued_cmd *qc)
566{
567 struct pdc_port_priv *pp = qc->ap->private_data;
568 unsigned int i;
569
570 VPRINTK("ENTER\n");
571
572 switch (qc->tf.protocol) {
573 case ATA_PROT_DMA:
b9ccd4a9 574 pdc_fill_sg(qc);
7715a6f9 575 /*FALLTHROUGH*/
1da177e4
LT		 576 case ATA_PROT_NODATA:
577 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
578 qc->dev->devno, pp->pkt);
1da177e4
LT		 579 if (qc->tf.flags & ATA_TFLAG_LBA48)
580 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
581 else
582 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
1da177e4
LT		 583 pdc_pkt_footer(&qc->tf, pp->pkt, i);
584 break;
0dc36888 585 case ATAPI_PROT_PIO:
b9ccd4a9 586 pdc_fill_sg(qc);
95006188 587 break;
0dc36888 588 case ATAPI_PROT_DMA:
b9ccd4a9 589 pdc_fill_sg(qc);
fba6edbd 590 /*FALLTHROUGH*/
0dc36888 591 case ATAPI_PROT_NODATA:
fba6edbd 592 pdc_atapi_pkt(qc);
95006188 593 break;
1da177e4
LT		 594 default:
595 break;
596 }
597}
598
c07a9c49
MP		 599static int pdc_is_sataii_tx4(unsigned long flags)
600{
601 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
602 return (flags & mask) == mask;
603}
604
605static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
606 int is_sataii_tx4)
607{
608 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
609 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
610}
611
612static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
613{
614 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
615}
616
617static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
618{
619 const struct ata_host *host = ap->host;
620 unsigned int nr_ports = pdc_sata_nr_ports(ap);
621 unsigned int i;
622
7715a6f9 623 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
c07a9c49
MP		 624 ;
625 BUG_ON(i >= nr_ports);
626 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
627}
628
629static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
630{
631 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
632}
633
25b93d81
MP		 634static void pdc_freeze(struct ata_port *ap)
635{
821d22cd 636 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 637 u32 tmp;
638
821d22cd 639 tmp = readl(ata_mmio + PDC_CTLSTAT);
25b93d81
MP		 640 tmp |= PDC_IRQ_DISABLE;
641 tmp &= ~PDC_DMA_ENABLE;
821d22cd
MP		 642 writel(tmp, ata_mmio + PDC_CTLSTAT);
643 readl(ata_mmio + PDC_CTLSTAT); /* flush */
25b93d81
MP		 644}
645
c07a9c49
MP		 646static void pdc_sata_freeze(struct ata_port *ap)
647{
648 struct ata_host *host = ap->host;
649 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
650 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
651 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
652 u32 hotplug_status;
653
654 /* Disable hotplug events on this port.
655 *
656 * Locking:
657 * 1) hotplug register accesses must be serialised via host->lock
658 * 2) ap->lock == &ap->host->lock
659 * 3) ->freeze() and ->thaw() are called with ap->lock held
660 */
661 hotplug_status = readl(host_mmio + hotplug_offset);
662 hotplug_status |= 0x11 << (ata_no + 16);
663 writel(hotplug_status, host_mmio + hotplug_offset);
664 readl(host_mmio + hotplug_offset); /* flush */
665
666 pdc_freeze(ap);
667}
668
25b93d81
MP		 669static void pdc_thaw(struct ata_port *ap)
670{
821d22cd 671 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 672 u32 tmp;
673
674 /* clear IRQ */
821d22cd 675 readl(ata_mmio + PDC_COMMAND);
25b93d81
MP		 676
677 /* turn IRQ back on */
821d22cd 678 tmp = readl(ata_mmio + PDC_CTLSTAT);
25b93d81 679 tmp &= ~PDC_IRQ_DISABLE;
821d22cd
MP		 680 writel(tmp, ata_mmio + PDC_CTLSTAT);
681 readl(ata_mmio + PDC_CTLSTAT); /* flush */
25b93d81
MP		 682}
683
c07a9c49
MP		 684static void pdc_sata_thaw(struct ata_port *ap)
685{
686 struct ata_host *host = ap->host;
687 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
688 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
689 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
690 u32 hotplug_status;
691
692 pdc_thaw(ap);
693
694 /* Enable hotplug events on this port.
695 * Locking: see pdc_sata_freeze().
696 */
697 hotplug_status = readl(host_mmio + hotplug_offset);
698 hotplug_status |= 0x11 << ata_no;
699 hotplug_status &= ~(0x11 << (ata_no + 16));
700 writel(hotplug_status, host_mmio + hotplug_offset);
701 readl(host_mmio + hotplug_offset); /* flush */
702}
703
cadef677
MP		 704static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
705 unsigned long deadline)
706{
707 pdc_reset_port(link->ap);
708 return ata_sff_softreset(link, class, deadline);
709}
710
711static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
712 unsigned long deadline)
713{
714 pdc_reset_port(link->ap);
715 return sata_sff_hardreset(link, class, deadline);
716}
717
a1efdaba 718static void pdc_error_handler(struct ata_port *ap)
25b93d81 719{
25b93d81
MP		 720 if (!(ap->pflags & ATA_PFLAG_FROZEN))
721 pdc_reset_port(ap);
722
a1efdaba 723 ata_std_error_handler(ap);
724114a5
MP		 724}
725
25b93d81
MP		 726static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
727{
728 struct ata_port *ap = qc->ap;
729
25b93d81 730 /* make DMA engine forget about the failed command */
a51d644a 731 if (qc->flags & ATA_QCFLAG_FAILED)
25b93d81
MP		 732 pdc_reset_port(ap);
733}
734
176efb05
MP		 735static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
736 u32 port_status, u32 err_mask)
737{
9af5c9c9 738 struct ata_eh_info *ehi = &ap->link.eh_info;
176efb05
MP		 739 unsigned int ac_err_mask = 0;
740
741 ata_ehi_clear_desc(ehi);
742 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
743 port_status &= err_mask;
744
745 if (port_status & PDC_DRIVE_ERR)
746 ac_err_mask |= AC_ERR_DEV;
747 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
748 ac_err_mask |= AC_ERR_HSM;
749 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
750 ac_err_mask |= AC_ERR_ATA_BUS;
751 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
752 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
753 ac_err_mask |= AC_ERR_HOST_BUS;
754
936fd732 755 if (sata_scr_valid(&ap->link)) {
da3dbb17
TH		 756 u32 serror;
757
82ef04fb 758 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
da3dbb17
TH		 759 ehi->serror |= serror;
760 }
ce2d3abc 761
176efb05 762 qc->err_mask |= ac_err_mask;
ce2d3abc
MP		 763
764 pdc_reset_port(ap);
8ffcfd9d
MP		 765
766 ata_port_abort(ap);
176efb05
MP		 767}
768
7715a6f9
MP		 769static unsigned int pdc_host_intr(struct ata_port *ap,
770 struct ata_queued_cmd *qc)
1da177e4 771{
a22e2eb0 772 unsigned int handled = 0;
821d22cd 773 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
176efb05
MP		 774 u32 port_status, err_mask;
775
776 err_mask = PDC_ERR_MASK;
eca25dca 777 if (ap->flags & PDC_FLAG_GEN_II)
176efb05
MP		 778 err_mask &= ~PDC1_ERR_MASK;
779 else
780 err_mask &= ~PDC2_ERR_MASK;
821d22cd 781 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
176efb05
MP		 782 if (unlikely(port_status & err_mask)) {
783 pdc_error_intr(ap, qc, port_status, err_mask);
784 return 1;
1da177e4
LT		 785 }
786
787 switch (qc->tf.protocol) {
788 case ATA_PROT_DMA:
789 case ATA_PROT_NODATA:
0dc36888
TH		 790 case ATAPI_PROT_DMA:
791 case ATAPI_PROT_NODATA:
a22e2eb0
AL		 792 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
793 ata_qc_complete(qc);
1da177e4
LT		 794 handled = 1;
795 break;
d0e58031 796 default:
ee500aab
AL		 797 ap->stats.idle_irq++;
798 break;
d0e58031 799 }
1da177e4 800
ee500aab 801 return handled;
1da177e4
LT		 802}
803
804static void pdc_irq_clear(struct ata_port *ap)
805{
821d22cd 806 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1da177e4 807
821d22cd 808 readl(ata_mmio + PDC_COMMAND);
1da177e4
LT		 809}
810
5796d1c4 811static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
1da177e4 812{
cca3974e 813 struct ata_host *host = dev_instance;
1da177e4
LT		 814 struct ata_port *ap;
815 u32 mask = 0;
816 unsigned int i, tmp;
817 unsigned int handled = 0;
821d22cd 818 void __iomem *host_mmio;
a77720ad
MP		 819 unsigned int hotplug_offset, ata_no;
820 u32 hotplug_status;
821 int is_sataii_tx4;
1da177e4
LT		 822
823 VPRINTK("ENTER\n");
824
0d5ff566 825 if (!host || !host->iomap[PDC_MMIO_BAR]) {
1da177e4
LT		 826 VPRINTK("QUICK EXIT\n");
827 return IRQ_NONE;
828 }
829
821d22cd 830 host_mmio = host->iomap[PDC_MMIO_BAR];
1da177e4 831
c07a9c49
MP		 832 spin_lock(&host->lock);
833
a77720ad
MP		 834 /* read and clear hotplug flags for all ports */
835 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
836 hotplug_offset = PDC2_SATA_PLUG_CSR;
837 else
838 hotplug_offset = PDC_SATA_PLUG_CSR;
821d22cd 839 hotplug_status = readl(host_mmio + hotplug_offset);
a77720ad 840 if (hotplug_status & 0xff)
821d22cd 841 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
a77720ad
MP		 842 hotplug_status &= 0xff; /* clear uninteresting bits */
843
1da177e4 844 /* reading should also clear interrupts */
821d22cd 845 mask = readl(host_mmio + PDC_INT_SEQMASK);
1da177e4 846
a77720ad 847 if (mask == 0xffffffff && hotplug_status == 0) {
1da177e4 848 VPRINTK("QUICK EXIT 2\n");
c07a9c49 849 goto done_irq;
1da177e4 850 }
6340f019 851
7715a6f9 852 mask &= 0xffff; /* only 16 SEQIDs possible */
a77720ad 853 if (mask == 0 && hotplug_status == 0) {
1da177e4 854 VPRINTK("QUICK EXIT 3\n");
6340f019 855 goto done_irq;
1da177e4
LT		 856 }
857
821d22cd 858 writel(mask, host_mmio + PDC_INT_SEQMASK);
1da177e4 859
a77720ad
MP		 860 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
861
cca3974e 862 for (i = 0; i < host->n_ports; i++) {
1da177e4 863 VPRINTK("port %u\n", i);
cca3974e 864 ap = host->ports[i];
a77720ad
MP		 865
866 /* check for a plug or unplug event */
867 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
868 tmp = hotplug_status & (0x11 << ata_no);
869 if (tmp && ap &&
870 !(ap->flags & ATA_FLAG_DISABLED)) {
9af5c9c9 871 struct ata_eh_info *ehi = &ap->link.eh_info;
a77720ad
MP		 872 ata_ehi_clear_desc(ehi);
873 ata_ehi_hotplugged(ehi);
874 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
875 ata_port_freeze(ap);
876 ++handled;
877 continue;
878 }
879
880 /* check for a packet interrupt */
1da177e4 881 tmp = mask & (1 << (i + 1));
c1389503 882 if (tmp && ap &&
029f5468 883 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 884 struct ata_queued_cmd *qc;
885
9af5c9c9 886 qc = ata_qc_from_tag(ap, ap->link.active_tag);
e50362ec 887 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4
LT		 888 handled += pdc_host_intr(ap, qc);
889 }
890 }
891
1da177e4
LT		 892 VPRINTK("EXIT\n");
893
6340f019 894done_irq:
cca3974e 895 spin_unlock(&host->lock);
1da177e4
LT		 896 return IRQ_RETVAL(handled);
897}
898
7715a6f9 899static void pdc_packet_start(struct ata_queued_cmd *qc)
1da177e4
LT		 900{
901 struct ata_port *ap = qc->ap;
902 struct pdc_port_priv *pp = ap->private_data;
821d22cd
MP		 903 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
904 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 905 unsigned int port_no = ap->port_no;
906 u8 seq = (u8) (port_no + 1);
907
908 VPRINTK("ENTER, ap %p\n", ap);
909
821d22cd
MP		 910 writel(0x00000001, host_mmio + (seq * 4));
911 readl(host_mmio + (seq * 4)); /* flush */
1da177e4
LT		 912
913 pp->pkt[2] = seq;
914 wmb(); /* flush PRD, pkt writes */
821d22cd
MP		 915 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
916 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1da177e4
LT		 917}
918
9363c382 919static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 920{
921 switch (qc->tf.protocol) {
0dc36888 922 case ATAPI_PROT_NODATA:
fba6edbd
MP		 923 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
924 break;
925 /*FALLTHROUGH*/
51b94d2a
TH		 926 case ATA_PROT_NODATA:
927 if (qc->tf.flags & ATA_TFLAG_POLLING)
928 break;
929 /*FALLTHROUGH*/
0dc36888 930 case ATAPI_PROT_DMA:
1da177e4 931 case ATA_PROT_DMA:
1da177e4
LT		 932 pdc_packet_start(qc);
933 return 0;
1da177e4
LT		 934 default:
935 break;
936 }
9363c382 937 return ata_sff_qc_issue(qc);
1da177e4
LT		 938}
939
057ace5e 940static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4 941{
0dc36888 942 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
9363c382 943 ata_sff_tf_load(ap, tf);
1da177e4
LT		 944}
945
5796d1c4
JG		 946static void pdc_exec_command_mmio(struct ata_port *ap,
947 const struct ata_taskfile *tf)
1da177e4 948{
0dc36888 949 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
9363c382 950 ata_sff_exec_command(ap, tf);
1da177e4
LT		 951}
952
95006188
MP		 953static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
954{
955 u8 *scsicmd = qc->scsicmd->cmnd;
956 int pio = 1; /* atapi dma off by default */
957
958 /* Whitelist commands that may use DMA. */
959 switch (scsicmd[0]) {
960 case WRITE_12:
961 case WRITE_10:
962 case WRITE_6:
963 case READ_12:
964 case READ_10:
965 case READ_6:
966 case 0xad: /* READ_DVD_STRUCTURE */
967 case 0xbe: /* READ_CD */
968 pio = 0;
969 }
970 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
971 if (scsicmd[0] == WRITE_10) {
5796d1c4
JG		 972 unsigned int lba =
973 (scsicmd[2] << 24) |
974 (scsicmd[3] << 16) |
975 (scsicmd[4] << 8) |
976 scsicmd[5];
95006188
MP		 977 if (lba >= 0xFFFF4FA2)
978 pio = 1;
979 }
980 return pio;
981}
982
724114a5 983static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
95006188 984{
95006188 985 /* First generation chips cannot use ATAPI DMA on SATA ports */
724114a5 986 return 1;
95006188 987}
1da177e4 988
eca25dca
TH		 989static void pdc_ata_setup_port(struct ata_port *ap,
990 void __iomem *base, void __iomem *scr_addr)
1da177e4 991{
eca25dca
TH		 992 ap->ioaddr.cmd_addr = base;
993 ap->ioaddr.data_addr = base;
994 ap->ioaddr.feature_addr =
995 ap->ioaddr.error_addr = base + 0x4;
996 ap->ioaddr.nsect_addr = base + 0x8;
997 ap->ioaddr.lbal_addr = base + 0xc;
998 ap->ioaddr.lbam_addr = base + 0x10;
999 ap->ioaddr.lbah_addr = base + 0x14;
1000 ap->ioaddr.device_addr = base + 0x18;
1001 ap->ioaddr.command_addr =
1002 ap->ioaddr.status_addr = base + 0x1c;
1003 ap->ioaddr.altstatus_addr =
1004 ap->ioaddr.ctl_addr = base + 0x38;
1005 ap->ioaddr.scr_addr = scr_addr;
1da177e4
LT		 1006}
1007
eca25dca 1008static void pdc_host_init(struct ata_host *host)
1da177e4 1009{
821d22cd 1010 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
eca25dca 1011 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
d324d462 1012 int hotplug_offset;
1da177e4
LT		 1013 u32 tmp;
1014
eca25dca 1015 if (is_gen2)
d324d462
MP		 1016 hotplug_offset = PDC2_SATA_PLUG_CSR;
1017 else
1018 hotplug_offset = PDC_SATA_PLUG_CSR;
1019
1da177e4
LT		 1020 /*
1021 * Except for the hotplug stuff, this is voodoo from the
1022 * Promise driver. Label this entire section
1023 * "TODO: figure out why we do this"
1024 */
1025
b2d1eee1 1026 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
821d22cd 1027 tmp = readl(host_mmio + PDC_FLASH_CTL);
b2d1eee1 1028 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
eca25dca 1029 if (!is_gen2)
b2d1eee1 1030 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
821d22cd 1031 writel(tmp, host_mmio + PDC_FLASH_CTL);
1da177e4
LT		 1032
1033 /* clear plug/unplug flags for all ports */
821d22cd
MP		 1034 tmp = readl(host_mmio + hotplug_offset);
1035 writel(tmp | 0xff, host_mmio + hotplug_offset);
1da177e4 1036
a77720ad 1037 /* unmask plug/unplug ints */
821d22cd
MP		 1038 tmp = readl(host_mmio + hotplug_offset);
1039 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1da177e4 1040
b2d1eee1 1041 /* don't initialise TBG or SLEW on 2nd generation chips */
eca25dca 1042 if (is_gen2)
b2d1eee1
MP		 1043 return;
1044
1da177e4 1045 /* reduce TBG clock to 133 Mhz. */
821d22cd 1046 tmp = readl(host_mmio + PDC_TBG_MODE);
1da177e4
LT		 1047 tmp &= ~0x30000; /* clear bit 17, 16*/
1048 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
821d22cd 1049 writel(tmp, host_mmio + PDC_TBG_MODE);
1da177e4 1050
821d22cd 1051 readl(host_mmio + PDC_TBG_MODE); /* flush */
1da177e4
LT		 1052 msleep(10);
1053
1054 /* adjust slew rate control register. */
821d22cd 1055 tmp = readl(host_mmio + PDC_SLEW_CTL);
1da177e4
LT		 1056 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1057 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
821d22cd 1058 writel(tmp, host_mmio + PDC_SLEW_CTL);
1da177e4
LT		 1059}
1060
5796d1c4
JG		 1061static int pdc_ata_init_one(struct pci_dev *pdev,
1062 const struct pci_device_id *ent)
1da177e4
LT		 1063{
1064 static int printed_version;
eca25dca
TH		 1065 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1066 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1067 struct ata_host *host;
821d22cd 1068 void __iomem *host_mmio;
eca25dca 1069 int n_ports, i, rc;
5ac2fe57 1070 int is_sataii_tx4;
1da177e4
LT		 1071
1072 if (!printed_version++)
a9524a76 1073 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1074
eca25dca 1075 /* enable and acquire resources */
24dc5f33 1076 rc = pcim_enable_device(pdev);
1da177e4
LT		 1077 if (rc)
1078 return rc;
1079
0d5ff566
TH		 1080 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1081 if (rc == -EBUSY)
24dc5f33 1082 pcim_pin_device(pdev);
0d5ff566 1083 if (rc)
24dc5f33 1084 return rc;
821d22cd 1085 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1da177e4 1086
eca25dca
TH		 1087 /* determine port configuration and setup host */
1088 n_ports = 2;
1089 if (pi->flags & PDC_FLAG_4_PORTS)
1090 n_ports = 4;
1091 for (i = 0; i < n_ports; i++)
1092 ppi[i] = pi;
1da177e4 1093
eca25dca 1094 if (pi->flags & PDC_FLAG_SATA_PATA) {
821d22cd 1095 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
d0e58031 1096 if (!(tmp & 0x80))
eca25dca 1097 ppi[n_ports++] = pi + 1;
eca25dca 1098 }
1da177e4 1099
eca25dca
TH		 1100 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1101 if (!host) {
1102 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
24dc5f33 1103 return -ENOMEM;
1da177e4 1104 }
eca25dca 1105 host->iomap = pcim_iomap_table(pdev);
1da177e4 1106
d0e58031 1107 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
5ac2fe57 1108 for (i = 0; i < host->n_ports; i++) {
cbcdd875 1109 struct ata_port *ap = host->ports[i];
d0e58031 1110 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
821d22cd 1111 unsigned int ata_offset = 0x200 + ata_no * 0x80;
cbcdd875
TH		 1112 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1113
821d22cd 1114 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
cbcdd875
TH		 1115
1116 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
821d22cd 1117 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
5ac2fe57 1118 }
1da177e4
LT		 1119
1120 /* initialize adapter */
eca25dca 1121 pdc_host_init(host);
1da177e4 1122
eca25dca
TH		 1123 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1124 if (rc)
1125 return rc;
1126 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1127 if (rc)
1128 return rc;
1da177e4 1129
eca25dca
TH		 1130 /* start host, request IRQ and attach */
1131 pci_set_master(pdev);
1132 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1133 &pdc_ata_sht);
1da177e4
LT		 1134}
1135
1da177e4
LT		 1136static int __init pdc_ata_init(void)
1137{
b7887196 1138 return pci_register_driver(&pdc_ata_pci_driver);
1da177e4
LT		 1139}
1140
1da177e4
LT		 1141static void __exit pdc_ata_exit(void)
1142{
1143 pci_unregister_driver(&pdc_ata_pci_driver);
1144}
1145
1da177e4 1146MODULE_AUTHOR("Jeff Garzik");
f497ba73 1147MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1da177e4
LT		 1148MODULE_LICENSE("GPL");
1149MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1150MODULE_VERSION(DRV_VERSION);
1151
1152module_init(pdc_ata_init);
1153module_exit(pdc_ata_exit);
Linux kernel - Deliverables
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