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libata: normalize port_info, port_operations and sht tables
[deliverable/linux.git] / drivers / ata / sata_promise.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5595ddf9 5 * Mikael Pettersson <mikpe@it.uu.se>
1da177e4
LT		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
1da177e4 11 *
af36d7f0
JG		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
1da177e4
LT		 31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
a9524a76 41#include <linux/device.h>
95006188 42#include <scsi/scsi.h>
1da177e4 43#include <scsi/scsi_host.h>
193515d5 44#include <scsi/scsi_cmnd.h>
1da177e4 45#include <linux/libata.h>
1da177e4
LT		 46#include "sata_promise.h"
47
48#define DRV_NAME "sata_promise"
c07a9c49 49#define DRV_VERSION "2.12"
1da177e4
LT		 50
51enum {
eca25dca 52 PDC_MAX_PORTS = 4,
0d5ff566 53 PDC_MMIO_BAR = 3,
b9ccd4a9 54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
0d5ff566 55
95006188
MP		 56 /* register offsets */
57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
60 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
61 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
62 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
73fd456b 64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
1da177e4
LT		 65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
1da177e4 67 PDC_FLASH_CTL = 0x44, /* Flash control register */
1da177e4
LT		 68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
6340f019 71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
b2d1eee1
MP		 72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
1da177e4 74
176efb05
MP		 75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR = (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
5796d1c4
JG		 88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
89 PDC2_ATA_DMA_CNT_ERR,
90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
93 PDC1_ERR_MASK | PDC2_ERR_MASK,
1da177e4
LT		 94
95 board_2037x = 0, /* FastTrak S150 TX2plus */
eca25dca
TH		 96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
97 board_20319 = 2, /* FastTrak S150 TX4 */
98 board_20619 = 3, /* FastTrak TX4000 */
99 board_2057x = 4, /* SATAII150 Tx2plus */
d0e58031 100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
eca25dca 101 board_40518 = 6, /* SATAII150 Tx4 */
1da177e4 102
6340f019 103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
1da177e4 104
95006188
MP		 105 /* Sequence counter control registers bit definitions */
106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
107
108 /* Feature register values */
109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
111
112 /* Device/Head register values */
113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
114
25b93d81
MP		 115 /* PDC_CTLSTAT bit definitions */
116 PDC_DMA_ENABLE = (1 << 7),
117 PDC_IRQ_DISABLE = (1 << 10),
1da177e4 118 PDC_RESET = (1 << 11), /* HDMA reset */
50630195 119
25b93d81 120 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
95006188 121 ATA_FLAG_MMIO |
3d0a59c0 122 ATA_FLAG_PIO_POLLING,
b2d1eee1 123
eca25dca
TH		 124 /* ap->flags bits */
125 PDC_FLAG_GEN_II = (1 << 24),
126 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
127 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
1da177e4
LT		 128};
129
1da177e4
LT		 130struct pdc_port_priv {
131 u8 *pkt;
132 dma_addr_t pkt_dma;
133};
134
da3dbb17
TH		 135static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
136static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
1da177e4 137static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
eca25dca
TH		 138static int pdc_common_port_start(struct ata_port *ap);
139static int pdc_sata_port_start(struct ata_port *ap);
1da177e4 140static void pdc_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 141static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
142static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
95006188 143static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
724114a5 144static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
1da177e4 145static void pdc_irq_clear(struct ata_port *ap);
9a3d9eb0 146static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
25b93d81 147static void pdc_freeze(struct ata_port *ap);
c07a9c49 148static void pdc_sata_freeze(struct ata_port *ap);
25b93d81 149static void pdc_thaw(struct ata_port *ap);
c07a9c49 150static void pdc_sata_thaw(struct ata_port *ap);
724114a5
MP		 151static void pdc_pata_error_handler(struct ata_port *ap);
152static void pdc_sata_error_handler(struct ata_port *ap);
25b93d81 153static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
724114a5
MP		 154static int pdc_pata_cable_detect(struct ata_port *ap);
155static int pdc_sata_cable_detect(struct ata_port *ap);
374b1873 156
193515d5 157static struct scsi_host_template pdc_ata_sht = {
1da177e4
LT		 158 .module = THIS_MODULE,
159 .name = DRV_NAME,
160 .ioctl = ata_scsi_ioctl,
161 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 162 .can_queue = ATA_DEF_QUEUE,
163 .this_id = ATA_SHT_THIS_ID,
b9ccd4a9 164 .sg_tablesize = PDC_MAX_PRD,
1da177e4
LT		 165 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
166 .emulated = ATA_SHT_EMULATED,
167 .use_clustering = ATA_SHT_USE_CLUSTERING,
168 .proc_name = DRV_NAME,
169 .dma_boundary = ATA_DMA_BOUNDARY,
170 .slave_configure = ata_scsi_slave_config,
ccf68c34 171 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 172 .bios_param = ata_std_bios_param,
1da177e4
LT		 173};
174
057ace5e 175static const struct ata_port_operations pdc_sata_ops = {
1da177e4
LT		 176 .tf_load = pdc_tf_load_mmio,
177 .tf_read = ata_tf_read,
178 .check_status = ata_check_status,
179 .exec_command = pdc_exec_command_mmio,
180 .dev_select = ata_std_dev_select,
95006188
MP		 181 .check_atapi_dma = pdc_check_atapi_dma,
182
183 .qc_prep = pdc_qc_prep,
184 .qc_issue = pdc_qc_issue_prot,
c07a9c49
MP		 185 .freeze = pdc_sata_freeze,
186 .thaw = pdc_sata_thaw,
724114a5 187 .error_handler = pdc_sata_error_handler,
95006188 188 .post_internal_cmd = pdc_post_internal_cmd,
724114a5 189 .cable_detect = pdc_sata_cable_detect,
0d5ff566 190 .data_xfer = ata_data_xfer,
95006188 191 .irq_clear = pdc_irq_clear,
246ce3b6 192 .irq_on = ata_irq_on,
95006188
MP		 193
194 .scr_read = pdc_sata_scr_read,
195 .scr_write = pdc_sata_scr_write,
eca25dca 196 .port_start = pdc_sata_port_start,
95006188
MP		 197};
198
199/* First-generation chips need a more restrictive ->check_atapi_dma op */
200static const struct ata_port_operations pdc_old_sata_ops = {
95006188
MP		 201 .tf_load = pdc_tf_load_mmio,
202 .tf_read = ata_tf_read,
203 .check_status = ata_check_status,
204 .exec_command = pdc_exec_command_mmio,
205 .dev_select = ata_std_dev_select,
724114a5 206 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
2cba582a 207
1da177e4
LT		 208 .qc_prep = pdc_qc_prep,
209 .qc_issue = pdc_qc_issue_prot,
c07a9c49
MP		 210 .freeze = pdc_sata_freeze,
211 .thaw = pdc_sata_thaw,
724114a5 212 .error_handler = pdc_sata_error_handler,
25b93d81 213 .post_internal_cmd = pdc_post_internal_cmd,
724114a5 214 .cable_detect = pdc_sata_cable_detect,
0d5ff566 215 .data_xfer = ata_data_xfer,
1da177e4 216 .irq_clear = pdc_irq_clear,
246ce3b6 217 .irq_on = ata_irq_on,
2cba582a 218
1da177e4
LT		 219 .scr_read = pdc_sata_scr_read,
220 .scr_write = pdc_sata_scr_write,
eca25dca 221 .port_start = pdc_sata_port_start,
1da177e4
LT		 222};
223
057ace5e 224static const struct ata_port_operations pdc_pata_ops = {
2cba582a
JG		 225 .tf_load = pdc_tf_load_mmio,
226 .tf_read = ata_tf_read,
227 .check_status = ata_check_status,
228 .exec_command = pdc_exec_command_mmio,
229 .dev_select = ata_std_dev_select,
95006188 230 .check_atapi_dma = pdc_check_atapi_dma,
2cba582a 231
2cba582a
JG		 232 .qc_prep = pdc_qc_prep,
233 .qc_issue = pdc_qc_issue_prot,
5387373b
MP		 234 .freeze = pdc_freeze,
235 .thaw = pdc_thaw,
724114a5 236 .error_handler = pdc_pata_error_handler,
540477b4 237 .post_internal_cmd = pdc_post_internal_cmd,
724114a5 238 .cable_detect = pdc_pata_cable_detect,
0d5ff566 239 .data_xfer = ata_data_xfer,
2cba582a 240 .irq_clear = pdc_irq_clear,
246ce3b6 241 .irq_on = ata_irq_on,
2cba582a 242
eca25dca 243 .port_start = pdc_common_port_start,
2cba582a
JG		 244};
245
98ac62de 246static const struct ata_port_info pdc_port_info[] = {
5595ddf9 247 [board_2037x] =
1da177e4 248 {
eca25dca
TH		 249 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
250 PDC_FLAG_SATA_PATA,
1da177e4
LT		 251 .pio_mask = 0x1f, /* pio0-4 */
252 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 253 .udma_mask = ATA_UDMA6,
95006188 254 .port_ops = &pdc_old_sata_ops,
1da177e4
LT		 255 },
256
5595ddf9 257 [board_2037x_pata] =
eca25dca
TH		 258 {
259 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
260 .pio_mask = 0x1f, /* pio0-4 */
261 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 262 .udma_mask = ATA_UDMA6,
eca25dca
TH		 263 .port_ops = &pdc_pata_ops,
264 },
265
5595ddf9 266 [board_20319] =
1da177e4 267 {
eca25dca
TH		 268 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
269 PDC_FLAG_4_PORTS,
1da177e4
LT		 270 .pio_mask = 0x1f, /* pio0-4 */
271 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 272 .udma_mask = ATA_UDMA6,
95006188 273 .port_ops = &pdc_old_sata_ops,
1da177e4 274 },
f497ba73 275
5595ddf9 276 [board_20619] =
f497ba73 277 {
eca25dca
TH		 278 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
279 PDC_FLAG_4_PORTS,
f497ba73
TL		 280 .pio_mask = 0x1f, /* pio0-4 */
281 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 282 .udma_mask = ATA_UDMA6,
2cba582a 283 .port_ops = &pdc_pata_ops,
f497ba73 284 },
5a46fe89 285
5595ddf9 286 [board_2057x] =
6340f019 287 {
eca25dca
TH		 288 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
289 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
6340f019
LK		 290 .pio_mask = 0x1f, /* pio0-4 */
291 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 292 .udma_mask = ATA_UDMA6,
6340f019
LK		 293 .port_ops = &pdc_sata_ops,
294 },
295
5595ddf9 296 [board_2057x_pata] =
eca25dca 297 {
bb312235 298 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
eca25dca
TH		 299 PDC_FLAG_GEN_II,
300 .pio_mask = 0x1f, /* pio0-4 */
301 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 302 .udma_mask = ATA_UDMA6,
eca25dca
TH		 303 .port_ops = &pdc_pata_ops,
304 },
305
5595ddf9 306 [board_40518] =
6340f019 307 {
eca25dca
TH		 308 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
309 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
6340f019
LK		 310 .pio_mask = 0x1f, /* pio0-4 */
311 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 312 .udma_mask = ATA_UDMA6,
6340f019
LK		 313 .port_ops = &pdc_sata_ops,
314 },
1da177e4
LT		 315};
316
3b7d697d 317static const struct pci_device_id pdc_ata_pci_tbl[] = {
54bb3a94 318 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
54bb3a94
JG		 319 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
320 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
321 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
b2d1eee1
MP		 322 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
323 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
54bb3a94 324 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
d324d462 325 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
b2d1eee1 326 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
54bb3a94 327 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
54bb3a94
JG		 328
329 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
330 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
7f9992a2
MP		 331 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
332 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
b2d1eee1 333 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
54bb3a94
JG		 334 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
335
336 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
f497ba73 337
1da177e4
LT		 338 { } /* terminate list */
339};
340
1da177e4
LT		 341static struct pci_driver pdc_ata_pci_driver = {
342 .name = DRV_NAME,
343 .id_table = pdc_ata_pci_tbl,
344 .probe = pdc_ata_init_one,
345 .remove = ata_pci_remove_one,
346};
347
724114a5 348static int pdc_common_port_start(struct ata_port *ap)
1da177e4 349{
cca3974e 350 struct device *dev = ap->host->dev;
1da177e4
LT		 351 struct pdc_port_priv *pp;
352 int rc;
353
354 rc = ata_port_start(ap);
355 if (rc)
356 return rc;
357
24dc5f33
TH		 358 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
359 if (!pp)
360 return -ENOMEM;
1da177e4 361
24dc5f33
TH		 362 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
363 if (!pp->pkt)
364 return -ENOMEM;
1da177e4
LT		 365
366 ap->private_data = pp;
367
724114a5
MP		 368 return 0;
369}
370
371static int pdc_sata_port_start(struct ata_port *ap)
372{
724114a5
MP		 373 int rc;
374
375 rc = pdc_common_port_start(ap);
376 if (rc)
377 return rc;
378
599b7202 379 /* fix up PHYMODE4 align timing */
eca25dca 380 if (ap->flags & PDC_FLAG_GEN_II) {
59f99880 381 void __iomem *mmio = ap->ioaddr.scr_addr;
599b7202
MP		 382 unsigned int tmp;
383
384 tmp = readl(mmio + 0x014);
385 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
386 writel(tmp, mmio + 0x014);
387 }
388
1da177e4 389 return 0;
1da177e4
LT		 390}
391
1da177e4
LT		 392static void pdc_reset_port(struct ata_port *ap)
393{
0d5ff566 394 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
1da177e4
LT		 395 unsigned int i;
396 u32 tmp;
397
398 for (i = 11; i > 0; i--) {
399 tmp = readl(mmio);
400 if (tmp & PDC_RESET)
401 break;
402
403 udelay(100);
404
405 tmp |= PDC_RESET;
406 writel(tmp, mmio);
407 }
408
409 tmp &= ~PDC_RESET;
410 writel(tmp, mmio);
411 readl(mmio); /* flush */
412}
413
724114a5 414static int pdc_pata_cable_detect(struct ata_port *ap)
2cba582a 415{
d3fb4e8d 416 u8 tmp;
59f99880 417 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
d3fb4e8d 418
724114a5
MP		 419 tmp = readb(mmio);
420 if (tmp & 0x01)
421 return ATA_CBL_PATA40;
422 return ATA_CBL_PATA80;
423}
424
425static int pdc_sata_cable_detect(struct ata_port *ap)
426{
e2a9752a 427 return ATA_CBL_SATA;
d3fb4e8d 428}
2cba582a 429
da3dbb17 430static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 431{
724114a5 432 if (sc_reg > SCR_CONTROL)
da3dbb17
TH		 433 return -EINVAL;
434 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
435 return 0;
1da177e4
LT		 436}
437
da3dbb17 438static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4 439{
724114a5 440 if (sc_reg > SCR_CONTROL)
da3dbb17 441 return -EINVAL;
0d5ff566 442 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17 443 return 0;
1da177e4
LT		 444}
445
fba6edbd 446static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
95006188 447{
4113bb6b
MP		 448 struct ata_port *ap = qc->ap;
449 dma_addr_t sg_table = ap->prd_dma;
450 unsigned int cdb_len = qc->dev->cdb_len;
451 u8 *cdb = qc->cdb;
452 struct pdc_port_priv *pp = ap->private_data;
453 u8 *buf = pp->pkt;
95006188 454 u32 *buf32 = (u32 *) buf;
46a67143 455 unsigned int dev_sel, feature;
95006188
MP		 456
457 /* set control bits (byte 0), zero delay seq id (byte 3),
458 * and seq id (byte 2)
459 */
fba6edbd 460 switch (qc->tf.protocol) {
0dc36888 461 case ATAPI_PROT_DMA:
fba6edbd
MP		 462 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
463 buf32[0] = cpu_to_le32(PDC_PKT_READ);
464 else
465 buf32[0] = 0;
466 break;
0dc36888 467 case ATAPI_PROT_NODATA:
fba6edbd
MP		 468 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
469 break;
470 default:
471 BUG();
472 break;
473 }
95006188
MP		 474 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
475 buf32[2] = 0; /* no next-packet */
476
4113bb6b 477 /* select drive */
46a67143 478 if (sata_scr_valid(&ap->link))
4113bb6b 479 dev_sel = PDC_DEVICE_SATA;
46a67143
TH		 480 else
481 dev_sel = qc->tf.device;
482
4113bb6b
MP		 483 buf[12] = (1 << 5) | ATA_REG_DEVICE;
484 buf[13] = dev_sel;
485 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
486 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
487
488 buf[16] = (1 << 5) | ATA_REG_NSECT;
46a67143 489 buf[17] = qc->tf.nsect;
4113bb6b 490 buf[18] = (1 << 5) | ATA_REG_LBAL;
46a67143 491 buf[19] = qc->tf.lbal;
4113bb6b
MP		 492
493 /* set feature and byte counter registers */
0dc36888 494 if (qc->tf.protocol != ATAPI_PROT_DMA)
4113bb6b 495 feature = PDC_FEATURE_ATAPI_PIO;
46a67143 496 else
4113bb6b 497 feature = PDC_FEATURE_ATAPI_DMA;
46a67143 498
4113bb6b
MP		 499 buf[20] = (1 << 5) | ATA_REG_FEATURE;
500 buf[21] = feature;
501 buf[22] = (1 << 5) | ATA_REG_BYTEL;
46a67143 502 buf[23] = qc->tf.lbam;
4113bb6b 503 buf[24] = (1 << 5) | ATA_REG_BYTEH;
46a67143 504 buf[25] = qc->tf.lbah;
4113bb6b
MP		 505
506 /* send ATAPI packet command 0xA0 */
507 buf[26] = (1 << 5) | ATA_REG_CMD;
46a67143 508 buf[27] = qc->tf.command;
4113bb6b
MP		 509
510 /* select drive and check DRQ */
511 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
512 buf[29] = dev_sel;
513
95006188
MP		 514 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
515 BUG_ON(cdb_len & ~0x1E);
516
4113bb6b
MP		 517 /* append the CDB as the final part */
518 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
519 memcpy(buf+31, cdb, cdb_len);
95006188
MP		 520}
521
b9ccd4a9
MP		 522/**
523 * pdc_fill_sg - Fill PCI IDE PRD table
524 * @qc: Metadata associated with taskfile to be transferred
525 *
526 * Fill PCI IDE PRD (scatter-gather) table with segments
527 * associated with the current disk command.
528 * Make sure hardware does not choke on it.
529 *
530 * LOCKING:
531 * spin_lock_irqsave(host lock)
532 *
533 */
534static void pdc_fill_sg(struct ata_queued_cmd *qc)
535{
536 struct ata_port *ap = qc->ap;
537 struct scatterlist *sg;
b9ccd4a9 538 const u32 SG_COUNT_ASIC_BUG = 41*4;
ff2aeb1e
TH		 539 unsigned int si, idx;
540 u32 len;
b9ccd4a9
MP		 541
542 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
543 return;
544
b9ccd4a9 545 idx = 0;
ff2aeb1e 546 for_each_sg(qc->sg, sg, qc->n_elem, si) {
b9ccd4a9 547 u32 addr, offset;
6903c0f7 548 u32 sg_len;
b9ccd4a9
MP		 549
550 /* determine if physical DMA addr spans 64K boundary.
551 * Note h/w doesn't support 64-bit, so we unconditionally
552 * truncate dma_addr_t to u32.
553 */
554 addr = (u32) sg_dma_address(sg);
555 sg_len = sg_dma_len(sg);
556
557 while (sg_len) {
558 offset = addr & 0xffff;
559 len = sg_len;
560 if ((offset + sg_len) > 0x10000)
561 len = 0x10000 - offset;
562
563 ap->prd[idx].addr = cpu_to_le32(addr);
564 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
565 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
566
567 idx++;
568 sg_len -= len;
569 addr += len;
570 }
571 }
572
ff2aeb1e 573 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
b9ccd4a9 574
ff2aeb1e
TH		 575 if (len > SG_COUNT_ASIC_BUG) {
576 u32 addr;
b9ccd4a9 577
ff2aeb1e 578 VPRINTK("Splitting last PRD.\n");
b9ccd4a9 579
ff2aeb1e
TH		 580 addr = le32_to_cpu(ap->prd[idx - 1].addr);
581 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
582 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
b9ccd4a9 583
ff2aeb1e
TH		 584 addr = addr + len - SG_COUNT_ASIC_BUG;
585 len = SG_COUNT_ASIC_BUG;
586 ap->prd[idx].addr = cpu_to_le32(addr);
587 ap->prd[idx].flags_len = cpu_to_le32(len);
588 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
b9ccd4a9 589
ff2aeb1e 590 idx++;
b9ccd4a9 591 }
ff2aeb1e
TH		 592
593 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
b9ccd4a9
MP		 594}
595
1da177e4
LT		 596static void pdc_qc_prep(struct ata_queued_cmd *qc)
597{
598 struct pdc_port_priv *pp = qc->ap->private_data;
599 unsigned int i;
600
601 VPRINTK("ENTER\n");
602
603 switch (qc->tf.protocol) {
604 case ATA_PROT_DMA:
b9ccd4a9 605 pdc_fill_sg(qc);
1da177e4
LT		 606 /* fall through */
607
608 case ATA_PROT_NODATA:
609 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
610 qc->dev->devno, pp->pkt);
611
612 if (qc->tf.flags & ATA_TFLAG_LBA48)
613 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
614 else
615 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
616
617 pdc_pkt_footer(&qc->tf, pp->pkt, i);
618 break;
619
0dc36888 620 case ATAPI_PROT_PIO:
b9ccd4a9 621 pdc_fill_sg(qc);
95006188
MP		 622 break;
623
0dc36888 624 case ATAPI_PROT_DMA:
b9ccd4a9 625 pdc_fill_sg(qc);
fba6edbd 626 /*FALLTHROUGH*/
0dc36888 627 case ATAPI_PROT_NODATA:
fba6edbd 628 pdc_atapi_pkt(qc);
95006188
MP		 629 break;
630
1da177e4
LT		 631 default:
632 break;
633 }
634}
635
c07a9c49
MP		 636static int pdc_is_sataii_tx4(unsigned long flags)
637{
638 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
639 return (flags & mask) == mask;
640}
641
642static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
643 int is_sataii_tx4)
644{
645 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
646 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
647}
648
649static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
650{
651 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
652}
653
654static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
655{
656 const struct ata_host *host = ap->host;
657 unsigned int nr_ports = pdc_sata_nr_ports(ap);
658 unsigned int i;
659
660 for(i = 0; i < nr_ports && host->ports[i] != ap; ++i)
661 ;
662 BUG_ON(i >= nr_ports);
663 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
664}
665
666static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
667{
668 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
669}
670
25b93d81
MP		 671static void pdc_freeze(struct ata_port *ap)
672{
59f99880 673 void __iomem *mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 674 u32 tmp;
675
676 tmp = readl(mmio + PDC_CTLSTAT);
677 tmp |= PDC_IRQ_DISABLE;
678 tmp &= ~PDC_DMA_ENABLE;
679 writel(tmp, mmio + PDC_CTLSTAT);
680 readl(mmio + PDC_CTLSTAT); /* flush */
681}
682
c07a9c49
MP		 683static void pdc_sata_freeze(struct ata_port *ap)
684{
685 struct ata_host *host = ap->host;
686 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
687 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
688 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
689 u32 hotplug_status;
690
691 /* Disable hotplug events on this port.
692 *
693 * Locking:
694 * 1) hotplug register accesses must be serialised via host->lock
695 * 2) ap->lock == &ap->host->lock
696 * 3) ->freeze() and ->thaw() are called with ap->lock held
697 */
698 hotplug_status = readl(host_mmio + hotplug_offset);
699 hotplug_status |= 0x11 << (ata_no + 16);
700 writel(hotplug_status, host_mmio + hotplug_offset);
701 readl(host_mmio + hotplug_offset); /* flush */
702
703 pdc_freeze(ap);
704}
705
25b93d81
MP		 706static void pdc_thaw(struct ata_port *ap)
707{
59f99880 708 void __iomem *mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 709 u32 tmp;
710
711 /* clear IRQ */
712 readl(mmio + PDC_INT_SEQMASK);
713
714 /* turn IRQ back on */
715 tmp = readl(mmio + PDC_CTLSTAT);
716 tmp &= ~PDC_IRQ_DISABLE;
717 writel(tmp, mmio + PDC_CTLSTAT);
718 readl(mmio + PDC_CTLSTAT); /* flush */
719}
720
c07a9c49
MP		 721static void pdc_sata_thaw(struct ata_port *ap)
722{
723 struct ata_host *host = ap->host;
724 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
725 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
726 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
727 u32 hotplug_status;
728
729 pdc_thaw(ap);
730
731 /* Enable hotplug events on this port.
732 * Locking: see pdc_sata_freeze().
733 */
734 hotplug_status = readl(host_mmio + hotplug_offset);
735 hotplug_status |= 0x11 << ata_no;
736 hotplug_status &= ~(0x11 << (ata_no + 16));
737 writel(hotplug_status, host_mmio + hotplug_offset);
738 readl(host_mmio + hotplug_offset); /* flush */
739}
740
724114a5 741static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
25b93d81 742{
25b93d81
MP		 743 if (!(ap->pflags & ATA_PFLAG_FROZEN))
744 pdc_reset_port(ap);
745
25b93d81 746 /* perform recovery */
e2a9752a 747 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
25b93d81
MP		 748 ata_std_postreset);
749}
750
724114a5
MP		 751static void pdc_pata_error_handler(struct ata_port *ap)
752{
753 pdc_common_error_handler(ap, NULL);
754}
755
756static void pdc_sata_error_handler(struct ata_port *ap)
757{
758 pdc_common_error_handler(ap, sata_std_hardreset);
759}
760
25b93d81
MP		 761static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
762{
763 struct ata_port *ap = qc->ap;
764
25b93d81 765 /* make DMA engine forget about the failed command */
a51d644a 766 if (qc->flags & ATA_QCFLAG_FAILED)
25b93d81
MP		 767 pdc_reset_port(ap);
768}
769
176efb05
MP		 770static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
771 u32 port_status, u32 err_mask)
772{
9af5c9c9 773 struct ata_eh_info *ehi = &ap->link.eh_info;
176efb05
MP		 774 unsigned int ac_err_mask = 0;
775
776 ata_ehi_clear_desc(ehi);
777 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
778 port_status &= err_mask;
779
780 if (port_status & PDC_DRIVE_ERR)
781 ac_err_mask |= AC_ERR_DEV;
782 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
783 ac_err_mask |= AC_ERR_HSM;
784 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
785 ac_err_mask |= AC_ERR_ATA_BUS;
786 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
787 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
788 ac_err_mask |= AC_ERR_HOST_BUS;
789
936fd732 790 if (sata_scr_valid(&ap->link)) {
da3dbb17
TH		 791 u32 serror;
792
793 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
794 ehi->serror |= serror;
795 }
ce2d3abc 796
176efb05 797 qc->err_mask |= ac_err_mask;
ce2d3abc
MP		 798
799 pdc_reset_port(ap);
8ffcfd9d
MP		 800
801 ata_port_abort(ap);
176efb05
MP		 802}
803
d0e58031
MP		 804static inline unsigned int pdc_host_intr(struct ata_port *ap,
805 struct ata_queued_cmd *qc)
1da177e4 806{
a22e2eb0 807 unsigned int handled = 0;
176efb05 808 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
176efb05
MP		 809 u32 port_status, err_mask;
810
811 err_mask = PDC_ERR_MASK;
eca25dca 812 if (ap->flags & PDC_FLAG_GEN_II)
176efb05
MP		 813 err_mask &= ~PDC1_ERR_MASK;
814 else
815 err_mask &= ~PDC2_ERR_MASK;
816 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
817 if (unlikely(port_status & err_mask)) {
818 pdc_error_intr(ap, qc, port_status, err_mask);
819 return 1;
1da177e4
LT		 820 }
821
822 switch (qc->tf.protocol) {
823 case ATA_PROT_DMA:
824 case ATA_PROT_NODATA:
0dc36888
TH		 825 case ATAPI_PROT_DMA:
826 case ATAPI_PROT_NODATA:
a22e2eb0
AL		 827 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
828 ata_qc_complete(qc);
1da177e4
LT		 829 handled = 1;
830 break;
831
d0e58031 832 default:
ee500aab
AL		 833 ap->stats.idle_irq++;
834 break;
d0e58031 835 }
1da177e4 836
ee500aab 837 return handled;
1da177e4
LT		 838}
839
840static void pdc_irq_clear(struct ata_port *ap)
841{
cca3974e 842 struct ata_host *host = ap->host;
0d5ff566 843 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 844
845 readl(mmio + PDC_INT_SEQMASK);
846}
847
5796d1c4 848static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
1da177e4 849{
cca3974e 850 struct ata_host *host = dev_instance;
1da177e4
LT		 851 struct ata_port *ap;
852 u32 mask = 0;
853 unsigned int i, tmp;
854 unsigned int handled = 0;
ea6ba10b 855 void __iomem *mmio_base;
a77720ad
MP		 856 unsigned int hotplug_offset, ata_no;
857 u32 hotplug_status;
858 int is_sataii_tx4;
1da177e4
LT		 859
860 VPRINTK("ENTER\n");
861
0d5ff566 862 if (!host || !host->iomap[PDC_MMIO_BAR]) {
1da177e4
LT		 863 VPRINTK("QUICK EXIT\n");
864 return IRQ_NONE;
865 }
866
0d5ff566 867 mmio_base = host->iomap[PDC_MMIO_BAR];
1da177e4 868
c07a9c49
MP		 869 spin_lock(&host->lock);
870
a77720ad
MP		 871 /* read and clear hotplug flags for all ports */
872 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
873 hotplug_offset = PDC2_SATA_PLUG_CSR;
874 else
875 hotplug_offset = PDC_SATA_PLUG_CSR;
876 hotplug_status = readl(mmio_base + hotplug_offset);
877 if (hotplug_status & 0xff)
878 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
879 hotplug_status &= 0xff; /* clear uninteresting bits */
880
1da177e4
LT		 881 /* reading should also clear interrupts */
882 mask = readl(mmio_base + PDC_INT_SEQMASK);
883
a77720ad 884 if (mask == 0xffffffff && hotplug_status == 0) {
1da177e4 885 VPRINTK("QUICK EXIT 2\n");
c07a9c49 886 goto done_irq;
1da177e4 887 }
6340f019 888
1da177e4 889 mask &= 0xffff; /* only 16 tags possible */
a77720ad 890 if (mask == 0 && hotplug_status == 0) {
1da177e4 891 VPRINTK("QUICK EXIT 3\n");
6340f019 892 goto done_irq;
1da177e4
LT		 893 }
894
1da177e4
LT		 895 writel(mask, mmio_base + PDC_INT_SEQMASK);
896
a77720ad
MP		 897 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
898
cca3974e 899 for (i = 0; i < host->n_ports; i++) {
1da177e4 900 VPRINTK("port %u\n", i);
cca3974e 901 ap = host->ports[i];
a77720ad
MP		 902
903 /* check for a plug or unplug event */
904 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
905 tmp = hotplug_status & (0x11 << ata_no);
906 if (tmp && ap &&
907 !(ap->flags & ATA_FLAG_DISABLED)) {
9af5c9c9 908 struct ata_eh_info *ehi = &ap->link.eh_info;
a77720ad
MP		 909 ata_ehi_clear_desc(ehi);
910 ata_ehi_hotplugged(ehi);
911 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
912 ata_port_freeze(ap);
913 ++handled;
914 continue;
915 }
916
917 /* check for a packet interrupt */
1da177e4 918 tmp = mask & (1 << (i + 1));
c1389503 919 if (tmp && ap &&
029f5468 920 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 921 struct ata_queued_cmd *qc;
922
9af5c9c9 923 qc = ata_qc_from_tag(ap, ap->link.active_tag);
e50362ec 924 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4
LT		 925 handled += pdc_host_intr(ap, qc);
926 }
927 }
928
1da177e4
LT		 929 VPRINTK("EXIT\n");
930
6340f019 931done_irq:
cca3974e 932 spin_unlock(&host->lock);
1da177e4
LT		 933 return IRQ_RETVAL(handled);
934}
935
936static inline void pdc_packet_start(struct ata_queued_cmd *qc)
937{
938 struct ata_port *ap = qc->ap;
939 struct pdc_port_priv *pp = ap->private_data;
0d5ff566 940 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 941 unsigned int port_no = ap->port_no;
942 u8 seq = (u8) (port_no + 1);
943
944 VPRINTK("ENTER, ap %p\n", ap);
945
0d5ff566
TH		 946 writel(0x00000001, mmio + (seq * 4));
947 readl(mmio + (seq * 4)); /* flush */
1da177e4
LT		 948
949 pp->pkt[2] = seq;
950 wmb(); /* flush PRD, pkt writes */
0d5ff566
TH		 951 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
952 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
1da177e4
LT		 953}
954
9a3d9eb0 955static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 956{
957 switch (qc->tf.protocol) {
0dc36888 958 case ATAPI_PROT_NODATA:
fba6edbd
MP		 959 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
960 break;
961 /*FALLTHROUGH*/
51b94d2a
TH		 962 case ATA_PROT_NODATA:
963 if (qc->tf.flags & ATA_TFLAG_POLLING)
964 break;
965 /*FALLTHROUGH*/
0dc36888 966 case ATAPI_PROT_DMA:
1da177e4 967 case ATA_PROT_DMA:
1da177e4
LT		 968 pdc_packet_start(qc);
969 return 0;
970
1da177e4
LT		 971 default:
972 break;
973 }
974
975 return ata_qc_issue_prot(qc);
976}
977
057ace5e 978static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4 979{
0dc36888 980 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1da177e4
LT		 981 ata_tf_load(ap, tf);
982}
983
5796d1c4
JG		 984static void pdc_exec_command_mmio(struct ata_port *ap,
985 const struct ata_taskfile *tf)
1da177e4 986{
0dc36888 987 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1da177e4
LT		 988 ata_exec_command(ap, tf);
989}
990
95006188
MP		 991static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
992{
993 u8 *scsicmd = qc->scsicmd->cmnd;
994 int pio = 1; /* atapi dma off by default */
995
996 /* Whitelist commands that may use DMA. */
997 switch (scsicmd[0]) {
998 case WRITE_12:
999 case WRITE_10:
1000 case WRITE_6:
1001 case READ_12:
1002 case READ_10:
1003 case READ_6:
1004 case 0xad: /* READ_DVD_STRUCTURE */
1005 case 0xbe: /* READ_CD */
1006 pio = 0;
1007 }
1008 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1009 if (scsicmd[0] == WRITE_10) {
5796d1c4
JG		 1010 unsigned int lba =
1011 (scsicmd[2] << 24) |
1012 (scsicmd[3] << 16) |
1013 (scsicmd[4] << 8) |
1014 scsicmd[5];
95006188
MP		 1015 if (lba >= 0xFFFF4FA2)
1016 pio = 1;
1017 }
1018 return pio;
1019}
1020
724114a5 1021static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
95006188 1022{
95006188 1023 /* First generation chips cannot use ATAPI DMA on SATA ports */
724114a5 1024 return 1;
95006188 1025}
1da177e4 1026
eca25dca
TH		 1027static void pdc_ata_setup_port(struct ata_port *ap,
1028 void __iomem *base, void __iomem *scr_addr)
1da177e4 1029{
eca25dca
TH		 1030 ap->ioaddr.cmd_addr = base;
1031 ap->ioaddr.data_addr = base;
1032 ap->ioaddr.feature_addr =
1033 ap->ioaddr.error_addr = base + 0x4;
1034 ap->ioaddr.nsect_addr = base + 0x8;
1035 ap->ioaddr.lbal_addr = base + 0xc;
1036 ap->ioaddr.lbam_addr = base + 0x10;
1037 ap->ioaddr.lbah_addr = base + 0x14;
1038 ap->ioaddr.device_addr = base + 0x18;
1039 ap->ioaddr.command_addr =
1040 ap->ioaddr.status_addr = base + 0x1c;
1041 ap->ioaddr.altstatus_addr =
1042 ap->ioaddr.ctl_addr = base + 0x38;
1043 ap->ioaddr.scr_addr = scr_addr;
1da177e4
LT		 1044}
1045
eca25dca 1046static void pdc_host_init(struct ata_host *host)
1da177e4 1047{
eca25dca
TH		 1048 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1049 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
d324d462 1050 int hotplug_offset;
1da177e4
LT		 1051 u32 tmp;
1052
eca25dca 1053 if (is_gen2)
d324d462
MP		 1054 hotplug_offset = PDC2_SATA_PLUG_CSR;
1055 else
1056 hotplug_offset = PDC_SATA_PLUG_CSR;
1057
1da177e4
LT		 1058 /*
1059 * Except for the hotplug stuff, this is voodoo from the
1060 * Promise driver. Label this entire section
1061 * "TODO: figure out why we do this"
1062 */
1063
b2d1eee1 1064 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1da177e4 1065 tmp = readl(mmio + PDC_FLASH_CTL);
b2d1eee1 1066 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
eca25dca 1067 if (!is_gen2)
b2d1eee1 1068 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1da177e4
LT		 1069 writel(tmp, mmio + PDC_FLASH_CTL);
1070
1071 /* clear plug/unplug flags for all ports */
6340f019
LK		 1072 tmp = readl(mmio + hotplug_offset);
1073 writel(tmp | 0xff, mmio + hotplug_offset);
1da177e4 1074
a77720ad 1075 /* unmask plug/unplug ints */
6340f019 1076 tmp = readl(mmio + hotplug_offset);
a77720ad 1077 writel(tmp & ~0xff0000, mmio + hotplug_offset);
1da177e4 1078
b2d1eee1 1079 /* don't initialise TBG or SLEW on 2nd generation chips */
eca25dca 1080 if (is_gen2)
b2d1eee1
MP		 1081 return;
1082
1da177e4
LT		 1083 /* reduce TBG clock to 133 Mhz. */
1084 tmp = readl(mmio + PDC_TBG_MODE);
1085 tmp &= ~0x30000; /* clear bit 17, 16*/
1086 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1087 writel(tmp, mmio + PDC_TBG_MODE);
1088
1089 readl(mmio + PDC_TBG_MODE); /* flush */
1090 msleep(10);
1091
1092 /* adjust slew rate control register. */
1093 tmp = readl(mmio + PDC_SLEW_CTL);
1094 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1095 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1096 writel(tmp, mmio + PDC_SLEW_CTL);
1097}
1098
5796d1c4
JG		 1099static int pdc_ata_init_one(struct pci_dev *pdev,
1100 const struct pci_device_id *ent)
1da177e4
LT		 1101{
1102 static int printed_version;
eca25dca
TH		 1103 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1104 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1105 struct ata_host *host;
0d5ff566 1106 void __iomem *base;
eca25dca 1107 int n_ports, i, rc;
5ac2fe57 1108 int is_sataii_tx4;
1da177e4
LT		 1109
1110 if (!printed_version++)
a9524a76 1111 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1112
eca25dca 1113 /* enable and acquire resources */
24dc5f33 1114 rc = pcim_enable_device(pdev);
1da177e4
LT		 1115 if (rc)
1116 return rc;
1117
0d5ff566
TH		 1118 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1119 if (rc == -EBUSY)
24dc5f33 1120 pcim_pin_device(pdev);
0d5ff566 1121 if (rc)
24dc5f33 1122 return rc;
eca25dca 1123 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1da177e4 1124
eca25dca
TH		 1125 /* determine port configuration and setup host */
1126 n_ports = 2;
1127 if (pi->flags & PDC_FLAG_4_PORTS)
1128 n_ports = 4;
1129 for (i = 0; i < n_ports; i++)
1130 ppi[i] = pi;
1da177e4 1131
eca25dca
TH		 1132 if (pi->flags & PDC_FLAG_SATA_PATA) {
1133 u8 tmp = readb(base + PDC_FLASH_CTL+1);
d0e58031 1134 if (!(tmp & 0x80))
eca25dca 1135 ppi[n_ports++] = pi + 1;
eca25dca 1136 }
1da177e4 1137
eca25dca
TH		 1138 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1139 if (!host) {
1140 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
24dc5f33 1141 return -ENOMEM;
1da177e4 1142 }
eca25dca 1143 host->iomap = pcim_iomap_table(pdev);
1da177e4 1144
d0e58031 1145 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
5ac2fe57 1146 for (i = 0; i < host->n_ports; i++) {
cbcdd875 1147 struct ata_port *ap = host->ports[i];
d0e58031 1148 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
cbcdd875
TH		 1149 unsigned int port_offset = 0x200 + ata_no * 0x80;
1150 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1151
1152 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1153
1154 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1155 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
5ac2fe57 1156 }
1da177e4
LT		 1157
1158 /* initialize adapter */
eca25dca 1159 pdc_host_init(host);
1da177e4 1160
eca25dca
TH		 1161 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1162 if (rc)
1163 return rc;
1164 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1165 if (rc)
1166 return rc;
1da177e4 1167
eca25dca
TH		 1168 /* start host, request IRQ and attach */
1169 pci_set_master(pdev);
1170 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1171 &pdc_ata_sht);
1da177e4
LT		 1172}
1173
1da177e4
LT		 1174static int __init pdc_ata_init(void)
1175{
b7887196 1176 return pci_register_driver(&pdc_ata_pci_driver);
1da177e4
LT		 1177}
1178
1da177e4
LT		 1179static void __exit pdc_ata_exit(void)
1180{
1181 pci_unregister_driver(&pdc_ata_pci_driver);
1182}
1183
1da177e4 1184MODULE_AUTHOR("Jeff Garzik");
f497ba73 1185MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1da177e4
LT		 1186MODULE_LICENSE("GPL");
1187MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1188MODULE_VERSION(DRV_VERSION);
1189
1190module_init(pdc_ata_init);
1191module_exit(pdc_ata_exit);
Linux kernel - Deliverables
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