Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
95006188 | 42 | #include <scsi/scsi.h> |
1da177e4 | 43 | #include <scsi/scsi_host.h> |
193515d5 | 44 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
45 | #include <linux/libata.h> |
46 | #include <asm/io.h> | |
47 | #include "sata_promise.h" | |
48 | ||
49 | #define DRV_NAME "sata_promise" | |
46b027cc | 50 | #define DRV_VERSION "1.05" |
1da177e4 LT |
51 | |
52 | ||
53 | enum { | |
95006188 MP |
54 | /* register offsets */ |
55 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
56 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
57 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
58 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
59 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
60 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
61 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 62 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 LT |
63 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
64 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 65 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
66 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
67 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
68 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 69 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
70 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
71 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 LT |
72 | |
73 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
74 | (1<<8) | (1<<9) | (1<<10), | |
75 | ||
76 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
77 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 78 | board_20619 = 2, /* FastTrak TX4000 */ |
d324d462 MP |
79 | board_2057x = 3, /* SATAII150 Tx2plus */ |
80 | board_40518 = 4, /* SATAII150 Tx4 */ | |
1da177e4 | 81 | |
6340f019 | 82 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 83 | |
95006188 MP |
84 | /* Sequence counter control registers bit definitions */ |
85 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
86 | ||
87 | /* Feature register values */ | |
88 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
89 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
90 | ||
91 | /* Device/Head register values */ | |
92 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
93 | ||
25b93d81 MP |
94 | /* PDC_CTLSTAT bit definitions */ |
95 | PDC_DMA_ENABLE = (1 << 7), | |
96 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 97 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 98 | |
25b93d81 | 99 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 100 | ATA_FLAG_MMIO | |
3d0a59c0 | 101 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 MP |
102 | |
103 | /* hp->flags bits */ | |
104 | PDC_FLAG_GEN_II = (1 << 0), | |
1da177e4 LT |
105 | }; |
106 | ||
107 | ||
108 | struct pdc_port_priv { | |
109 | u8 *pkt; | |
110 | dma_addr_t pkt_dma; | |
111 | }; | |
112 | ||
6340f019 | 113 | struct pdc_host_priv { |
b2d1eee1 | 114 | unsigned long flags; |
870ae337 | 115 | unsigned long port_flags[ATA_MAX_PORTS]; |
6340f019 LK |
116 | }; |
117 | ||
1da177e4 LT |
118 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
119 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
120 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
7d12e780 | 121 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance); |
1da177e4 LT |
122 | static void pdc_eng_timeout(struct ata_port *ap); |
123 | static int pdc_port_start(struct ata_port *ap); | |
124 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a | 125 | static void pdc_pata_phy_reset(struct ata_port *ap); |
1da177e4 | 126 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
127 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
128 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 MP |
129 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
130 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc); | |
1da177e4 | 131 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 132 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
cca3974e | 133 | static void pdc_host_stop(struct ata_host *host); |
25b93d81 MP |
134 | static void pdc_freeze(struct ata_port *ap); |
135 | static void pdc_thaw(struct ata_port *ap); | |
136 | static void pdc_error_handler(struct ata_port *ap); | |
137 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); | |
1da177e4 | 138 | |
374b1873 | 139 | |
193515d5 | 140 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
141 | .module = THIS_MODULE, |
142 | .name = DRV_NAME, | |
143 | .ioctl = ata_scsi_ioctl, | |
144 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
145 | .can_queue = ATA_DEF_QUEUE, |
146 | .this_id = ATA_SHT_THIS_ID, | |
147 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
148 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
149 | .emulated = ATA_SHT_EMULATED, | |
150 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
151 | .proc_name = DRV_NAME, | |
152 | .dma_boundary = ATA_DMA_BOUNDARY, | |
153 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 154 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 155 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
156 | }; |
157 | ||
057ace5e | 158 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
159 | .port_disable = ata_port_disable, |
160 | .tf_load = pdc_tf_load_mmio, | |
161 | .tf_read = ata_tf_read, | |
162 | .check_status = ata_check_status, | |
163 | .exec_command = pdc_exec_command_mmio, | |
164 | .dev_select = ata_std_dev_select, | |
95006188 MP |
165 | .check_atapi_dma = pdc_check_atapi_dma, |
166 | ||
167 | .qc_prep = pdc_qc_prep, | |
168 | .qc_issue = pdc_qc_issue_prot, | |
169 | .freeze = pdc_freeze, | |
170 | .thaw = pdc_thaw, | |
171 | .error_handler = pdc_error_handler, | |
172 | .post_internal_cmd = pdc_post_internal_cmd, | |
173 | .data_xfer = ata_mmio_data_xfer, | |
174 | .irq_handler = pdc_interrupt, | |
175 | .irq_clear = pdc_irq_clear, | |
176 | ||
177 | .scr_read = pdc_sata_scr_read, | |
178 | .scr_write = pdc_sata_scr_write, | |
179 | .port_start = pdc_port_start, | |
180 | .port_stop = pdc_port_stop, | |
181 | .host_stop = pdc_host_stop, | |
182 | }; | |
183 | ||
184 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
185 | static const struct ata_port_operations pdc_old_sata_ops = { | |
186 | .port_disable = ata_port_disable, | |
187 | .tf_load = pdc_tf_load_mmio, | |
188 | .tf_read = ata_tf_read, | |
189 | .check_status = ata_check_status, | |
190 | .exec_command = pdc_exec_command_mmio, | |
191 | .dev_select = ata_std_dev_select, | |
192 | .check_atapi_dma = pdc_old_check_atapi_dma, | |
2cba582a | 193 | |
1da177e4 LT |
194 | .qc_prep = pdc_qc_prep, |
195 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
196 | .freeze = pdc_freeze, |
197 | .thaw = pdc_thaw, | |
198 | .error_handler = pdc_error_handler, | |
199 | .post_internal_cmd = pdc_post_internal_cmd, | |
a6b2c5d4 | 200 | .data_xfer = ata_mmio_data_xfer, |
1da177e4 LT |
201 | .irq_handler = pdc_interrupt, |
202 | .irq_clear = pdc_irq_clear, | |
2cba582a | 203 | |
1da177e4 LT |
204 | .scr_read = pdc_sata_scr_read, |
205 | .scr_write = pdc_sata_scr_write, | |
206 | .port_start = pdc_port_start, | |
207 | .port_stop = pdc_port_stop, | |
6340f019 | 208 | .host_stop = pdc_host_stop, |
1da177e4 LT |
209 | }; |
210 | ||
057ace5e | 211 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
212 | .port_disable = ata_port_disable, |
213 | .tf_load = pdc_tf_load_mmio, | |
214 | .tf_read = ata_tf_read, | |
215 | .check_status = ata_check_status, | |
216 | .exec_command = pdc_exec_command_mmio, | |
217 | .dev_select = ata_std_dev_select, | |
95006188 | 218 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a JG |
219 | |
220 | .phy_reset = pdc_pata_phy_reset, | |
221 | ||
222 | .qc_prep = pdc_qc_prep, | |
223 | .qc_issue = pdc_qc_issue_prot, | |
a6b2c5d4 | 224 | .data_xfer = ata_mmio_data_xfer, |
2cba582a JG |
225 | .eng_timeout = pdc_eng_timeout, |
226 | .irq_handler = pdc_interrupt, | |
227 | .irq_clear = pdc_irq_clear, | |
228 | ||
229 | .port_start = pdc_port_start, | |
230 | .port_stop = pdc_port_stop, | |
6340f019 | 231 | .host_stop = pdc_host_stop, |
2cba582a JG |
232 | }; |
233 | ||
98ac62de | 234 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
235 | /* board_2037x */ |
236 | { | |
237 | .sht = &pdc_ata_sht, | |
870ae337 | 238 | .flags = PDC_COMMON_FLAGS, |
1da177e4 LT |
239 | .pio_mask = 0x1f, /* pio0-4 */ |
240 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
241 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 242 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
243 | }, |
244 | ||
245 | /* board_20319 */ | |
246 | { | |
247 | .sht = &pdc_ata_sht, | |
cca3974e | 248 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
249 | .pio_mask = 0x1f, /* pio0-4 */ |
250 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
251 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 252 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 253 | }, |
f497ba73 TL |
254 | |
255 | /* board_20619 */ | |
256 | { | |
257 | .sht = &pdc_ata_sht, | |
25b93d81 | 258 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
259 | .pio_mask = 0x1f, /* pio0-4 */ |
260 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
261 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 262 | .port_ops = &pdc_pata_ops, |
f497ba73 | 263 | }, |
5a46fe89 | 264 | |
6340f019 LK |
265 | /* board_2057x */ |
266 | { | |
267 | .sht = &pdc_ata_sht, | |
870ae337 | 268 | .flags = PDC_COMMON_FLAGS, |
6340f019 LK |
269 | .pio_mask = 0x1f, /* pio0-4 */ |
270 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
271 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
272 | .port_ops = &pdc_sata_ops, | |
273 | }, | |
274 | ||
275 | /* board_40518 */ | |
276 | { | |
277 | .sht = &pdc_ata_sht, | |
cca3974e | 278 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
279 | .pio_mask = 0x1f, /* pio0-4 */ |
280 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
281 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
282 | .port_ops = &pdc_sata_ops, | |
283 | }, | |
1da177e4 LT |
284 | }; |
285 | ||
3b7d697d | 286 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 287 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
288 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
289 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
290 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
291 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
292 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 293 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 294 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 295 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 296 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
297 | |
298 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
299 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
300 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
301 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
b2d1eee1 | 302 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
303 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
304 | ||
305 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 306 | |
1da177e4 LT |
307 | { } /* terminate list */ |
308 | }; | |
309 | ||
310 | ||
311 | static struct pci_driver pdc_ata_pci_driver = { | |
312 | .name = DRV_NAME, | |
313 | .id_table = pdc_ata_pci_tbl, | |
314 | .probe = pdc_ata_init_one, | |
315 | .remove = ata_pci_remove_one, | |
316 | }; | |
317 | ||
318 | ||
319 | static int pdc_port_start(struct ata_port *ap) | |
320 | { | |
cca3974e | 321 | struct device *dev = ap->host->dev; |
599b7202 | 322 | struct pdc_host_priv *hp = ap->host->private_data; |
1da177e4 LT |
323 | struct pdc_port_priv *pp; |
324 | int rc; | |
325 | ||
870ae337 MP |
326 | /* fix up port flags and cable type for SATA+PATA chips */ |
327 | ap->flags |= hp->port_flags[ap->port_no]; | |
328 | if (ap->flags & ATA_FLAG_SATA) | |
329 | ap->cbl = ATA_CBL_SATA; | |
330 | ||
1da177e4 LT |
331 | rc = ata_port_start(ap); |
332 | if (rc) | |
333 | return rc; | |
334 | ||
6340f019 | 335 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
336 | if (!pp) { |
337 | rc = -ENOMEM; | |
338 | goto err_out; | |
339 | } | |
1da177e4 LT |
340 | |
341 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
342 | if (!pp->pkt) { | |
343 | rc = -ENOMEM; | |
344 | goto err_out_kfree; | |
345 | } | |
346 | ||
347 | ap->private_data = pp; | |
348 | ||
599b7202 MP |
349 | /* fix up PHYMODE4 align timing */ |
350 | if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) { | |
351 | void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr; | |
352 | unsigned int tmp; | |
353 | ||
354 | tmp = readl(mmio + 0x014); | |
355 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
356 | writel(tmp, mmio + 0x014); | |
357 | } | |
358 | ||
1da177e4 LT |
359 | return 0; |
360 | ||
361 | err_out_kfree: | |
362 | kfree(pp); | |
363 | err_out: | |
364 | ata_port_stop(ap); | |
365 | return rc; | |
366 | } | |
367 | ||
368 | ||
369 | static void pdc_port_stop(struct ata_port *ap) | |
370 | { | |
cca3974e | 371 | struct device *dev = ap->host->dev; |
1da177e4 LT |
372 | struct pdc_port_priv *pp = ap->private_data; |
373 | ||
374 | ap->private_data = NULL; | |
375 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
376 | kfree(pp); | |
377 | ata_port_stop(ap); | |
378 | } | |
379 | ||
380 | ||
cca3974e | 381 | static void pdc_host_stop(struct ata_host *host) |
6340f019 | 382 | { |
cca3974e | 383 | struct pdc_host_priv *hp = host->private_data; |
6340f019 | 384 | |
cca3974e | 385 | ata_pci_host_stop(host); |
6340f019 LK |
386 | |
387 | kfree(hp); | |
388 | } | |
389 | ||
390 | ||
1da177e4 LT |
391 | static void pdc_reset_port(struct ata_port *ap) |
392 | { | |
ea6ba10b | 393 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
394 | unsigned int i; |
395 | u32 tmp; | |
396 | ||
397 | for (i = 11; i > 0; i--) { | |
398 | tmp = readl(mmio); | |
399 | if (tmp & PDC_RESET) | |
400 | break; | |
401 | ||
402 | udelay(100); | |
403 | ||
404 | tmp |= PDC_RESET; | |
405 | writel(tmp, mmio); | |
406 | } | |
407 | ||
408 | tmp &= ~PDC_RESET; | |
409 | writel(tmp, mmio); | |
410 | readl(mmio); /* flush */ | |
411 | } | |
412 | ||
d3fb4e8d | 413 | static void pdc_pata_cbl_detect(struct ata_port *ap) |
2cba582a | 414 | { |
d3fb4e8d | 415 | u8 tmp; |
03dc5506 | 416 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d JG |
417 | |
418 | tmp = readb(mmio); | |
419 | ||
420 | if (tmp & 0x01) { | |
421 | ap->cbl = ATA_CBL_PATA40; | |
422 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
423 | } else | |
424 | ap->cbl = ATA_CBL_PATA80; | |
425 | } | |
2cba582a | 426 | |
d3fb4e8d JG |
427 | static void pdc_pata_phy_reset(struct ata_port *ap) |
428 | { | |
429 | pdc_pata_cbl_detect(ap); | |
2cba582a JG |
430 | pdc_reset_port(ap); |
431 | ata_port_probe(ap); | |
432 | ata_bus_reset(ap); | |
433 | } | |
434 | ||
1da177e4 LT |
435 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
436 | { | |
870ae337 | 437 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 438 | return 0xffffffffU; |
b181d3b0 | 439 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
440 | } |
441 | ||
442 | ||
443 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
444 | u32 val) | |
445 | { | |
870ae337 | 446 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 447 | return; |
b181d3b0 | 448 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
449 | } |
450 | ||
95006188 MP |
451 | static void pdc_atapi_dma_pkt(struct ata_taskfile *tf, |
452 | dma_addr_t sg_table, | |
453 | unsigned int cdb_len, u8 *cdb, | |
454 | u8 *buf) | |
455 | { | |
456 | u32 *buf32 = (u32 *) buf; | |
457 | ||
458 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
459 | * and seq id (byte 2) | |
460 | */ | |
461 | if (!(tf->flags & ATA_TFLAG_WRITE)) | |
462 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
463 | else | |
464 | buf32[0] = 0; | |
465 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ | |
466 | buf32[2] = 0; /* no next-packet */ | |
467 | ||
468 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ | |
469 | BUG_ON(cdb_len & ~0x1E); | |
470 | ||
471 | buf[12] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
472 | memcpy(buf+13, cdb, cdb_len); | |
473 | } | |
474 | ||
1da177e4 LT |
475 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
476 | { | |
477 | struct pdc_port_priv *pp = qc->ap->private_data; | |
478 | unsigned int i; | |
479 | ||
480 | VPRINTK("ENTER\n"); | |
481 | ||
482 | switch (qc->tf.protocol) { | |
483 | case ATA_PROT_DMA: | |
484 | ata_qc_prep(qc); | |
485 | /* fall through */ | |
486 | ||
487 | case ATA_PROT_NODATA: | |
488 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
489 | qc->dev->devno, pp->pkt); | |
490 | ||
491 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
492 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
493 | else | |
494 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
495 | ||
496 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
497 | break; | |
498 | ||
95006188 MP |
499 | case ATA_PROT_ATAPI: |
500 | case ATA_PROT_ATAPI_NODATA: | |
501 | ata_qc_prep(qc); | |
502 | break; | |
503 | ||
504 | case ATA_PROT_ATAPI_DMA: | |
505 | ata_qc_prep(qc); | |
506 | pdc_atapi_dma_pkt(&qc->tf, qc->ap->prd_dma, qc->dev->cdb_len, qc->cdb, pp->pkt); | |
507 | break; | |
508 | ||
1da177e4 LT |
509 | default: |
510 | break; | |
511 | } | |
512 | } | |
513 | ||
25b93d81 MP |
514 | static void pdc_freeze(struct ata_port *ap) |
515 | { | |
516 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
517 | u32 tmp; | |
518 | ||
519 | tmp = readl(mmio + PDC_CTLSTAT); | |
520 | tmp |= PDC_IRQ_DISABLE; | |
521 | tmp &= ~PDC_DMA_ENABLE; | |
522 | writel(tmp, mmio + PDC_CTLSTAT); | |
523 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
524 | } | |
525 | ||
526 | static void pdc_thaw(struct ata_port *ap) | |
527 | { | |
528 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
529 | u32 tmp; | |
530 | ||
531 | /* clear IRQ */ | |
532 | readl(mmio + PDC_INT_SEQMASK); | |
533 | ||
534 | /* turn IRQ back on */ | |
535 | tmp = readl(mmio + PDC_CTLSTAT); | |
536 | tmp &= ~PDC_IRQ_DISABLE; | |
537 | writel(tmp, mmio + PDC_CTLSTAT); | |
538 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
539 | } | |
540 | ||
541 | static void pdc_error_handler(struct ata_port *ap) | |
542 | { | |
543 | ata_reset_fn_t hardreset; | |
544 | ||
545 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) | |
546 | pdc_reset_port(ap); | |
547 | ||
548 | hardreset = NULL; | |
549 | if (sata_scr_valid(ap)) | |
550 | hardreset = sata_std_hardreset; | |
551 | ||
552 | /* perform recovery */ | |
553 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, | |
554 | ata_std_postreset); | |
555 | } | |
556 | ||
557 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) | |
558 | { | |
559 | struct ata_port *ap = qc->ap; | |
560 | ||
561 | if (qc->flags & ATA_QCFLAG_FAILED) | |
562 | qc->err_mask |= AC_ERR_OTHER; | |
563 | ||
564 | /* make DMA engine forget about the failed command */ | |
565 | if (qc->err_mask) | |
566 | pdc_reset_port(ap); | |
567 | } | |
568 | ||
1da177e4 LT |
569 | static void pdc_eng_timeout(struct ata_port *ap) |
570 | { | |
cca3974e | 571 | struct ata_host *host = ap->host; |
1da177e4 LT |
572 | u8 drv_stat; |
573 | struct ata_queued_cmd *qc; | |
b8f6153e | 574 | unsigned long flags; |
1da177e4 LT |
575 | |
576 | DPRINTK("ENTER\n"); | |
577 | ||
cca3974e | 578 | spin_lock_irqsave(&host->lock, flags); |
b8f6153e | 579 | |
1da177e4 | 580 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1da177e4 | 581 | |
1da177e4 LT |
582 | switch (qc->tf.protocol) { |
583 | case ATA_PROT_DMA: | |
584 | case ATA_PROT_NODATA: | |
f15a1daf | 585 | ata_port_printk(ap, KERN_ERR, "command timeout\n"); |
a7dac447 | 586 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 587 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
588 | break; |
589 | ||
590 | default: | |
591 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
592 | ||
f15a1daf TH |
593 | ata_port_printk(ap, KERN_ERR, |
594 | "unknown timeout, cmd 0x%x stat 0x%x\n", | |
595 | qc->tf.command, drv_stat); | |
1da177e4 | 596 | |
a22e2eb0 | 597 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
598 | break; |
599 | } | |
600 | ||
cca3974e | 601 | spin_unlock_irqrestore(&host->lock, flags); |
f6379020 | 602 | ata_eh_qc_complete(qc); |
1da177e4 LT |
603 | DPRINTK("EXIT\n"); |
604 | } | |
605 | ||
606 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
607 | struct ata_queued_cmd *qc) | |
608 | { | |
a22e2eb0 | 609 | unsigned int handled = 0; |
1da177e4 | 610 | u32 tmp; |
ea6ba10b | 611 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
612 | |
613 | tmp = readl(mmio); | |
614 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 615 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
616 | pdc_reset_port(ap); |
617 | } | |
618 | ||
619 | switch (qc->tf.protocol) { | |
620 | case ATA_PROT_DMA: | |
621 | case ATA_PROT_NODATA: | |
95006188 | 622 | case ATA_PROT_ATAPI_DMA: |
a22e2eb0 AL |
623 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
624 | ata_qc_complete(qc); | |
1da177e4 LT |
625 | handled = 1; |
626 | break; | |
627 | ||
628 | default: | |
ee500aab AL |
629 | ap->stats.idle_irq++; |
630 | break; | |
1da177e4 LT |
631 | } |
632 | ||
ee500aab | 633 | return handled; |
1da177e4 LT |
634 | } |
635 | ||
636 | static void pdc_irq_clear(struct ata_port *ap) | |
637 | { | |
cca3974e JG |
638 | struct ata_host *host = ap->host; |
639 | void __iomem *mmio = host->mmio_base; | |
1da177e4 LT |
640 | |
641 | readl(mmio + PDC_INT_SEQMASK); | |
642 | } | |
643 | ||
7d12e780 | 644 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 645 | { |
cca3974e | 646 | struct ata_host *host = dev_instance; |
1da177e4 LT |
647 | struct ata_port *ap; |
648 | u32 mask = 0; | |
649 | unsigned int i, tmp; | |
650 | unsigned int handled = 0; | |
ea6ba10b | 651 | void __iomem *mmio_base; |
1da177e4 LT |
652 | |
653 | VPRINTK("ENTER\n"); | |
654 | ||
cca3974e | 655 | if (!host || !host->mmio_base) { |
1da177e4 LT |
656 | VPRINTK("QUICK EXIT\n"); |
657 | return IRQ_NONE; | |
658 | } | |
659 | ||
cca3974e | 660 | mmio_base = host->mmio_base; |
1da177e4 LT |
661 | |
662 | /* reading should also clear interrupts */ | |
663 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
664 | ||
665 | if (mask == 0xffffffff) { | |
666 | VPRINTK("QUICK EXIT 2\n"); | |
667 | return IRQ_NONE; | |
668 | } | |
6340f019 | 669 | |
cca3974e | 670 | spin_lock(&host->lock); |
6340f019 | 671 | |
1da177e4 LT |
672 | mask &= 0xffff; /* only 16 tags possible */ |
673 | if (!mask) { | |
674 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 675 | goto done_irq; |
1da177e4 LT |
676 | } |
677 | ||
1da177e4 LT |
678 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
679 | ||
cca3974e | 680 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 681 | VPRINTK("port %u\n", i); |
cca3974e | 682 | ap = host->ports[i]; |
1da177e4 | 683 | tmp = mask & (1 << (i + 1)); |
c1389503 | 684 | if (tmp && ap && |
029f5468 | 685 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
686 | struct ata_queued_cmd *qc; |
687 | ||
688 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 689 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
690 | handled += pdc_host_intr(ap, qc); |
691 | } | |
692 | } | |
693 | ||
1da177e4 LT |
694 | VPRINTK("EXIT\n"); |
695 | ||
6340f019 | 696 | done_irq: |
cca3974e | 697 | spin_unlock(&host->lock); |
1da177e4 LT |
698 | return IRQ_RETVAL(handled); |
699 | } | |
700 | ||
701 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
702 | { | |
703 | struct ata_port *ap = qc->ap; | |
704 | struct pdc_port_priv *pp = ap->private_data; | |
705 | unsigned int port_no = ap->port_no; | |
706 | u8 seq = (u8) (port_no + 1); | |
707 | ||
708 | VPRINTK("ENTER, ap %p\n", ap); | |
709 | ||
cca3974e JG |
710 | writel(0x00000001, ap->host->mmio_base + (seq * 4)); |
711 | readl(ap->host->mmio_base + (seq * 4)); /* flush */ | |
1da177e4 LT |
712 | |
713 | pp->pkt[2] = seq; | |
714 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
715 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
716 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
717 | } |
718 | ||
95006188 MP |
719 | static unsigned int pdc_wait_for_drq(struct ata_port *ap) |
720 | { | |
721 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
722 | unsigned int i; | |
723 | unsigned int status; | |
724 | ||
725 | /* Following pdc-ultra's WaitForDrq() we loop here until BSY | |
726 | * is clear and DRQ is set in altstatus. We could possibly call | |
727 | * ata_busy_wait() and loop until DRQ is set, but since we don't | |
728 | * know how much time a call to ata_busy_wait() took, we don't | |
729 | * know when to time out the outer loop. | |
730 | */ | |
731 | for(i = 0; i < 1000; ++i) { | |
73fd456b | 732 | status = readb(port_mmio + PDC_ALTSTATUS); |
95006188 MP |
733 | if (status == 0xFF) |
734 | break; | |
735 | if (status & ATA_BUSY) | |
736 | ; | |
737 | else if (status & (ATA_DRQ | ATA_ERR)) | |
738 | break; | |
739 | mdelay(1); | |
740 | } | |
741 | if (i >= 1000) | |
73fd456b MP |
742 | ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__); |
743 | return status; | |
744 | } | |
745 | ||
746 | static unsigned int pdc_wait_on_busy(struct ata_port *ap) | |
747 | { | |
748 | unsigned int status = ata_busy_wait(ap, ATA_BUSY, 1000); | |
749 | if (status != 0xff && (status & ATA_BUSY)) | |
750 | ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__); | |
95006188 MP |
751 | return status; |
752 | } | |
753 | ||
754 | static void pdc_issue_atapi_pkt_cmd(struct ata_queued_cmd *qc) | |
755 | { | |
756 | struct ata_port *ap = qc->ap; | |
757 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
758 | void __iomem *host_mmio = ap->host->mmio_base; | |
759 | unsigned int nbytes; | |
760 | unsigned int tmp; | |
761 | ||
762 | writeb(0x00, port_mmio + PDC_CTLSTAT); /* route drive INT to SEQ 0 */ | |
763 | writeb(PDC_SEQCNTRL_INT_MASK, host_mmio + 0); /* but mask SEQ 0 INT */ | |
764 | ||
765 | /* select drive */ | |
766 | if (sata_scr_valid(ap)) { | |
767 | tmp = PDC_DEVICE_SATA; | |
768 | } else { | |
769 | tmp = ATA_DEVICE_OBS; | |
770 | if (qc->dev->devno != 0) | |
771 | tmp |= ATA_DEV1; | |
772 | } | |
773 | writeb(tmp, port_mmio + PDC_DEVICE); | |
73fd456b | 774 | pdc_wait_on_busy(ap); |
95006188 MP |
775 | |
776 | writeb(0x00, port_mmio + PDC_SECTOR_COUNT); | |
777 | writeb(0x00, port_mmio + PDC_SECTOR_NUMBER); | |
778 | ||
779 | /* set feature and byte counter registers */ | |
780 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { | |
781 | tmp = PDC_FEATURE_ATAPI_PIO; | |
782 | /* set byte counter register to real transfer byte count */ | |
783 | nbytes = qc->nbytes; | |
784 | if (!nbytes) | |
785 | nbytes = qc->nsect << 9; | |
786 | if (nbytes > 0xffff) | |
787 | nbytes = 0xffff; | |
788 | } else { | |
789 | tmp = PDC_FEATURE_ATAPI_DMA; | |
790 | /* set byte counter register to 0 */ | |
791 | nbytes = 0; | |
792 | } | |
793 | writeb(tmp, port_mmio + PDC_FEATURE); | |
794 | writeb(nbytes & 0xFF, port_mmio + PDC_CYLINDER_LOW); | |
795 | writeb((nbytes >> 8) & 0xFF, port_mmio + PDC_CYLINDER_HIGH); | |
796 | ||
797 | /* send ATAPI packet command 0xA0 */ | |
798 | writeb(ATA_CMD_PACKET, port_mmio + PDC_COMMAND); | |
799 | ||
73fd456b MP |
800 | /* pdc_qc_issue_prot() currently sends ATAPI PIO packets back |
801 | * to libata. If we start handling those packets ourselves, | |
802 | * then we must busy-wait for INT (CTLSTAT bit 27) at this point | |
803 | * if the device has ATA_DFLAG_CDB_INTR set. | |
95006188 MP |
804 | */ |
805 | ||
806 | pdc_wait_for_drq(ap); | |
807 | ||
808 | /* now the device only waits for the CDB */ | |
809 | } | |
810 | ||
9a3d9eb0 | 811 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
812 | { |
813 | switch (qc->tf.protocol) { | |
95006188 MP |
814 | case ATA_PROT_ATAPI_DMA: |
815 | pdc_issue_atapi_pkt_cmd(qc); | |
816 | /*FALLTHROUGH*/ | |
1da177e4 LT |
817 | case ATA_PROT_DMA: |
818 | case ATA_PROT_NODATA: | |
819 | pdc_packet_start(qc); | |
820 | return 0; | |
821 | ||
1da177e4 LT |
822 | default: |
823 | break; | |
824 | } | |
825 | ||
826 | return ata_qc_issue_prot(qc); | |
827 | } | |
828 | ||
057ace5e | 829 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
830 | { |
831 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
832 | tf->protocol == ATA_PROT_NODATA); | |
833 | ata_tf_load(ap, tf); | |
834 | } | |
835 | ||
836 | ||
057ace5e | 837 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
838 | { |
839 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
840 | tf->protocol == ATA_PROT_NODATA); | |
841 | ata_exec_command(ap, tf); | |
842 | } | |
843 | ||
95006188 MP |
844 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
845 | { | |
846 | u8 *scsicmd = qc->scsicmd->cmnd; | |
847 | int pio = 1; /* atapi dma off by default */ | |
848 | ||
849 | /* Whitelist commands that may use DMA. */ | |
850 | switch (scsicmd[0]) { | |
851 | case WRITE_12: | |
852 | case WRITE_10: | |
853 | case WRITE_6: | |
854 | case READ_12: | |
855 | case READ_10: | |
856 | case READ_6: | |
857 | case 0xad: /* READ_DVD_STRUCTURE */ | |
858 | case 0xbe: /* READ_CD */ | |
859 | pio = 0; | |
860 | } | |
861 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
862 | if (scsicmd[0] == WRITE_10) { | |
863 | unsigned int lba; | |
864 | lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; | |
865 | if (lba >= 0xFFFF4FA2) | |
866 | pio = 1; | |
867 | } | |
868 | return pio; | |
869 | } | |
870 | ||
871 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc) | |
872 | { | |
873 | struct ata_port *ap = qc->ap; | |
874 | ||
875 | /* First generation chips cannot use ATAPI DMA on SATA ports */ | |
876 | if (sata_scr_valid(ap)) | |
877 | return 1; | |
878 | return pdc_check_atapi_dma(qc); | |
879 | } | |
1da177e4 LT |
880 | |
881 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
882 | { | |
883 | port->cmd_addr = base; | |
884 | port->data_addr = base; | |
885 | port->feature_addr = | |
886 | port->error_addr = base + 0x4; | |
887 | port->nsect_addr = base + 0x8; | |
888 | port->lbal_addr = base + 0xc; | |
889 | port->lbam_addr = base + 0x10; | |
890 | port->lbah_addr = base + 0x14; | |
891 | port->device_addr = base + 0x18; | |
892 | port->command_addr = | |
893 | port->status_addr = base + 0x1c; | |
894 | port->altstatus_addr = | |
895 | port->ctl_addr = base + 0x38; | |
896 | } | |
897 | ||
898 | ||
899 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
900 | { | |
ea6ba10b | 901 | void __iomem *mmio = pe->mmio_base; |
6340f019 | 902 | struct pdc_host_priv *hp = pe->private_data; |
d324d462 | 903 | int hotplug_offset; |
1da177e4 LT |
904 | u32 tmp; |
905 | ||
d324d462 MP |
906 | if (hp->flags & PDC_FLAG_GEN_II) |
907 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
908 | else | |
909 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
910 | ||
1da177e4 LT |
911 | /* |
912 | * Except for the hotplug stuff, this is voodoo from the | |
913 | * Promise driver. Label this entire section | |
914 | * "TODO: figure out why we do this" | |
915 | */ | |
916 | ||
b2d1eee1 | 917 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 918 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 MP |
919 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
920 | if (!(hp->flags & PDC_FLAG_GEN_II)) | |
921 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ | |
1da177e4 LT |
922 | writel(tmp, mmio + PDC_FLASH_CTL); |
923 | ||
924 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
925 | tmp = readl(mmio + hotplug_offset); |
926 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
927 | |
928 | /* mask plug/unplug ints */ | |
6340f019 LK |
929 | tmp = readl(mmio + hotplug_offset); |
930 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 | 931 | |
b2d1eee1 MP |
932 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
933 | if (hp->flags & PDC_FLAG_GEN_II) | |
934 | return; | |
935 | ||
1da177e4 LT |
936 | /* reduce TBG clock to 133 Mhz. */ |
937 | tmp = readl(mmio + PDC_TBG_MODE); | |
938 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
939 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
940 | writel(tmp, mmio + PDC_TBG_MODE); | |
941 | ||
942 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
943 | msleep(10); | |
944 | ||
945 | /* adjust slew rate control register. */ | |
946 | tmp = readl(mmio + PDC_SLEW_CTL); | |
947 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
948 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
949 | writel(tmp, mmio + PDC_SLEW_CTL); | |
950 | } | |
951 | ||
952 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
953 | { | |
954 | static int printed_version; | |
955 | struct ata_probe_ent *probe_ent = NULL; | |
6340f019 | 956 | struct pdc_host_priv *hp; |
1da177e4 | 957 | unsigned long base; |
ea6ba10b | 958 | void __iomem *mmio_base; |
1da177e4 LT |
959 | unsigned int board_idx = (unsigned int) ent->driver_data; |
960 | int pci_dev_busy = 0; | |
961 | int rc; | |
870ae337 | 962 | u8 tmp; |
1da177e4 LT |
963 | |
964 | if (!printed_version++) | |
a9524a76 | 965 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 966 | |
1da177e4 LT |
967 | rc = pci_enable_device(pdev); |
968 | if (rc) | |
969 | return rc; | |
970 | ||
971 | rc = pci_request_regions(pdev, DRV_NAME); | |
972 | if (rc) { | |
973 | pci_dev_busy = 1; | |
974 | goto err_out; | |
975 | } | |
976 | ||
977 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
978 | if (rc) | |
979 | goto err_out_regions; | |
980 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
981 | if (rc) | |
982 | goto err_out_regions; | |
983 | ||
6340f019 | 984 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
985 | if (probe_ent == NULL) { |
986 | rc = -ENOMEM; | |
987 | goto err_out_regions; | |
988 | } | |
989 | ||
1da177e4 LT |
990 | probe_ent->dev = pci_dev_to_dev(pdev); |
991 | INIT_LIST_HEAD(&probe_ent->node); | |
992 | ||
374b1873 | 993 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
994 | if (mmio_base == NULL) { |
995 | rc = -ENOMEM; | |
996 | goto err_out_free_ent; | |
997 | } | |
998 | base = (unsigned long) mmio_base; | |
999 | ||
6340f019 LK |
1000 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); |
1001 | if (hp == NULL) { | |
1002 | rc = -ENOMEM; | |
1003 | goto err_out_free_ent; | |
1004 | } | |
1005 | ||
6340f019 LK |
1006 | probe_ent->private_data = hp; |
1007 | ||
1da177e4 | 1008 | probe_ent->sht = pdc_port_info[board_idx].sht; |
cca3974e | 1009 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1da177e4 LT |
1010 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
1011 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
1012 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
1013 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
1014 | ||
1015 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1016 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
1017 | probe_ent->mmio_base = mmio_base; |
1018 | ||
1019 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
1020 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
1021 | ||
1022 | probe_ent->port[0].scr_addr = base + 0x400; | |
1023 | probe_ent->port[1].scr_addr = base + 0x500; | |
1024 | ||
1025 | /* notice 4-port boards */ | |
1026 | switch (board_idx) { | |
6340f019 | 1027 | case board_40518: |
b2d1eee1 | 1028 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 1029 | /* Fall through */ |
1da177e4 LT |
1030 | case board_20319: |
1031 | probe_ent->n_ports = 4; | |
1032 | ||
1033 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1034 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
1035 | ||
1036 | probe_ent->port[2].scr_addr = base + 0x600; | |
1037 | probe_ent->port[3].scr_addr = base + 0x700; | |
1038 | break; | |
6340f019 | 1039 | case board_2057x: |
b2d1eee1 | 1040 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 1041 | /* Fall through */ |
1da177e4 | 1042 | case board_2037x: |
870ae337 MP |
1043 | /* TX2plus boards also have a PATA port */ |
1044 | tmp = readb(mmio_base + PDC_FLASH_CTL+1); | |
1045 | if (!(tmp & 0x80)) { | |
1046 | probe_ent->n_ports = 3; | |
1047 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1048 | hp->port_flags[2] = ATA_FLAG_SLAVE_POSS; | |
1049 | printk(KERN_INFO DRV_NAME " PATA port found\n"); | |
1050 | } else | |
1051 | probe_ent->n_ports = 2; | |
1052 | hp->port_flags[0] = ATA_FLAG_SATA; | |
1053 | hp->port_flags[1] = ATA_FLAG_SATA; | |
1da177e4 | 1054 | break; |
f497ba73 TL |
1055 | case board_20619: |
1056 | probe_ent->n_ports = 4; | |
1057 | ||
1058 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1059 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
1060 | ||
1061 | probe_ent->port[2].scr_addr = base + 0x600; | |
1062 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 1063 | break; |
1da177e4 LT |
1064 | default: |
1065 | BUG(); | |
1066 | break; | |
1067 | } | |
1068 | ||
1069 | pci_set_master(pdev); | |
1070 | ||
1071 | /* initialize adapter */ | |
1072 | pdc_host_init(board_idx, probe_ent); | |
1073 | ||
6340f019 LK |
1074 | /* FIXME: Need any other frees than hp? */ |
1075 | if (!ata_device_add(probe_ent)) | |
1076 | kfree(hp); | |
1077 | ||
1da177e4 LT |
1078 | kfree(probe_ent); |
1079 | ||
1080 | return 0; | |
1081 | ||
1082 | err_out_free_ent: | |
1083 | kfree(probe_ent); | |
1084 | err_out_regions: | |
1085 | pci_release_regions(pdev); | |
1086 | err_out: | |
1087 | if (!pci_dev_busy) | |
1088 | pci_disable_device(pdev); | |
1089 | return rc; | |
1090 | } | |
1091 | ||
1092 | ||
1093 | static int __init pdc_ata_init(void) | |
1094 | { | |
b7887196 | 1095 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1096 | } |
1097 | ||
1098 | ||
1099 | static void __exit pdc_ata_exit(void) | |
1100 | { | |
1101 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1102 | } | |
1103 | ||
1104 | ||
1105 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 1106 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1107 | MODULE_LICENSE("GPL"); |
1108 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1109 | MODULE_VERSION(DRV_VERSION); | |
1110 | ||
1111 | module_init(pdc_ata_init); | |
1112 | module_exit(pdc_ata_exit); |