Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
44 | #include <linux/libata.h> |
45 | #include <asm/io.h> | |
46 | #include "sata_promise.h" | |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
46b027cc | 49 | #define DRV_VERSION "1.05" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
54 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 55 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
56 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
57 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
58 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 59 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
60 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
61 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 LT |
62 | |
63 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
64 | (1<<8) | (1<<9) | (1<<10), | |
65 | ||
66 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
67 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 68 | board_20619 = 2, /* FastTrak TX4000 */ |
5a46fe89 | 69 | board_20771 = 3, /* FastTrak TX2300 */ |
6340f019 LK |
70 | board_2057x = 4, /* SATAII150 Tx2plus */ |
71 | board_40518 = 5, /* SATAII150 Tx4 */ | |
1da177e4 | 72 | |
6340f019 | 73 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 LT |
74 | |
75 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
50630195 JG |
76 | |
77 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | | |
3d0a59c0 JG |
78 | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | |
79 | ATA_FLAG_PIO_POLLING, | |
b2d1eee1 MP |
80 | |
81 | /* hp->flags bits */ | |
82 | PDC_FLAG_GEN_II = (1 << 0), | |
1da177e4 LT |
83 | }; |
84 | ||
85 | ||
86 | struct pdc_port_priv { | |
87 | u8 *pkt; | |
88 | dma_addr_t pkt_dma; | |
89 | }; | |
90 | ||
6340f019 | 91 | struct pdc_host_priv { |
b2d1eee1 | 92 | unsigned long flags; |
6340f019 LK |
93 | int hotplug_offset; |
94 | }; | |
95 | ||
1da177e4 LT |
96 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
97 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
98 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
7d12e780 | 99 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance); |
1da177e4 LT |
100 | static void pdc_eng_timeout(struct ata_port *ap); |
101 | static int pdc_port_start(struct ata_port *ap); | |
102 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a JG |
103 | static void pdc_pata_phy_reset(struct ata_port *ap); |
104 | static void pdc_sata_phy_reset(struct ata_port *ap); | |
1da177e4 | 105 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
106 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
107 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
1da177e4 | 108 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 109 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
cca3974e | 110 | static void pdc_host_stop(struct ata_host *host); |
1da177e4 | 111 | |
374b1873 | 112 | |
193515d5 | 113 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
114 | .module = THIS_MODULE, |
115 | .name = DRV_NAME, | |
116 | .ioctl = ata_scsi_ioctl, | |
117 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
118 | .can_queue = ATA_DEF_QUEUE, |
119 | .this_id = ATA_SHT_THIS_ID, | |
120 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
121 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
122 | .emulated = ATA_SHT_EMULATED, | |
123 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
124 | .proc_name = DRV_NAME, | |
125 | .dma_boundary = ATA_DMA_BOUNDARY, | |
126 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 127 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 128 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
129 | }; |
130 | ||
057ace5e | 131 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
132 | .port_disable = ata_port_disable, |
133 | .tf_load = pdc_tf_load_mmio, | |
134 | .tf_read = ata_tf_read, | |
135 | .check_status = ata_check_status, | |
136 | .exec_command = pdc_exec_command_mmio, | |
137 | .dev_select = ata_std_dev_select, | |
2cba582a JG |
138 | |
139 | .phy_reset = pdc_sata_phy_reset, | |
140 | ||
1da177e4 LT |
141 | .qc_prep = pdc_qc_prep, |
142 | .qc_issue = pdc_qc_issue_prot, | |
143 | .eng_timeout = pdc_eng_timeout, | |
a6b2c5d4 | 144 | .data_xfer = ata_mmio_data_xfer, |
1da177e4 LT |
145 | .irq_handler = pdc_interrupt, |
146 | .irq_clear = pdc_irq_clear, | |
2cba582a | 147 | |
1da177e4 LT |
148 | .scr_read = pdc_sata_scr_read, |
149 | .scr_write = pdc_sata_scr_write, | |
150 | .port_start = pdc_port_start, | |
151 | .port_stop = pdc_port_stop, | |
6340f019 | 152 | .host_stop = pdc_host_stop, |
1da177e4 LT |
153 | }; |
154 | ||
057ace5e | 155 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
156 | .port_disable = ata_port_disable, |
157 | .tf_load = pdc_tf_load_mmio, | |
158 | .tf_read = ata_tf_read, | |
159 | .check_status = ata_check_status, | |
160 | .exec_command = pdc_exec_command_mmio, | |
161 | .dev_select = ata_std_dev_select, | |
162 | ||
163 | .phy_reset = pdc_pata_phy_reset, | |
164 | ||
165 | .qc_prep = pdc_qc_prep, | |
166 | .qc_issue = pdc_qc_issue_prot, | |
a6b2c5d4 | 167 | .data_xfer = ata_mmio_data_xfer, |
2cba582a JG |
168 | .eng_timeout = pdc_eng_timeout, |
169 | .irq_handler = pdc_interrupt, | |
170 | .irq_clear = pdc_irq_clear, | |
171 | ||
172 | .port_start = pdc_port_start, | |
173 | .port_stop = pdc_port_stop, | |
6340f019 | 174 | .host_stop = pdc_host_stop, |
2cba582a JG |
175 | }; |
176 | ||
98ac62de | 177 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
178 | /* board_2037x */ |
179 | { | |
180 | .sht = &pdc_ata_sht, | |
cca3974e | 181 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
182 | .pio_mask = 0x1f, /* pio0-4 */ |
183 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
184 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 185 | .port_ops = &pdc_sata_ops, |
1da177e4 LT |
186 | }, |
187 | ||
188 | /* board_20319 */ | |
189 | { | |
190 | .sht = &pdc_ata_sht, | |
cca3974e | 191 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
192 | .pio_mask = 0x1f, /* pio0-4 */ |
193 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
194 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 195 | .port_ops = &pdc_sata_ops, |
1da177e4 | 196 | }, |
f497ba73 TL |
197 | |
198 | /* board_20619 */ | |
199 | { | |
200 | .sht = &pdc_ata_sht, | |
cca3974e | 201 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
202 | .pio_mask = 0x1f, /* pio0-4 */ |
203 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
204 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 205 | .port_ops = &pdc_pata_ops, |
f497ba73 | 206 | }, |
5a46fe89 YI |
207 | |
208 | /* board_20771 */ | |
209 | { | |
210 | .sht = &pdc_ata_sht, | |
cca3974e | 211 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
5a46fe89 YI |
212 | .pio_mask = 0x1f, /* pio0-4 */ |
213 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
214 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
215 | .port_ops = &pdc_sata_ops, | |
216 | }, | |
6340f019 LK |
217 | |
218 | /* board_2057x */ | |
219 | { | |
220 | .sht = &pdc_ata_sht, | |
cca3974e | 221 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
222 | .pio_mask = 0x1f, /* pio0-4 */ |
223 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
224 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
225 | .port_ops = &pdc_sata_ops, | |
226 | }, | |
227 | ||
228 | /* board_40518 */ | |
229 | { | |
230 | .sht = &pdc_ata_sht, | |
cca3974e | 231 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
232 | .pio_mask = 0x1f, /* pio0-4 */ |
233 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
234 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
235 | .port_ops = &pdc_sata_ops, | |
236 | }, | |
1da177e4 LT |
237 | }; |
238 | ||
3b7d697d | 239 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 240 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
241 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
242 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
243 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
244 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
245 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 246 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
b2d1eee1 | 247 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 248 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
249 | |
250 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
251 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
252 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
253 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
b2d1eee1 | 254 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
255 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
256 | ||
257 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 258 | |
8419dc8a JG |
259 | /* TODO: remove all associated board_20771 code, as it completely |
260 | * duplicates board_2037x code, unless reason for separation can be | |
261 | * divined. | |
262 | */ | |
263 | #if 0 | |
54bb3a94 | 264 | { PCI_VDEVICE(PROMISE, 0x3570), board_20771 }, |
8419dc8a | 265 | #endif |
a83068bb | 266 | { PCI_VDEVICE(PROMISE, 0x3577), board_20771 }, |
8419dc8a | 267 | |
1da177e4 LT |
268 | { } /* terminate list */ |
269 | }; | |
270 | ||
271 | ||
272 | static struct pci_driver pdc_ata_pci_driver = { | |
273 | .name = DRV_NAME, | |
274 | .id_table = pdc_ata_pci_tbl, | |
275 | .probe = pdc_ata_init_one, | |
276 | .remove = ata_pci_remove_one, | |
277 | }; | |
278 | ||
279 | ||
280 | static int pdc_port_start(struct ata_port *ap) | |
281 | { | |
cca3974e | 282 | struct device *dev = ap->host->dev; |
1da177e4 LT |
283 | struct pdc_port_priv *pp; |
284 | int rc; | |
285 | ||
286 | rc = ata_port_start(ap); | |
287 | if (rc) | |
288 | return rc; | |
289 | ||
6340f019 | 290 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
291 | if (!pp) { |
292 | rc = -ENOMEM; | |
293 | goto err_out; | |
294 | } | |
1da177e4 LT |
295 | |
296 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
297 | if (!pp->pkt) { | |
298 | rc = -ENOMEM; | |
299 | goto err_out_kfree; | |
300 | } | |
301 | ||
302 | ap->private_data = pp; | |
303 | ||
304 | return 0; | |
305 | ||
306 | err_out_kfree: | |
307 | kfree(pp); | |
308 | err_out: | |
309 | ata_port_stop(ap); | |
310 | return rc; | |
311 | } | |
312 | ||
313 | ||
314 | static void pdc_port_stop(struct ata_port *ap) | |
315 | { | |
cca3974e | 316 | struct device *dev = ap->host->dev; |
1da177e4 LT |
317 | struct pdc_port_priv *pp = ap->private_data; |
318 | ||
319 | ap->private_data = NULL; | |
320 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
321 | kfree(pp); | |
322 | ata_port_stop(ap); | |
323 | } | |
324 | ||
325 | ||
cca3974e | 326 | static void pdc_host_stop(struct ata_host *host) |
6340f019 | 327 | { |
cca3974e | 328 | struct pdc_host_priv *hp = host->private_data; |
6340f019 | 329 | |
cca3974e | 330 | ata_pci_host_stop(host); |
6340f019 LK |
331 | |
332 | kfree(hp); | |
333 | } | |
334 | ||
335 | ||
1da177e4 LT |
336 | static void pdc_reset_port(struct ata_port *ap) |
337 | { | |
ea6ba10b | 338 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
339 | unsigned int i; |
340 | u32 tmp; | |
341 | ||
342 | for (i = 11; i > 0; i--) { | |
343 | tmp = readl(mmio); | |
344 | if (tmp & PDC_RESET) | |
345 | break; | |
346 | ||
347 | udelay(100); | |
348 | ||
349 | tmp |= PDC_RESET; | |
350 | writel(tmp, mmio); | |
351 | } | |
352 | ||
353 | tmp &= ~PDC_RESET; | |
354 | writel(tmp, mmio); | |
355 | readl(mmio); /* flush */ | |
356 | } | |
357 | ||
2cba582a | 358 | static void pdc_sata_phy_reset(struct ata_port *ap) |
1da177e4 LT |
359 | { |
360 | pdc_reset_port(ap); | |
361 | sata_phy_reset(ap); | |
362 | } | |
363 | ||
d3fb4e8d | 364 | static void pdc_pata_cbl_detect(struct ata_port *ap) |
2cba582a | 365 | { |
d3fb4e8d | 366 | u8 tmp; |
03dc5506 | 367 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d JG |
368 | |
369 | tmp = readb(mmio); | |
370 | ||
371 | if (tmp & 0x01) { | |
372 | ap->cbl = ATA_CBL_PATA40; | |
373 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
374 | } else | |
375 | ap->cbl = ATA_CBL_PATA80; | |
376 | } | |
2cba582a | 377 | |
d3fb4e8d JG |
378 | static void pdc_pata_phy_reset(struct ata_port *ap) |
379 | { | |
380 | pdc_pata_cbl_detect(ap); | |
2cba582a JG |
381 | pdc_reset_port(ap); |
382 | ata_port_probe(ap); | |
383 | ata_bus_reset(ap); | |
384 | } | |
385 | ||
1da177e4 LT |
386 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
387 | { | |
388 | if (sc_reg > SCR_CONTROL) | |
389 | return 0xffffffffU; | |
b181d3b0 | 390 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
391 | } |
392 | ||
393 | ||
394 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
395 | u32 val) | |
396 | { | |
397 | if (sc_reg > SCR_CONTROL) | |
398 | return; | |
b181d3b0 | 399 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
400 | } |
401 | ||
402 | static void pdc_qc_prep(struct ata_queued_cmd *qc) | |
403 | { | |
404 | struct pdc_port_priv *pp = qc->ap->private_data; | |
405 | unsigned int i; | |
406 | ||
407 | VPRINTK("ENTER\n"); | |
408 | ||
409 | switch (qc->tf.protocol) { | |
410 | case ATA_PROT_DMA: | |
411 | ata_qc_prep(qc); | |
412 | /* fall through */ | |
413 | ||
414 | case ATA_PROT_NODATA: | |
415 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
416 | qc->dev->devno, pp->pkt); | |
417 | ||
418 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
419 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
420 | else | |
421 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
422 | ||
423 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
424 | break; | |
425 | ||
426 | default: | |
427 | break; | |
428 | } | |
429 | } | |
430 | ||
431 | static void pdc_eng_timeout(struct ata_port *ap) | |
432 | { | |
cca3974e | 433 | struct ata_host *host = ap->host; |
1da177e4 LT |
434 | u8 drv_stat; |
435 | struct ata_queued_cmd *qc; | |
b8f6153e | 436 | unsigned long flags; |
1da177e4 LT |
437 | |
438 | DPRINTK("ENTER\n"); | |
439 | ||
cca3974e | 440 | spin_lock_irqsave(&host->lock, flags); |
b8f6153e | 441 | |
1da177e4 | 442 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1da177e4 | 443 | |
1da177e4 LT |
444 | switch (qc->tf.protocol) { |
445 | case ATA_PROT_DMA: | |
446 | case ATA_PROT_NODATA: | |
f15a1daf | 447 | ata_port_printk(ap, KERN_ERR, "command timeout\n"); |
a7dac447 | 448 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 449 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
450 | break; |
451 | ||
452 | default: | |
453 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
454 | ||
f15a1daf TH |
455 | ata_port_printk(ap, KERN_ERR, |
456 | "unknown timeout, cmd 0x%x stat 0x%x\n", | |
457 | qc->tf.command, drv_stat); | |
1da177e4 | 458 | |
a22e2eb0 | 459 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
460 | break; |
461 | } | |
462 | ||
cca3974e | 463 | spin_unlock_irqrestore(&host->lock, flags); |
f6379020 | 464 | ata_eh_qc_complete(qc); |
1da177e4 LT |
465 | DPRINTK("EXIT\n"); |
466 | } | |
467 | ||
468 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
469 | struct ata_queued_cmd *qc) | |
470 | { | |
a22e2eb0 | 471 | unsigned int handled = 0; |
1da177e4 | 472 | u32 tmp; |
ea6ba10b | 473 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
474 | |
475 | tmp = readl(mmio); | |
476 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 477 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
478 | pdc_reset_port(ap); |
479 | } | |
480 | ||
481 | switch (qc->tf.protocol) { | |
482 | case ATA_PROT_DMA: | |
483 | case ATA_PROT_NODATA: | |
a22e2eb0 AL |
484 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
485 | ata_qc_complete(qc); | |
1da177e4 LT |
486 | handled = 1; |
487 | break; | |
488 | ||
489 | default: | |
ee500aab AL |
490 | ap->stats.idle_irq++; |
491 | break; | |
1da177e4 LT |
492 | } |
493 | ||
ee500aab | 494 | return handled; |
1da177e4 LT |
495 | } |
496 | ||
497 | static void pdc_irq_clear(struct ata_port *ap) | |
498 | { | |
cca3974e JG |
499 | struct ata_host *host = ap->host; |
500 | void __iomem *mmio = host->mmio_base; | |
1da177e4 LT |
501 | |
502 | readl(mmio + PDC_INT_SEQMASK); | |
503 | } | |
504 | ||
7d12e780 | 505 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 506 | { |
cca3974e | 507 | struct ata_host *host = dev_instance; |
1da177e4 LT |
508 | struct ata_port *ap; |
509 | u32 mask = 0; | |
510 | unsigned int i, tmp; | |
511 | unsigned int handled = 0; | |
ea6ba10b | 512 | void __iomem *mmio_base; |
1da177e4 LT |
513 | |
514 | VPRINTK("ENTER\n"); | |
515 | ||
cca3974e | 516 | if (!host || !host->mmio_base) { |
1da177e4 LT |
517 | VPRINTK("QUICK EXIT\n"); |
518 | return IRQ_NONE; | |
519 | } | |
520 | ||
cca3974e | 521 | mmio_base = host->mmio_base; |
1da177e4 LT |
522 | |
523 | /* reading should also clear interrupts */ | |
524 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
525 | ||
526 | if (mask == 0xffffffff) { | |
527 | VPRINTK("QUICK EXIT 2\n"); | |
528 | return IRQ_NONE; | |
529 | } | |
6340f019 | 530 | |
cca3974e | 531 | spin_lock(&host->lock); |
6340f019 | 532 | |
1da177e4 LT |
533 | mask &= 0xffff; /* only 16 tags possible */ |
534 | if (!mask) { | |
535 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 536 | goto done_irq; |
1da177e4 LT |
537 | } |
538 | ||
1da177e4 LT |
539 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
540 | ||
cca3974e | 541 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 542 | VPRINTK("port %u\n", i); |
cca3974e | 543 | ap = host->ports[i]; |
1da177e4 | 544 | tmp = mask & (1 << (i + 1)); |
c1389503 | 545 | if (tmp && ap && |
029f5468 | 546 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
547 | struct ata_queued_cmd *qc; |
548 | ||
549 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 550 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
551 | handled += pdc_host_intr(ap, qc); |
552 | } | |
553 | } | |
554 | ||
1da177e4 LT |
555 | VPRINTK("EXIT\n"); |
556 | ||
6340f019 | 557 | done_irq: |
cca3974e | 558 | spin_unlock(&host->lock); |
1da177e4 LT |
559 | return IRQ_RETVAL(handled); |
560 | } | |
561 | ||
562 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
563 | { | |
564 | struct ata_port *ap = qc->ap; | |
565 | struct pdc_port_priv *pp = ap->private_data; | |
566 | unsigned int port_no = ap->port_no; | |
567 | u8 seq = (u8) (port_no + 1); | |
568 | ||
569 | VPRINTK("ENTER, ap %p\n", ap); | |
570 | ||
cca3974e JG |
571 | writel(0x00000001, ap->host->mmio_base + (seq * 4)); |
572 | readl(ap->host->mmio_base + (seq * 4)); /* flush */ | |
1da177e4 LT |
573 | |
574 | pp->pkt[2] = seq; | |
575 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
576 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
577 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
578 | } |
579 | ||
9a3d9eb0 | 580 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
581 | { |
582 | switch (qc->tf.protocol) { | |
583 | case ATA_PROT_DMA: | |
584 | case ATA_PROT_NODATA: | |
585 | pdc_packet_start(qc); | |
586 | return 0; | |
587 | ||
588 | case ATA_PROT_ATAPI_DMA: | |
589 | BUG(); | |
590 | break; | |
591 | ||
592 | default: | |
593 | break; | |
594 | } | |
595 | ||
596 | return ata_qc_issue_prot(qc); | |
597 | } | |
598 | ||
057ace5e | 599 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
600 | { |
601 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
602 | tf->protocol == ATA_PROT_NODATA); | |
603 | ata_tf_load(ap, tf); | |
604 | } | |
605 | ||
606 | ||
057ace5e | 607 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
608 | { |
609 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
610 | tf->protocol == ATA_PROT_NODATA); | |
611 | ata_exec_command(ap, tf); | |
612 | } | |
613 | ||
614 | ||
615 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
616 | { | |
617 | port->cmd_addr = base; | |
618 | port->data_addr = base; | |
619 | port->feature_addr = | |
620 | port->error_addr = base + 0x4; | |
621 | port->nsect_addr = base + 0x8; | |
622 | port->lbal_addr = base + 0xc; | |
623 | port->lbam_addr = base + 0x10; | |
624 | port->lbah_addr = base + 0x14; | |
625 | port->device_addr = base + 0x18; | |
626 | port->command_addr = | |
627 | port->status_addr = base + 0x1c; | |
628 | port->altstatus_addr = | |
629 | port->ctl_addr = base + 0x38; | |
630 | } | |
631 | ||
632 | ||
633 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
634 | { | |
ea6ba10b | 635 | void __iomem *mmio = pe->mmio_base; |
6340f019 LK |
636 | struct pdc_host_priv *hp = pe->private_data; |
637 | int hotplug_offset = hp->hotplug_offset; | |
1da177e4 LT |
638 | u32 tmp; |
639 | ||
640 | /* | |
641 | * Except for the hotplug stuff, this is voodoo from the | |
642 | * Promise driver. Label this entire section | |
643 | * "TODO: figure out why we do this" | |
644 | */ | |
645 | ||
b2d1eee1 | 646 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 647 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 MP |
648 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
649 | if (!(hp->flags & PDC_FLAG_GEN_II)) | |
650 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ | |
1da177e4 LT |
651 | writel(tmp, mmio + PDC_FLASH_CTL); |
652 | ||
653 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
654 | tmp = readl(mmio + hotplug_offset); |
655 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
656 | |
657 | /* mask plug/unplug ints */ | |
6340f019 LK |
658 | tmp = readl(mmio + hotplug_offset); |
659 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 | 660 | |
b2d1eee1 MP |
661 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
662 | if (hp->flags & PDC_FLAG_GEN_II) | |
663 | return; | |
664 | ||
1da177e4 LT |
665 | /* reduce TBG clock to 133 Mhz. */ |
666 | tmp = readl(mmio + PDC_TBG_MODE); | |
667 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
668 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
669 | writel(tmp, mmio + PDC_TBG_MODE); | |
670 | ||
671 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
672 | msleep(10); | |
673 | ||
674 | /* adjust slew rate control register. */ | |
675 | tmp = readl(mmio + PDC_SLEW_CTL); | |
676 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
677 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
678 | writel(tmp, mmio + PDC_SLEW_CTL); | |
679 | } | |
680 | ||
681 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
682 | { | |
683 | static int printed_version; | |
684 | struct ata_probe_ent *probe_ent = NULL; | |
6340f019 | 685 | struct pdc_host_priv *hp; |
1da177e4 | 686 | unsigned long base; |
ea6ba10b | 687 | void __iomem *mmio_base; |
1da177e4 LT |
688 | unsigned int board_idx = (unsigned int) ent->driver_data; |
689 | int pci_dev_busy = 0; | |
690 | int rc; | |
691 | ||
692 | if (!printed_version++) | |
a9524a76 | 693 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 694 | |
1da177e4 LT |
695 | rc = pci_enable_device(pdev); |
696 | if (rc) | |
697 | return rc; | |
698 | ||
699 | rc = pci_request_regions(pdev, DRV_NAME); | |
700 | if (rc) { | |
701 | pci_dev_busy = 1; | |
702 | goto err_out; | |
703 | } | |
704 | ||
705 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
706 | if (rc) | |
707 | goto err_out_regions; | |
708 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
709 | if (rc) | |
710 | goto err_out_regions; | |
711 | ||
6340f019 | 712 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
713 | if (probe_ent == NULL) { |
714 | rc = -ENOMEM; | |
715 | goto err_out_regions; | |
716 | } | |
717 | ||
1da177e4 LT |
718 | probe_ent->dev = pci_dev_to_dev(pdev); |
719 | INIT_LIST_HEAD(&probe_ent->node); | |
720 | ||
374b1873 | 721 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
722 | if (mmio_base == NULL) { |
723 | rc = -ENOMEM; | |
724 | goto err_out_free_ent; | |
725 | } | |
726 | base = (unsigned long) mmio_base; | |
727 | ||
6340f019 LK |
728 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); |
729 | if (hp == NULL) { | |
730 | rc = -ENOMEM; | |
731 | goto err_out_free_ent; | |
732 | } | |
733 | ||
734 | /* Set default hotplug offset */ | |
735 | hp->hotplug_offset = PDC_SATA_PLUG_CSR; | |
736 | probe_ent->private_data = hp; | |
737 | ||
1da177e4 | 738 | probe_ent->sht = pdc_port_info[board_idx].sht; |
cca3974e | 739 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1da177e4 LT |
740 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
741 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
742 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
743 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
744 | ||
745 | probe_ent->irq = pdev->irq; | |
1d6f359a | 746 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
747 | probe_ent->mmio_base = mmio_base; |
748 | ||
749 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
750 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
751 | ||
752 | probe_ent->port[0].scr_addr = base + 0x400; | |
753 | probe_ent->port[1].scr_addr = base + 0x500; | |
754 | ||
755 | /* notice 4-port boards */ | |
756 | switch (board_idx) { | |
6340f019 | 757 | case board_40518: |
b2d1eee1 | 758 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 LK |
759 | /* Override hotplug offset for SATAII150 */ |
760 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
761 | /* Fall through */ | |
1da177e4 LT |
762 | case board_20319: |
763 | probe_ent->n_ports = 4; | |
764 | ||
765 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
766 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
767 | ||
768 | probe_ent->port[2].scr_addr = base + 0x600; | |
769 | probe_ent->port[3].scr_addr = base + 0x700; | |
770 | break; | |
6340f019 | 771 | case board_2057x: |
b2d1eee1 MP |
772 | case board_20771: |
773 | hp->flags |= PDC_FLAG_GEN_II; | |
6340f019 LK |
774 | /* Override hotplug offset for SATAII150 */ |
775 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
776 | /* Fall through */ | |
1da177e4 | 777 | case board_2037x: |
6c9e5eb5 | 778 | probe_ent->n_ports = 2; |
1da177e4 | 779 | break; |
f497ba73 TL |
780 | case board_20619: |
781 | probe_ent->n_ports = 4; | |
782 | ||
783 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
784 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
785 | ||
786 | probe_ent->port[2].scr_addr = base + 0x600; | |
787 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 788 | break; |
1da177e4 LT |
789 | default: |
790 | BUG(); | |
791 | break; | |
792 | } | |
793 | ||
794 | pci_set_master(pdev); | |
795 | ||
796 | /* initialize adapter */ | |
797 | pdc_host_init(board_idx, probe_ent); | |
798 | ||
6340f019 LK |
799 | /* FIXME: Need any other frees than hp? */ |
800 | if (!ata_device_add(probe_ent)) | |
801 | kfree(hp); | |
802 | ||
1da177e4 LT |
803 | kfree(probe_ent); |
804 | ||
805 | return 0; | |
806 | ||
807 | err_out_free_ent: | |
808 | kfree(probe_ent); | |
809 | err_out_regions: | |
810 | pci_release_regions(pdev); | |
811 | err_out: | |
812 | if (!pci_dev_busy) | |
813 | pci_disable_device(pdev); | |
814 | return rc; | |
815 | } | |
816 | ||
817 | ||
818 | static int __init pdc_ata_init(void) | |
819 | { | |
b7887196 | 820 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
821 | } |
822 | ||
823 | ||
824 | static void __exit pdc_ata_exit(void) | |
825 | { | |
826 | pci_unregister_driver(&pdc_ata_pci_driver); | |
827 | } | |
828 | ||
829 | ||
830 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 831 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
832 | MODULE_LICENSE("GPL"); |
833 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
834 | MODULE_VERSION(DRV_VERSION); | |
835 | ||
836 | module_init(pdc_ata_init); | |
837 | module_exit(pdc_ata_exit); |