Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5595ddf9 | 5 | * Mikael Pettersson <mikpe@it.uu.se> |
1da177e4 LT |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003-2004 Red Hat, Inc. | |
10 | * | |
1da177e4 | 11 | * |
af36d7f0 JG |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware information only available under NDA. | |
1da177e4 LT |
31 | * |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
5a0e3ad6 | 36 | #include <linux/gfp.h> |
1da177e4 LT |
37 | #include <linux/pci.h> |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
a9524a76 | 42 | #include <linux/device.h> |
95006188 | 43 | #include <scsi/scsi.h> |
1da177e4 | 44 | #include <scsi/scsi_host.h> |
193515d5 | 45 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 46 | #include <linux/libata.h> |
1da177e4 LT |
47 | #include "sata_promise.h" |
48 | ||
49 | #define DRV_NAME "sata_promise" | |
c07a9c49 | 50 | #define DRV_VERSION "2.12" |
1da177e4 LT |
51 | |
52 | enum { | |
eca25dca | 53 | PDC_MAX_PORTS = 4, |
0d5ff566 | 54 | PDC_MMIO_BAR = 3, |
b9ccd4a9 | 55 | PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ |
0d5ff566 | 56 | |
821d22cd MP |
57 | /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ |
58 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
59 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
ff7cddf5 | 60 | PDC_PCI_CTL = 0x48, /* PCI control/status reg */ |
821d22cd MP |
61 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ |
62 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ | |
63 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ | |
64 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
65 | ||
66 | /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */ | |
95006188 MP |
67 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ |
68 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
69 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
70 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
71 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
72 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
73 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 74 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 | 75 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
1da177e4 LT |
76 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
77 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
821d22cd MP |
78 | |
79 | /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ | |
ff7cddf5 | 80 | PDC_SATA_ERROR = 0x04, |
821d22cd | 81 | PDC_PHYMODE4 = 0x14, |
ff7cddf5 MP |
82 | PDC_LINK_LAYER_ERRORS = 0x6C, |
83 | PDC_FPDMA_CTLSTAT = 0xD8, | |
84 | PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */ | |
85 | PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */ | |
86 | ||
87 | /* PDC_FPDMA_CTLSTAT bit definitions */ | |
88 | PDC_FPDMA_CTLSTAT_RESET = 1 << 3, | |
89 | PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10, | |
90 | PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11, | |
1da177e4 | 91 | |
176efb05 MP |
92 | /* PDC_GLOBAL_CTL bit definitions */ |
93 | PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ | |
94 | PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ | |
95 | PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ | |
96 | PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ | |
97 | PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ | |
98 | PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ | |
99 | PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ | |
100 | PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ | |
101 | PDC_DRIVE_ERR = (1 << 21), /* drive error */ | |
102 | PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ | |
103 | PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ | |
104 | PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, | |
5796d1c4 JG |
105 | PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | |
106 | PDC2_ATA_DMA_CNT_ERR, | |
107 | PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | | |
108 | PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | | |
109 | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | | |
110 | PDC1_ERR_MASK | PDC2_ERR_MASK, | |
1da177e4 LT |
111 | |
112 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
eca25dca TH |
113 | board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ |
114 | board_20319 = 2, /* FastTrak S150 TX4 */ | |
115 | board_20619 = 3, /* FastTrak TX4000 */ | |
116 | board_2057x = 4, /* SATAII150 Tx2plus */ | |
d0e58031 | 117 | board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ |
eca25dca | 118 | board_40518 = 6, /* SATAII150 Tx4 */ |
1da177e4 | 119 | |
6340f019 | 120 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 121 | |
95006188 MP |
122 | /* Sequence counter control registers bit definitions */ |
123 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
124 | ||
125 | /* Feature register values */ | |
126 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
127 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
128 | ||
129 | /* Device/Head register values */ | |
130 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
131 | ||
25b93d81 MP |
132 | /* PDC_CTLSTAT bit definitions */ |
133 | PDC_DMA_ENABLE = (1 << 7), | |
134 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 135 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 136 | |
25b93d81 | 137 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 138 | ATA_FLAG_MMIO | |
3d0a59c0 | 139 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 | 140 | |
eca25dca TH |
141 | /* ap->flags bits */ |
142 | PDC_FLAG_GEN_II = (1 << 24), | |
143 | PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ | |
144 | PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ | |
1da177e4 LT |
145 | }; |
146 | ||
1da177e4 LT |
147 | struct pdc_port_priv { |
148 | u8 *pkt; | |
149 | dma_addr_t pkt_dma; | |
150 | }; | |
151 | ||
82ef04fb TH |
152 | static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
153 | static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
7715a6f9 | 154 | static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
eca25dca TH |
155 | static int pdc_common_port_start(struct ata_port *ap); |
156 | static int pdc_sata_port_start(struct ata_port *ap); | |
1da177e4 | 157 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
158 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
159 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 | 160 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
724114a5 | 161 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); |
1da177e4 | 162 | static void pdc_irq_clear(struct ata_port *ap); |
9363c382 | 163 | static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc); |
25b93d81 | 164 | static void pdc_freeze(struct ata_port *ap); |
c07a9c49 | 165 | static void pdc_sata_freeze(struct ata_port *ap); |
25b93d81 | 166 | static void pdc_thaw(struct ata_port *ap); |
c07a9c49 | 167 | static void pdc_sata_thaw(struct ata_port *ap); |
cadef677 MP |
168 | static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, |
169 | unsigned long deadline); | |
170 | static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, | |
171 | unsigned long deadline); | |
a1efdaba | 172 | static void pdc_error_handler(struct ata_port *ap); |
25b93d81 | 173 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); |
724114a5 MP |
174 | static int pdc_pata_cable_detect(struct ata_port *ap); |
175 | static int pdc_sata_cable_detect(struct ata_port *ap); | |
374b1873 | 176 | |
193515d5 | 177 | static struct scsi_host_template pdc_ata_sht = { |
68d1d07b | 178 | ATA_BASE_SHT(DRV_NAME), |
b9ccd4a9 | 179 | .sg_tablesize = PDC_MAX_PRD, |
1da177e4 | 180 | .dma_boundary = ATA_DMA_BOUNDARY, |
1da177e4 LT |
181 | }; |
182 | ||
029cfd6b TH |
183 | static const struct ata_port_operations pdc_common_ops = { |
184 | .inherits = &ata_sff_port_ops, | |
185 | ||
5682ed33 TH |
186 | .sff_tf_load = pdc_tf_load_mmio, |
187 | .sff_exec_command = pdc_exec_command_mmio, | |
95006188 | 188 | .check_atapi_dma = pdc_check_atapi_dma, |
95006188 | 189 | .qc_prep = pdc_qc_prep, |
9363c382 | 190 | .qc_issue = pdc_qc_issue, |
c96f1732 | 191 | |
5682ed33 | 192 | .sff_irq_clear = pdc_irq_clear, |
c96f1732 | 193 | .lost_interrupt = ATA_OP_NULL, |
95006188 | 194 | |
029cfd6b | 195 | .post_internal_cmd = pdc_post_internal_cmd, |
a1efdaba | 196 | .error_handler = pdc_error_handler, |
95006188 MP |
197 | }; |
198 | ||
029cfd6b TH |
199 | static struct ata_port_operations pdc_sata_ops = { |
200 | .inherits = &pdc_common_ops, | |
201 | .cable_detect = pdc_sata_cable_detect, | |
c07a9c49 MP |
202 | .freeze = pdc_sata_freeze, |
203 | .thaw = pdc_sata_thaw, | |
1da177e4 LT |
204 | .scr_read = pdc_sata_scr_read, |
205 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 206 | .port_start = pdc_sata_port_start, |
cadef677 | 207 | .hardreset = pdc_sata_hardreset, |
1da177e4 LT |
208 | }; |
209 | ||
0ae6654d MP |
210 | /* First-generation chips need a more restrictive ->check_atapi_dma op, |
211 | and ->freeze/thaw that ignore the hotplug controls. */ | |
029cfd6b TH |
212 | static struct ata_port_operations pdc_old_sata_ops = { |
213 | .inherits = &pdc_sata_ops, | |
0ae6654d MP |
214 | .freeze = pdc_freeze, |
215 | .thaw = pdc_thaw, | |
029cfd6b TH |
216 | .check_atapi_dma = pdc_old_sata_check_atapi_dma, |
217 | }; | |
2cba582a | 218 | |
029cfd6b TH |
219 | static struct ata_port_operations pdc_pata_ops = { |
220 | .inherits = &pdc_common_ops, | |
221 | .cable_detect = pdc_pata_cable_detect, | |
5387373b MP |
222 | .freeze = pdc_freeze, |
223 | .thaw = pdc_thaw, | |
eca25dca | 224 | .port_start = pdc_common_port_start, |
cadef677 | 225 | .softreset = pdc_pata_softreset, |
2cba582a JG |
226 | }; |
227 | ||
98ac62de | 228 | static const struct ata_port_info pdc_port_info[] = { |
5595ddf9 | 229 | [board_2037x] = |
1da177e4 | 230 | { |
eca25dca TH |
231 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
232 | PDC_FLAG_SATA_PATA, | |
14bdef98 EIB |
233 | .pio_mask = ATA_PIO4, |
234 | .mwdma_mask = ATA_MWDMA2, | |
469248ab | 235 | .udma_mask = ATA_UDMA6, |
95006188 | 236 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
237 | }, |
238 | ||
5595ddf9 | 239 | [board_2037x_pata] = |
eca25dca TH |
240 | { |
241 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, | |
14bdef98 EIB |
242 | .pio_mask = ATA_PIO4, |
243 | .mwdma_mask = ATA_MWDMA2, | |
469248ab | 244 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
245 | .port_ops = &pdc_pata_ops, |
246 | }, | |
247 | ||
5595ddf9 | 248 | [board_20319] = |
1da177e4 | 249 | { |
eca25dca TH |
250 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
251 | PDC_FLAG_4_PORTS, | |
14bdef98 EIB |
252 | .pio_mask = ATA_PIO4, |
253 | .mwdma_mask = ATA_MWDMA2, | |
469248ab | 254 | .udma_mask = ATA_UDMA6, |
95006188 | 255 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 256 | }, |
f497ba73 | 257 | |
5595ddf9 | 258 | [board_20619] = |
f497ba73 | 259 | { |
eca25dca TH |
260 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
261 | PDC_FLAG_4_PORTS, | |
14bdef98 EIB |
262 | .pio_mask = ATA_PIO4, |
263 | .mwdma_mask = ATA_MWDMA2, | |
469248ab | 264 | .udma_mask = ATA_UDMA6, |
2cba582a | 265 | .port_ops = &pdc_pata_ops, |
f497ba73 | 266 | }, |
5a46fe89 | 267 | |
5595ddf9 | 268 | [board_2057x] = |
6340f019 | 269 | { |
eca25dca TH |
270 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
271 | PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, | |
14bdef98 EIB |
272 | .pio_mask = ATA_PIO4, |
273 | .mwdma_mask = ATA_MWDMA2, | |
469248ab | 274 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
275 | .port_ops = &pdc_sata_ops, |
276 | }, | |
277 | ||
5595ddf9 | 278 | [board_2057x_pata] = |
eca25dca | 279 | { |
bb312235 | 280 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
eca25dca | 281 | PDC_FLAG_GEN_II, |
14bdef98 EIB |
282 | .pio_mask = ATA_PIO4, |
283 | .mwdma_mask = ATA_MWDMA2, | |
469248ab | 284 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
285 | .port_ops = &pdc_pata_ops, |
286 | }, | |
287 | ||
5595ddf9 | 288 | [board_40518] = |
6340f019 | 289 | { |
eca25dca TH |
290 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
291 | PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, | |
14bdef98 EIB |
292 | .pio_mask = ATA_PIO4, |
293 | .mwdma_mask = ATA_MWDMA2, | |
469248ab | 294 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
295 | .port_ops = &pdc_sata_ops, |
296 | }, | |
1da177e4 LT |
297 | }; |
298 | ||
3b7d697d | 299 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 300 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
301 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
302 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
303 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
304 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
305 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 306 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 307 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 308 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 309 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
310 | |
311 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
312 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
7f9992a2 MP |
313 | { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, |
314 | { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, | |
b2d1eee1 | 315 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
316 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
317 | ||
318 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 319 | |
1da177e4 LT |
320 | { } /* terminate list */ |
321 | }; | |
322 | ||
1da177e4 LT |
323 | static struct pci_driver pdc_ata_pci_driver = { |
324 | .name = DRV_NAME, | |
325 | .id_table = pdc_ata_pci_tbl, | |
326 | .probe = pdc_ata_init_one, | |
327 | .remove = ata_pci_remove_one, | |
328 | }; | |
329 | ||
724114a5 | 330 | static int pdc_common_port_start(struct ata_port *ap) |
1da177e4 | 331 | { |
cca3974e | 332 | struct device *dev = ap->host->dev; |
1da177e4 LT |
333 | struct pdc_port_priv *pp; |
334 | int rc; | |
335 | ||
336 | rc = ata_port_start(ap); | |
337 | if (rc) | |
338 | return rc; | |
339 | ||
24dc5f33 TH |
340 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
341 | if (!pp) | |
342 | return -ENOMEM; | |
1da177e4 | 343 | |
24dc5f33 TH |
344 | pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); |
345 | if (!pp->pkt) | |
346 | return -ENOMEM; | |
1da177e4 LT |
347 | |
348 | ap->private_data = pp; | |
349 | ||
724114a5 MP |
350 | return 0; |
351 | } | |
352 | ||
353 | static int pdc_sata_port_start(struct ata_port *ap) | |
354 | { | |
724114a5 MP |
355 | int rc; |
356 | ||
357 | rc = pdc_common_port_start(ap); | |
358 | if (rc) | |
359 | return rc; | |
360 | ||
599b7202 | 361 | /* fix up PHYMODE4 align timing */ |
eca25dca | 362 | if (ap->flags & PDC_FLAG_GEN_II) { |
821d22cd | 363 | void __iomem *sata_mmio = ap->ioaddr.scr_addr; |
599b7202 MP |
364 | unsigned int tmp; |
365 | ||
821d22cd | 366 | tmp = readl(sata_mmio + PDC_PHYMODE4); |
599b7202 | 367 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ |
821d22cd | 368 | writel(tmp, sata_mmio + PDC_PHYMODE4); |
599b7202 MP |
369 | } |
370 | ||
1da177e4 | 371 | return 0; |
1da177e4 LT |
372 | } |
373 | ||
ff7cddf5 MP |
374 | static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap) |
375 | { | |
376 | void __iomem *sata_mmio = ap->ioaddr.scr_addr; | |
377 | u32 tmp; | |
378 | ||
379 | tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT); | |
380 | tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG; | |
381 | tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG; | |
382 | ||
383 | /* It's not allowed to write to the entire FPDMA_CTLSTAT register | |
384 | when NCQ is running. So do a byte-sized write to bits 10 and 11. */ | |
385 | writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1); | |
386 | readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */ | |
387 | } | |
388 | ||
389 | static void pdc_fpdma_reset(struct ata_port *ap) | |
390 | { | |
391 | void __iomem *sata_mmio = ap->ioaddr.scr_addr; | |
392 | u8 tmp; | |
393 | ||
394 | tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT); | |
395 | tmp &= 0x7F; | |
396 | tmp |= PDC_FPDMA_CTLSTAT_RESET; | |
397 | writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); | |
398 | readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ | |
399 | udelay(100); | |
400 | tmp &= ~PDC_FPDMA_CTLSTAT_RESET; | |
401 | writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); | |
402 | readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ | |
403 | ||
404 | pdc_fpdma_clear_interrupt_flag(ap); | |
405 | } | |
406 | ||
407 | static void pdc_not_at_command_packet_phase(struct ata_port *ap) | |
408 | { | |
409 | void __iomem *sata_mmio = ap->ioaddr.scr_addr; | |
410 | unsigned int i; | |
411 | u32 tmp; | |
412 | ||
413 | /* check not at ASIC packet command phase */ | |
414 | for (i = 0; i < 100; ++i) { | |
415 | writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1); | |
416 | tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2); | |
417 | if ((tmp & 0xF) != 1) | |
418 | break; | |
419 | udelay(100); | |
420 | } | |
421 | } | |
422 | ||
423 | static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap) | |
424 | { | |
425 | void __iomem *sata_mmio = ap->ioaddr.scr_addr; | |
426 | ||
427 | writel(0xffffffff, sata_mmio + PDC_SATA_ERROR); | |
428 | writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS); | |
429 | } | |
430 | ||
1da177e4 LT |
431 | static void pdc_reset_port(struct ata_port *ap) |
432 | { | |
821d22cd | 433 | void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
434 | unsigned int i; |
435 | u32 tmp; | |
436 | ||
ff7cddf5 MP |
437 | if (ap->flags & PDC_FLAG_GEN_II) |
438 | pdc_not_at_command_packet_phase(ap); | |
439 | ||
440 | tmp = readl(ata_ctlstat_mmio); | |
441 | tmp |= PDC_RESET; | |
442 | writel(tmp, ata_ctlstat_mmio); | |
443 | ||
1da177e4 | 444 | for (i = 11; i > 0; i--) { |
821d22cd | 445 | tmp = readl(ata_ctlstat_mmio); |
1da177e4 LT |
446 | if (tmp & PDC_RESET) |
447 | break; | |
448 | ||
449 | udelay(100); | |
450 | ||
451 | tmp |= PDC_RESET; | |
821d22cd | 452 | writel(tmp, ata_ctlstat_mmio); |
1da177e4 LT |
453 | } |
454 | ||
455 | tmp &= ~PDC_RESET; | |
821d22cd MP |
456 | writel(tmp, ata_ctlstat_mmio); |
457 | readl(ata_ctlstat_mmio); /* flush */ | |
ff7cddf5 MP |
458 | |
459 | if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) { | |
460 | pdc_fpdma_reset(ap); | |
461 | pdc_clear_internal_debug_record_error_register(ap); | |
462 | } | |
1da177e4 LT |
463 | } |
464 | ||
724114a5 | 465 | static int pdc_pata_cable_detect(struct ata_port *ap) |
2cba582a | 466 | { |
d3fb4e8d | 467 | u8 tmp; |
821d22cd | 468 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
d3fb4e8d | 469 | |
821d22cd | 470 | tmp = readb(ata_mmio + PDC_CTLSTAT + 3); |
724114a5 MP |
471 | if (tmp & 0x01) |
472 | return ATA_CBL_PATA40; | |
473 | return ATA_CBL_PATA80; | |
474 | } | |
475 | ||
476 | static int pdc_sata_cable_detect(struct ata_port *ap) | |
477 | { | |
e2a9752a | 478 | return ATA_CBL_SATA; |
d3fb4e8d | 479 | } |
2cba582a | 480 | |
82ef04fb TH |
481 | static int pdc_sata_scr_read(struct ata_link *link, |
482 | unsigned int sc_reg, u32 *val) | |
1da177e4 | 483 | { |
724114a5 | 484 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 485 | return -EINVAL; |
82ef04fb | 486 | *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 487 | return 0; |
1da177e4 LT |
488 | } |
489 | ||
82ef04fb TH |
490 | static int pdc_sata_scr_write(struct ata_link *link, |
491 | unsigned int sc_reg, u32 val) | |
1da177e4 | 492 | { |
724114a5 | 493 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 494 | return -EINVAL; |
82ef04fb | 495 | writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 496 | return 0; |
1da177e4 LT |
497 | } |
498 | ||
fba6edbd | 499 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 500 | { |
4113bb6b MP |
501 | struct ata_port *ap = qc->ap; |
502 | dma_addr_t sg_table = ap->prd_dma; | |
503 | unsigned int cdb_len = qc->dev->cdb_len; | |
504 | u8 *cdb = qc->cdb; | |
505 | struct pdc_port_priv *pp = ap->private_data; | |
506 | u8 *buf = pp->pkt; | |
826cd156 | 507 | __le32 *buf32 = (__le32 *) buf; |
46a67143 | 508 | unsigned int dev_sel, feature; |
95006188 MP |
509 | |
510 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
511 | * and seq id (byte 2) | |
512 | */ | |
fba6edbd | 513 | switch (qc->tf.protocol) { |
0dc36888 | 514 | case ATAPI_PROT_DMA: |
fba6edbd MP |
515 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
516 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
517 | else | |
518 | buf32[0] = 0; | |
519 | break; | |
0dc36888 | 520 | case ATAPI_PROT_NODATA: |
fba6edbd MP |
521 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); |
522 | break; | |
523 | default: | |
524 | BUG(); | |
525 | break; | |
526 | } | |
95006188 MP |
527 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
528 | buf32[2] = 0; /* no next-packet */ | |
529 | ||
4113bb6b | 530 | /* select drive */ |
46a67143 | 531 | if (sata_scr_valid(&ap->link)) |
4113bb6b | 532 | dev_sel = PDC_DEVICE_SATA; |
46a67143 TH |
533 | else |
534 | dev_sel = qc->tf.device; | |
535 | ||
4113bb6b MP |
536 | buf[12] = (1 << 5) | ATA_REG_DEVICE; |
537 | buf[13] = dev_sel; | |
538 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
539 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
540 | ||
541 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
46a67143 | 542 | buf[17] = qc->tf.nsect; |
4113bb6b | 543 | buf[18] = (1 << 5) | ATA_REG_LBAL; |
46a67143 | 544 | buf[19] = qc->tf.lbal; |
4113bb6b MP |
545 | |
546 | /* set feature and byte counter registers */ | |
0dc36888 | 547 | if (qc->tf.protocol != ATAPI_PROT_DMA) |
4113bb6b | 548 | feature = PDC_FEATURE_ATAPI_PIO; |
46a67143 | 549 | else |
4113bb6b | 550 | feature = PDC_FEATURE_ATAPI_DMA; |
46a67143 | 551 | |
4113bb6b MP |
552 | buf[20] = (1 << 5) | ATA_REG_FEATURE; |
553 | buf[21] = feature; | |
554 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
46a67143 | 555 | buf[23] = qc->tf.lbam; |
4113bb6b | 556 | buf[24] = (1 << 5) | ATA_REG_BYTEH; |
46a67143 | 557 | buf[25] = qc->tf.lbah; |
4113bb6b MP |
558 | |
559 | /* send ATAPI packet command 0xA0 */ | |
560 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
46a67143 | 561 | buf[27] = qc->tf.command; |
4113bb6b MP |
562 | |
563 | /* select drive and check DRQ */ | |
564 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
565 | buf[29] = dev_sel; | |
566 | ||
95006188 MP |
567 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
568 | BUG_ON(cdb_len & ~0x1E); | |
569 | ||
4113bb6b MP |
570 | /* append the CDB as the final part */ |
571 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
572 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
573 | } |
574 | ||
b9ccd4a9 MP |
575 | /** |
576 | * pdc_fill_sg - Fill PCI IDE PRD table | |
577 | * @qc: Metadata associated with taskfile to be transferred | |
578 | * | |
579 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
580 | * associated with the current disk command. | |
581 | * Make sure hardware does not choke on it. | |
582 | * | |
583 | * LOCKING: | |
584 | * spin_lock_irqsave(host lock) | |
585 | * | |
586 | */ | |
587 | static void pdc_fill_sg(struct ata_queued_cmd *qc) | |
588 | { | |
589 | struct ata_port *ap = qc->ap; | |
590 | struct scatterlist *sg; | |
b9ccd4a9 | 591 | const u32 SG_COUNT_ASIC_BUG = 41*4; |
ff2aeb1e TH |
592 | unsigned int si, idx; |
593 | u32 len; | |
b9ccd4a9 MP |
594 | |
595 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
596 | return; | |
597 | ||
b9ccd4a9 | 598 | idx = 0; |
ff2aeb1e | 599 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
b9ccd4a9 | 600 | u32 addr, offset; |
6903c0f7 | 601 | u32 sg_len; |
b9ccd4a9 MP |
602 | |
603 | /* determine if physical DMA addr spans 64K boundary. | |
604 | * Note h/w doesn't support 64-bit, so we unconditionally | |
605 | * truncate dma_addr_t to u32. | |
606 | */ | |
607 | addr = (u32) sg_dma_address(sg); | |
608 | sg_len = sg_dma_len(sg); | |
609 | ||
610 | while (sg_len) { | |
611 | offset = addr & 0xffff; | |
612 | len = sg_len; | |
613 | if ((offset + sg_len) > 0x10000) | |
614 | len = 0x10000 - offset; | |
615 | ||
616 | ap->prd[idx].addr = cpu_to_le32(addr); | |
617 | ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff); | |
618 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); | |
619 | ||
620 | idx++; | |
621 | sg_len -= len; | |
622 | addr += len; | |
623 | } | |
624 | } | |
625 | ||
ff2aeb1e | 626 | len = le32_to_cpu(ap->prd[idx - 1].flags_len); |
b9ccd4a9 | 627 | |
ff2aeb1e TH |
628 | if (len > SG_COUNT_ASIC_BUG) { |
629 | u32 addr; | |
b9ccd4a9 | 630 | |
ff2aeb1e | 631 | VPRINTK("Splitting last PRD.\n"); |
b9ccd4a9 | 632 | |
ff2aeb1e TH |
633 | addr = le32_to_cpu(ap->prd[idx - 1].addr); |
634 | ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); | |
635 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG); | |
b9ccd4a9 | 636 | |
ff2aeb1e TH |
637 | addr = addr + len - SG_COUNT_ASIC_BUG; |
638 | len = SG_COUNT_ASIC_BUG; | |
639 | ap->prd[idx].addr = cpu_to_le32(addr); | |
640 | ap->prd[idx].flags_len = cpu_to_le32(len); | |
641 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); | |
b9ccd4a9 | 642 | |
ff2aeb1e | 643 | idx++; |
b9ccd4a9 | 644 | } |
ff2aeb1e TH |
645 | |
646 | ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
b9ccd4a9 MP |
647 | } |
648 | ||
1da177e4 LT |
649 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
650 | { | |
651 | struct pdc_port_priv *pp = qc->ap->private_data; | |
652 | unsigned int i; | |
653 | ||
654 | VPRINTK("ENTER\n"); | |
655 | ||
656 | switch (qc->tf.protocol) { | |
657 | case ATA_PROT_DMA: | |
b9ccd4a9 | 658 | pdc_fill_sg(qc); |
7715a6f9 | 659 | /*FALLTHROUGH*/ |
1da177e4 LT |
660 | case ATA_PROT_NODATA: |
661 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
662 | qc->dev->devno, pp->pkt); | |
1da177e4 LT |
663 | if (qc->tf.flags & ATA_TFLAG_LBA48) |
664 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
665 | else | |
666 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
1da177e4 LT |
667 | pdc_pkt_footer(&qc->tf, pp->pkt, i); |
668 | break; | |
0dc36888 | 669 | case ATAPI_PROT_PIO: |
b9ccd4a9 | 670 | pdc_fill_sg(qc); |
95006188 | 671 | break; |
0dc36888 | 672 | case ATAPI_PROT_DMA: |
b9ccd4a9 | 673 | pdc_fill_sg(qc); |
fba6edbd | 674 | /*FALLTHROUGH*/ |
0dc36888 | 675 | case ATAPI_PROT_NODATA: |
fba6edbd | 676 | pdc_atapi_pkt(qc); |
95006188 | 677 | break; |
1da177e4 LT |
678 | default: |
679 | break; | |
680 | } | |
681 | } | |
682 | ||
c07a9c49 MP |
683 | static int pdc_is_sataii_tx4(unsigned long flags) |
684 | { | |
685 | const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; | |
686 | return (flags & mask) == mask; | |
687 | } | |
688 | ||
689 | static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, | |
690 | int is_sataii_tx4) | |
691 | { | |
692 | static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; | |
693 | return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; | |
694 | } | |
695 | ||
696 | static unsigned int pdc_sata_nr_ports(const struct ata_port *ap) | |
697 | { | |
698 | return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2; | |
699 | } | |
700 | ||
701 | static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap) | |
702 | { | |
703 | const struct ata_host *host = ap->host; | |
704 | unsigned int nr_ports = pdc_sata_nr_ports(ap); | |
705 | unsigned int i; | |
706 | ||
7715a6f9 | 707 | for (i = 0; i < nr_ports && host->ports[i] != ap; ++i) |
c07a9c49 MP |
708 | ; |
709 | BUG_ON(i >= nr_ports); | |
710 | return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); | |
711 | } | |
712 | ||
25b93d81 MP |
713 | static void pdc_freeze(struct ata_port *ap) |
714 | { | |
821d22cd | 715 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
716 | u32 tmp; |
717 | ||
821d22cd | 718 | tmp = readl(ata_mmio + PDC_CTLSTAT); |
25b93d81 MP |
719 | tmp |= PDC_IRQ_DISABLE; |
720 | tmp &= ~PDC_DMA_ENABLE; | |
821d22cd MP |
721 | writel(tmp, ata_mmio + PDC_CTLSTAT); |
722 | readl(ata_mmio + PDC_CTLSTAT); /* flush */ | |
25b93d81 MP |
723 | } |
724 | ||
c07a9c49 MP |
725 | static void pdc_sata_freeze(struct ata_port *ap) |
726 | { | |
727 | struct ata_host *host = ap->host; | |
728 | void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; | |
0ae6654d | 729 | unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR; |
c07a9c49 MP |
730 | unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); |
731 | u32 hotplug_status; | |
732 | ||
733 | /* Disable hotplug events on this port. | |
734 | * | |
735 | * Locking: | |
736 | * 1) hotplug register accesses must be serialised via host->lock | |
737 | * 2) ap->lock == &ap->host->lock | |
738 | * 3) ->freeze() and ->thaw() are called with ap->lock held | |
739 | */ | |
740 | hotplug_status = readl(host_mmio + hotplug_offset); | |
741 | hotplug_status |= 0x11 << (ata_no + 16); | |
742 | writel(hotplug_status, host_mmio + hotplug_offset); | |
743 | readl(host_mmio + hotplug_offset); /* flush */ | |
744 | ||
745 | pdc_freeze(ap); | |
746 | } | |
747 | ||
25b93d81 MP |
748 | static void pdc_thaw(struct ata_port *ap) |
749 | { | |
821d22cd | 750 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
751 | u32 tmp; |
752 | ||
753 | /* clear IRQ */ | |
821d22cd | 754 | readl(ata_mmio + PDC_COMMAND); |
25b93d81 MP |
755 | |
756 | /* turn IRQ back on */ | |
821d22cd | 757 | tmp = readl(ata_mmio + PDC_CTLSTAT); |
25b93d81 | 758 | tmp &= ~PDC_IRQ_DISABLE; |
821d22cd MP |
759 | writel(tmp, ata_mmio + PDC_CTLSTAT); |
760 | readl(ata_mmio + PDC_CTLSTAT); /* flush */ | |
25b93d81 MP |
761 | } |
762 | ||
c07a9c49 MP |
763 | static void pdc_sata_thaw(struct ata_port *ap) |
764 | { | |
765 | struct ata_host *host = ap->host; | |
766 | void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; | |
0ae6654d | 767 | unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR; |
c07a9c49 MP |
768 | unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); |
769 | u32 hotplug_status; | |
770 | ||
771 | pdc_thaw(ap); | |
772 | ||
773 | /* Enable hotplug events on this port. | |
774 | * Locking: see pdc_sata_freeze(). | |
775 | */ | |
776 | hotplug_status = readl(host_mmio + hotplug_offset); | |
777 | hotplug_status |= 0x11 << ata_no; | |
778 | hotplug_status &= ~(0x11 << (ata_no + 16)); | |
779 | writel(hotplug_status, host_mmio + hotplug_offset); | |
780 | readl(host_mmio + hotplug_offset); /* flush */ | |
781 | } | |
782 | ||
cadef677 MP |
783 | static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, |
784 | unsigned long deadline) | |
785 | { | |
786 | pdc_reset_port(link->ap); | |
787 | return ata_sff_softreset(link, class, deadline); | |
788 | } | |
789 | ||
ff7cddf5 MP |
790 | static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap) |
791 | { | |
792 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; | |
793 | void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; | |
794 | ||
795 | /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */ | |
796 | return (ata_mmio - host_mmio - 0x200) / 0x80; | |
797 | } | |
798 | ||
799 | static void pdc_hard_reset_port(struct ata_port *ap) | |
800 | { | |
801 | void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; | |
802 | void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1; | |
803 | unsigned int ata_no = pdc_ata_port_to_ata_no(ap); | |
804 | u8 tmp; | |
805 | ||
806 | spin_lock(&ap->host->lock); | |
807 | ||
808 | tmp = readb(pcictl_b1_mmio); | |
809 | tmp &= ~(0x10 << ata_no); | |
810 | writeb(tmp, pcictl_b1_mmio); | |
811 | readb(pcictl_b1_mmio); /* flush */ | |
812 | udelay(100); | |
813 | tmp |= (0x10 << ata_no); | |
814 | writeb(tmp, pcictl_b1_mmio); | |
815 | readb(pcictl_b1_mmio); /* flush */ | |
816 | ||
817 | spin_unlock(&ap->host->lock); | |
818 | } | |
819 | ||
cadef677 MP |
820 | static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, |
821 | unsigned long deadline) | |
822 | { | |
ff7cddf5 MP |
823 | if (link->ap->flags & PDC_FLAG_GEN_II) |
824 | pdc_not_at_command_packet_phase(link->ap); | |
825 | /* hotplug IRQs should have been masked by pdc_sata_freeze() */ | |
826 | pdc_hard_reset_port(link->ap); | |
cadef677 | 827 | pdc_reset_port(link->ap); |
ff7cddf5 MP |
828 | |
829 | /* sata_promise can't reliably acquire the first D2H Reg FIS | |
830 | * after hardreset. Do non-waiting hardreset and request | |
831 | * follow-up SRST. | |
832 | */ | |
833 | return sata_std_hardreset(link, class, deadline); | |
cadef677 MP |
834 | } |
835 | ||
a1efdaba | 836 | static void pdc_error_handler(struct ata_port *ap) |
25b93d81 | 837 | { |
25b93d81 MP |
838 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) |
839 | pdc_reset_port(ap); | |
840 | ||
a1efdaba | 841 | ata_std_error_handler(ap); |
724114a5 MP |
842 | } |
843 | ||
25b93d81 MP |
844 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) |
845 | { | |
846 | struct ata_port *ap = qc->ap; | |
847 | ||
25b93d81 | 848 | /* make DMA engine forget about the failed command */ |
a51d644a | 849 | if (qc->flags & ATA_QCFLAG_FAILED) |
25b93d81 MP |
850 | pdc_reset_port(ap); |
851 | } | |
852 | ||
176efb05 MP |
853 | static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, |
854 | u32 port_status, u32 err_mask) | |
855 | { | |
9af5c9c9 | 856 | struct ata_eh_info *ehi = &ap->link.eh_info; |
176efb05 MP |
857 | unsigned int ac_err_mask = 0; |
858 | ||
859 | ata_ehi_clear_desc(ehi); | |
860 | ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); | |
861 | port_status &= err_mask; | |
862 | ||
863 | if (port_status & PDC_DRIVE_ERR) | |
864 | ac_err_mask |= AC_ERR_DEV; | |
865 | if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) | |
a2342f46 | 866 | ac_err_mask |= AC_ERR_OTHER; |
176efb05 MP |
867 | if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) |
868 | ac_err_mask |= AC_ERR_ATA_BUS; | |
869 | if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR | |
870 | | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) | |
871 | ac_err_mask |= AC_ERR_HOST_BUS; | |
872 | ||
936fd732 | 873 | if (sata_scr_valid(&ap->link)) { |
da3dbb17 TH |
874 | u32 serror; |
875 | ||
82ef04fb | 876 | pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror); |
da3dbb17 TH |
877 | ehi->serror |= serror; |
878 | } | |
ce2d3abc | 879 | |
176efb05 | 880 | qc->err_mask |= ac_err_mask; |
ce2d3abc MP |
881 | |
882 | pdc_reset_port(ap); | |
8ffcfd9d MP |
883 | |
884 | ata_port_abort(ap); | |
176efb05 MP |
885 | } |
886 | ||
7715a6f9 MP |
887 | static unsigned int pdc_host_intr(struct ata_port *ap, |
888 | struct ata_queued_cmd *qc) | |
1da177e4 | 889 | { |
a22e2eb0 | 890 | unsigned int handled = 0; |
821d22cd | 891 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
176efb05 MP |
892 | u32 port_status, err_mask; |
893 | ||
894 | err_mask = PDC_ERR_MASK; | |
eca25dca | 895 | if (ap->flags & PDC_FLAG_GEN_II) |
176efb05 MP |
896 | err_mask &= ~PDC1_ERR_MASK; |
897 | else | |
898 | err_mask &= ~PDC2_ERR_MASK; | |
821d22cd | 899 | port_status = readl(ata_mmio + PDC_GLOBAL_CTL); |
176efb05 MP |
900 | if (unlikely(port_status & err_mask)) { |
901 | pdc_error_intr(ap, qc, port_status, err_mask); | |
902 | return 1; | |
1da177e4 LT |
903 | } |
904 | ||
905 | switch (qc->tf.protocol) { | |
906 | case ATA_PROT_DMA: | |
907 | case ATA_PROT_NODATA: | |
0dc36888 TH |
908 | case ATAPI_PROT_DMA: |
909 | case ATAPI_PROT_NODATA: | |
a22e2eb0 AL |
910 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
911 | ata_qc_complete(qc); | |
1da177e4 LT |
912 | handled = 1; |
913 | break; | |
d0e58031 | 914 | default: |
ee500aab AL |
915 | ap->stats.idle_irq++; |
916 | break; | |
d0e58031 | 917 | } |
1da177e4 | 918 | |
ee500aab | 919 | return handled; |
1da177e4 LT |
920 | } |
921 | ||
922 | static void pdc_irq_clear(struct ata_port *ap) | |
923 | { | |
821d22cd | 924 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
1da177e4 | 925 | |
821d22cd | 926 | readl(ata_mmio + PDC_COMMAND); |
1da177e4 LT |
927 | } |
928 | ||
5796d1c4 | 929 | static irqreturn_t pdc_interrupt(int irq, void *dev_instance) |
1da177e4 | 930 | { |
cca3974e | 931 | struct ata_host *host = dev_instance; |
1da177e4 LT |
932 | struct ata_port *ap; |
933 | u32 mask = 0; | |
934 | unsigned int i, tmp; | |
935 | unsigned int handled = 0; | |
821d22cd | 936 | void __iomem *host_mmio; |
a77720ad MP |
937 | unsigned int hotplug_offset, ata_no; |
938 | u32 hotplug_status; | |
939 | int is_sataii_tx4; | |
1da177e4 LT |
940 | |
941 | VPRINTK("ENTER\n"); | |
942 | ||
0d5ff566 | 943 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
1da177e4 LT |
944 | VPRINTK("QUICK EXIT\n"); |
945 | return IRQ_NONE; | |
946 | } | |
947 | ||
821d22cd | 948 | host_mmio = host->iomap[PDC_MMIO_BAR]; |
1da177e4 | 949 | |
c07a9c49 MP |
950 | spin_lock(&host->lock); |
951 | ||
a77720ad | 952 | /* read and clear hotplug flags for all ports */ |
0ae6654d | 953 | if (host->ports[0]->flags & PDC_FLAG_GEN_II) { |
a77720ad | 954 | hotplug_offset = PDC2_SATA_PLUG_CSR; |
0ae6654d MP |
955 | hotplug_status = readl(host_mmio + hotplug_offset); |
956 | if (hotplug_status & 0xff) | |
957 | writel(hotplug_status | 0xff, host_mmio + hotplug_offset); | |
958 | hotplug_status &= 0xff; /* clear uninteresting bits */ | |
959 | } else | |
960 | hotplug_status = 0; | |
a77720ad | 961 | |
1da177e4 | 962 | /* reading should also clear interrupts */ |
821d22cd | 963 | mask = readl(host_mmio + PDC_INT_SEQMASK); |
1da177e4 | 964 | |
a77720ad | 965 | if (mask == 0xffffffff && hotplug_status == 0) { |
1da177e4 | 966 | VPRINTK("QUICK EXIT 2\n"); |
c07a9c49 | 967 | goto done_irq; |
1da177e4 | 968 | } |
6340f019 | 969 | |
7715a6f9 | 970 | mask &= 0xffff; /* only 16 SEQIDs possible */ |
a77720ad | 971 | if (mask == 0 && hotplug_status == 0) { |
1da177e4 | 972 | VPRINTK("QUICK EXIT 3\n"); |
6340f019 | 973 | goto done_irq; |
1da177e4 LT |
974 | } |
975 | ||
821d22cd | 976 | writel(mask, host_mmio + PDC_INT_SEQMASK); |
1da177e4 | 977 | |
a77720ad MP |
978 | is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); |
979 | ||
cca3974e | 980 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 981 | VPRINTK("port %u\n", i); |
cca3974e | 982 | ap = host->ports[i]; |
a77720ad MP |
983 | |
984 | /* check for a plug or unplug event */ | |
985 | ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); | |
986 | tmp = hotplug_status & (0x11 << ata_no); | |
3e4ec344 | 987 | if (tmp) { |
9af5c9c9 | 988 | struct ata_eh_info *ehi = &ap->link.eh_info; |
a77720ad MP |
989 | ata_ehi_clear_desc(ehi); |
990 | ata_ehi_hotplugged(ehi); | |
991 | ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); | |
992 | ata_port_freeze(ap); | |
993 | ++handled; | |
994 | continue; | |
995 | } | |
996 | ||
997 | /* check for a packet interrupt */ | |
1da177e4 | 998 | tmp = mask & (1 << (i + 1)); |
3e4ec344 | 999 | if (tmp) { |
1da177e4 LT |
1000 | struct ata_queued_cmd *qc; |
1001 | ||
9af5c9c9 | 1002 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
e50362ec | 1003 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
1004 | handled += pdc_host_intr(ap, qc); |
1005 | } | |
1006 | } | |
1007 | ||
1da177e4 LT |
1008 | VPRINTK("EXIT\n"); |
1009 | ||
6340f019 | 1010 | done_irq: |
cca3974e | 1011 | spin_unlock(&host->lock); |
1da177e4 LT |
1012 | return IRQ_RETVAL(handled); |
1013 | } | |
1014 | ||
7715a6f9 | 1015 | static void pdc_packet_start(struct ata_queued_cmd *qc) |
1da177e4 LT |
1016 | { |
1017 | struct ata_port *ap = qc->ap; | |
1018 | struct pdc_port_priv *pp = ap->private_data; | |
821d22cd MP |
1019 | void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; |
1020 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; | |
1da177e4 LT |
1021 | unsigned int port_no = ap->port_no; |
1022 | u8 seq = (u8) (port_no + 1); | |
1023 | ||
1024 | VPRINTK("ENTER, ap %p\n", ap); | |
1025 | ||
821d22cd MP |
1026 | writel(0x00000001, host_mmio + (seq * 4)); |
1027 | readl(host_mmio + (seq * 4)); /* flush */ | |
1da177e4 LT |
1028 | |
1029 | pp->pkt[2] = seq; | |
1030 | wmb(); /* flush PRD, pkt writes */ | |
821d22cd MP |
1031 | writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT); |
1032 | readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
1033 | } |
1034 | ||
9363c382 | 1035 | static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1036 | { |
1037 | switch (qc->tf.protocol) { | |
0dc36888 | 1038 | case ATAPI_PROT_NODATA: |
fba6edbd MP |
1039 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) |
1040 | break; | |
1041 | /*FALLTHROUGH*/ | |
51b94d2a TH |
1042 | case ATA_PROT_NODATA: |
1043 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1044 | break; | |
1045 | /*FALLTHROUGH*/ | |
0dc36888 | 1046 | case ATAPI_PROT_DMA: |
1da177e4 | 1047 | case ATA_PROT_DMA: |
1da177e4 LT |
1048 | pdc_packet_start(qc); |
1049 | return 0; | |
1da177e4 LT |
1050 | default: |
1051 | break; | |
1052 | } | |
9363c382 | 1053 | return ata_sff_qc_issue(qc); |
1da177e4 LT |
1054 | } |
1055 | ||
057ace5e | 1056 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 | 1057 | { |
0dc36888 | 1058 | WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); |
9363c382 | 1059 | ata_sff_tf_load(ap, tf); |
1da177e4 LT |
1060 | } |
1061 | ||
5796d1c4 JG |
1062 | static void pdc_exec_command_mmio(struct ata_port *ap, |
1063 | const struct ata_taskfile *tf) | |
1da177e4 | 1064 | { |
0dc36888 | 1065 | WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); |
9363c382 | 1066 | ata_sff_exec_command(ap, tf); |
1da177e4 LT |
1067 | } |
1068 | ||
95006188 MP |
1069 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
1070 | { | |
1071 | u8 *scsicmd = qc->scsicmd->cmnd; | |
1072 | int pio = 1; /* atapi dma off by default */ | |
1073 | ||
1074 | /* Whitelist commands that may use DMA. */ | |
1075 | switch (scsicmd[0]) { | |
1076 | case WRITE_12: | |
1077 | case WRITE_10: | |
1078 | case WRITE_6: | |
1079 | case READ_12: | |
1080 | case READ_10: | |
1081 | case READ_6: | |
1082 | case 0xad: /* READ_DVD_STRUCTURE */ | |
1083 | case 0xbe: /* READ_CD */ | |
1084 | pio = 0; | |
1085 | } | |
1086 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
1087 | if (scsicmd[0] == WRITE_10) { | |
5796d1c4 JG |
1088 | unsigned int lba = |
1089 | (scsicmd[2] << 24) | | |
1090 | (scsicmd[3] << 16) | | |
1091 | (scsicmd[4] << 8) | | |
1092 | scsicmd[5]; | |
95006188 MP |
1093 | if (lba >= 0xFFFF4FA2) |
1094 | pio = 1; | |
1095 | } | |
1096 | return pio; | |
1097 | } | |
1098 | ||
724114a5 | 1099 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
95006188 | 1100 | { |
95006188 | 1101 | /* First generation chips cannot use ATAPI DMA on SATA ports */ |
724114a5 | 1102 | return 1; |
95006188 | 1103 | } |
1da177e4 | 1104 | |
eca25dca TH |
1105 | static void pdc_ata_setup_port(struct ata_port *ap, |
1106 | void __iomem *base, void __iomem *scr_addr) | |
1da177e4 | 1107 | { |
eca25dca TH |
1108 | ap->ioaddr.cmd_addr = base; |
1109 | ap->ioaddr.data_addr = base; | |
1110 | ap->ioaddr.feature_addr = | |
1111 | ap->ioaddr.error_addr = base + 0x4; | |
1112 | ap->ioaddr.nsect_addr = base + 0x8; | |
1113 | ap->ioaddr.lbal_addr = base + 0xc; | |
1114 | ap->ioaddr.lbam_addr = base + 0x10; | |
1115 | ap->ioaddr.lbah_addr = base + 0x14; | |
1116 | ap->ioaddr.device_addr = base + 0x18; | |
1117 | ap->ioaddr.command_addr = | |
1118 | ap->ioaddr.status_addr = base + 0x1c; | |
1119 | ap->ioaddr.altstatus_addr = | |
1120 | ap->ioaddr.ctl_addr = base + 0x38; | |
1121 | ap->ioaddr.scr_addr = scr_addr; | |
1da177e4 LT |
1122 | } |
1123 | ||
eca25dca | 1124 | static void pdc_host_init(struct ata_host *host) |
1da177e4 | 1125 | { |
821d22cd | 1126 | void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; |
eca25dca | 1127 | int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; |
d324d462 | 1128 | int hotplug_offset; |
1da177e4 LT |
1129 | u32 tmp; |
1130 | ||
eca25dca | 1131 | if (is_gen2) |
d324d462 MP |
1132 | hotplug_offset = PDC2_SATA_PLUG_CSR; |
1133 | else | |
1134 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
1135 | ||
1da177e4 LT |
1136 | /* |
1137 | * Except for the hotplug stuff, this is voodoo from the | |
1138 | * Promise driver. Label this entire section | |
1139 | * "TODO: figure out why we do this" | |
1140 | */ | |
1141 | ||
b2d1eee1 | 1142 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
821d22cd | 1143 | tmp = readl(host_mmio + PDC_FLASH_CTL); |
b2d1eee1 | 1144 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
eca25dca | 1145 | if (!is_gen2) |
b2d1eee1 | 1146 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ |
821d22cd | 1147 | writel(tmp, host_mmio + PDC_FLASH_CTL); |
1da177e4 LT |
1148 | |
1149 | /* clear plug/unplug flags for all ports */ | |
821d22cd MP |
1150 | tmp = readl(host_mmio + hotplug_offset); |
1151 | writel(tmp | 0xff, host_mmio + hotplug_offset); | |
1da177e4 | 1152 | |
821d22cd | 1153 | tmp = readl(host_mmio + hotplug_offset); |
0ae6654d MP |
1154 | if (is_gen2) /* unmask plug/unplug ints */ |
1155 | writel(tmp & ~0xff0000, host_mmio + hotplug_offset); | |
1156 | else /* mask plug/unplug ints */ | |
1157 | writel(tmp | 0xff0000, host_mmio + hotplug_offset); | |
1da177e4 | 1158 | |
b2d1eee1 | 1159 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
eca25dca | 1160 | if (is_gen2) |
b2d1eee1 MP |
1161 | return; |
1162 | ||
1da177e4 | 1163 | /* reduce TBG clock to 133 Mhz. */ |
821d22cd | 1164 | tmp = readl(host_mmio + PDC_TBG_MODE); |
1da177e4 LT |
1165 | tmp &= ~0x30000; /* clear bit 17, 16*/ |
1166 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
821d22cd | 1167 | writel(tmp, host_mmio + PDC_TBG_MODE); |
1da177e4 | 1168 | |
821d22cd | 1169 | readl(host_mmio + PDC_TBG_MODE); /* flush */ |
1da177e4 LT |
1170 | msleep(10); |
1171 | ||
1172 | /* adjust slew rate control register. */ | |
821d22cd | 1173 | tmp = readl(host_mmio + PDC_SLEW_CTL); |
1da177e4 LT |
1174 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ |
1175 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
821d22cd | 1176 | writel(tmp, host_mmio + PDC_SLEW_CTL); |
1da177e4 LT |
1177 | } |
1178 | ||
5796d1c4 JG |
1179 | static int pdc_ata_init_one(struct pci_dev *pdev, |
1180 | const struct pci_device_id *ent) | |
1da177e4 LT |
1181 | { |
1182 | static int printed_version; | |
eca25dca TH |
1183 | const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; |
1184 | const struct ata_port_info *ppi[PDC_MAX_PORTS]; | |
1185 | struct ata_host *host; | |
821d22cd | 1186 | void __iomem *host_mmio; |
eca25dca | 1187 | int n_ports, i, rc; |
5ac2fe57 | 1188 | int is_sataii_tx4; |
1da177e4 LT |
1189 | |
1190 | if (!printed_version++) | |
a9524a76 | 1191 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1192 | |
eca25dca | 1193 | /* enable and acquire resources */ |
24dc5f33 | 1194 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1195 | if (rc) |
1196 | return rc; | |
1197 | ||
0d5ff566 TH |
1198 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
1199 | if (rc == -EBUSY) | |
24dc5f33 | 1200 | pcim_pin_device(pdev); |
0d5ff566 | 1201 | if (rc) |
24dc5f33 | 1202 | return rc; |
821d22cd | 1203 | host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; |
1da177e4 | 1204 | |
eca25dca TH |
1205 | /* determine port configuration and setup host */ |
1206 | n_ports = 2; | |
1207 | if (pi->flags & PDC_FLAG_4_PORTS) | |
1208 | n_ports = 4; | |
1209 | for (i = 0; i < n_ports; i++) | |
1210 | ppi[i] = pi; | |
1da177e4 | 1211 | |
eca25dca | 1212 | if (pi->flags & PDC_FLAG_SATA_PATA) { |
821d22cd | 1213 | u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); |
d0e58031 | 1214 | if (!(tmp & 0x80)) |
eca25dca | 1215 | ppi[n_ports++] = pi + 1; |
eca25dca | 1216 | } |
1da177e4 | 1217 | |
eca25dca TH |
1218 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
1219 | if (!host) { | |
1220 | dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); | |
24dc5f33 | 1221 | return -ENOMEM; |
1da177e4 | 1222 | } |
eca25dca | 1223 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 | 1224 | |
d0e58031 | 1225 | is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); |
5ac2fe57 | 1226 | for (i = 0; i < host->n_ports; i++) { |
cbcdd875 | 1227 | struct ata_port *ap = host->ports[i]; |
d0e58031 | 1228 | unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); |
821d22cd | 1229 | unsigned int ata_offset = 0x200 + ata_no * 0x80; |
cbcdd875 TH |
1230 | unsigned int scr_offset = 0x400 + ata_no * 0x100; |
1231 | ||
821d22cd | 1232 | pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset); |
cbcdd875 TH |
1233 | |
1234 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); | |
821d22cd | 1235 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata"); |
5ac2fe57 | 1236 | } |
1da177e4 LT |
1237 | |
1238 | /* initialize adapter */ | |
eca25dca | 1239 | pdc_host_init(host); |
1da177e4 | 1240 | |
eca25dca TH |
1241 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1242 | if (rc) | |
1243 | return rc; | |
1244 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1245 | if (rc) | |
1246 | return rc; | |
1da177e4 | 1247 | |
eca25dca TH |
1248 | /* start host, request IRQ and attach */ |
1249 | pci_set_master(pdev); | |
1250 | return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, | |
1251 | &pdc_ata_sht); | |
1da177e4 LT |
1252 | } |
1253 | ||
1da177e4 LT |
1254 | static int __init pdc_ata_init(void) |
1255 | { | |
b7887196 | 1256 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1257 | } |
1258 | ||
1da177e4 LT |
1259 | static void __exit pdc_ata_exit(void) |
1260 | { | |
1261 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1262 | } | |
1263 | ||
1da177e4 | 1264 | MODULE_AUTHOR("Jeff Garzik"); |
f497ba73 | 1265 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1266 | MODULE_LICENSE("GPL"); |
1267 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1268 | MODULE_VERSION(DRV_VERSION); | |
1269 | ||
1270 | module_init(pdc_ata_init); | |
1271 | module_exit(pdc_ata_exit); |