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sata_promise: ASIC PRD table bug workaround, take 2
[deliverable/linux.git] / drivers / ata / sata_promise.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
1da177e4 10 *
af36d7f0
JG		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
1da177e4
LT		 30 *
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
a9524a76 40#include <linux/device.h>
95006188 41#include <scsi/scsi.h>
1da177e4 42#include <scsi/scsi_host.h>
193515d5 43#include <scsi/scsi_cmnd.h>
1da177e4 44#include <linux/libata.h>
1da177e4
LT		 45#include "sata_promise.h"
46
47#define DRV_NAME "sata_promise"
7f9992a2 48#define DRV_VERSION "2.10"
1da177e4
LT		 49
50enum {
eca25dca 51 PDC_MAX_PORTS = 4,
0d5ff566 52 PDC_MMIO_BAR = 3,
b9ccd4a9 53 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
0d5ff566 54
95006188
MP		 55 /* register offsets */
56 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
57 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
58 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
59 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
60 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
61 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
62 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
73fd456b 63 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
1da177e4
LT		 64 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
65 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
1da177e4 66 PDC_FLASH_CTL = 0x44, /* Flash control register */
1da177e4
LT		 67 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
68 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
69 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
6340f019 70 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
b2d1eee1
MP		 71 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
72 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
1da177e4 73
176efb05
MP		 74 /* PDC_GLOBAL_CTL bit definitions */
75 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
76 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
77 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
78 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
79 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
80 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
81 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
82 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
83 PDC_DRIVE_ERR = (1 << 21), /* drive error */
84 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
85 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
86 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
5796d1c4
JG		 87 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
88 PDC2_ATA_DMA_CNT_ERR,
89 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
90 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
91 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
92 PDC1_ERR_MASK | PDC2_ERR_MASK,
1da177e4
LT		 93
94 board_2037x = 0, /* FastTrak S150 TX2plus */
eca25dca
TH		 95 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
96 board_20319 = 2, /* FastTrak S150 TX4 */
97 board_20619 = 3, /* FastTrak TX4000 */
98 board_2057x = 4, /* SATAII150 Tx2plus */
d0e58031 99 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
eca25dca 100 board_40518 = 6, /* SATAII150 Tx4 */
1da177e4 101
6340f019 102 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
1da177e4 103
95006188
MP		 104 /* Sequence counter control registers bit definitions */
105 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
106
107 /* Feature register values */
108 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
109 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
110
111 /* Device/Head register values */
112 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
113
25b93d81
MP		 114 /* PDC_CTLSTAT bit definitions */
115 PDC_DMA_ENABLE = (1 << 7),
116 PDC_IRQ_DISABLE = (1 << 10),
1da177e4 117 PDC_RESET = (1 << 11), /* HDMA reset */
50630195 118
25b93d81 119 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
95006188 120 ATA_FLAG_MMIO |
3d0a59c0 121 ATA_FLAG_PIO_POLLING,
b2d1eee1 122
eca25dca
TH		 123 /* ap->flags bits */
124 PDC_FLAG_GEN_II = (1 << 24),
125 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
126 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
1da177e4
LT		 127};
128
1da177e4
LT		 129struct pdc_port_priv {
130 u8 *pkt;
131 dma_addr_t pkt_dma;
132};
133
da3dbb17
TH		 134static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
135static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
1da177e4 136static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
eca25dca
TH		 137static int pdc_common_port_start(struct ata_port *ap);
138static int pdc_sata_port_start(struct ata_port *ap);
1da177e4 139static void pdc_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 140static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
141static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
95006188 142static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
724114a5 143static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
1da177e4 144static void pdc_irq_clear(struct ata_port *ap);
9a3d9eb0 145static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
25b93d81
MP		 146static void pdc_freeze(struct ata_port *ap);
147static void pdc_thaw(struct ata_port *ap);
724114a5
MP		 148static void pdc_pata_error_handler(struct ata_port *ap);
149static void pdc_sata_error_handler(struct ata_port *ap);
25b93d81 150static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
724114a5
MP		 151static int pdc_pata_cable_detect(struct ata_port *ap);
152static int pdc_sata_cable_detect(struct ata_port *ap);
374b1873 153
193515d5 154static struct scsi_host_template pdc_ata_sht = {
1da177e4
LT		 155 .module = THIS_MODULE,
156 .name = DRV_NAME,
157 .ioctl = ata_scsi_ioctl,
158 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 159 .can_queue = ATA_DEF_QUEUE,
160 .this_id = ATA_SHT_THIS_ID,
b9ccd4a9 161 .sg_tablesize = PDC_MAX_PRD,
1da177e4
LT		 162 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
163 .emulated = ATA_SHT_EMULATED,
164 .use_clustering = ATA_SHT_USE_CLUSTERING,
165 .proc_name = DRV_NAME,
166 .dma_boundary = ATA_DMA_BOUNDARY,
167 .slave_configure = ata_scsi_slave_config,
ccf68c34 168 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 169 .bios_param = ata_std_bios_param,
1da177e4
LT		 170};
171
057ace5e 172static const struct ata_port_operations pdc_sata_ops = {
1da177e4
LT		 173 .tf_load = pdc_tf_load_mmio,
174 .tf_read = ata_tf_read,
175 .check_status = ata_check_status,
176 .exec_command = pdc_exec_command_mmio,
177 .dev_select = ata_std_dev_select,
95006188
MP		 178 .check_atapi_dma = pdc_check_atapi_dma,
179
180 .qc_prep = pdc_qc_prep,
181 .qc_issue = pdc_qc_issue_prot,
182 .freeze = pdc_freeze,
183 .thaw = pdc_thaw,
724114a5 184 .error_handler = pdc_sata_error_handler,
95006188 185 .post_internal_cmd = pdc_post_internal_cmd,
724114a5 186 .cable_detect = pdc_sata_cable_detect,
0d5ff566 187 .data_xfer = ata_data_xfer,
95006188 188 .irq_clear = pdc_irq_clear,
246ce3b6 189 .irq_on = ata_irq_on,
95006188
MP		 190
191 .scr_read = pdc_sata_scr_read,
192 .scr_write = pdc_sata_scr_write,
eca25dca 193 .port_start = pdc_sata_port_start,
95006188
MP		 194};
195
196/* First-generation chips need a more restrictive ->check_atapi_dma op */
197static const struct ata_port_operations pdc_old_sata_ops = {
95006188
MP		 198 .tf_load = pdc_tf_load_mmio,
199 .tf_read = ata_tf_read,
200 .check_status = ata_check_status,
201 .exec_command = pdc_exec_command_mmio,
202 .dev_select = ata_std_dev_select,
724114a5 203 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
2cba582a 204
1da177e4
LT		 205 .qc_prep = pdc_qc_prep,
206 .qc_issue = pdc_qc_issue_prot,
25b93d81
MP		 207 .freeze = pdc_freeze,
208 .thaw = pdc_thaw,
724114a5 209 .error_handler = pdc_sata_error_handler,
25b93d81 210 .post_internal_cmd = pdc_post_internal_cmd,
724114a5 211 .cable_detect = pdc_sata_cable_detect,
0d5ff566 212 .data_xfer = ata_data_xfer,
1da177e4 213 .irq_clear = pdc_irq_clear,
246ce3b6 214 .irq_on = ata_irq_on,
2cba582a 215
1da177e4
LT		 216 .scr_read = pdc_sata_scr_read,
217 .scr_write = pdc_sata_scr_write,
eca25dca 218 .port_start = pdc_sata_port_start,
1da177e4
LT		 219};
220
057ace5e 221static const struct ata_port_operations pdc_pata_ops = {
2cba582a
JG		 222 .tf_load = pdc_tf_load_mmio,
223 .tf_read = ata_tf_read,
224 .check_status = ata_check_status,
225 .exec_command = pdc_exec_command_mmio,
226 .dev_select = ata_std_dev_select,
95006188 227 .check_atapi_dma = pdc_check_atapi_dma,
2cba582a 228
2cba582a
JG		 229 .qc_prep = pdc_qc_prep,
230 .qc_issue = pdc_qc_issue_prot,
5387373b
MP		 231 .freeze = pdc_freeze,
232 .thaw = pdc_thaw,
724114a5 233 .error_handler = pdc_pata_error_handler,
540477b4 234 .post_internal_cmd = pdc_post_internal_cmd,
724114a5 235 .cable_detect = pdc_pata_cable_detect,
0d5ff566 236 .data_xfer = ata_data_xfer,
2cba582a 237 .irq_clear = pdc_irq_clear,
246ce3b6 238 .irq_on = ata_irq_on,
2cba582a 239
eca25dca 240 .port_start = pdc_common_port_start,
2cba582a
JG		 241};
242
98ac62de 243static const struct ata_port_info pdc_port_info[] = {
1da177e4
LT		 244 /* board_2037x */
245 {
eca25dca
TH		 246 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
247 PDC_FLAG_SATA_PATA,
1da177e4
LT		 248 .pio_mask = 0x1f, /* pio0-4 */
249 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 250 .udma_mask = ATA_UDMA6,
95006188 251 .port_ops = &pdc_old_sata_ops,
1da177e4
LT		 252 },
253
eca25dca
TH		 254 /* board_2037x_pata */
255 {
256 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
257 .pio_mask = 0x1f, /* pio0-4 */
258 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 259 .udma_mask = ATA_UDMA6,
eca25dca
TH		 260 .port_ops = &pdc_pata_ops,
261 },
262
1da177e4
LT		 263 /* board_20319 */
264 {
eca25dca
TH		 265 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
266 PDC_FLAG_4_PORTS,
1da177e4
LT		 267 .pio_mask = 0x1f, /* pio0-4 */
268 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 269 .udma_mask = ATA_UDMA6,
95006188 270 .port_ops = &pdc_old_sata_ops,
1da177e4 271 },
f497ba73
TL		 272
273 /* board_20619 */
274 {
eca25dca
TH		 275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
276 PDC_FLAG_4_PORTS,
f497ba73
TL		 277 .pio_mask = 0x1f, /* pio0-4 */
278 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 279 .udma_mask = ATA_UDMA6,
2cba582a 280 .port_ops = &pdc_pata_ops,
f497ba73 281 },
5a46fe89 282
6340f019
LK		 283 /* board_2057x */
284 {
eca25dca
TH		 285 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
286 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
6340f019
LK		 287 .pio_mask = 0x1f, /* pio0-4 */
288 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 289 .udma_mask = ATA_UDMA6,
6340f019
LK		 290 .port_ops = &pdc_sata_ops,
291 },
292
eca25dca
TH		 293 /* board_2057x_pata */
294 {
bb312235 295 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
eca25dca
TH		 296 PDC_FLAG_GEN_II,
297 .pio_mask = 0x1f, /* pio0-4 */
298 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 299 .udma_mask = ATA_UDMA6,
eca25dca
TH		 300 .port_ops = &pdc_pata_ops,
301 },
302
6340f019
LK		 303 /* board_40518 */
304 {
eca25dca
TH		 305 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
306 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
6340f019
LK		 307 .pio_mask = 0x1f, /* pio0-4 */
308 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 309 .udma_mask = ATA_UDMA6,
6340f019
LK		 310 .port_ops = &pdc_sata_ops,
311 },
1da177e4
LT		 312};
313
3b7d697d 314static const struct pci_device_id pdc_ata_pci_tbl[] = {
54bb3a94 315 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
54bb3a94
JG		 316 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
317 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
318 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
b2d1eee1
MP		 319 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
320 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
54bb3a94 321 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
d324d462 322 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
b2d1eee1 323 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
54bb3a94 324 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
54bb3a94
JG		 325
326 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
327 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
7f9992a2
MP		 328 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
329 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
b2d1eee1 330 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
54bb3a94
JG		 331 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
332
333 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
f497ba73 334
1da177e4
LT		 335 { } /* terminate list */
336};
337
1da177e4
LT		 338static struct pci_driver pdc_ata_pci_driver = {
339 .name = DRV_NAME,
340 .id_table = pdc_ata_pci_tbl,
341 .probe = pdc_ata_init_one,
342 .remove = ata_pci_remove_one,
343};
344
724114a5 345static int pdc_common_port_start(struct ata_port *ap)
1da177e4 346{
cca3974e 347 struct device *dev = ap->host->dev;
1da177e4
LT		 348 struct pdc_port_priv *pp;
349 int rc;
350
351 rc = ata_port_start(ap);
352 if (rc)
353 return rc;
354
24dc5f33
TH		 355 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
356 if (!pp)
357 return -ENOMEM;
1da177e4 358
24dc5f33
TH		 359 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
360 if (!pp->pkt)
361 return -ENOMEM;
1da177e4
LT		 362
363 ap->private_data = pp;
364
724114a5
MP		 365 return 0;
366}
367
368static int pdc_sata_port_start(struct ata_port *ap)
369{
724114a5
MP		 370 int rc;
371
372 rc = pdc_common_port_start(ap);
373 if (rc)
374 return rc;
375
599b7202 376 /* fix up PHYMODE4 align timing */
eca25dca 377 if (ap->flags & PDC_FLAG_GEN_II) {
59f99880 378 void __iomem *mmio = ap->ioaddr.scr_addr;
599b7202
MP		 379 unsigned int tmp;
380
381 tmp = readl(mmio + 0x014);
382 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
383 writel(tmp, mmio + 0x014);
384 }
385
1da177e4 386 return 0;
1da177e4
LT		 387}
388
1da177e4
LT		 389static void pdc_reset_port(struct ata_port *ap)
390{
0d5ff566 391 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
1da177e4
LT		 392 unsigned int i;
393 u32 tmp;
394
395 for (i = 11; i > 0; i--) {
396 tmp = readl(mmio);
397 if (tmp & PDC_RESET)
398 break;
399
400 udelay(100);
401
402 tmp |= PDC_RESET;
403 writel(tmp, mmio);
404 }
405
406 tmp &= ~PDC_RESET;
407 writel(tmp, mmio);
408 readl(mmio); /* flush */
409}
410
724114a5 411static int pdc_pata_cable_detect(struct ata_port *ap)
2cba582a 412{
d3fb4e8d 413 u8 tmp;
59f99880 414 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
d3fb4e8d 415
724114a5
MP		 416 tmp = readb(mmio);
417 if (tmp & 0x01)
418 return ATA_CBL_PATA40;
419 return ATA_CBL_PATA80;
420}
421
422static int pdc_sata_cable_detect(struct ata_port *ap)
423{
e2a9752a 424 return ATA_CBL_SATA;
d3fb4e8d 425}
2cba582a 426
da3dbb17 427static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 428{
724114a5 429 if (sc_reg > SCR_CONTROL)
da3dbb17
TH		 430 return -EINVAL;
431 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
432 return 0;
1da177e4
LT		 433}
434
da3dbb17 435static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4 436{
724114a5 437 if (sc_reg > SCR_CONTROL)
da3dbb17 438 return -EINVAL;
0d5ff566 439 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17 440 return 0;
1da177e4
LT		 441}
442
fba6edbd 443static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
95006188 444{
4113bb6b
MP		 445 struct ata_port *ap = qc->ap;
446 dma_addr_t sg_table = ap->prd_dma;
447 unsigned int cdb_len = qc->dev->cdb_len;
448 u8 *cdb = qc->cdb;
449 struct pdc_port_priv *pp = ap->private_data;
450 u8 *buf = pp->pkt;
95006188 451 u32 *buf32 = (u32 *) buf;
4113bb6b 452 unsigned int dev_sel, feature, nbytes;
95006188
MP		 453
454 /* set control bits (byte 0), zero delay seq id (byte 3),
455 * and seq id (byte 2)
456 */
fba6edbd
MP		 457 switch (qc->tf.protocol) {
458 case ATA_PROT_ATAPI_DMA:
459 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
460 buf32[0] = cpu_to_le32(PDC_PKT_READ);
461 else
462 buf32[0] = 0;
463 break;
464 case ATA_PROT_ATAPI_NODATA:
465 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
466 break;
467 default:
468 BUG();
469 break;
470 }
95006188
MP		 471 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
472 buf32[2] = 0; /* no next-packet */
473
4113bb6b 474 /* select drive */
936fd732 475 if (sata_scr_valid(&ap->link)) {
4113bb6b
MP		 476 dev_sel = PDC_DEVICE_SATA;
477 } else {
478 dev_sel = ATA_DEVICE_OBS;
479 if (qc->dev->devno != 0)
480 dev_sel |= ATA_DEV1;
481 }
482 buf[12] = (1 << 5) | ATA_REG_DEVICE;
483 buf[13] = dev_sel;
484 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
485 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
486
487 buf[16] = (1 << 5) | ATA_REG_NSECT;
488 buf[17] = 0x00;
489 buf[18] = (1 << 5) | ATA_REG_LBAL;
490 buf[19] = 0x00;
491
492 /* set feature and byte counter registers */
493 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
494 feature = PDC_FEATURE_ATAPI_PIO;
495 /* set byte counter register to real transfer byte count */
496 nbytes = qc->nbytes;
4113bb6b
MP		 497 if (nbytes > 0xffff)
498 nbytes = 0xffff;
499 } else {
500 feature = PDC_FEATURE_ATAPI_DMA;
501 /* set byte counter register to 0 */
502 nbytes = 0;
503 }
504 buf[20] = (1 << 5) | ATA_REG_FEATURE;
505 buf[21] = feature;
506 buf[22] = (1 << 5) | ATA_REG_BYTEL;
507 buf[23] = nbytes & 0xFF;
508 buf[24] = (1 << 5) | ATA_REG_BYTEH;
509 buf[25] = (nbytes >> 8) & 0xFF;
510
511 /* send ATAPI packet command 0xA0 */
512 buf[26] = (1 << 5) | ATA_REG_CMD;
513 buf[27] = ATA_CMD_PACKET;
514
515 /* select drive and check DRQ */
516 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
517 buf[29] = dev_sel;
518
95006188
MP		 519 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
520 BUG_ON(cdb_len & ~0x1E);
521
4113bb6b
MP		 522 /* append the CDB as the final part */
523 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
524 memcpy(buf+31, cdb, cdb_len);
95006188
MP		 525}
526
b9ccd4a9
MP		 527/**
528 * pdc_fill_sg - Fill PCI IDE PRD table
529 * @qc: Metadata associated with taskfile to be transferred
530 *
531 * Fill PCI IDE PRD (scatter-gather) table with segments
532 * associated with the current disk command.
533 * Make sure hardware does not choke on it.
534 *
535 * LOCKING:
536 * spin_lock_irqsave(host lock)
537 *
538 */
539static void pdc_fill_sg(struct ata_queued_cmd *qc)
540{
541 struct ata_port *ap = qc->ap;
542 struct scatterlist *sg;
543 unsigned int idx;
544 const u32 SG_COUNT_ASIC_BUG = 41*4;
545
546 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
547 return;
548
549 WARN_ON(qc->__sg == NULL);
550 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
551
552 idx = 0;
553 ata_for_each_sg(sg, qc) {
554 u32 addr, offset;
555 u32 sg_len, len;
556
557 /* determine if physical DMA addr spans 64K boundary.
558 * Note h/w doesn't support 64-bit, so we unconditionally
559 * truncate dma_addr_t to u32.
560 */
561 addr = (u32) sg_dma_address(sg);
562 sg_len = sg_dma_len(sg);
563
564 while (sg_len) {
565 offset = addr & 0xffff;
566 len = sg_len;
567 if ((offset + sg_len) > 0x10000)
568 len = 0x10000 - offset;
569
570 ap->prd[idx].addr = cpu_to_le32(addr);
571 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
572 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
573
574 idx++;
575 sg_len -= len;
576 addr += len;
577 }
578 }
579
580 if (idx) {
581 u32 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
582
583 if (len > SG_COUNT_ASIC_BUG) {
584 u32 addr;
585
586 VPRINTK("Splitting last PRD.\n");
587
588 addr = le32_to_cpu(ap->prd[idx - 1].addr);
589 ap->prd[idx - 1].flags_len -= cpu_to_le32(SG_COUNT_ASIC_BUG);
590 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
591
592 addr = addr + len - SG_COUNT_ASIC_BUG;
593 len = SG_COUNT_ASIC_BUG;
594 ap->prd[idx].addr = cpu_to_le32(addr);
595 ap->prd[idx].flags_len = cpu_to_le32(len);
596 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
597
598 idx++;
599 }
600
601 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
602 }
603}
604
1da177e4
LT		 605static void pdc_qc_prep(struct ata_queued_cmd *qc)
606{
607 struct pdc_port_priv *pp = qc->ap->private_data;
608 unsigned int i;
609
610 VPRINTK("ENTER\n");
611
612 switch (qc->tf.protocol) {
613 case ATA_PROT_DMA:
b9ccd4a9 614 pdc_fill_sg(qc);
1da177e4
LT		 615 /* fall through */
616
617 case ATA_PROT_NODATA:
618 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
619 qc->dev->devno, pp->pkt);
620
621 if (qc->tf.flags & ATA_TFLAG_LBA48)
622 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
623 else
624 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
625
626 pdc_pkt_footer(&qc->tf, pp->pkt, i);
627 break;
628
95006188 629 case ATA_PROT_ATAPI:
b9ccd4a9 630 pdc_fill_sg(qc);
95006188
MP		 631 break;
632
633 case ATA_PROT_ATAPI_DMA:
b9ccd4a9 634 pdc_fill_sg(qc);
fba6edbd
MP		 635 /*FALLTHROUGH*/
636 case ATA_PROT_ATAPI_NODATA:
637 pdc_atapi_pkt(qc);
95006188
MP		 638 break;
639
1da177e4
LT		 640 default:
641 break;
642 }
643}
644
25b93d81
MP		 645static void pdc_freeze(struct ata_port *ap)
646{
59f99880 647 void __iomem *mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 648 u32 tmp;
649
650 tmp = readl(mmio + PDC_CTLSTAT);
651 tmp |= PDC_IRQ_DISABLE;
652 tmp &= ~PDC_DMA_ENABLE;
653 writel(tmp, mmio + PDC_CTLSTAT);
654 readl(mmio + PDC_CTLSTAT); /* flush */
655}
656
657static void pdc_thaw(struct ata_port *ap)
658{
59f99880 659 void __iomem *mmio = ap->ioaddr.cmd_addr;
25b93d81
MP		 660 u32 tmp;
661
662 /* clear IRQ */
663 readl(mmio + PDC_INT_SEQMASK);
664
665 /* turn IRQ back on */
666 tmp = readl(mmio + PDC_CTLSTAT);
667 tmp &= ~PDC_IRQ_DISABLE;
668 writel(tmp, mmio + PDC_CTLSTAT);
669 readl(mmio + PDC_CTLSTAT); /* flush */
670}
671
724114a5 672static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
25b93d81 673{
25b93d81
MP		 674 if (!(ap->pflags & ATA_PFLAG_FROZEN))
675 pdc_reset_port(ap);
676
25b93d81 677 /* perform recovery */
e2a9752a 678 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
25b93d81
MP		 679 ata_std_postreset);
680}
681
724114a5
MP		 682static void pdc_pata_error_handler(struct ata_port *ap)
683{
684 pdc_common_error_handler(ap, NULL);
685}
686
687static void pdc_sata_error_handler(struct ata_port *ap)
688{
689 pdc_common_error_handler(ap, sata_std_hardreset);
690}
691
25b93d81
MP		 692static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
693{
694 struct ata_port *ap = qc->ap;
695
25b93d81 696 /* make DMA engine forget about the failed command */
a51d644a 697 if (qc->flags & ATA_QCFLAG_FAILED)
25b93d81
MP		 698 pdc_reset_port(ap);
699}
700
176efb05
MP		 701static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
702 u32 port_status, u32 err_mask)
703{
9af5c9c9 704 struct ata_eh_info *ehi = &ap->link.eh_info;
176efb05
MP		 705 unsigned int ac_err_mask = 0;
706
707 ata_ehi_clear_desc(ehi);
708 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
709 port_status &= err_mask;
710
711 if (port_status & PDC_DRIVE_ERR)
712 ac_err_mask |= AC_ERR_DEV;
713 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
714 ac_err_mask |= AC_ERR_HSM;
715 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
716 ac_err_mask |= AC_ERR_ATA_BUS;
717 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
718 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
719 ac_err_mask |= AC_ERR_HOST_BUS;
720
936fd732 721 if (sata_scr_valid(&ap->link)) {
da3dbb17
TH		 722 u32 serror;
723
724 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
725 ehi->serror |= serror;
726 }
ce2d3abc 727
176efb05 728 qc->err_mask |= ac_err_mask;
ce2d3abc
MP		 729
730 pdc_reset_port(ap);
8ffcfd9d
MP		 731
732 ata_port_abort(ap);
176efb05
MP		 733}
734
d0e58031
MP		 735static inline unsigned int pdc_host_intr(struct ata_port *ap,
736 struct ata_queued_cmd *qc)
1da177e4 737{
a22e2eb0 738 unsigned int handled = 0;
176efb05 739 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
176efb05
MP		 740 u32 port_status, err_mask;
741
742 err_mask = PDC_ERR_MASK;
eca25dca 743 if (ap->flags & PDC_FLAG_GEN_II)
176efb05
MP		 744 err_mask &= ~PDC1_ERR_MASK;
745 else
746 err_mask &= ~PDC2_ERR_MASK;
747 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
748 if (unlikely(port_status & err_mask)) {
749 pdc_error_intr(ap, qc, port_status, err_mask);
750 return 1;
1da177e4
LT		 751 }
752
753 switch (qc->tf.protocol) {
754 case ATA_PROT_DMA:
755 case ATA_PROT_NODATA:
95006188 756 case ATA_PROT_ATAPI_DMA:
fba6edbd 757 case ATA_PROT_ATAPI_NODATA:
a22e2eb0
AL		 758 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
759 ata_qc_complete(qc);
1da177e4
LT		 760 handled = 1;
761 break;
762
d0e58031 763 default:
ee500aab
AL		 764 ap->stats.idle_irq++;
765 break;
d0e58031 766 }
1da177e4 767
ee500aab 768 return handled;
1da177e4
LT		 769}
770
771static void pdc_irq_clear(struct ata_port *ap)
772{
cca3974e 773 struct ata_host *host = ap->host;
0d5ff566 774 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 775
776 readl(mmio + PDC_INT_SEQMASK);
777}
778
5796d1c4 779static int pdc_is_sataii_tx4(unsigned long flags)
d0e58031
MP		 780{
781 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
782 return (flags & mask) == mask;
783}
784
5796d1c4
JG		 785static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
786 int is_sataii_tx4)
d0e58031
MP		 787{
788 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
789 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
790}
791
5796d1c4 792static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
1da177e4 793{
cca3974e 794 struct ata_host *host = dev_instance;
1da177e4
LT		 795 struct ata_port *ap;
796 u32 mask = 0;
797 unsigned int i, tmp;
798 unsigned int handled = 0;
ea6ba10b 799 void __iomem *mmio_base;
a77720ad
MP		 800 unsigned int hotplug_offset, ata_no;
801 u32 hotplug_status;
802 int is_sataii_tx4;
1da177e4
LT		 803
804 VPRINTK("ENTER\n");
805
0d5ff566 806 if (!host || !host->iomap[PDC_MMIO_BAR]) {
1da177e4
LT		 807 VPRINTK("QUICK EXIT\n");
808 return IRQ_NONE;
809 }
810
0d5ff566 811 mmio_base = host->iomap[PDC_MMIO_BAR];
1da177e4 812
a77720ad
MP		 813 /* read and clear hotplug flags for all ports */
814 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
815 hotplug_offset = PDC2_SATA_PLUG_CSR;
816 else
817 hotplug_offset = PDC_SATA_PLUG_CSR;
818 hotplug_status = readl(mmio_base + hotplug_offset);
819 if (hotplug_status & 0xff)
820 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
821 hotplug_status &= 0xff; /* clear uninteresting bits */
822
1da177e4
LT		 823 /* reading should also clear interrupts */
824 mask = readl(mmio_base + PDC_INT_SEQMASK);
825
a77720ad 826 if (mask == 0xffffffff && hotplug_status == 0) {
1da177e4
LT		 827 VPRINTK("QUICK EXIT 2\n");
828 return IRQ_NONE;
829 }
6340f019 830
cca3974e 831 spin_lock(&host->lock);
6340f019 832
1da177e4 833 mask &= 0xffff; /* only 16 tags possible */
a77720ad 834 if (mask == 0 && hotplug_status == 0) {
1da177e4 835 VPRINTK("QUICK EXIT 3\n");
6340f019 836 goto done_irq;
1da177e4
LT		 837 }
838
1da177e4
LT		 839 writel(mask, mmio_base + PDC_INT_SEQMASK);
840
a77720ad
MP		 841 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
842
cca3974e 843 for (i = 0; i < host->n_ports; i++) {
1da177e4 844 VPRINTK("port %u\n", i);
cca3974e 845 ap = host->ports[i];
a77720ad
MP		 846
847 /* check for a plug or unplug event */
848 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
849 tmp = hotplug_status & (0x11 << ata_no);
850 if (tmp && ap &&
851 !(ap->flags & ATA_FLAG_DISABLED)) {
9af5c9c9 852 struct ata_eh_info *ehi = &ap->link.eh_info;
a77720ad
MP		 853 ata_ehi_clear_desc(ehi);
854 ata_ehi_hotplugged(ehi);
855 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
856 ata_port_freeze(ap);
857 ++handled;
858 continue;
859 }
860
861 /* check for a packet interrupt */
1da177e4 862 tmp = mask & (1 << (i + 1));
c1389503 863 if (tmp && ap &&
029f5468 864 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 865 struct ata_queued_cmd *qc;
866
9af5c9c9 867 qc = ata_qc_from_tag(ap, ap->link.active_tag);
e50362ec 868 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4
LT		 869 handled += pdc_host_intr(ap, qc);
870 }
871 }
872
1da177e4
LT		 873 VPRINTK("EXIT\n");
874
6340f019 875done_irq:
cca3974e 876 spin_unlock(&host->lock);
1da177e4
LT		 877 return IRQ_RETVAL(handled);
878}
879
880static inline void pdc_packet_start(struct ata_queued_cmd *qc)
881{
882 struct ata_port *ap = qc->ap;
883 struct pdc_port_priv *pp = ap->private_data;
0d5ff566 884 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 885 unsigned int port_no = ap->port_no;
886 u8 seq = (u8) (port_no + 1);
887
888 VPRINTK("ENTER, ap %p\n", ap);
889
0d5ff566
TH		 890 writel(0x00000001, mmio + (seq * 4));
891 readl(mmio + (seq * 4)); /* flush */
1da177e4
LT		 892
893 pp->pkt[2] = seq;
894 wmb(); /* flush PRD, pkt writes */
0d5ff566
TH		 895 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
896 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
1da177e4
LT		 897}
898
9a3d9eb0 899static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 900{
901 switch (qc->tf.protocol) {
fba6edbd
MP		 902 case ATA_PROT_ATAPI_NODATA:
903 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
904 break;
905 /*FALLTHROUGH*/
51b94d2a
TH		 906 case ATA_PROT_NODATA:
907 if (qc->tf.flags & ATA_TFLAG_POLLING)
908 break;
909 /*FALLTHROUGH*/
95006188 910 case ATA_PROT_ATAPI_DMA:
1da177e4 911 case ATA_PROT_DMA:
1da177e4
LT		 912 pdc_packet_start(qc);
913 return 0;
914
1da177e4
LT		 915 default:
916 break;
917 }
918
919 return ata_qc_issue_prot(qc);
920}
921
057ace5e 922static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4 923{
5796d1c4
JG		 924 WARN_ON(tf->protocol == ATA_PROT_DMA ||
925 tf->protocol == ATA_PROT_ATAPI_DMA);
1da177e4
LT		 926 ata_tf_load(ap, tf);
927}
928
5796d1c4
JG		 929static void pdc_exec_command_mmio(struct ata_port *ap,
930 const struct ata_taskfile *tf)
1da177e4 931{
5796d1c4
JG		 932 WARN_ON(tf->protocol == ATA_PROT_DMA ||
933 tf->protocol == ATA_PROT_ATAPI_DMA);
1da177e4
LT		 934 ata_exec_command(ap, tf);
935}
936
95006188
MP		 937static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
938{
939 u8 *scsicmd = qc->scsicmd->cmnd;
940 int pio = 1; /* atapi dma off by default */
941
942 /* Whitelist commands that may use DMA. */
943 switch (scsicmd[0]) {
944 case WRITE_12:
945 case WRITE_10:
946 case WRITE_6:
947 case READ_12:
948 case READ_10:
949 case READ_6:
950 case 0xad: /* READ_DVD_STRUCTURE */
951 case 0xbe: /* READ_CD */
952 pio = 0;
953 }
954 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
955 if (scsicmd[0] == WRITE_10) {
5796d1c4
JG		 956 unsigned int lba =
957 (scsicmd[2] << 24) |
958 (scsicmd[3] << 16) |
959 (scsicmd[4] << 8) |
960 scsicmd[5];
95006188
MP		 961 if (lba >= 0xFFFF4FA2)
962 pio = 1;
963 }
964 return pio;
965}
966
724114a5 967static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
95006188 968{
95006188 969 /* First generation chips cannot use ATAPI DMA on SATA ports */
724114a5 970 return 1;
95006188 971}
1da177e4 972
eca25dca
TH		 973static void pdc_ata_setup_port(struct ata_port *ap,
974 void __iomem *base, void __iomem *scr_addr)
1da177e4 975{
eca25dca
TH		 976 ap->ioaddr.cmd_addr = base;
977 ap->ioaddr.data_addr = base;
978 ap->ioaddr.feature_addr =
979 ap->ioaddr.error_addr = base + 0x4;
980 ap->ioaddr.nsect_addr = base + 0x8;
981 ap->ioaddr.lbal_addr = base + 0xc;
982 ap->ioaddr.lbam_addr = base + 0x10;
983 ap->ioaddr.lbah_addr = base + 0x14;
984 ap->ioaddr.device_addr = base + 0x18;
985 ap->ioaddr.command_addr =
986 ap->ioaddr.status_addr = base + 0x1c;
987 ap->ioaddr.altstatus_addr =
988 ap->ioaddr.ctl_addr = base + 0x38;
989 ap->ioaddr.scr_addr = scr_addr;
1da177e4
LT		 990}
991
eca25dca 992static void pdc_host_init(struct ata_host *host)
1da177e4 993{
eca25dca
TH		 994 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
995 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
d324d462 996 int hotplug_offset;
1da177e4
LT		 997 u32 tmp;
998
eca25dca 999 if (is_gen2)
d324d462
MP		 1000 hotplug_offset = PDC2_SATA_PLUG_CSR;
1001 else
1002 hotplug_offset = PDC_SATA_PLUG_CSR;
1003
1da177e4
LT		 1004 /*
1005 * Except for the hotplug stuff, this is voodoo from the
1006 * Promise driver. Label this entire section
1007 * "TODO: figure out why we do this"
1008 */
1009
b2d1eee1 1010 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1da177e4 1011 tmp = readl(mmio + PDC_FLASH_CTL);
b2d1eee1 1012 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
eca25dca 1013 if (!is_gen2)
b2d1eee1 1014 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1da177e4
LT		 1015 writel(tmp, mmio + PDC_FLASH_CTL);
1016
1017 /* clear plug/unplug flags for all ports */
6340f019
LK		 1018 tmp = readl(mmio + hotplug_offset);
1019 writel(tmp | 0xff, mmio + hotplug_offset);
1da177e4 1020
a77720ad 1021 /* unmask plug/unplug ints */
6340f019 1022 tmp = readl(mmio + hotplug_offset);
a77720ad 1023 writel(tmp & ~0xff0000, mmio + hotplug_offset);
1da177e4 1024
b2d1eee1 1025 /* don't initialise TBG or SLEW on 2nd generation chips */
eca25dca 1026 if (is_gen2)
b2d1eee1
MP		 1027 return;
1028
1da177e4
LT		 1029 /* reduce TBG clock to 133 Mhz. */
1030 tmp = readl(mmio + PDC_TBG_MODE);
1031 tmp &= ~0x30000; /* clear bit 17, 16*/
1032 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1033 writel(tmp, mmio + PDC_TBG_MODE);
1034
1035 readl(mmio + PDC_TBG_MODE); /* flush */
1036 msleep(10);
1037
1038 /* adjust slew rate control register. */
1039 tmp = readl(mmio + PDC_SLEW_CTL);
1040 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1041 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1042 writel(tmp, mmio + PDC_SLEW_CTL);
1043}
1044
5796d1c4
JG		 1045static int pdc_ata_init_one(struct pci_dev *pdev,
1046 const struct pci_device_id *ent)
1da177e4
LT		 1047{
1048 static int printed_version;
eca25dca
TH		 1049 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1050 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1051 struct ata_host *host;
0d5ff566 1052 void __iomem *base;
eca25dca 1053 int n_ports, i, rc;
5ac2fe57 1054 int is_sataii_tx4;
1da177e4
LT		 1055
1056 if (!printed_version++)
a9524a76 1057 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1058
eca25dca 1059 /* enable and acquire resources */
24dc5f33 1060 rc = pcim_enable_device(pdev);
1da177e4
LT		 1061 if (rc)
1062 return rc;
1063
0d5ff566
TH		 1064 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1065 if (rc == -EBUSY)
24dc5f33 1066 pcim_pin_device(pdev);
0d5ff566 1067 if (rc)
24dc5f33 1068 return rc;
eca25dca 1069 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1da177e4 1070
eca25dca
TH		 1071 /* determine port configuration and setup host */
1072 n_ports = 2;
1073 if (pi->flags & PDC_FLAG_4_PORTS)
1074 n_ports = 4;
1075 for (i = 0; i < n_ports; i++)
1076 ppi[i] = pi;
1da177e4 1077
eca25dca
TH		 1078 if (pi->flags & PDC_FLAG_SATA_PATA) {
1079 u8 tmp = readb(base + PDC_FLASH_CTL+1);
d0e58031 1080 if (!(tmp & 0x80))
eca25dca 1081 ppi[n_ports++] = pi + 1;
eca25dca 1082 }
1da177e4 1083
eca25dca
TH		 1084 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1085 if (!host) {
1086 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
24dc5f33 1087 return -ENOMEM;
1da177e4 1088 }
eca25dca 1089 host->iomap = pcim_iomap_table(pdev);
1da177e4 1090
d0e58031 1091 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
5ac2fe57 1092 for (i = 0; i < host->n_ports; i++) {
cbcdd875 1093 struct ata_port *ap = host->ports[i];
d0e58031 1094 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
cbcdd875
TH		 1095 unsigned int port_offset = 0x200 + ata_no * 0x80;
1096 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1097
1098 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1099
1100 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1101 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
5ac2fe57 1102 }
1da177e4
LT		 1103
1104 /* initialize adapter */
eca25dca 1105 pdc_host_init(host);
1da177e4 1106
eca25dca
TH		 1107 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1108 if (rc)
1109 return rc;
1110 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1111 if (rc)
1112 return rc;
1da177e4 1113
eca25dca
TH		 1114 /* start host, request IRQ and attach */
1115 pci_set_master(pdev);
1116 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1117 &pdc_ata_sht);
1da177e4
LT		 1118}
1119
1da177e4
LT		 1120static int __init pdc_ata_init(void)
1121{
b7887196 1122 return pci_register_driver(&pdc_ata_pci_driver);
1da177e4
LT		 1123}
1124
1da177e4
LT		 1125static void __exit pdc_ata_exit(void)
1126{
1127 pci_unregister_driver(&pdc_ata_pci_driver);
1128}
1129
1da177e4 1130MODULE_AUTHOR("Jeff Garzik");
f497ba73 1131MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1da177e4
LT		 1132MODULE_LICENSE("GPL");
1133MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1134MODULE_VERSION(DRV_VERSION);
1135
1136module_init(pdc_ata_init);
1137module_exit(pdc_ata_exit);
Linux kernel - Deliverables
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