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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
95006188 | 41 | #include <scsi/scsi.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 44 | #include <linux/libata.h> |
1da177e4 LT |
45 | #include "sata_promise.h" |
46 | ||
47 | #define DRV_NAME "sata_promise" | |
a77720ad | 48 | #define DRV_VERSION "2.09" |
1da177e4 LT |
49 | |
50 | enum { | |
eca25dca | 51 | PDC_MAX_PORTS = 4, |
0d5ff566 TH |
52 | PDC_MMIO_BAR = 3, |
53 | ||
95006188 MP |
54 | /* register offsets */ |
55 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
56 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
57 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
58 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
59 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
60 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
61 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 62 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 LT |
63 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
64 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 65 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
66 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
67 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
68 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 69 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
70 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
71 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 | 72 | |
176efb05 MP |
73 | /* PDC_GLOBAL_CTL bit definitions */ |
74 | PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ | |
75 | PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ | |
76 | PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ | |
77 | PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ | |
78 | PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ | |
79 | PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ | |
80 | PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ | |
81 | PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ | |
82 | PDC_DRIVE_ERR = (1 << 21), /* drive error */ | |
83 | PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ | |
84 | PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ | |
85 | PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, | |
86 | PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR, | |
87 | PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR | |
88 | | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | |
89 | | PDC1_ERR_MASK | PDC2_ERR_MASK), | |
1da177e4 LT |
90 | |
91 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
eca25dca TH |
92 | board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ |
93 | board_20319 = 2, /* FastTrak S150 TX4 */ | |
94 | board_20619 = 3, /* FastTrak TX4000 */ | |
95 | board_2057x = 4, /* SATAII150 Tx2plus */ | |
d0e58031 | 96 | board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ |
eca25dca | 97 | board_40518 = 6, /* SATAII150 Tx4 */ |
1da177e4 | 98 | |
6340f019 | 99 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 100 | |
95006188 MP |
101 | /* Sequence counter control registers bit definitions */ |
102 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
103 | ||
104 | /* Feature register values */ | |
105 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
106 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
107 | ||
108 | /* Device/Head register values */ | |
109 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
110 | ||
25b93d81 MP |
111 | /* PDC_CTLSTAT bit definitions */ |
112 | PDC_DMA_ENABLE = (1 << 7), | |
113 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 114 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 115 | |
25b93d81 | 116 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 117 | ATA_FLAG_MMIO | |
3d0a59c0 | 118 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 | 119 | |
eca25dca TH |
120 | /* ap->flags bits */ |
121 | PDC_FLAG_GEN_II = (1 << 24), | |
122 | PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ | |
123 | PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ | |
1da177e4 LT |
124 | }; |
125 | ||
1da177e4 LT |
126 | struct pdc_port_priv { |
127 | u8 *pkt; | |
128 | dma_addr_t pkt_dma; | |
129 | }; | |
130 | ||
da3dbb17 TH |
131 | static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
132 | static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 133 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
eca25dca TH |
134 | static int pdc_common_port_start(struct ata_port *ap); |
135 | static int pdc_sata_port_start(struct ata_port *ap); | |
1da177e4 | 136 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
137 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
138 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 | 139 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
724114a5 | 140 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); |
1da177e4 | 141 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 142 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
25b93d81 MP |
143 | static void pdc_freeze(struct ata_port *ap); |
144 | static void pdc_thaw(struct ata_port *ap); | |
724114a5 MP |
145 | static void pdc_pata_error_handler(struct ata_port *ap); |
146 | static void pdc_sata_error_handler(struct ata_port *ap); | |
25b93d81 | 147 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); |
724114a5 MP |
148 | static int pdc_pata_cable_detect(struct ata_port *ap); |
149 | static int pdc_sata_cable_detect(struct ata_port *ap); | |
374b1873 | 150 | |
193515d5 | 151 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
152 | .module = THIS_MODULE, |
153 | .name = DRV_NAME, | |
154 | .ioctl = ata_scsi_ioctl, | |
155 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
156 | .can_queue = ATA_DEF_QUEUE, |
157 | .this_id = ATA_SHT_THIS_ID, | |
158 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
159 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
160 | .emulated = ATA_SHT_EMULATED, | |
161 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
162 | .proc_name = DRV_NAME, | |
163 | .dma_boundary = ATA_DMA_BOUNDARY, | |
164 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 165 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 166 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
167 | }; |
168 | ||
057ace5e | 169 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
170 | .port_disable = ata_port_disable, |
171 | .tf_load = pdc_tf_load_mmio, | |
172 | .tf_read = ata_tf_read, | |
173 | .check_status = ata_check_status, | |
174 | .exec_command = pdc_exec_command_mmio, | |
175 | .dev_select = ata_std_dev_select, | |
95006188 MP |
176 | .check_atapi_dma = pdc_check_atapi_dma, |
177 | ||
178 | .qc_prep = pdc_qc_prep, | |
179 | .qc_issue = pdc_qc_issue_prot, | |
180 | .freeze = pdc_freeze, | |
181 | .thaw = pdc_thaw, | |
724114a5 | 182 | .error_handler = pdc_sata_error_handler, |
95006188 | 183 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 184 | .cable_detect = pdc_sata_cable_detect, |
0d5ff566 | 185 | .data_xfer = ata_data_xfer, |
95006188 | 186 | .irq_clear = pdc_irq_clear, |
246ce3b6 AI |
187 | .irq_on = ata_irq_on, |
188 | .irq_ack = ata_irq_ack, | |
95006188 MP |
189 | |
190 | .scr_read = pdc_sata_scr_read, | |
191 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 192 | .port_start = pdc_sata_port_start, |
95006188 MP |
193 | }; |
194 | ||
195 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
196 | static const struct ata_port_operations pdc_old_sata_ops = { | |
197 | .port_disable = ata_port_disable, | |
198 | .tf_load = pdc_tf_load_mmio, | |
199 | .tf_read = ata_tf_read, | |
200 | .check_status = ata_check_status, | |
201 | .exec_command = pdc_exec_command_mmio, | |
202 | .dev_select = ata_std_dev_select, | |
724114a5 | 203 | .check_atapi_dma = pdc_old_sata_check_atapi_dma, |
2cba582a | 204 | |
1da177e4 LT |
205 | .qc_prep = pdc_qc_prep, |
206 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
207 | .freeze = pdc_freeze, |
208 | .thaw = pdc_thaw, | |
724114a5 | 209 | .error_handler = pdc_sata_error_handler, |
25b93d81 | 210 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 211 | .cable_detect = pdc_sata_cable_detect, |
0d5ff566 | 212 | .data_xfer = ata_data_xfer, |
1da177e4 | 213 | .irq_clear = pdc_irq_clear, |
246ce3b6 AI |
214 | .irq_on = ata_irq_on, |
215 | .irq_ack = ata_irq_ack, | |
2cba582a | 216 | |
1da177e4 LT |
217 | .scr_read = pdc_sata_scr_read, |
218 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 219 | .port_start = pdc_sata_port_start, |
1da177e4 LT |
220 | }; |
221 | ||
057ace5e | 222 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
223 | .port_disable = ata_port_disable, |
224 | .tf_load = pdc_tf_load_mmio, | |
225 | .tf_read = ata_tf_read, | |
226 | .check_status = ata_check_status, | |
227 | .exec_command = pdc_exec_command_mmio, | |
228 | .dev_select = ata_std_dev_select, | |
95006188 | 229 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a | 230 | |
2cba582a JG |
231 | .qc_prep = pdc_qc_prep, |
232 | .qc_issue = pdc_qc_issue_prot, | |
5387373b MP |
233 | .freeze = pdc_freeze, |
234 | .thaw = pdc_thaw, | |
724114a5 | 235 | .error_handler = pdc_pata_error_handler, |
540477b4 | 236 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 237 | .cable_detect = pdc_pata_cable_detect, |
0d5ff566 | 238 | .data_xfer = ata_data_xfer, |
2cba582a | 239 | .irq_clear = pdc_irq_clear, |
246ce3b6 AI |
240 | .irq_on = ata_irq_on, |
241 | .irq_ack = ata_irq_ack, | |
2cba582a | 242 | |
eca25dca | 243 | .port_start = pdc_common_port_start, |
2cba582a JG |
244 | }; |
245 | ||
98ac62de | 246 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
247 | /* board_2037x */ |
248 | { | |
eca25dca TH |
249 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
250 | PDC_FLAG_SATA_PATA, | |
1da177e4 LT |
251 | .pio_mask = 0x1f, /* pio0-4 */ |
252 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 253 | .udma_mask = ATA_UDMA6, |
95006188 | 254 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
255 | }, |
256 | ||
eca25dca TH |
257 | /* board_2037x_pata */ |
258 | { | |
259 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, | |
260 | .pio_mask = 0x1f, /* pio0-4 */ | |
261 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 262 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
263 | .port_ops = &pdc_pata_ops, |
264 | }, | |
265 | ||
1da177e4 LT |
266 | /* board_20319 */ |
267 | { | |
eca25dca TH |
268 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
269 | PDC_FLAG_4_PORTS, | |
1da177e4 LT |
270 | .pio_mask = 0x1f, /* pio0-4 */ |
271 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 272 | .udma_mask = ATA_UDMA6, |
95006188 | 273 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 274 | }, |
f497ba73 TL |
275 | |
276 | /* board_20619 */ | |
277 | { | |
eca25dca TH |
278 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
279 | PDC_FLAG_4_PORTS, | |
f497ba73 TL |
280 | .pio_mask = 0x1f, /* pio0-4 */ |
281 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 282 | .udma_mask = ATA_UDMA6, |
2cba582a | 283 | .port_ops = &pdc_pata_ops, |
f497ba73 | 284 | }, |
5a46fe89 | 285 | |
6340f019 LK |
286 | /* board_2057x */ |
287 | { | |
eca25dca TH |
288 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
289 | PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, | |
6340f019 LK |
290 | .pio_mask = 0x1f, /* pio0-4 */ |
291 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 292 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
293 | .port_ops = &pdc_sata_ops, |
294 | }, | |
295 | ||
eca25dca TH |
296 | /* board_2057x_pata */ |
297 | { | |
bb312235 | 298 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
eca25dca TH |
299 | PDC_FLAG_GEN_II, |
300 | .pio_mask = 0x1f, /* pio0-4 */ | |
301 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 302 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
303 | .port_ops = &pdc_pata_ops, |
304 | }, | |
305 | ||
6340f019 LK |
306 | /* board_40518 */ |
307 | { | |
eca25dca TH |
308 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
309 | PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, | |
6340f019 LK |
310 | .pio_mask = 0x1f, /* pio0-4 */ |
311 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 312 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
313 | .port_ops = &pdc_sata_ops, |
314 | }, | |
1da177e4 LT |
315 | }; |
316 | ||
3b7d697d | 317 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 318 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
319 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
320 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
321 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
322 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
323 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 324 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 325 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 326 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 327 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
328 | |
329 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
330 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
331 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
332 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
b2d1eee1 | 333 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
334 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
335 | ||
336 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 337 | |
1da177e4 LT |
338 | { } /* terminate list */ |
339 | }; | |
340 | ||
1da177e4 LT |
341 | static struct pci_driver pdc_ata_pci_driver = { |
342 | .name = DRV_NAME, | |
343 | .id_table = pdc_ata_pci_tbl, | |
344 | .probe = pdc_ata_init_one, | |
345 | .remove = ata_pci_remove_one, | |
346 | }; | |
347 | ||
724114a5 | 348 | static int pdc_common_port_start(struct ata_port *ap) |
1da177e4 | 349 | { |
cca3974e | 350 | struct device *dev = ap->host->dev; |
1da177e4 LT |
351 | struct pdc_port_priv *pp; |
352 | int rc; | |
353 | ||
354 | rc = ata_port_start(ap); | |
355 | if (rc) | |
356 | return rc; | |
357 | ||
24dc5f33 TH |
358 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
359 | if (!pp) | |
360 | return -ENOMEM; | |
1da177e4 | 361 | |
24dc5f33 TH |
362 | pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); |
363 | if (!pp->pkt) | |
364 | return -ENOMEM; | |
1da177e4 LT |
365 | |
366 | ap->private_data = pp; | |
367 | ||
724114a5 MP |
368 | return 0; |
369 | } | |
370 | ||
371 | static int pdc_sata_port_start(struct ata_port *ap) | |
372 | { | |
724114a5 MP |
373 | int rc; |
374 | ||
375 | rc = pdc_common_port_start(ap); | |
376 | if (rc) | |
377 | return rc; | |
378 | ||
599b7202 | 379 | /* fix up PHYMODE4 align timing */ |
eca25dca | 380 | if (ap->flags & PDC_FLAG_GEN_II) { |
59f99880 | 381 | void __iomem *mmio = ap->ioaddr.scr_addr; |
599b7202 MP |
382 | unsigned int tmp; |
383 | ||
384 | tmp = readl(mmio + 0x014); | |
385 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
386 | writel(tmp, mmio + 0x014); | |
387 | } | |
388 | ||
1da177e4 | 389 | return 0; |
1da177e4 LT |
390 | } |
391 | ||
1da177e4 LT |
392 | static void pdc_reset_port(struct ata_port *ap) |
393 | { | |
0d5ff566 | 394 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
395 | unsigned int i; |
396 | u32 tmp; | |
397 | ||
398 | for (i = 11; i > 0; i--) { | |
399 | tmp = readl(mmio); | |
400 | if (tmp & PDC_RESET) | |
401 | break; | |
402 | ||
403 | udelay(100); | |
404 | ||
405 | tmp |= PDC_RESET; | |
406 | writel(tmp, mmio); | |
407 | } | |
408 | ||
409 | tmp &= ~PDC_RESET; | |
410 | writel(tmp, mmio); | |
411 | readl(mmio); /* flush */ | |
412 | } | |
413 | ||
724114a5 | 414 | static int pdc_pata_cable_detect(struct ata_port *ap) |
2cba582a | 415 | { |
d3fb4e8d | 416 | u8 tmp; |
59f99880 | 417 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d | 418 | |
724114a5 MP |
419 | tmp = readb(mmio); |
420 | if (tmp & 0x01) | |
421 | return ATA_CBL_PATA40; | |
422 | return ATA_CBL_PATA80; | |
423 | } | |
424 | ||
425 | static int pdc_sata_cable_detect(struct ata_port *ap) | |
426 | { | |
e2a9752a | 427 | return ATA_CBL_SATA; |
d3fb4e8d | 428 | } |
2cba582a | 429 | |
da3dbb17 | 430 | static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 431 | { |
724114a5 | 432 | if (sc_reg > SCR_CONTROL) |
da3dbb17 TH |
433 | return -EINVAL; |
434 | *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
435 | return 0; | |
1da177e4 LT |
436 | } |
437 | ||
da3dbb17 | 438 | static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 439 | { |
724114a5 | 440 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 441 | return -EINVAL; |
0d5ff566 | 442 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 443 | return 0; |
1da177e4 LT |
444 | } |
445 | ||
fba6edbd | 446 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 447 | { |
4113bb6b MP |
448 | struct ata_port *ap = qc->ap; |
449 | dma_addr_t sg_table = ap->prd_dma; | |
450 | unsigned int cdb_len = qc->dev->cdb_len; | |
451 | u8 *cdb = qc->cdb; | |
452 | struct pdc_port_priv *pp = ap->private_data; | |
453 | u8 *buf = pp->pkt; | |
95006188 | 454 | u32 *buf32 = (u32 *) buf; |
4113bb6b | 455 | unsigned int dev_sel, feature, nbytes; |
95006188 MP |
456 | |
457 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
458 | * and seq id (byte 2) | |
459 | */ | |
fba6edbd MP |
460 | switch (qc->tf.protocol) { |
461 | case ATA_PROT_ATAPI_DMA: | |
462 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
463 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
464 | else | |
465 | buf32[0] = 0; | |
466 | break; | |
467 | case ATA_PROT_ATAPI_NODATA: | |
468 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); | |
469 | break; | |
470 | default: | |
471 | BUG(); | |
472 | break; | |
473 | } | |
95006188 MP |
474 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
475 | buf32[2] = 0; /* no next-packet */ | |
476 | ||
4113bb6b MP |
477 | /* select drive */ |
478 | if (sata_scr_valid(ap)) { | |
479 | dev_sel = PDC_DEVICE_SATA; | |
480 | } else { | |
481 | dev_sel = ATA_DEVICE_OBS; | |
482 | if (qc->dev->devno != 0) | |
483 | dev_sel |= ATA_DEV1; | |
484 | } | |
485 | buf[12] = (1 << 5) | ATA_REG_DEVICE; | |
486 | buf[13] = dev_sel; | |
487 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
488 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
489 | ||
490 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
491 | buf[17] = 0x00; | |
492 | buf[18] = (1 << 5) | ATA_REG_LBAL; | |
493 | buf[19] = 0x00; | |
494 | ||
495 | /* set feature and byte counter registers */ | |
496 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { | |
497 | feature = PDC_FEATURE_ATAPI_PIO; | |
498 | /* set byte counter register to real transfer byte count */ | |
499 | nbytes = qc->nbytes; | |
4113bb6b MP |
500 | if (nbytes > 0xffff) |
501 | nbytes = 0xffff; | |
502 | } else { | |
503 | feature = PDC_FEATURE_ATAPI_DMA; | |
504 | /* set byte counter register to 0 */ | |
505 | nbytes = 0; | |
506 | } | |
507 | buf[20] = (1 << 5) | ATA_REG_FEATURE; | |
508 | buf[21] = feature; | |
509 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
510 | buf[23] = nbytes & 0xFF; | |
511 | buf[24] = (1 << 5) | ATA_REG_BYTEH; | |
512 | buf[25] = (nbytes >> 8) & 0xFF; | |
513 | ||
514 | /* send ATAPI packet command 0xA0 */ | |
515 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
516 | buf[27] = ATA_CMD_PACKET; | |
517 | ||
518 | /* select drive and check DRQ */ | |
519 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
520 | buf[29] = dev_sel; | |
521 | ||
95006188 MP |
522 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
523 | BUG_ON(cdb_len & ~0x1E); | |
524 | ||
4113bb6b MP |
525 | /* append the CDB as the final part */ |
526 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
527 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
528 | } |
529 | ||
1da177e4 LT |
530 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
531 | { | |
532 | struct pdc_port_priv *pp = qc->ap->private_data; | |
533 | unsigned int i; | |
534 | ||
535 | VPRINTK("ENTER\n"); | |
536 | ||
537 | switch (qc->tf.protocol) { | |
538 | case ATA_PROT_DMA: | |
539 | ata_qc_prep(qc); | |
540 | /* fall through */ | |
541 | ||
542 | case ATA_PROT_NODATA: | |
543 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
544 | qc->dev->devno, pp->pkt); | |
545 | ||
546 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
547 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
548 | else | |
549 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
550 | ||
551 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
552 | break; | |
553 | ||
95006188 | 554 | case ATA_PROT_ATAPI: |
95006188 MP |
555 | ata_qc_prep(qc); |
556 | break; | |
557 | ||
558 | case ATA_PROT_ATAPI_DMA: | |
559 | ata_qc_prep(qc); | |
fba6edbd MP |
560 | /*FALLTHROUGH*/ |
561 | case ATA_PROT_ATAPI_NODATA: | |
562 | pdc_atapi_pkt(qc); | |
95006188 MP |
563 | break; |
564 | ||
1da177e4 LT |
565 | default: |
566 | break; | |
567 | } | |
568 | } | |
569 | ||
25b93d81 MP |
570 | static void pdc_freeze(struct ata_port *ap) |
571 | { | |
59f99880 | 572 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
573 | u32 tmp; |
574 | ||
575 | tmp = readl(mmio + PDC_CTLSTAT); | |
576 | tmp |= PDC_IRQ_DISABLE; | |
577 | tmp &= ~PDC_DMA_ENABLE; | |
578 | writel(tmp, mmio + PDC_CTLSTAT); | |
579 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
580 | } | |
581 | ||
582 | static void pdc_thaw(struct ata_port *ap) | |
583 | { | |
59f99880 | 584 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
585 | u32 tmp; |
586 | ||
587 | /* clear IRQ */ | |
588 | readl(mmio + PDC_INT_SEQMASK); | |
589 | ||
590 | /* turn IRQ back on */ | |
591 | tmp = readl(mmio + PDC_CTLSTAT); | |
592 | tmp &= ~PDC_IRQ_DISABLE; | |
593 | writel(tmp, mmio + PDC_CTLSTAT); | |
594 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
595 | } | |
596 | ||
724114a5 | 597 | static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset) |
25b93d81 | 598 | { |
25b93d81 MP |
599 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) |
600 | pdc_reset_port(ap); | |
601 | ||
25b93d81 | 602 | /* perform recovery */ |
e2a9752a | 603 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, |
25b93d81 MP |
604 | ata_std_postreset); |
605 | } | |
606 | ||
724114a5 MP |
607 | static void pdc_pata_error_handler(struct ata_port *ap) |
608 | { | |
609 | pdc_common_error_handler(ap, NULL); | |
610 | } | |
611 | ||
612 | static void pdc_sata_error_handler(struct ata_port *ap) | |
613 | { | |
614 | pdc_common_error_handler(ap, sata_std_hardreset); | |
615 | } | |
616 | ||
25b93d81 MP |
617 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) |
618 | { | |
619 | struct ata_port *ap = qc->ap; | |
620 | ||
25b93d81 | 621 | /* make DMA engine forget about the failed command */ |
a51d644a | 622 | if (qc->flags & ATA_QCFLAG_FAILED) |
25b93d81 MP |
623 | pdc_reset_port(ap); |
624 | } | |
625 | ||
176efb05 MP |
626 | static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, |
627 | u32 port_status, u32 err_mask) | |
628 | { | |
629 | struct ata_eh_info *ehi = &ap->eh_info; | |
630 | unsigned int ac_err_mask = 0; | |
631 | ||
632 | ata_ehi_clear_desc(ehi); | |
633 | ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); | |
634 | port_status &= err_mask; | |
635 | ||
636 | if (port_status & PDC_DRIVE_ERR) | |
637 | ac_err_mask |= AC_ERR_DEV; | |
638 | if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) | |
639 | ac_err_mask |= AC_ERR_HSM; | |
640 | if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) | |
641 | ac_err_mask |= AC_ERR_ATA_BUS; | |
642 | if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR | |
643 | | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) | |
644 | ac_err_mask |= AC_ERR_HOST_BUS; | |
645 | ||
da3dbb17 TH |
646 | if (sata_scr_valid(ap)) { |
647 | u32 serror; | |
648 | ||
649 | pdc_sata_scr_read(ap, SCR_ERROR, &serror); | |
650 | ehi->serror |= serror; | |
651 | } | |
ce2d3abc | 652 | |
176efb05 | 653 | qc->err_mask |= ac_err_mask; |
ce2d3abc MP |
654 | |
655 | pdc_reset_port(ap); | |
8ffcfd9d MP |
656 | |
657 | ata_port_abort(ap); | |
176efb05 MP |
658 | } |
659 | ||
d0e58031 MP |
660 | static inline unsigned int pdc_host_intr(struct ata_port *ap, |
661 | struct ata_queued_cmd *qc) | |
1da177e4 | 662 | { |
a22e2eb0 | 663 | unsigned int handled = 0; |
176efb05 | 664 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
176efb05 MP |
665 | u32 port_status, err_mask; |
666 | ||
667 | err_mask = PDC_ERR_MASK; | |
eca25dca | 668 | if (ap->flags & PDC_FLAG_GEN_II) |
176efb05 MP |
669 | err_mask &= ~PDC1_ERR_MASK; |
670 | else | |
671 | err_mask &= ~PDC2_ERR_MASK; | |
672 | port_status = readl(port_mmio + PDC_GLOBAL_CTL); | |
673 | if (unlikely(port_status & err_mask)) { | |
674 | pdc_error_intr(ap, qc, port_status, err_mask); | |
675 | return 1; | |
1da177e4 LT |
676 | } |
677 | ||
678 | switch (qc->tf.protocol) { | |
679 | case ATA_PROT_DMA: | |
680 | case ATA_PROT_NODATA: | |
95006188 | 681 | case ATA_PROT_ATAPI_DMA: |
fba6edbd | 682 | case ATA_PROT_ATAPI_NODATA: |
a22e2eb0 AL |
683 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
684 | ata_qc_complete(qc); | |
1da177e4 LT |
685 | handled = 1; |
686 | break; | |
687 | ||
d0e58031 | 688 | default: |
ee500aab AL |
689 | ap->stats.idle_irq++; |
690 | break; | |
d0e58031 | 691 | } |
1da177e4 | 692 | |
ee500aab | 693 | return handled; |
1da177e4 LT |
694 | } |
695 | ||
696 | static void pdc_irq_clear(struct ata_port *ap) | |
697 | { | |
cca3974e | 698 | struct ata_host *host = ap->host; |
0d5ff566 | 699 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
700 | |
701 | readl(mmio + PDC_INT_SEQMASK); | |
702 | } | |
703 | ||
d0e58031 MP |
704 | static inline int pdc_is_sataii_tx4(unsigned long flags) |
705 | { | |
706 | const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; | |
707 | return (flags & mask) == mask; | |
708 | } | |
709 | ||
710 | static inline unsigned int pdc_port_no_to_ata_no(unsigned int port_no, int is_sataii_tx4) | |
711 | { | |
712 | static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; | |
713 | return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; | |
714 | } | |
715 | ||
7d12e780 | 716 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 717 | { |
cca3974e | 718 | struct ata_host *host = dev_instance; |
1da177e4 LT |
719 | struct ata_port *ap; |
720 | u32 mask = 0; | |
721 | unsigned int i, tmp; | |
722 | unsigned int handled = 0; | |
ea6ba10b | 723 | void __iomem *mmio_base; |
a77720ad MP |
724 | unsigned int hotplug_offset, ata_no; |
725 | u32 hotplug_status; | |
726 | int is_sataii_tx4; | |
1da177e4 LT |
727 | |
728 | VPRINTK("ENTER\n"); | |
729 | ||
0d5ff566 | 730 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
1da177e4 LT |
731 | VPRINTK("QUICK EXIT\n"); |
732 | return IRQ_NONE; | |
733 | } | |
734 | ||
0d5ff566 | 735 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
1da177e4 | 736 | |
a77720ad MP |
737 | /* read and clear hotplug flags for all ports */ |
738 | if (host->ports[0]->flags & PDC_FLAG_GEN_II) | |
739 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
740 | else | |
741 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
742 | hotplug_status = readl(mmio_base + hotplug_offset); | |
743 | if (hotplug_status & 0xff) | |
744 | writel(hotplug_status | 0xff, mmio_base + hotplug_offset); | |
745 | hotplug_status &= 0xff; /* clear uninteresting bits */ | |
746 | ||
1da177e4 LT |
747 | /* reading should also clear interrupts */ |
748 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
749 | ||
a77720ad | 750 | if (mask == 0xffffffff && hotplug_status == 0) { |
1da177e4 LT |
751 | VPRINTK("QUICK EXIT 2\n"); |
752 | return IRQ_NONE; | |
753 | } | |
6340f019 | 754 | |
cca3974e | 755 | spin_lock(&host->lock); |
6340f019 | 756 | |
1da177e4 | 757 | mask &= 0xffff; /* only 16 tags possible */ |
a77720ad | 758 | if (mask == 0 && hotplug_status == 0) { |
1da177e4 | 759 | VPRINTK("QUICK EXIT 3\n"); |
6340f019 | 760 | goto done_irq; |
1da177e4 LT |
761 | } |
762 | ||
1da177e4 LT |
763 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
764 | ||
a77720ad MP |
765 | is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); |
766 | ||
cca3974e | 767 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 768 | VPRINTK("port %u\n", i); |
cca3974e | 769 | ap = host->ports[i]; |
a77720ad MP |
770 | |
771 | /* check for a plug or unplug event */ | |
772 | ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); | |
773 | tmp = hotplug_status & (0x11 << ata_no); | |
774 | if (tmp && ap && | |
775 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
776 | struct ata_eh_info *ehi = &ap->eh_info; | |
777 | ata_ehi_clear_desc(ehi); | |
778 | ata_ehi_hotplugged(ehi); | |
779 | ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); | |
780 | ata_port_freeze(ap); | |
781 | ++handled; | |
782 | continue; | |
783 | } | |
784 | ||
785 | /* check for a packet interrupt */ | |
1da177e4 | 786 | tmp = mask & (1 << (i + 1)); |
c1389503 | 787 | if (tmp && ap && |
029f5468 | 788 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
789 | struct ata_queued_cmd *qc; |
790 | ||
791 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 792 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
793 | handled += pdc_host_intr(ap, qc); |
794 | } | |
795 | } | |
796 | ||
1da177e4 LT |
797 | VPRINTK("EXIT\n"); |
798 | ||
6340f019 | 799 | done_irq: |
cca3974e | 800 | spin_unlock(&host->lock); |
1da177e4 LT |
801 | return IRQ_RETVAL(handled); |
802 | } | |
803 | ||
804 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
805 | { | |
806 | struct ata_port *ap = qc->ap; | |
807 | struct pdc_port_priv *pp = ap->private_data; | |
0d5ff566 | 808 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
809 | unsigned int port_no = ap->port_no; |
810 | u8 seq = (u8) (port_no + 1); | |
811 | ||
812 | VPRINTK("ENTER, ap %p\n", ap); | |
813 | ||
0d5ff566 TH |
814 | writel(0x00000001, mmio + (seq * 4)); |
815 | readl(mmio + (seq * 4)); /* flush */ | |
1da177e4 LT |
816 | |
817 | pp->pkt[2] = seq; | |
818 | wmb(); /* flush PRD, pkt writes */ | |
0d5ff566 TH |
819 | writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
820 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
821 | } |
822 | ||
9a3d9eb0 | 823 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
824 | { |
825 | switch (qc->tf.protocol) { | |
fba6edbd MP |
826 | case ATA_PROT_ATAPI_NODATA: |
827 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
828 | break; | |
829 | /*FALLTHROUGH*/ | |
51b94d2a TH |
830 | case ATA_PROT_NODATA: |
831 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
832 | break; | |
833 | /*FALLTHROUGH*/ | |
95006188 | 834 | case ATA_PROT_ATAPI_DMA: |
1da177e4 | 835 | case ATA_PROT_DMA: |
1da177e4 LT |
836 | pdc_packet_start(qc); |
837 | return 0; | |
838 | ||
1da177e4 LT |
839 | default: |
840 | break; | |
841 | } | |
842 | ||
843 | return ata_qc_issue_prot(qc); | |
844 | } | |
845 | ||
057ace5e | 846 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
847 | { |
848 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
51b94d2a | 849 | tf->protocol == ATA_PROT_ATAPI_DMA); |
1da177e4 LT |
850 | ata_tf_load(ap, tf); |
851 | } | |
852 | ||
057ace5e | 853 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
854 | { |
855 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
51b94d2a | 856 | tf->protocol == ATA_PROT_ATAPI_DMA); |
1da177e4 LT |
857 | ata_exec_command(ap, tf); |
858 | } | |
859 | ||
95006188 MP |
860 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
861 | { | |
862 | u8 *scsicmd = qc->scsicmd->cmnd; | |
863 | int pio = 1; /* atapi dma off by default */ | |
864 | ||
865 | /* Whitelist commands that may use DMA. */ | |
866 | switch (scsicmd[0]) { | |
867 | case WRITE_12: | |
868 | case WRITE_10: | |
869 | case WRITE_6: | |
870 | case READ_12: | |
871 | case READ_10: | |
872 | case READ_6: | |
873 | case 0xad: /* READ_DVD_STRUCTURE */ | |
874 | case 0xbe: /* READ_CD */ | |
875 | pio = 0; | |
876 | } | |
877 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
878 | if (scsicmd[0] == WRITE_10) { | |
879 | unsigned int lba; | |
880 | lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; | |
881 | if (lba >= 0xFFFF4FA2) | |
882 | pio = 1; | |
883 | } | |
884 | return pio; | |
885 | } | |
886 | ||
724114a5 | 887 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
95006188 | 888 | { |
95006188 | 889 | /* First generation chips cannot use ATAPI DMA on SATA ports */ |
724114a5 | 890 | return 1; |
95006188 | 891 | } |
1da177e4 | 892 | |
eca25dca TH |
893 | static void pdc_ata_setup_port(struct ata_port *ap, |
894 | void __iomem *base, void __iomem *scr_addr) | |
1da177e4 | 895 | { |
eca25dca TH |
896 | ap->ioaddr.cmd_addr = base; |
897 | ap->ioaddr.data_addr = base; | |
898 | ap->ioaddr.feature_addr = | |
899 | ap->ioaddr.error_addr = base + 0x4; | |
900 | ap->ioaddr.nsect_addr = base + 0x8; | |
901 | ap->ioaddr.lbal_addr = base + 0xc; | |
902 | ap->ioaddr.lbam_addr = base + 0x10; | |
903 | ap->ioaddr.lbah_addr = base + 0x14; | |
904 | ap->ioaddr.device_addr = base + 0x18; | |
905 | ap->ioaddr.command_addr = | |
906 | ap->ioaddr.status_addr = base + 0x1c; | |
907 | ap->ioaddr.altstatus_addr = | |
908 | ap->ioaddr.ctl_addr = base + 0x38; | |
909 | ap->ioaddr.scr_addr = scr_addr; | |
1da177e4 LT |
910 | } |
911 | ||
eca25dca | 912 | static void pdc_host_init(struct ata_host *host) |
1da177e4 | 913 | { |
eca25dca TH |
914 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
915 | int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; | |
d324d462 | 916 | int hotplug_offset; |
1da177e4 LT |
917 | u32 tmp; |
918 | ||
eca25dca | 919 | if (is_gen2) |
d324d462 MP |
920 | hotplug_offset = PDC2_SATA_PLUG_CSR; |
921 | else | |
922 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
923 | ||
1da177e4 LT |
924 | /* |
925 | * Except for the hotplug stuff, this is voodoo from the | |
926 | * Promise driver. Label this entire section | |
927 | * "TODO: figure out why we do this" | |
928 | */ | |
929 | ||
b2d1eee1 | 930 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 931 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 | 932 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
eca25dca | 933 | if (!is_gen2) |
b2d1eee1 | 934 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ |
1da177e4 LT |
935 | writel(tmp, mmio + PDC_FLASH_CTL); |
936 | ||
937 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
938 | tmp = readl(mmio + hotplug_offset); |
939 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 | 940 | |
a77720ad | 941 | /* unmask plug/unplug ints */ |
6340f019 | 942 | tmp = readl(mmio + hotplug_offset); |
a77720ad | 943 | writel(tmp & ~0xff0000, mmio + hotplug_offset); |
1da177e4 | 944 | |
b2d1eee1 | 945 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
eca25dca | 946 | if (is_gen2) |
b2d1eee1 MP |
947 | return; |
948 | ||
1da177e4 LT |
949 | /* reduce TBG clock to 133 Mhz. */ |
950 | tmp = readl(mmio + PDC_TBG_MODE); | |
951 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
952 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
953 | writel(tmp, mmio + PDC_TBG_MODE); | |
954 | ||
955 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
956 | msleep(10); | |
957 | ||
958 | /* adjust slew rate control register. */ | |
959 | tmp = readl(mmio + PDC_SLEW_CTL); | |
960 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
961 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
962 | writel(tmp, mmio + PDC_SLEW_CTL); | |
963 | } | |
964 | ||
965 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
966 | { | |
967 | static int printed_version; | |
eca25dca TH |
968 | const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; |
969 | const struct ata_port_info *ppi[PDC_MAX_PORTS]; | |
970 | struct ata_host *host; | |
0d5ff566 | 971 | void __iomem *base; |
eca25dca | 972 | int n_ports, i, rc; |
5ac2fe57 | 973 | int is_sataii_tx4; |
1da177e4 LT |
974 | |
975 | if (!printed_version++) | |
a9524a76 | 976 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 977 | |
eca25dca | 978 | /* enable and acquire resources */ |
24dc5f33 | 979 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
980 | if (rc) |
981 | return rc; | |
982 | ||
0d5ff566 TH |
983 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
984 | if (rc == -EBUSY) | |
24dc5f33 | 985 | pcim_pin_device(pdev); |
0d5ff566 | 986 | if (rc) |
24dc5f33 | 987 | return rc; |
eca25dca | 988 | base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; |
1da177e4 | 989 | |
eca25dca TH |
990 | /* determine port configuration and setup host */ |
991 | n_ports = 2; | |
992 | if (pi->flags & PDC_FLAG_4_PORTS) | |
993 | n_ports = 4; | |
994 | for (i = 0; i < n_ports; i++) | |
995 | ppi[i] = pi; | |
1da177e4 | 996 | |
eca25dca TH |
997 | if (pi->flags & PDC_FLAG_SATA_PATA) { |
998 | u8 tmp = readb(base + PDC_FLASH_CTL+1); | |
d0e58031 | 999 | if (!(tmp & 0x80)) |
eca25dca | 1000 | ppi[n_ports++] = pi + 1; |
eca25dca | 1001 | } |
1da177e4 | 1002 | |
eca25dca TH |
1003 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
1004 | if (!host) { | |
1005 | dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); | |
24dc5f33 | 1006 | return -ENOMEM; |
1da177e4 | 1007 | } |
eca25dca | 1008 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 | 1009 | |
d0e58031 | 1010 | is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); |
5ac2fe57 | 1011 | for (i = 0; i < host->n_ports; i++) { |
d0e58031 | 1012 | unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); |
eca25dca | 1013 | pdc_ata_setup_port(host->ports[i], |
d0e58031 MP |
1014 | base + 0x200 + ata_no * 0x80, |
1015 | base + 0x400 + ata_no * 0x100); | |
5ac2fe57 | 1016 | } |
1da177e4 LT |
1017 | |
1018 | /* initialize adapter */ | |
eca25dca | 1019 | pdc_host_init(host); |
1da177e4 | 1020 | |
eca25dca TH |
1021 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1022 | if (rc) | |
1023 | return rc; | |
1024 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1025 | if (rc) | |
1026 | return rc; | |
1da177e4 | 1027 | |
eca25dca TH |
1028 | /* start host, request IRQ and attach */ |
1029 | pci_set_master(pdev); | |
1030 | return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, | |
1031 | &pdc_ata_sht); | |
1da177e4 LT |
1032 | } |
1033 | ||
1da177e4 LT |
1034 | static int __init pdc_ata_init(void) |
1035 | { | |
b7887196 | 1036 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1037 | } |
1038 | ||
1da177e4 LT |
1039 | static void __exit pdc_ata_exit(void) |
1040 | { | |
1041 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1042 | } | |
1043 | ||
1da177e4 | 1044 | MODULE_AUTHOR("Jeff Garzik"); |
f497ba73 | 1045 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1046 | MODULE_LICENSE("GPL"); |
1047 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1048 | MODULE_VERSION(DRV_VERSION); | |
1049 | ||
1050 | module_init(pdc_ata_init); | |
1051 | module_exit(pdc_ata_exit); |