Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
95006188 | 42 | #include <scsi/scsi.h> |
1da177e4 | 43 | #include <scsi/scsi_host.h> |
193515d5 | 44 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
45 | #include <linux/libata.h> |
46 | #include <asm/io.h> | |
47 | #include "sata_promise.h" | |
48 | ||
49 | #define DRV_NAME "sata_promise" | |
46b027cc | 50 | #define DRV_VERSION "1.05" |
1da177e4 LT |
51 | |
52 | ||
53 | enum { | |
95006188 MP |
54 | /* register offsets */ |
55 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
56 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
57 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
58 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
59 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
60 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
61 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 62 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 LT |
63 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
64 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 65 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
66 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
67 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
68 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 69 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
70 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
71 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 LT |
72 | |
73 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
74 | (1<<8) | (1<<9) | (1<<10), | |
75 | ||
76 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
77 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 78 | board_20619 = 2, /* FastTrak TX4000 */ |
d324d462 MP |
79 | board_2057x = 3, /* SATAII150 Tx2plus */ |
80 | board_40518 = 4, /* SATAII150 Tx4 */ | |
1da177e4 | 81 | |
6340f019 | 82 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 83 | |
95006188 MP |
84 | /* Sequence counter control registers bit definitions */ |
85 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
86 | ||
87 | /* Feature register values */ | |
88 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
89 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
90 | ||
91 | /* Device/Head register values */ | |
92 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
93 | ||
25b93d81 MP |
94 | /* PDC_CTLSTAT bit definitions */ |
95 | PDC_DMA_ENABLE = (1 << 7), | |
96 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 97 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 98 | |
25b93d81 | 99 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 100 | ATA_FLAG_MMIO | |
3d0a59c0 | 101 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 MP |
102 | |
103 | /* hp->flags bits */ | |
104 | PDC_FLAG_GEN_II = (1 << 0), | |
1da177e4 LT |
105 | }; |
106 | ||
107 | ||
108 | struct pdc_port_priv { | |
109 | u8 *pkt; | |
110 | dma_addr_t pkt_dma; | |
111 | }; | |
112 | ||
6340f019 | 113 | struct pdc_host_priv { |
b2d1eee1 | 114 | unsigned long flags; |
870ae337 | 115 | unsigned long port_flags[ATA_MAX_PORTS]; |
6340f019 LK |
116 | }; |
117 | ||
1da177e4 LT |
118 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
119 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
120 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
7d12e780 | 121 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance); |
1da177e4 LT |
122 | static void pdc_eng_timeout(struct ata_port *ap); |
123 | static int pdc_port_start(struct ata_port *ap); | |
124 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a | 125 | static void pdc_pata_phy_reset(struct ata_port *ap); |
1da177e4 | 126 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
127 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
128 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 MP |
129 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
130 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc); | |
1da177e4 | 131 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 132 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
cca3974e | 133 | static void pdc_host_stop(struct ata_host *host); |
25b93d81 MP |
134 | static void pdc_freeze(struct ata_port *ap); |
135 | static void pdc_thaw(struct ata_port *ap); | |
136 | static void pdc_error_handler(struct ata_port *ap); | |
137 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); | |
1da177e4 | 138 | |
374b1873 | 139 | |
193515d5 | 140 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
141 | .module = THIS_MODULE, |
142 | .name = DRV_NAME, | |
143 | .ioctl = ata_scsi_ioctl, | |
144 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
145 | .can_queue = ATA_DEF_QUEUE, |
146 | .this_id = ATA_SHT_THIS_ID, | |
147 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
148 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
149 | .emulated = ATA_SHT_EMULATED, | |
150 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
151 | .proc_name = DRV_NAME, | |
152 | .dma_boundary = ATA_DMA_BOUNDARY, | |
153 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 154 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 155 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
156 | }; |
157 | ||
057ace5e | 158 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
159 | .port_disable = ata_port_disable, |
160 | .tf_load = pdc_tf_load_mmio, | |
161 | .tf_read = ata_tf_read, | |
162 | .check_status = ata_check_status, | |
163 | .exec_command = pdc_exec_command_mmio, | |
164 | .dev_select = ata_std_dev_select, | |
95006188 MP |
165 | .check_atapi_dma = pdc_check_atapi_dma, |
166 | ||
167 | .qc_prep = pdc_qc_prep, | |
168 | .qc_issue = pdc_qc_issue_prot, | |
169 | .freeze = pdc_freeze, | |
170 | .thaw = pdc_thaw, | |
171 | .error_handler = pdc_error_handler, | |
172 | .post_internal_cmd = pdc_post_internal_cmd, | |
173 | .data_xfer = ata_mmio_data_xfer, | |
174 | .irq_handler = pdc_interrupt, | |
175 | .irq_clear = pdc_irq_clear, | |
176 | ||
177 | .scr_read = pdc_sata_scr_read, | |
178 | .scr_write = pdc_sata_scr_write, | |
179 | .port_start = pdc_port_start, | |
180 | .port_stop = pdc_port_stop, | |
181 | .host_stop = pdc_host_stop, | |
182 | }; | |
183 | ||
184 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
185 | static const struct ata_port_operations pdc_old_sata_ops = { | |
186 | .port_disable = ata_port_disable, | |
187 | .tf_load = pdc_tf_load_mmio, | |
188 | .tf_read = ata_tf_read, | |
189 | .check_status = ata_check_status, | |
190 | .exec_command = pdc_exec_command_mmio, | |
191 | .dev_select = ata_std_dev_select, | |
192 | .check_atapi_dma = pdc_old_check_atapi_dma, | |
2cba582a | 193 | |
1da177e4 LT |
194 | .qc_prep = pdc_qc_prep, |
195 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
196 | .freeze = pdc_freeze, |
197 | .thaw = pdc_thaw, | |
198 | .error_handler = pdc_error_handler, | |
199 | .post_internal_cmd = pdc_post_internal_cmd, | |
a6b2c5d4 | 200 | .data_xfer = ata_mmio_data_xfer, |
1da177e4 LT |
201 | .irq_handler = pdc_interrupt, |
202 | .irq_clear = pdc_irq_clear, | |
2cba582a | 203 | |
1da177e4 LT |
204 | .scr_read = pdc_sata_scr_read, |
205 | .scr_write = pdc_sata_scr_write, | |
206 | .port_start = pdc_port_start, | |
207 | .port_stop = pdc_port_stop, | |
6340f019 | 208 | .host_stop = pdc_host_stop, |
1da177e4 LT |
209 | }; |
210 | ||
057ace5e | 211 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
212 | .port_disable = ata_port_disable, |
213 | .tf_load = pdc_tf_load_mmio, | |
214 | .tf_read = ata_tf_read, | |
215 | .check_status = ata_check_status, | |
216 | .exec_command = pdc_exec_command_mmio, | |
217 | .dev_select = ata_std_dev_select, | |
95006188 | 218 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a JG |
219 | |
220 | .phy_reset = pdc_pata_phy_reset, | |
221 | ||
222 | .qc_prep = pdc_qc_prep, | |
223 | .qc_issue = pdc_qc_issue_prot, | |
a6b2c5d4 | 224 | .data_xfer = ata_mmio_data_xfer, |
2cba582a JG |
225 | .eng_timeout = pdc_eng_timeout, |
226 | .irq_handler = pdc_interrupt, | |
227 | .irq_clear = pdc_irq_clear, | |
228 | ||
229 | .port_start = pdc_port_start, | |
230 | .port_stop = pdc_port_stop, | |
6340f019 | 231 | .host_stop = pdc_host_stop, |
2cba582a JG |
232 | }; |
233 | ||
98ac62de | 234 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
235 | /* board_2037x */ |
236 | { | |
237 | .sht = &pdc_ata_sht, | |
870ae337 | 238 | .flags = PDC_COMMON_FLAGS, |
1da177e4 LT |
239 | .pio_mask = 0x1f, /* pio0-4 */ |
240 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
241 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 242 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
243 | }, |
244 | ||
245 | /* board_20319 */ | |
246 | { | |
247 | .sht = &pdc_ata_sht, | |
cca3974e | 248 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
249 | .pio_mask = 0x1f, /* pio0-4 */ |
250 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
251 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 252 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 253 | }, |
f497ba73 TL |
254 | |
255 | /* board_20619 */ | |
256 | { | |
257 | .sht = &pdc_ata_sht, | |
25b93d81 | 258 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
259 | .pio_mask = 0x1f, /* pio0-4 */ |
260 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
261 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 262 | .port_ops = &pdc_pata_ops, |
f497ba73 | 263 | }, |
5a46fe89 | 264 | |
6340f019 LK |
265 | /* board_2057x */ |
266 | { | |
267 | .sht = &pdc_ata_sht, | |
870ae337 | 268 | .flags = PDC_COMMON_FLAGS, |
6340f019 LK |
269 | .pio_mask = 0x1f, /* pio0-4 */ |
270 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
271 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
272 | .port_ops = &pdc_sata_ops, | |
273 | }, | |
274 | ||
275 | /* board_40518 */ | |
276 | { | |
277 | .sht = &pdc_ata_sht, | |
cca3974e | 278 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
279 | .pio_mask = 0x1f, /* pio0-4 */ |
280 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
281 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
282 | .port_ops = &pdc_sata_ops, | |
283 | }, | |
1da177e4 LT |
284 | }; |
285 | ||
3b7d697d | 286 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 287 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
288 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
289 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
290 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
291 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
292 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 293 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 294 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 295 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 296 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
297 | |
298 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
299 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
300 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
301 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
b2d1eee1 | 302 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
303 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
304 | ||
305 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 306 | |
1da177e4 LT |
307 | { } /* terminate list */ |
308 | }; | |
309 | ||
310 | ||
311 | static struct pci_driver pdc_ata_pci_driver = { | |
312 | .name = DRV_NAME, | |
313 | .id_table = pdc_ata_pci_tbl, | |
314 | .probe = pdc_ata_init_one, | |
315 | .remove = ata_pci_remove_one, | |
316 | }; | |
317 | ||
318 | ||
319 | static int pdc_port_start(struct ata_port *ap) | |
320 | { | |
cca3974e | 321 | struct device *dev = ap->host->dev; |
599b7202 | 322 | struct pdc_host_priv *hp = ap->host->private_data; |
1da177e4 LT |
323 | struct pdc_port_priv *pp; |
324 | int rc; | |
325 | ||
870ae337 MP |
326 | /* fix up port flags and cable type for SATA+PATA chips */ |
327 | ap->flags |= hp->port_flags[ap->port_no]; | |
328 | if (ap->flags & ATA_FLAG_SATA) | |
329 | ap->cbl = ATA_CBL_SATA; | |
330 | ||
1da177e4 LT |
331 | rc = ata_port_start(ap); |
332 | if (rc) | |
333 | return rc; | |
334 | ||
6340f019 | 335 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
336 | if (!pp) { |
337 | rc = -ENOMEM; | |
338 | goto err_out; | |
339 | } | |
1da177e4 LT |
340 | |
341 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
342 | if (!pp->pkt) { | |
343 | rc = -ENOMEM; | |
344 | goto err_out_kfree; | |
345 | } | |
346 | ||
347 | ap->private_data = pp; | |
348 | ||
599b7202 MP |
349 | /* fix up PHYMODE4 align timing */ |
350 | if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) { | |
351 | void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr; | |
352 | unsigned int tmp; | |
353 | ||
354 | tmp = readl(mmio + 0x014); | |
355 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
356 | writel(tmp, mmio + 0x014); | |
357 | } | |
358 | ||
1da177e4 LT |
359 | return 0; |
360 | ||
361 | err_out_kfree: | |
362 | kfree(pp); | |
363 | err_out: | |
364 | ata_port_stop(ap); | |
365 | return rc; | |
366 | } | |
367 | ||
368 | ||
369 | static void pdc_port_stop(struct ata_port *ap) | |
370 | { | |
cca3974e | 371 | struct device *dev = ap->host->dev; |
1da177e4 LT |
372 | struct pdc_port_priv *pp = ap->private_data; |
373 | ||
374 | ap->private_data = NULL; | |
375 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
376 | kfree(pp); | |
377 | ata_port_stop(ap); | |
378 | } | |
379 | ||
380 | ||
cca3974e | 381 | static void pdc_host_stop(struct ata_host *host) |
6340f019 | 382 | { |
cca3974e | 383 | struct pdc_host_priv *hp = host->private_data; |
6340f019 | 384 | |
cca3974e | 385 | ata_pci_host_stop(host); |
6340f019 LK |
386 | |
387 | kfree(hp); | |
388 | } | |
389 | ||
390 | ||
1da177e4 LT |
391 | static void pdc_reset_port(struct ata_port *ap) |
392 | { | |
ea6ba10b | 393 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
394 | unsigned int i; |
395 | u32 tmp; | |
396 | ||
397 | for (i = 11; i > 0; i--) { | |
398 | tmp = readl(mmio); | |
399 | if (tmp & PDC_RESET) | |
400 | break; | |
401 | ||
402 | udelay(100); | |
403 | ||
404 | tmp |= PDC_RESET; | |
405 | writel(tmp, mmio); | |
406 | } | |
407 | ||
408 | tmp &= ~PDC_RESET; | |
409 | writel(tmp, mmio); | |
410 | readl(mmio); /* flush */ | |
411 | } | |
412 | ||
d3fb4e8d | 413 | static void pdc_pata_cbl_detect(struct ata_port *ap) |
2cba582a | 414 | { |
d3fb4e8d | 415 | u8 tmp; |
03dc5506 | 416 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d JG |
417 | |
418 | tmp = readb(mmio); | |
419 | ||
420 | if (tmp & 0x01) { | |
421 | ap->cbl = ATA_CBL_PATA40; | |
422 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
423 | } else | |
424 | ap->cbl = ATA_CBL_PATA80; | |
425 | } | |
2cba582a | 426 | |
d3fb4e8d JG |
427 | static void pdc_pata_phy_reset(struct ata_port *ap) |
428 | { | |
429 | pdc_pata_cbl_detect(ap); | |
2cba582a JG |
430 | pdc_reset_port(ap); |
431 | ata_port_probe(ap); | |
432 | ata_bus_reset(ap); | |
433 | } | |
434 | ||
1da177e4 LT |
435 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
436 | { | |
870ae337 | 437 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 438 | return 0xffffffffU; |
b181d3b0 | 439 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
440 | } |
441 | ||
442 | ||
443 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
444 | u32 val) | |
445 | { | |
870ae337 | 446 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 447 | return; |
b181d3b0 | 448 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
449 | } |
450 | ||
fba6edbd | 451 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 452 | { |
4113bb6b MP |
453 | struct ata_port *ap = qc->ap; |
454 | dma_addr_t sg_table = ap->prd_dma; | |
455 | unsigned int cdb_len = qc->dev->cdb_len; | |
456 | u8 *cdb = qc->cdb; | |
457 | struct pdc_port_priv *pp = ap->private_data; | |
458 | u8 *buf = pp->pkt; | |
95006188 | 459 | u32 *buf32 = (u32 *) buf; |
4113bb6b | 460 | unsigned int dev_sel, feature, nbytes; |
95006188 MP |
461 | |
462 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
463 | * and seq id (byte 2) | |
464 | */ | |
fba6edbd MP |
465 | switch (qc->tf.protocol) { |
466 | case ATA_PROT_ATAPI_DMA: | |
467 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
468 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
469 | else | |
470 | buf32[0] = 0; | |
471 | break; | |
472 | case ATA_PROT_ATAPI_NODATA: | |
473 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); | |
474 | break; | |
475 | default: | |
476 | BUG(); | |
477 | break; | |
478 | } | |
95006188 MP |
479 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
480 | buf32[2] = 0; /* no next-packet */ | |
481 | ||
4113bb6b MP |
482 | /* select drive */ |
483 | if (sata_scr_valid(ap)) { | |
484 | dev_sel = PDC_DEVICE_SATA; | |
485 | } else { | |
486 | dev_sel = ATA_DEVICE_OBS; | |
487 | if (qc->dev->devno != 0) | |
488 | dev_sel |= ATA_DEV1; | |
489 | } | |
490 | buf[12] = (1 << 5) | ATA_REG_DEVICE; | |
491 | buf[13] = dev_sel; | |
492 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
493 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
494 | ||
495 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
496 | buf[17] = 0x00; | |
497 | buf[18] = (1 << 5) | ATA_REG_LBAL; | |
498 | buf[19] = 0x00; | |
499 | ||
500 | /* set feature and byte counter registers */ | |
501 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { | |
502 | feature = PDC_FEATURE_ATAPI_PIO; | |
503 | /* set byte counter register to real transfer byte count */ | |
504 | nbytes = qc->nbytes; | |
4113bb6b MP |
505 | if (nbytes > 0xffff) |
506 | nbytes = 0xffff; | |
507 | } else { | |
508 | feature = PDC_FEATURE_ATAPI_DMA; | |
509 | /* set byte counter register to 0 */ | |
510 | nbytes = 0; | |
511 | } | |
512 | buf[20] = (1 << 5) | ATA_REG_FEATURE; | |
513 | buf[21] = feature; | |
514 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
515 | buf[23] = nbytes & 0xFF; | |
516 | buf[24] = (1 << 5) | ATA_REG_BYTEH; | |
517 | buf[25] = (nbytes >> 8) & 0xFF; | |
518 | ||
519 | /* send ATAPI packet command 0xA0 */ | |
520 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
521 | buf[27] = ATA_CMD_PACKET; | |
522 | ||
523 | /* select drive and check DRQ */ | |
524 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
525 | buf[29] = dev_sel; | |
526 | ||
95006188 MP |
527 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
528 | BUG_ON(cdb_len & ~0x1E); | |
529 | ||
4113bb6b MP |
530 | /* append the CDB as the final part */ |
531 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
532 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
533 | } |
534 | ||
1da177e4 LT |
535 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
536 | { | |
537 | struct pdc_port_priv *pp = qc->ap->private_data; | |
538 | unsigned int i; | |
539 | ||
540 | VPRINTK("ENTER\n"); | |
541 | ||
542 | switch (qc->tf.protocol) { | |
543 | case ATA_PROT_DMA: | |
544 | ata_qc_prep(qc); | |
545 | /* fall through */ | |
546 | ||
547 | case ATA_PROT_NODATA: | |
548 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
549 | qc->dev->devno, pp->pkt); | |
550 | ||
551 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
552 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
553 | else | |
554 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
555 | ||
556 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
557 | break; | |
558 | ||
95006188 | 559 | case ATA_PROT_ATAPI: |
95006188 MP |
560 | ata_qc_prep(qc); |
561 | break; | |
562 | ||
563 | case ATA_PROT_ATAPI_DMA: | |
564 | ata_qc_prep(qc); | |
fba6edbd MP |
565 | /*FALLTHROUGH*/ |
566 | case ATA_PROT_ATAPI_NODATA: | |
567 | pdc_atapi_pkt(qc); | |
95006188 MP |
568 | break; |
569 | ||
1da177e4 LT |
570 | default: |
571 | break; | |
572 | } | |
573 | } | |
574 | ||
25b93d81 MP |
575 | static void pdc_freeze(struct ata_port *ap) |
576 | { | |
577 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
578 | u32 tmp; | |
579 | ||
580 | tmp = readl(mmio + PDC_CTLSTAT); | |
581 | tmp |= PDC_IRQ_DISABLE; | |
582 | tmp &= ~PDC_DMA_ENABLE; | |
583 | writel(tmp, mmio + PDC_CTLSTAT); | |
584 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
585 | } | |
586 | ||
587 | static void pdc_thaw(struct ata_port *ap) | |
588 | { | |
589 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
590 | u32 tmp; | |
591 | ||
592 | /* clear IRQ */ | |
593 | readl(mmio + PDC_INT_SEQMASK); | |
594 | ||
595 | /* turn IRQ back on */ | |
596 | tmp = readl(mmio + PDC_CTLSTAT); | |
597 | tmp &= ~PDC_IRQ_DISABLE; | |
598 | writel(tmp, mmio + PDC_CTLSTAT); | |
599 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
600 | } | |
601 | ||
602 | static void pdc_error_handler(struct ata_port *ap) | |
603 | { | |
604 | ata_reset_fn_t hardreset; | |
605 | ||
606 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) | |
607 | pdc_reset_port(ap); | |
608 | ||
609 | hardreset = NULL; | |
610 | if (sata_scr_valid(ap)) | |
611 | hardreset = sata_std_hardreset; | |
612 | ||
613 | /* perform recovery */ | |
614 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, | |
615 | ata_std_postreset); | |
616 | } | |
617 | ||
618 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) | |
619 | { | |
620 | struct ata_port *ap = qc->ap; | |
621 | ||
622 | if (qc->flags & ATA_QCFLAG_FAILED) | |
623 | qc->err_mask |= AC_ERR_OTHER; | |
624 | ||
625 | /* make DMA engine forget about the failed command */ | |
626 | if (qc->err_mask) | |
627 | pdc_reset_port(ap); | |
628 | } | |
629 | ||
1da177e4 LT |
630 | static void pdc_eng_timeout(struct ata_port *ap) |
631 | { | |
cca3974e | 632 | struct ata_host *host = ap->host; |
1da177e4 LT |
633 | u8 drv_stat; |
634 | struct ata_queued_cmd *qc; | |
b8f6153e | 635 | unsigned long flags; |
1da177e4 LT |
636 | |
637 | DPRINTK("ENTER\n"); | |
638 | ||
cca3974e | 639 | spin_lock_irqsave(&host->lock, flags); |
b8f6153e | 640 | |
1da177e4 | 641 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1da177e4 | 642 | |
1da177e4 LT |
643 | switch (qc->tf.protocol) { |
644 | case ATA_PROT_DMA: | |
645 | case ATA_PROT_NODATA: | |
f15a1daf | 646 | ata_port_printk(ap, KERN_ERR, "command timeout\n"); |
a7dac447 | 647 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 648 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
649 | break; |
650 | ||
651 | default: | |
652 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
653 | ||
f15a1daf TH |
654 | ata_port_printk(ap, KERN_ERR, |
655 | "unknown timeout, cmd 0x%x stat 0x%x\n", | |
656 | qc->tf.command, drv_stat); | |
1da177e4 | 657 | |
a22e2eb0 | 658 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
659 | break; |
660 | } | |
661 | ||
cca3974e | 662 | spin_unlock_irqrestore(&host->lock, flags); |
f6379020 | 663 | ata_eh_qc_complete(qc); |
1da177e4 LT |
664 | DPRINTK("EXIT\n"); |
665 | } | |
666 | ||
667 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
668 | struct ata_queued_cmd *qc) | |
669 | { | |
a22e2eb0 | 670 | unsigned int handled = 0; |
1da177e4 | 671 | u32 tmp; |
ea6ba10b | 672 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
673 | |
674 | tmp = readl(mmio); | |
675 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 676 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
677 | pdc_reset_port(ap); |
678 | } | |
679 | ||
680 | switch (qc->tf.protocol) { | |
681 | case ATA_PROT_DMA: | |
682 | case ATA_PROT_NODATA: | |
95006188 | 683 | case ATA_PROT_ATAPI_DMA: |
fba6edbd | 684 | case ATA_PROT_ATAPI_NODATA: |
a22e2eb0 AL |
685 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
686 | ata_qc_complete(qc); | |
1da177e4 LT |
687 | handled = 1; |
688 | break; | |
689 | ||
690 | default: | |
ee500aab AL |
691 | ap->stats.idle_irq++; |
692 | break; | |
1da177e4 LT |
693 | } |
694 | ||
ee500aab | 695 | return handled; |
1da177e4 LT |
696 | } |
697 | ||
698 | static void pdc_irq_clear(struct ata_port *ap) | |
699 | { | |
cca3974e JG |
700 | struct ata_host *host = ap->host; |
701 | void __iomem *mmio = host->mmio_base; | |
1da177e4 LT |
702 | |
703 | readl(mmio + PDC_INT_SEQMASK); | |
704 | } | |
705 | ||
7d12e780 | 706 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 707 | { |
cca3974e | 708 | struct ata_host *host = dev_instance; |
1da177e4 LT |
709 | struct ata_port *ap; |
710 | u32 mask = 0; | |
711 | unsigned int i, tmp; | |
712 | unsigned int handled = 0; | |
ea6ba10b | 713 | void __iomem *mmio_base; |
1da177e4 LT |
714 | |
715 | VPRINTK("ENTER\n"); | |
716 | ||
cca3974e | 717 | if (!host || !host->mmio_base) { |
1da177e4 LT |
718 | VPRINTK("QUICK EXIT\n"); |
719 | return IRQ_NONE; | |
720 | } | |
721 | ||
cca3974e | 722 | mmio_base = host->mmio_base; |
1da177e4 LT |
723 | |
724 | /* reading should also clear interrupts */ | |
725 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
726 | ||
727 | if (mask == 0xffffffff) { | |
728 | VPRINTK("QUICK EXIT 2\n"); | |
729 | return IRQ_NONE; | |
730 | } | |
6340f019 | 731 | |
cca3974e | 732 | spin_lock(&host->lock); |
6340f019 | 733 | |
1da177e4 LT |
734 | mask &= 0xffff; /* only 16 tags possible */ |
735 | if (!mask) { | |
736 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 737 | goto done_irq; |
1da177e4 LT |
738 | } |
739 | ||
1da177e4 LT |
740 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
741 | ||
cca3974e | 742 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 743 | VPRINTK("port %u\n", i); |
cca3974e | 744 | ap = host->ports[i]; |
1da177e4 | 745 | tmp = mask & (1 << (i + 1)); |
c1389503 | 746 | if (tmp && ap && |
029f5468 | 747 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
748 | struct ata_queued_cmd *qc; |
749 | ||
750 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 751 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
752 | handled += pdc_host_intr(ap, qc); |
753 | } | |
754 | } | |
755 | ||
1da177e4 LT |
756 | VPRINTK("EXIT\n"); |
757 | ||
6340f019 | 758 | done_irq: |
cca3974e | 759 | spin_unlock(&host->lock); |
1da177e4 LT |
760 | return IRQ_RETVAL(handled); |
761 | } | |
762 | ||
763 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
764 | { | |
765 | struct ata_port *ap = qc->ap; | |
766 | struct pdc_port_priv *pp = ap->private_data; | |
767 | unsigned int port_no = ap->port_no; | |
768 | u8 seq = (u8) (port_no + 1); | |
769 | ||
770 | VPRINTK("ENTER, ap %p\n", ap); | |
771 | ||
cca3974e JG |
772 | writel(0x00000001, ap->host->mmio_base + (seq * 4)); |
773 | readl(ap->host->mmio_base + (seq * 4)); /* flush */ | |
1da177e4 LT |
774 | |
775 | pp->pkt[2] = seq; | |
776 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
777 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
778 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
779 | } |
780 | ||
9a3d9eb0 | 781 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
782 | { |
783 | switch (qc->tf.protocol) { | |
fba6edbd MP |
784 | case ATA_PROT_ATAPI_NODATA: |
785 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
786 | break; | |
787 | /*FALLTHROUGH*/ | |
95006188 | 788 | case ATA_PROT_ATAPI_DMA: |
1da177e4 LT |
789 | case ATA_PROT_DMA: |
790 | case ATA_PROT_NODATA: | |
791 | pdc_packet_start(qc); | |
792 | return 0; | |
793 | ||
1da177e4 LT |
794 | default: |
795 | break; | |
796 | } | |
797 | ||
798 | return ata_qc_issue_prot(qc); | |
799 | } | |
800 | ||
057ace5e | 801 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
802 | { |
803 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
804 | tf->protocol == ATA_PROT_NODATA); | |
805 | ata_tf_load(ap, tf); | |
806 | } | |
807 | ||
808 | ||
057ace5e | 809 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
810 | { |
811 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
812 | tf->protocol == ATA_PROT_NODATA); | |
813 | ata_exec_command(ap, tf); | |
814 | } | |
815 | ||
95006188 MP |
816 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
817 | { | |
818 | u8 *scsicmd = qc->scsicmd->cmnd; | |
819 | int pio = 1; /* atapi dma off by default */ | |
820 | ||
821 | /* Whitelist commands that may use DMA. */ | |
822 | switch (scsicmd[0]) { | |
823 | case WRITE_12: | |
824 | case WRITE_10: | |
825 | case WRITE_6: | |
826 | case READ_12: | |
827 | case READ_10: | |
828 | case READ_6: | |
829 | case 0xad: /* READ_DVD_STRUCTURE */ | |
830 | case 0xbe: /* READ_CD */ | |
831 | pio = 0; | |
832 | } | |
833 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
834 | if (scsicmd[0] == WRITE_10) { | |
835 | unsigned int lba; | |
836 | lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; | |
837 | if (lba >= 0xFFFF4FA2) | |
838 | pio = 1; | |
839 | } | |
840 | return pio; | |
841 | } | |
842 | ||
843 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc) | |
844 | { | |
845 | struct ata_port *ap = qc->ap; | |
846 | ||
847 | /* First generation chips cannot use ATAPI DMA on SATA ports */ | |
848 | if (sata_scr_valid(ap)) | |
849 | return 1; | |
850 | return pdc_check_atapi_dma(qc); | |
851 | } | |
1da177e4 LT |
852 | |
853 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
854 | { | |
855 | port->cmd_addr = base; | |
856 | port->data_addr = base; | |
857 | port->feature_addr = | |
858 | port->error_addr = base + 0x4; | |
859 | port->nsect_addr = base + 0x8; | |
860 | port->lbal_addr = base + 0xc; | |
861 | port->lbam_addr = base + 0x10; | |
862 | port->lbah_addr = base + 0x14; | |
863 | port->device_addr = base + 0x18; | |
864 | port->command_addr = | |
865 | port->status_addr = base + 0x1c; | |
866 | port->altstatus_addr = | |
867 | port->ctl_addr = base + 0x38; | |
868 | } | |
869 | ||
870 | ||
871 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
872 | { | |
ea6ba10b | 873 | void __iomem *mmio = pe->mmio_base; |
6340f019 | 874 | struct pdc_host_priv *hp = pe->private_data; |
d324d462 | 875 | int hotplug_offset; |
1da177e4 LT |
876 | u32 tmp; |
877 | ||
d324d462 MP |
878 | if (hp->flags & PDC_FLAG_GEN_II) |
879 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
880 | else | |
881 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
882 | ||
1da177e4 LT |
883 | /* |
884 | * Except for the hotplug stuff, this is voodoo from the | |
885 | * Promise driver. Label this entire section | |
886 | * "TODO: figure out why we do this" | |
887 | */ | |
888 | ||
b2d1eee1 | 889 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 890 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 MP |
891 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
892 | if (!(hp->flags & PDC_FLAG_GEN_II)) | |
893 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ | |
1da177e4 LT |
894 | writel(tmp, mmio + PDC_FLASH_CTL); |
895 | ||
896 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
897 | tmp = readl(mmio + hotplug_offset); |
898 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
899 | |
900 | /* mask plug/unplug ints */ | |
6340f019 LK |
901 | tmp = readl(mmio + hotplug_offset); |
902 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 | 903 | |
b2d1eee1 MP |
904 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
905 | if (hp->flags & PDC_FLAG_GEN_II) | |
906 | return; | |
907 | ||
1da177e4 LT |
908 | /* reduce TBG clock to 133 Mhz. */ |
909 | tmp = readl(mmio + PDC_TBG_MODE); | |
910 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
911 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
912 | writel(tmp, mmio + PDC_TBG_MODE); | |
913 | ||
914 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
915 | msleep(10); | |
916 | ||
917 | /* adjust slew rate control register. */ | |
918 | tmp = readl(mmio + PDC_SLEW_CTL); | |
919 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
920 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
921 | writel(tmp, mmio + PDC_SLEW_CTL); | |
922 | } | |
923 | ||
924 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
925 | { | |
926 | static int printed_version; | |
927 | struct ata_probe_ent *probe_ent = NULL; | |
6340f019 | 928 | struct pdc_host_priv *hp; |
1da177e4 | 929 | unsigned long base; |
ea6ba10b | 930 | void __iomem *mmio_base; |
1da177e4 LT |
931 | unsigned int board_idx = (unsigned int) ent->driver_data; |
932 | int pci_dev_busy = 0; | |
933 | int rc; | |
870ae337 | 934 | u8 tmp; |
1da177e4 LT |
935 | |
936 | if (!printed_version++) | |
a9524a76 | 937 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 938 | |
1da177e4 LT |
939 | rc = pci_enable_device(pdev); |
940 | if (rc) | |
941 | return rc; | |
942 | ||
943 | rc = pci_request_regions(pdev, DRV_NAME); | |
944 | if (rc) { | |
945 | pci_dev_busy = 1; | |
946 | goto err_out; | |
947 | } | |
948 | ||
949 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
950 | if (rc) | |
951 | goto err_out_regions; | |
952 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
953 | if (rc) | |
954 | goto err_out_regions; | |
955 | ||
6340f019 | 956 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
957 | if (probe_ent == NULL) { |
958 | rc = -ENOMEM; | |
959 | goto err_out_regions; | |
960 | } | |
961 | ||
1da177e4 LT |
962 | probe_ent->dev = pci_dev_to_dev(pdev); |
963 | INIT_LIST_HEAD(&probe_ent->node); | |
964 | ||
374b1873 | 965 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
966 | if (mmio_base == NULL) { |
967 | rc = -ENOMEM; | |
968 | goto err_out_free_ent; | |
969 | } | |
970 | base = (unsigned long) mmio_base; | |
971 | ||
6340f019 LK |
972 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); |
973 | if (hp == NULL) { | |
974 | rc = -ENOMEM; | |
975 | goto err_out_free_ent; | |
976 | } | |
977 | ||
6340f019 LK |
978 | probe_ent->private_data = hp; |
979 | ||
1da177e4 | 980 | probe_ent->sht = pdc_port_info[board_idx].sht; |
cca3974e | 981 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1da177e4 LT |
982 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
983 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
984 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
985 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
986 | ||
987 | probe_ent->irq = pdev->irq; | |
1d6f359a | 988 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
989 | probe_ent->mmio_base = mmio_base; |
990 | ||
991 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
992 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
993 | ||
994 | probe_ent->port[0].scr_addr = base + 0x400; | |
995 | probe_ent->port[1].scr_addr = base + 0x500; | |
996 | ||
997 | /* notice 4-port boards */ | |
998 | switch (board_idx) { | |
6340f019 | 999 | case board_40518: |
b2d1eee1 | 1000 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 1001 | /* Fall through */ |
1da177e4 LT |
1002 | case board_20319: |
1003 | probe_ent->n_ports = 4; | |
1004 | ||
1005 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1006 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
1007 | ||
1008 | probe_ent->port[2].scr_addr = base + 0x600; | |
1009 | probe_ent->port[3].scr_addr = base + 0x700; | |
1010 | break; | |
6340f019 | 1011 | case board_2057x: |
b2d1eee1 | 1012 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 1013 | /* Fall through */ |
1da177e4 | 1014 | case board_2037x: |
870ae337 MP |
1015 | /* TX2plus boards also have a PATA port */ |
1016 | tmp = readb(mmio_base + PDC_FLASH_CTL+1); | |
1017 | if (!(tmp & 0x80)) { | |
1018 | probe_ent->n_ports = 3; | |
1019 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1020 | hp->port_flags[2] = ATA_FLAG_SLAVE_POSS; | |
1021 | printk(KERN_INFO DRV_NAME " PATA port found\n"); | |
1022 | } else | |
1023 | probe_ent->n_ports = 2; | |
1024 | hp->port_flags[0] = ATA_FLAG_SATA; | |
1025 | hp->port_flags[1] = ATA_FLAG_SATA; | |
1da177e4 | 1026 | break; |
f497ba73 TL |
1027 | case board_20619: |
1028 | probe_ent->n_ports = 4; | |
1029 | ||
1030 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1031 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
1032 | ||
1033 | probe_ent->port[2].scr_addr = base + 0x600; | |
1034 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 1035 | break; |
1da177e4 LT |
1036 | default: |
1037 | BUG(); | |
1038 | break; | |
1039 | } | |
1040 | ||
1041 | pci_set_master(pdev); | |
1042 | ||
1043 | /* initialize adapter */ | |
1044 | pdc_host_init(board_idx, probe_ent); | |
1045 | ||
6340f019 LK |
1046 | /* FIXME: Need any other frees than hp? */ |
1047 | if (!ata_device_add(probe_ent)) | |
1048 | kfree(hp); | |
1049 | ||
1da177e4 LT |
1050 | kfree(probe_ent); |
1051 | ||
1052 | return 0; | |
1053 | ||
1054 | err_out_free_ent: | |
1055 | kfree(probe_ent); | |
1056 | err_out_regions: | |
1057 | pci_release_regions(pdev); | |
1058 | err_out: | |
1059 | if (!pci_dev_busy) | |
1060 | pci_disable_device(pdev); | |
1061 | return rc; | |
1062 | } | |
1063 | ||
1064 | ||
1065 | static int __init pdc_ata_init(void) | |
1066 | { | |
b7887196 | 1067 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1068 | } |
1069 | ||
1070 | ||
1071 | static void __exit pdc_ata_exit(void) | |
1072 | { | |
1073 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1074 | } | |
1075 | ||
1076 | ||
1077 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 1078 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1079 | MODULE_LICENSE("GPL"); |
1080 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1081 | MODULE_VERSION(DRV_VERSION); | |
1082 | ||
1083 | module_init(pdc_ata_init); | |
1084 | module_exit(pdc_ata_exit); |