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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
edb33667 TH |
23 | #include <linux/pci.h> |
24 | #include <linux/blkdev.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/dma-mapping.h> | |
a9524a76 | 28 | #include <linux/device.h> |
edb33667 | 29 | #include <scsi/scsi_host.h> |
193515d5 | 30 | #include <scsi/scsi_cmnd.h> |
edb33667 | 31 | #include <linux/libata.h> |
edb33667 TH |
32 | |
33 | #define DRV_NAME "sata_sil24" | |
3454dc69 | 34 | #define DRV_VERSION "1.1" |
edb33667 | 35 | |
edb33667 TH |
36 | /* |
37 | * Port request block (PRB) 32 bytes | |
38 | */ | |
39 | struct sil24_prb { | |
b4772574 AD |
40 | __le16 ctrl; |
41 | __le16 prot; | |
42 | __le32 rx_cnt; | |
edb33667 TH |
43 | u8 fis[6 * 4]; |
44 | }; | |
45 | ||
46 | /* | |
47 | * Scatter gather entry (SGE) 16 bytes | |
48 | */ | |
49 | struct sil24_sge { | |
b4772574 AD |
50 | __le64 addr; |
51 | __le32 cnt; | |
52 | __le32 flags; | |
edb33667 TH |
53 | }; |
54 | ||
edb33667 TH |
55 | |
56 | enum { | |
0d5ff566 TH |
57 | SIL24_HOST_BAR = 0, |
58 | SIL24_PORT_BAR = 2, | |
59 | ||
93e2618e TH |
60 | /* sil24 fetches in chunks of 64bytes. The first block |
61 | * contains the PRB and two SGEs. From the second block, it's | |
62 | * consisted of four SGEs and called SGT. Calculate the | |
63 | * number of SGTs that fit into one page. | |
64 | */ | |
65 | SIL24_PRB_SZ = sizeof(struct sil24_prb) | |
66 | + 2 * sizeof(struct sil24_sge), | |
67 | SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ) | |
68 | / (4 * sizeof(struct sil24_sge)), | |
69 | ||
70 | /* This will give us one unused SGEs for ATA. This extra SGE | |
71 | * will be used to store CDB for ATAPI devices. | |
72 | */ | |
73 | SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1, | |
74 | ||
edb33667 TH |
75 | /* |
76 | * Global controller registers (128 bytes @ BAR0) | |
77 | */ | |
78 | /* 32 bit regs */ | |
79 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
80 | HOST_CTRL = 0x40, | |
81 | HOST_IRQ_STAT = 0x44, | |
82 | HOST_PHY_CFG = 0x48, | |
83 | HOST_BIST_CTRL = 0x50, | |
84 | HOST_BIST_PTRN = 0x54, | |
85 | HOST_BIST_STAT = 0x58, | |
86 | HOST_MEM_BIST_STAT = 0x5c, | |
87 | HOST_FLASH_CMD = 0x70, | |
88 | /* 8 bit regs */ | |
89 | HOST_FLASH_DATA = 0x74, | |
90 | HOST_TRANSITION_DETECT = 0x75, | |
91 | HOST_GPIO_CTRL = 0x76, | |
92 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
93 | HOST_I2C_DATA = 0x7c, | |
94 | HOST_I2C_XFER_CNT = 0x7e, | |
95 | HOST_I2C_CTRL = 0x7f, | |
96 | ||
97 | /* HOST_SLOT_STAT bits */ | |
98 | HOST_SSTAT_ATTN = (1 << 31), | |
99 | ||
7dafc3fd TH |
100 | /* HOST_CTRL bits */ |
101 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ | |
102 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ | |
103 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ | |
104 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ | |
105 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ | |
d2298dca | 106 | HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ |
7dafc3fd | 107 | |
edb33667 TH |
108 | /* |
109 | * Port registers | |
110 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
111 | */ | |
112 | PORT_REGS_SIZE = 0x2000, | |
135da345 | 113 | |
28c8f3b4 | 114 | PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ |
135da345 | 115 | PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ |
edb33667 | 116 | |
28c8f3b4 | 117 | PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ |
c0c55908 TH |
118 | PORT_PMP_STATUS = 0x0000, /* port device status offset */ |
119 | PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ | |
120 | PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ | |
121 | ||
edb33667 | 122 | /* 32 bit regs */ |
83bbecc9 TH |
123 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
124 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
125 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
126 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
127 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 128 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
129 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
130 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
131 | PORT_FIS_CFG = 0x1028, |
132 | PORT_FIFO_THRES = 0x102c, | |
133 | /* 16 bit regs */ | |
134 | PORT_DECODE_ERR_CNT = 0x1040, | |
135 | PORT_DECODE_ERR_THRESH = 0x1042, | |
136 | PORT_CRC_ERR_CNT = 0x1044, | |
137 | PORT_CRC_ERR_THRESH = 0x1046, | |
138 | PORT_HSHK_ERR_CNT = 0x1048, | |
139 | PORT_HSHK_ERR_THRESH = 0x104a, | |
140 | /* 32 bit regs */ | |
141 | PORT_PHY_CFG = 0x1050, | |
142 | PORT_SLOT_STAT = 0x1800, | |
143 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
c0c55908 | 144 | PORT_CONTEXT = 0x1e04, |
edb33667 TH |
145 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
146 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
147 | PORT_SCONTROL = 0x1f00, | |
148 | PORT_SSTATUS = 0x1f04, | |
149 | PORT_SERROR = 0x1f08, | |
150 | PORT_SACTIVE = 0x1f0c, | |
151 | ||
152 | /* PORT_CTRL_STAT bits */ | |
153 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
154 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
155 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
156 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 157 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
28c8f3b4 | 158 | PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ |
e382eb1d | 159 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
28c8f3b4 | 160 | PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ |
e382eb1d | 161 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
edb33667 TH |
162 | |
163 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
164 | /* bits[11:0] are masked */ | |
165 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
166 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
167 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
168 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
169 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
170 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
7dafc3fd TH |
171 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
172 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ | |
173 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ | |
174 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ | |
175 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ | |
3b9f1d0f | 176 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
edb33667 | 177 | |
88ce7550 | 178 | DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
0542925b | 179 | PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | |
854c73a2 | 180 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, |
88ce7550 | 181 | |
edb33667 TH |
182 | /* bits[27:16] are unmasked (raw) */ |
183 | PORT_IRQ_RAW_SHIFT = 16, | |
184 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
185 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
186 | ||
187 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
188 | PORT_IRQ_STEER_SHIFT = 30, | |
189 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
190 | ||
191 | /* PORT_CMD_ERR constants */ | |
192 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
193 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
194 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
195 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
196 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
197 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
198 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
199 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
200 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
201 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
202 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
203 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
204 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
205 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
206 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
207 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
208 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
209 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
210 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
64008802 | 211 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
edb33667 | 212 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
83bbecc9 | 213 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 214 | |
d10cb35a TH |
215 | /* bits of PRB control field */ |
216 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
217 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
218 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
219 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
220 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
221 | ||
222 | /* PRB protocol field */ | |
223 | PRB_PROT_PACKET = (1 << 0), | |
224 | PRB_PROT_TCQ = (1 << 1), | |
225 | PRB_PROT_NCQ = (1 << 2), | |
226 | PRB_PROT_READ = (1 << 3), | |
227 | PRB_PROT_WRITE = (1 << 4), | |
228 | PRB_PROT_TRANSPARENT = (1 << 5), | |
229 | ||
edb33667 TH |
230 | /* |
231 | * Other constants | |
232 | */ | |
233 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
234 | SGE_LNK = (1 << 30), /* linked list |
235 | Points to SGT, not SGE */ | |
236 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
237 | data address ignored */ | |
edb33667 | 238 | |
aee10a03 TH |
239 | SIL24_MAX_CMDS = 31, |
240 | ||
edb33667 TH |
241 | /* board id */ |
242 | BID_SIL3124 = 0, | |
243 | BID_SIL3132 = 1, | |
042c21fd | 244 | BID_SIL3131 = 2, |
edb33667 | 245 | |
9466d85b | 246 | /* host flags */ |
9cbe056f SS |
247 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | |
248 | ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | | |
3a028243 | 249 | ATA_FLAG_AN | ATA_FLAG_PMP, |
37024e8e | 250 | SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ |
9466d85b | 251 | |
edb33667 TH |
252 | IRQ_STAT_4PORTS = 0xf, |
253 | }; | |
254 | ||
69ad185f | 255 | struct sil24_ata_block { |
edb33667 | 256 | struct sil24_prb prb; |
93e2618e | 257 | struct sil24_sge sge[SIL24_MAX_SGE]; |
edb33667 TH |
258 | }; |
259 | ||
69ad185f TH |
260 | struct sil24_atapi_block { |
261 | struct sil24_prb prb; | |
262 | u8 cdb[16]; | |
93e2618e | 263 | struct sil24_sge sge[SIL24_MAX_SGE]; |
69ad185f TH |
264 | }; |
265 | ||
266 | union sil24_cmd_block { | |
267 | struct sil24_ata_block ata; | |
268 | struct sil24_atapi_block atapi; | |
269 | }; | |
270 | ||
fc8cc1d5 | 271 | static const struct sil24_cerr_info { |
88ce7550 TH |
272 | unsigned int err_mask, action; |
273 | const char *desc; | |
274 | } sil24_cerr_db[] = { | |
f90f0828 | 275 | [0] = { AC_ERR_DEV, 0, |
88ce7550 | 276 | "device error" }, |
f90f0828 | 277 | [PORT_CERR_DEV] = { AC_ERR_DEV, 0, |
88ce7550 | 278 | "device error via D2H FIS" }, |
f90f0828 | 279 | [PORT_CERR_SDB] = { AC_ERR_DEV, 0, |
88ce7550 | 280 | "device error via SDB FIS" }, |
cf480626 | 281 | [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
88ce7550 | 282 | "error in data FIS" }, |
cf480626 | 283 | [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
88ce7550 | 284 | "failed to transmit command FIS" }, |
cf480626 | 285 | [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 286 | "protocol mismatch" }, |
cf480626 | 287 | [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 288 | "data directon mismatch" }, |
cf480626 | 289 | [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 290 | "ran out of SGEs while writing" }, |
cf480626 | 291 | [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 292 | "ran out of SGEs while reading" }, |
cf480626 | 293 | [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 294 | "invalid data directon for ATAPI CDB" }, |
cf480626 | 295 | [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
7293fa8f | 296 | "SGT not on qword boundary" }, |
cf480626 | 297 | [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 298 | "PCI target abort while fetching SGT" }, |
cf480626 | 299 | [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 300 | "PCI master abort while fetching SGT" }, |
cf480626 | 301 | [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 302 | "PCI parity error while fetching SGT" }, |
cf480626 | 303 | [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
88ce7550 | 304 | "PRB not on qword boundary" }, |
cf480626 | 305 | [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 306 | "PCI target abort while fetching PRB" }, |
cf480626 | 307 | [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 308 | "PCI master abort while fetching PRB" }, |
cf480626 | 309 | [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 310 | "PCI parity error while fetching PRB" }, |
cf480626 | 311 | [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 312 | "undefined error while transferring data" }, |
cf480626 | 313 | [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 314 | "PCI target abort while transferring data" }, |
cf480626 | 315 | [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 316 | "PCI master abort while transferring data" }, |
cf480626 | 317 | [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 318 | "PCI parity error while transferring data" }, |
cf480626 | 319 | [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 TH |
320 | "FIS received while sending service FIS" }, |
321 | }; | |
322 | ||
edb33667 TH |
323 | /* |
324 | * ap->private_data | |
325 | * | |
326 | * The preview driver always returned 0 for status. We emulate it | |
327 | * here from the previous interrupt. | |
328 | */ | |
329 | struct sil24_port_priv { | |
69ad185f | 330 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 331 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
23818034 | 332 | int do_port_rst; |
edb33667 TH |
333 | }; |
334 | ||
cd0d3bbc | 335 | static void sil24_dev_config(struct ata_device *dev); |
82ef04fb TH |
336 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val); |
337 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val); | |
3454dc69 | 338 | static int sil24_qc_defer(struct ata_queued_cmd *qc); |
edb33667 | 339 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 340 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
79f97dad | 341 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc); |
3454dc69 TH |
342 | static void sil24_pmp_attach(struct ata_port *ap); |
343 | static void sil24_pmp_detach(struct ata_port *ap); | |
88ce7550 TH |
344 | static void sil24_freeze(struct ata_port *ap); |
345 | static void sil24_thaw(struct ata_port *ap); | |
a1efdaba TH |
346 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
347 | unsigned long deadline); | |
348 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, | |
349 | unsigned long deadline); | |
a1efdaba TH |
350 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
351 | unsigned long deadline); | |
88ce7550 TH |
352 | static void sil24_error_handler(struct ata_port *ap); |
353 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); | |
edb33667 | 354 | static int sil24_port_start(struct ata_port *ap); |
edb33667 | 355 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
58eb8cd5 | 356 | #ifdef CONFIG_PM_SLEEP |
d2298dca | 357 | static int sil24_pci_device_resume(struct pci_dev *pdev); |
58eb8cd5 BZ |
358 | #endif |
359 | #ifdef CONFIG_PM | |
3454dc69 | 360 | static int sil24_port_resume(struct ata_port *ap); |
281d426c | 361 | #endif |
edb33667 | 362 | |
3b7d697d | 363 | static const struct pci_device_id sil24_pci_tbl[] = { |
54bb3a94 JG |
364 | { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, |
365 | { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, | |
366 | { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, | |
722d67b6 | 367 | { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, |
464b3286 | 368 | { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 }, |
54bb3a94 JG |
369 | { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, |
370 | { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, | |
371 | ||
1fcce839 | 372 | { } /* terminate list */ |
edb33667 TH |
373 | }; |
374 | ||
375 | static struct pci_driver sil24_pci_driver = { | |
376 | .name = DRV_NAME, | |
377 | .id_table = sil24_pci_tbl, | |
378 | .probe = sil24_init_one, | |
24dc5f33 | 379 | .remove = ata_pci_remove_one, |
58eb8cd5 | 380 | #ifdef CONFIG_PM_SLEEP |
d2298dca TH |
381 | .suspend = ata_pci_device_suspend, |
382 | .resume = sil24_pci_device_resume, | |
281d426c | 383 | #endif |
edb33667 TH |
384 | }; |
385 | ||
193515d5 | 386 | static struct scsi_host_template sil24_sht = { |
68d1d07b | 387 | ATA_NCQ_SHT(DRV_NAME), |
aee10a03 | 388 | .can_queue = SIL24_MAX_CMDS, |
93e2618e | 389 | .sg_tablesize = SIL24_MAX_SGE, |
edb33667 | 390 | .dma_boundary = ATA_DMA_BOUNDARY, |
9269e234 | 391 | .tag_alloc_policy = BLK_TAG_ALLOC_FIFO, |
edb33667 TH |
392 | }; |
393 | ||
029cfd6b TH |
394 | static struct ata_port_operations sil24_ops = { |
395 | .inherits = &sata_pmp_port_ops, | |
69ad185f | 396 | |
3454dc69 | 397 | .qc_defer = sil24_qc_defer, |
edb33667 TH |
398 | .qc_prep = sil24_qc_prep, |
399 | .qc_issue = sil24_qc_issue, | |
79f97dad | 400 | .qc_fill_rtf = sil24_qc_fill_rtf, |
edb33667 | 401 | |
029cfd6b TH |
402 | .freeze = sil24_freeze, |
403 | .thaw = sil24_thaw, | |
a1efdaba TH |
404 | .softreset = sil24_softreset, |
405 | .hardreset = sil24_hardreset, | |
071f44b1 | 406 | .pmp_softreset = sil24_softreset, |
a1efdaba | 407 | .pmp_hardreset = sil24_pmp_hardreset, |
029cfd6b TH |
408 | .error_handler = sil24_error_handler, |
409 | .post_internal_cmd = sil24_post_internal_cmd, | |
410 | .dev_config = sil24_dev_config, | |
edb33667 TH |
411 | |
412 | .scr_read = sil24_scr_read, | |
413 | .scr_write = sil24_scr_write, | |
3454dc69 TH |
414 | .pmp_attach = sil24_pmp_attach, |
415 | .pmp_detach = sil24_pmp_detach, | |
3454dc69 | 416 | |
edb33667 | 417 | .port_start = sil24_port_start, |
3454dc69 TH |
418 | #ifdef CONFIG_PM |
419 | .port_resume = sil24_port_resume, | |
420 | #endif | |
edb33667 TH |
421 | }; |
422 | ||
90ab5ee9 | 423 | static bool sata_sil24_msi; /* Disable MSI */ |
dae77214 VM |
424 | module_param_named(msi, sata_sil24_msi, bool, S_IRUGO); |
425 | MODULE_PARM_DESC(msi, "Enable MSI (Default: false)"); | |
426 | ||
042c21fd | 427 | /* |
cca3974e | 428 | * Use bits 30-31 of port_flags to encode available port numbers. |
042c21fd TH |
429 | * Current maxium is 4. |
430 | */ | |
431 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
432 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
433 | ||
4447d351 | 434 | static const struct ata_port_info sil24_port_info[] = { |
edb33667 TH |
435 | /* sil_3124 */ |
436 | { | |
cca3974e | 437 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | |
37024e8e | 438 | SIL24_FLAG_PCIX_IRQ_WOC, |
14bdef98 EIB |
439 | .pio_mask = ATA_PIO4, |
440 | .mwdma_mask = ATA_MWDMA2, | |
441 | .udma_mask = ATA_UDMA5, | |
edb33667 TH |
442 | .port_ops = &sil24_ops, |
443 | }, | |
2e9edbf8 | 444 | /* sil_3132 */ |
edb33667 | 445 | { |
cca3974e | 446 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
14bdef98 EIB |
447 | .pio_mask = ATA_PIO4, |
448 | .mwdma_mask = ATA_MWDMA2, | |
449 | .udma_mask = ATA_UDMA5, | |
042c21fd TH |
450 | .port_ops = &sil24_ops, |
451 | }, | |
452 | /* sil_3131/sil_3531 */ | |
453 | { | |
cca3974e | 454 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
14bdef98 EIB |
455 | .pio_mask = ATA_PIO4, |
456 | .mwdma_mask = ATA_MWDMA2, | |
457 | .udma_mask = ATA_UDMA5, | |
edb33667 TH |
458 | .port_ops = &sil24_ops, |
459 | }, | |
460 | }; | |
461 | ||
aee10a03 TH |
462 | static int sil24_tag(int tag) |
463 | { | |
464 | if (unlikely(ata_tag_internal(tag))) | |
465 | return 0; | |
466 | return tag; | |
467 | } | |
468 | ||
350756f6 TH |
469 | static unsigned long sil24_port_offset(struct ata_port *ap) |
470 | { | |
471 | return ap->port_no * PORT_REGS_SIZE; | |
472 | } | |
473 | ||
474 | static void __iomem *sil24_port_base(struct ata_port *ap) | |
475 | { | |
476 | return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap); | |
477 | } | |
478 | ||
cd0d3bbc | 479 | static void sil24_dev_config(struct ata_device *dev) |
69ad185f | 480 | { |
350756f6 | 481 | void __iomem *port = sil24_port_base(dev->link->ap); |
69ad185f | 482 | |
6e7846e9 | 483 | if (dev->cdb_len == 16) |
69ad185f TH |
484 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
485 | else | |
486 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
487 | } | |
488 | ||
e59f0dad | 489 | static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf) |
6a575fa9 | 490 | { |
350756f6 | 491 | void __iomem *port = sil24_port_base(ap); |
e59f0dad | 492 | struct sil24_prb __iomem *prb; |
4b4a5eae | 493 | u8 fis[6 * 4]; |
6a575fa9 | 494 | |
e59f0dad TH |
495 | prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ; |
496 | memcpy_fromio(fis, prb->fis, sizeof(fis)); | |
497 | ata_tf_from_fis(fis, tf); | |
6a575fa9 TH |
498 | } |
499 | ||
edb33667 TH |
500 | static int sil24_scr_map[] = { |
501 | [SCR_CONTROL] = 0, | |
502 | [SCR_STATUS] = 1, | |
503 | [SCR_ERROR] = 2, | |
504 | [SCR_ACTIVE] = 3, | |
505 | }; | |
506 | ||
82ef04fb | 507 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) |
edb33667 | 508 | { |
82ef04fb | 509 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
da3dbb17 | 510 | |
edb33667 | 511 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
da3dbb17 TH |
512 | *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); |
513 | return 0; | |
edb33667 | 514 | } |
da3dbb17 | 515 | return -EINVAL; |
edb33667 TH |
516 | } |
517 | ||
82ef04fb | 518 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) |
edb33667 | 519 | { |
82ef04fb | 520 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
da3dbb17 | 521 | |
edb33667 | 522 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
edb33667 | 523 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); |
da3dbb17 | 524 | return 0; |
edb33667 | 525 | } |
da3dbb17 | 526 | return -EINVAL; |
edb33667 TH |
527 | } |
528 | ||
23818034 TH |
529 | static void sil24_config_port(struct ata_port *ap) |
530 | { | |
350756f6 | 531 | void __iomem *port = sil24_port_base(ap); |
23818034 TH |
532 | |
533 | /* configure IRQ WoC */ | |
534 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
535 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); | |
536 | else | |
537 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
538 | ||
539 | /* zero error counters. */ | |
7a4f876b CT |
540 | writew(0x8000, port + PORT_DECODE_ERR_THRESH); |
541 | writew(0x8000, port + PORT_CRC_ERR_THRESH); | |
542 | writew(0x8000, port + PORT_HSHK_ERR_THRESH); | |
543 | writew(0x0000, port + PORT_DECODE_ERR_CNT); | |
544 | writew(0x0000, port + PORT_CRC_ERR_CNT); | |
545 | writew(0x0000, port + PORT_HSHK_ERR_CNT); | |
23818034 TH |
546 | |
547 | /* always use 64bit activation */ | |
548 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); | |
549 | ||
550 | /* clear port multiplier enable and resume bits */ | |
551 | writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); | |
552 | } | |
553 | ||
3454dc69 TH |
554 | static void sil24_config_pmp(struct ata_port *ap, int attached) |
555 | { | |
350756f6 | 556 | void __iomem *port = sil24_port_base(ap); |
3454dc69 TH |
557 | |
558 | if (attached) | |
559 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); | |
560 | else | |
561 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); | |
562 | } | |
563 | ||
564 | static void sil24_clear_pmp(struct ata_port *ap) | |
565 | { | |
350756f6 | 566 | void __iomem *port = sil24_port_base(ap); |
3454dc69 TH |
567 | int i; |
568 | ||
569 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); | |
570 | ||
571 | for (i = 0; i < SATA_PMP_MAX_PORTS; i++) { | |
572 | void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE; | |
573 | ||
574 | writel(0, pmp_base + PORT_PMP_STATUS); | |
575 | writel(0, pmp_base + PORT_PMP_QACTIVE); | |
576 | } | |
577 | } | |
578 | ||
b5bc421c TH |
579 | static int sil24_init_port(struct ata_port *ap) |
580 | { | |
350756f6 | 581 | void __iomem *port = sil24_port_base(ap); |
23818034 | 582 | struct sil24_port_priv *pp = ap->private_data; |
b5bc421c TH |
583 | u32 tmp; |
584 | ||
3454dc69 | 585 | /* clear PMP error status */ |
071f44b1 | 586 | if (sata_pmp_attached(ap)) |
3454dc69 TH |
587 | sil24_clear_pmp(ap); |
588 | ||
b5bc421c | 589 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); |
97750ceb | 590 | ata_wait_register(ap, port + PORT_CTRL_STAT, |
b5bc421c | 591 | PORT_CS_INIT, PORT_CS_INIT, 10, 100); |
97750ceb | 592 | tmp = ata_wait_register(ap, port + PORT_CTRL_STAT, |
b5bc421c TH |
593 | PORT_CS_RDY, 0, 10, 100); |
594 | ||
23818034 TH |
595 | if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { |
596 | pp->do_port_rst = 1; | |
cf480626 | 597 | ap->link.eh_context.i.action |= ATA_EH_RESET; |
b5bc421c | 598 | return -EIO; |
23818034 TH |
599 | } |
600 | ||
b5bc421c TH |
601 | return 0; |
602 | } | |
603 | ||
37b99cba TH |
604 | static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, |
605 | const struct ata_taskfile *tf, | |
606 | int is_cmd, u32 ctrl, | |
607 | unsigned long timeout_msec) | |
edb33667 | 608 | { |
350756f6 | 609 | void __iomem *port = sil24_port_base(ap); |
ca45160d | 610 | struct sil24_port_priv *pp = ap->private_data; |
69ad185f | 611 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d | 612 | dma_addr_t paddr = pp->cmd_block_dma; |
37b99cba TH |
613 | u32 irq_enabled, irq_mask, irq_stat; |
614 | int rc; | |
615 | ||
616 | prb->ctrl = cpu_to_le16(ctrl); | |
617 | ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); | |
618 | ||
619 | /* temporarily plug completion and error interrupts */ | |
620 | irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); | |
621 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); | |
622 | ||
10823452 CM |
623 | /* |
624 | * The barrier is required to ensure that writes to cmd_block reach | |
625 | * the memory before the write to PORT_CMD_ACTIVATE. | |
626 | */ | |
627 | wmb(); | |
37b99cba TH |
628 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
629 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); | |
630 | ||
631 | irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; | |
97750ceb | 632 | irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0, |
37b99cba TH |
633 | 10, timeout_msec); |
634 | ||
635 | writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ | |
636 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
637 | ||
638 | if (irq_stat & PORT_IRQ_COMPLETE) | |
639 | rc = 0; | |
640 | else { | |
641 | /* force port into known state */ | |
642 | sil24_init_port(ap); | |
643 | ||
644 | if (irq_stat & PORT_IRQ_ERROR) | |
645 | rc = -EIO; | |
646 | else | |
647 | rc = -EBUSY; | |
648 | } | |
649 | ||
650 | /* restore IRQ enabled */ | |
651 | writel(irq_enabled, port + PORT_IRQ_ENABLE_SET); | |
652 | ||
653 | return rc; | |
654 | } | |
655 | ||
071f44b1 TH |
656 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
657 | unsigned long deadline) | |
37b99cba | 658 | { |
cc0680a5 | 659 | struct ata_port *ap = link->ap; |
071f44b1 | 660 | int pmp = sata_srst_pmp(link); |
37b99cba | 661 | unsigned long timeout_msec = 0; |
e59f0dad | 662 | struct ata_taskfile tf; |
643be977 | 663 | const char *reason; |
37b99cba | 664 | int rc; |
ca45160d | 665 | |
07b73470 TH |
666 | DPRINTK("ENTER\n"); |
667 | ||
2555d6c2 TH |
668 | /* put the port into known state */ |
669 | if (sil24_init_port(ap)) { | |
5796d1c4 | 670 | reason = "port not ready"; |
2555d6c2 TH |
671 | goto err; |
672 | } | |
673 | ||
0eaa6058 | 674 | /* do SRST */ |
37b99cba TH |
675 | if (time_after(deadline, jiffies)) |
676 | timeout_msec = jiffies_to_msecs(deadline - jiffies); | |
ca45160d | 677 | |
cc0680a5 | 678 | ata_tf_init(link->device, &tf); /* doesn't really matter */ |
975530e8 TH |
679 | rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST, |
680 | timeout_msec); | |
37b99cba TH |
681 | if (rc == -EBUSY) { |
682 | reason = "timeout"; | |
683 | goto err; | |
684 | } else if (rc) { | |
685 | reason = "SRST command error"; | |
643be977 | 686 | goto err; |
07b73470 | 687 | } |
10d996ad | 688 | |
e59f0dad TH |
689 | sil24_read_tf(ap, 0, &tf); |
690 | *class = ata_dev_classify(&tf); | |
10d996ad | 691 | |
07b73470 | 692 | DPRINTK("EXIT, class=%u\n", *class); |
ca45160d | 693 | return 0; |
643be977 TH |
694 | |
695 | err: | |
a9a79dfe | 696 | ata_link_err(link, "softreset failed (%s)\n", reason); |
643be977 | 697 | return -EIO; |
ca45160d TH |
698 | } |
699 | ||
cc0680a5 | 700 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 701 | unsigned long deadline) |
489ff4c7 | 702 | { |
cc0680a5 | 703 | struct ata_port *ap = link->ap; |
350756f6 | 704 | void __iomem *port = sil24_port_base(ap); |
23818034 TH |
705 | struct sil24_port_priv *pp = ap->private_data; |
706 | int did_port_rst = 0; | |
ecc2e2b9 | 707 | const char *reason; |
e8e008e7 | 708 | int tout_msec, rc; |
ecc2e2b9 TH |
709 | u32 tmp; |
710 | ||
23818034 TH |
711 | retry: |
712 | /* Sometimes, DEV_RST is not enough to recover the controller. | |
713 | * This happens often after PM DMA CS errata. | |
714 | */ | |
715 | if (pp->do_port_rst) { | |
a9a79dfe JP |
716 | ata_port_warn(ap, |
717 | "controller in dubious state, performing PORT_RST\n"); | |
23818034 TH |
718 | |
719 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); | |
97750ceb | 720 | ata_msleep(ap, 10); |
23818034 | 721 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); |
97750ceb | 722 | ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0, |
23818034 TH |
723 | 10, 5000); |
724 | ||
725 | /* restore port configuration */ | |
726 | sil24_config_port(ap); | |
727 | sil24_config_pmp(ap, ap->nr_pmp_links); | |
728 | ||
729 | pp->do_port_rst = 0; | |
730 | did_port_rst = 1; | |
731 | } | |
732 | ||
ecc2e2b9 | 733 | /* sil24 does the right thing(tm) without any protection */ |
cc0680a5 | 734 | sata_set_spd(link); |
ecc2e2b9 TH |
735 | |
736 | tout_msec = 100; | |
cc0680a5 | 737 | if (ata_link_online(link)) |
ecc2e2b9 TH |
738 | tout_msec = 5000; |
739 | ||
740 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
97750ceb | 741 | tmp = ata_wait_register(ap, port + PORT_CTRL_STAT, |
5796d1c4 JG |
742 | PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, |
743 | tout_msec); | |
ecc2e2b9 | 744 | |
e8e008e7 TH |
745 | /* SStatus oscillates between zero and valid status after |
746 | * DEV_RST, debounce it. | |
ecc2e2b9 | 747 | */ |
cc0680a5 | 748 | rc = sata_link_debounce(link, sata_deb_timing_long, deadline); |
e8e008e7 TH |
749 | if (rc) { |
750 | reason = "PHY debouncing failed"; | |
751 | goto err; | |
752 | } | |
ecc2e2b9 TH |
753 | |
754 | if (tmp & PORT_CS_DEV_RST) { | |
cc0680a5 | 755 | if (ata_link_offline(link)) |
ecc2e2b9 TH |
756 | return 0; |
757 | reason = "link not ready"; | |
758 | goto err; | |
759 | } | |
760 | ||
e8e008e7 TH |
761 | /* Sil24 doesn't store signature FIS after hardreset, so we |
762 | * can't wait for BSY to clear. Some devices take a long time | |
763 | * to get ready and those devices will choke if we don't wait | |
764 | * for BSY clearance here. Tell libata to perform follow-up | |
765 | * softreset. | |
ecc2e2b9 | 766 | */ |
e8e008e7 | 767 | return -EAGAIN; |
ecc2e2b9 TH |
768 | |
769 | err: | |
23818034 TH |
770 | if (!did_port_rst) { |
771 | pp->do_port_rst = 1; | |
772 | goto retry; | |
773 | } | |
774 | ||
a9a79dfe | 775 | ata_link_err(link, "hardreset failed (%s)\n", reason); |
ecc2e2b9 | 776 | return -EIO; |
489ff4c7 TH |
777 | } |
778 | ||
edb33667 | 779 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
69ad185f | 780 | struct sil24_sge *sge) |
edb33667 | 781 | { |
972c26bd | 782 | struct scatterlist *sg; |
3be6cbd7 | 783 | struct sil24_sge *last_sge = NULL; |
ff2aeb1e | 784 | unsigned int si; |
edb33667 | 785 | |
ff2aeb1e | 786 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
edb33667 TH |
787 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
788 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
3be6cbd7 JG |
789 | sge->flags = 0; |
790 | ||
791 | last_sge = sge; | |
972c26bd | 792 | sge++; |
edb33667 | 793 | } |
3be6cbd7 | 794 | |
ff2aeb1e | 795 | last_sge->flags = cpu_to_le32(SGE_TRM); |
edb33667 TH |
796 | } |
797 | ||
3454dc69 TH |
798 | static int sil24_qc_defer(struct ata_queued_cmd *qc) |
799 | { | |
800 | struct ata_link *link = qc->dev->link; | |
801 | struct ata_port *ap = link->ap; | |
802 | u8 prot = qc->tf.protocol; | |
13cc546b GG |
803 | |
804 | /* | |
805 | * There is a bug in the chip: | |
806 | * Port LRAM Causes the PRB/SGT Data to be Corrupted | |
807 | * If the host issues a read request for LRAM and SActive registers | |
808 | * while active commands are available in the port, PRB/SGT data in | |
809 | * the LRAM can become corrupted. This issue applies only when | |
810 | * reading from, but not writing to, the LRAM. | |
811 | * | |
812 | * Therefore, reading LRAM when there is no particular error [and | |
813 | * other commands may be outstanding] is prohibited. | |
814 | * | |
815 | * To avoid this bug there are two situations where a command must run | |
816 | * exclusive of any other commands on the port: | |
817 | * | |
818 | * - ATAPI commands which check the sense data | |
819 | * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF | |
820 | * set. | |
821 | * | |
822 | */ | |
405e66b3 | 823 | int is_excl = (ata_is_atapi(prot) || |
13cc546b GG |
824 | (qc->flags & ATA_QCFLAG_RESULT_TF)); |
825 | ||
3454dc69 TH |
826 | if (unlikely(ap->excl_link)) { |
827 | if (link == ap->excl_link) { | |
828 | if (ap->nr_active_links) | |
829 | return ATA_DEFER_PORT; | |
830 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
831 | } else | |
832 | return ATA_DEFER_PORT; | |
13cc546b | 833 | } else if (unlikely(is_excl)) { |
3454dc69 TH |
834 | ap->excl_link = link; |
835 | if (ap->nr_active_links) | |
836 | return ATA_DEFER_PORT; | |
837 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
838 | } | |
839 | ||
840 | return ata_std_qc_defer(qc); | |
841 | } | |
842 | ||
edb33667 TH |
843 | static void sil24_qc_prep(struct ata_queued_cmd *qc) |
844 | { | |
845 | struct ata_port *ap = qc->ap; | |
846 | struct sil24_port_priv *pp = ap->private_data; | |
aee10a03 | 847 | union sil24_cmd_block *cb; |
69ad185f TH |
848 | struct sil24_prb *prb; |
849 | struct sil24_sge *sge; | |
bad28a37 | 850 | u16 ctrl = 0; |
edb33667 | 851 | |
aee10a03 TH |
852 | cb = &pp->cmd_block[sil24_tag(qc->tag)]; |
853 | ||
405e66b3 | 854 | if (!ata_is_atapi(qc->tf.protocol)) { |
69ad185f TH |
855 | prb = &cb->ata.prb; |
856 | sge = cb->ata.sge; | |
4f1a0ee1 RH |
857 | if (ata_is_data(qc->tf.protocol)) { |
858 | u16 prot = 0; | |
859 | ctrl = PRB_CTRL_PROTOCOL; | |
860 | if (ata_is_ncq(qc->tf.protocol)) | |
861 | prot |= PRB_PROT_NCQ; | |
862 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
863 | prot |= PRB_PROT_WRITE; | |
864 | else | |
865 | prot |= PRB_PROT_READ; | |
866 | prb->prot = cpu_to_le16(prot); | |
867 | } | |
405e66b3 | 868 | } else { |
69ad185f TH |
869 | prb = &cb->atapi.prb; |
870 | sge = cb->atapi.sge; | |
14e45c15 | 871 | memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb)); |
6e7846e9 | 872 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
69ad185f | 873 | |
405e66b3 | 874 | if (ata_is_data(qc->tf.protocol)) { |
69ad185f | 875 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
bad28a37 | 876 | ctrl = PRB_CTRL_PACKET_WRITE; |
69ad185f | 877 | else |
bad28a37 TH |
878 | ctrl = PRB_CTRL_PACKET_READ; |
879 | } | |
edb33667 TH |
880 | } |
881 | ||
bad28a37 | 882 | prb->ctrl = cpu_to_le16(ctrl); |
3454dc69 | 883 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); |
edb33667 TH |
884 | |
885 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 886 | sil24_fill_sg(qc, sge); |
edb33667 TH |
887 | } |
888 | ||
9a3d9eb0 | 889 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
890 | { |
891 | struct ata_port *ap = qc->ap; | |
892 | struct sil24_port_priv *pp = ap->private_data; | |
350756f6 | 893 | void __iomem *port = sil24_port_base(ap); |
aee10a03 TH |
894 | unsigned int tag = sil24_tag(qc->tag); |
895 | dma_addr_t paddr; | |
896 | void __iomem *activate; | |
edb33667 | 897 | |
aee10a03 TH |
898 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); |
899 | activate = port + PORT_CMD_ACTIVATE + tag * 8; | |
900 | ||
10823452 CM |
901 | /* |
902 | * The barrier is required to ensure that writes to cmd_block reach | |
903 | * the memory before the write to PORT_CMD_ACTIVATE. | |
904 | */ | |
905 | wmb(); | |
aee10a03 TH |
906 | writel((u32)paddr, activate); |
907 | writel((u64)paddr >> 32, activate + 4); | |
26ec634c | 908 | |
edb33667 TH |
909 | return 0; |
910 | } | |
911 | ||
79f97dad TH |
912 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc) |
913 | { | |
914 | sil24_read_tf(qc->ap, qc->tag, &qc->result_tf); | |
915 | return true; | |
916 | } | |
917 | ||
3454dc69 TH |
918 | static void sil24_pmp_attach(struct ata_port *ap) |
919 | { | |
906c1ff4 TH |
920 | u32 *gscr = ap->link.device->gscr; |
921 | ||
3454dc69 TH |
922 | sil24_config_pmp(ap, 1); |
923 | sil24_init_port(ap); | |
906c1ff4 TH |
924 | |
925 | if (sata_pmp_gscr_vendor(gscr) == 0x11ab && | |
926 | sata_pmp_gscr_devid(gscr) == 0x4140) { | |
a9a79dfe | 927 | ata_port_info(ap, |
906c1ff4 TH |
928 | "disabling NCQ support due to sil24-mv4140 quirk\n"); |
929 | ap->flags &= ~ATA_FLAG_NCQ; | |
930 | } | |
3454dc69 TH |
931 | } |
932 | ||
933 | static void sil24_pmp_detach(struct ata_port *ap) | |
934 | { | |
935 | sil24_init_port(ap); | |
936 | sil24_config_pmp(ap, 0); | |
906c1ff4 TH |
937 | |
938 | ap->flags |= ATA_FLAG_NCQ; | |
3454dc69 TH |
939 | } |
940 | ||
3454dc69 TH |
941 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
942 | unsigned long deadline) | |
943 | { | |
944 | int rc; | |
945 | ||
946 | rc = sil24_init_port(link->ap); | |
947 | if (rc) { | |
a9a79dfe | 948 | ata_link_err(link, "hardreset failed (port not ready)\n"); |
3454dc69 TH |
949 | return rc; |
950 | } | |
951 | ||
5958e302 | 952 | return sata_std_hardreset(link, class, deadline); |
3454dc69 TH |
953 | } |
954 | ||
88ce7550 | 955 | static void sil24_freeze(struct ata_port *ap) |
7d1ce682 | 956 | { |
350756f6 | 957 | void __iomem *port = sil24_port_base(ap); |
7d1ce682 | 958 | |
88ce7550 TH |
959 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear |
960 | * PORT_IRQ_ENABLE instead. | |
961 | */ | |
962 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
7d1ce682 TH |
963 | } |
964 | ||
88ce7550 | 965 | static void sil24_thaw(struct ata_port *ap) |
edb33667 | 966 | { |
350756f6 | 967 | void __iomem *port = sil24_port_base(ap); |
edb33667 TH |
968 | u32 tmp; |
969 | ||
88ce7550 TH |
970 | /* clear IRQ */ |
971 | tmp = readl(port + PORT_IRQ_STAT); | |
972 | writel(tmp, port + PORT_IRQ_STAT); | |
edb33667 | 973 | |
88ce7550 TH |
974 | /* turn IRQ back on */ |
975 | writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); | |
edb33667 TH |
976 | } |
977 | ||
88ce7550 | 978 | static void sil24_error_intr(struct ata_port *ap) |
8746618d | 979 | { |
350756f6 | 980 | void __iomem *port = sil24_port_base(ap); |
e59f0dad | 981 | struct sil24_port_priv *pp = ap->private_data; |
3454dc69 TH |
982 | struct ata_queued_cmd *qc = NULL; |
983 | struct ata_link *link; | |
984 | struct ata_eh_info *ehi; | |
985 | int abort = 0, freeze = 0; | |
88ce7550 | 986 | u32 irq_stat; |
8746618d | 987 | |
88ce7550 | 988 | /* on error, we need to clear IRQ explicitly */ |
8746618d | 989 | irq_stat = readl(port + PORT_IRQ_STAT); |
88ce7550 | 990 | writel(irq_stat, port + PORT_IRQ_STAT); |
ad6e90f6 | 991 | |
88ce7550 | 992 | /* first, analyze and record host port events */ |
3454dc69 TH |
993 | link = &ap->link; |
994 | ehi = &link->eh_info; | |
88ce7550 | 995 | ata_ehi_clear_desc(ehi); |
ad6e90f6 | 996 | |
88ce7550 | 997 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
8746618d | 998 | |
854c73a2 | 999 | if (irq_stat & PORT_IRQ_SDB_NOTIFY) { |
854c73a2 | 1000 | ata_ehi_push_desc(ehi, "SDB notify"); |
7d77b247 | 1001 | sata_async_notification(ap); |
854c73a2 TH |
1002 | } |
1003 | ||
0542925b TH |
1004 | if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { |
1005 | ata_ehi_hotplugged(ehi); | |
b64bbc39 TH |
1006 | ata_ehi_push_desc(ehi, "%s", |
1007 | irq_stat & PORT_IRQ_PHYRDY_CHG ? | |
1008 | "PHY RDY changed" : "device exchanged"); | |
88ce7550 | 1009 | freeze = 1; |
6a575fa9 TH |
1010 | } |
1011 | ||
88ce7550 TH |
1012 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
1013 | ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 1014 | ehi->action |= ATA_EH_RESET; |
b64bbc39 | 1015 | ata_ehi_push_desc(ehi, "unknown FIS"); |
88ce7550 TH |
1016 | freeze = 1; |
1017 | } | |
1018 | ||
1019 | /* deal with command error */ | |
1020 | if (irq_stat & PORT_IRQ_ERROR) { | |
fc8cc1d5 | 1021 | const struct sil24_cerr_info *ci = NULL; |
88ce7550 | 1022 | unsigned int err_mask = 0, action = 0; |
3454dc69 TH |
1023 | u32 context, cerr; |
1024 | int pmp; | |
1025 | ||
1026 | abort = 1; | |
1027 | ||
1028 | /* DMA Context Switch Failure in Port Multiplier Mode | |
1029 | * errata. If we have active commands to 3 or more | |
1030 | * devices, any error condition on active devices can | |
1031 | * corrupt DMA context switching. | |
1032 | */ | |
1033 | if (ap->nr_active_links >= 3) { | |
1034 | ehi->err_mask |= AC_ERR_OTHER; | |
cf480626 | 1035 | ehi->action |= ATA_EH_RESET; |
3454dc69 | 1036 | ata_ehi_push_desc(ehi, "PMP DMA CS errata"); |
23818034 | 1037 | pp->do_port_rst = 1; |
3454dc69 TH |
1038 | freeze = 1; |
1039 | } | |
1040 | ||
1041 | /* find out the offending link and qc */ | |
071f44b1 | 1042 | if (sata_pmp_attached(ap)) { |
3454dc69 TH |
1043 | context = readl(port + PORT_CONTEXT); |
1044 | pmp = (context >> 5) & 0xf; | |
1045 | ||
1046 | if (pmp < ap->nr_pmp_links) { | |
1047 | link = &ap->pmp_link[pmp]; | |
1048 | ehi = &link->eh_info; | |
1049 | qc = ata_qc_from_tag(ap, link->active_tag); | |
1050 | ||
1051 | ata_ehi_clear_desc(ehi); | |
1052 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", | |
1053 | irq_stat); | |
1054 | } else { | |
1055 | err_mask |= AC_ERR_HSM; | |
cf480626 | 1056 | action |= ATA_EH_RESET; |
3454dc69 TH |
1057 | freeze = 1; |
1058 | } | |
1059 | } else | |
1060 | qc = ata_qc_from_tag(ap, link->active_tag); | |
88ce7550 TH |
1061 | |
1062 | /* analyze CMD_ERR */ | |
1063 | cerr = readl(port + PORT_CMD_ERR); | |
1064 | if (cerr < ARRAY_SIZE(sil24_cerr_db)) | |
1065 | ci = &sil24_cerr_db[cerr]; | |
1066 | ||
1067 | if (ci && ci->desc) { | |
1068 | err_mask |= ci->err_mask; | |
1069 | action |= ci->action; | |
cf480626 | 1070 | if (action & ATA_EH_RESET) |
c2e14f11 | 1071 | freeze = 1; |
b64bbc39 | 1072 | ata_ehi_push_desc(ehi, "%s", ci->desc); |
88ce7550 TH |
1073 | } else { |
1074 | err_mask |= AC_ERR_OTHER; | |
cf480626 | 1075 | action |= ATA_EH_RESET; |
c2e14f11 | 1076 | freeze = 1; |
b64bbc39 | 1077 | ata_ehi_push_desc(ehi, "unknown command error %d", |
88ce7550 TH |
1078 | cerr); |
1079 | } | |
1080 | ||
1081 | /* record error info */ | |
520d06f9 | 1082 | if (qc) |
88ce7550 | 1083 | qc->err_mask |= err_mask; |
520d06f9 | 1084 | else |
88ce7550 TH |
1085 | ehi->err_mask |= err_mask; |
1086 | ||
1087 | ehi->action |= action; | |
3454dc69 TH |
1088 | |
1089 | /* if PMP, resume */ | |
071f44b1 | 1090 | if (sata_pmp_attached(ap)) |
3454dc69 | 1091 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT); |
a22e2eb0 | 1092 | } |
88ce7550 TH |
1093 | |
1094 | /* freeze or abort */ | |
1095 | if (freeze) | |
1096 | ata_port_freeze(ap); | |
3454dc69 TH |
1097 | else if (abort) { |
1098 | if (qc) | |
1099 | ata_link_abort(qc->dev->link); | |
1100 | else | |
1101 | ata_port_abort(ap); | |
1102 | } | |
8746618d TH |
1103 | } |
1104 | ||
edb33667 TH |
1105 | static inline void sil24_host_intr(struct ata_port *ap) |
1106 | { | |
350756f6 | 1107 | void __iomem *port = sil24_port_base(ap); |
aee10a03 TH |
1108 | u32 slot_stat, qc_active; |
1109 | int rc; | |
edb33667 | 1110 | |
228f47b9 TH |
1111 | /* If PCIX_IRQ_WOC, there's an inherent race window between |
1112 | * clearing IRQ pending status and reading PORT_SLOT_STAT | |
1113 | * which may cause spurious interrupts afterwards. This is | |
1114 | * unavoidable and much better than losing interrupts which | |
1115 | * happens if IRQ pending is cleared after reading | |
1116 | * PORT_SLOT_STAT. | |
1117 | */ | |
1118 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
1119 | writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); | |
1120 | ||
edb33667 | 1121 | slot_stat = readl(port + PORT_SLOT_STAT); |
37024e8e | 1122 | |
88ce7550 TH |
1123 | if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { |
1124 | sil24_error_intr(ap); | |
1125 | return; | |
1126 | } | |
1127 | ||
aee10a03 | 1128 | qc_active = slot_stat & ~HOST_SSTAT_ATTN; |
79f97dad | 1129 | rc = ata_qc_complete_multiple(ap, qc_active); |
aee10a03 TH |
1130 | if (rc > 0) |
1131 | return; | |
1132 | if (rc < 0) { | |
9af5c9c9 | 1133 | struct ata_eh_info *ehi = &ap->link.eh_info; |
aee10a03 | 1134 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 1135 | ehi->action |= ATA_EH_RESET; |
aee10a03 | 1136 | ata_port_freeze(ap); |
88ce7550 TH |
1137 | return; |
1138 | } | |
1139 | ||
228f47b9 TH |
1140 | /* spurious interrupts are expected if PCIX_IRQ_WOC */ |
1141 | if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) | |
a9a79dfe JP |
1142 | ata_port_info(ap, |
1143 | "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n", | |
9af5c9c9 | 1144 | slot_stat, ap->link.active_tag, ap->link.sactive); |
edb33667 TH |
1145 | } |
1146 | ||
7d12e780 | 1147 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) |
edb33667 | 1148 | { |
cca3974e | 1149 | struct ata_host *host = dev_instance; |
0d5ff566 | 1150 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
edb33667 TH |
1151 | unsigned handled = 0; |
1152 | u32 status; | |
1153 | int i; | |
1154 | ||
0d5ff566 | 1155 | status = readl(host_base + HOST_IRQ_STAT); |
edb33667 | 1156 | |
06460aea | 1157 | if (status == 0xffffffff) { |
11838230 TS |
1158 | dev_err(host->dev, "IRQ status == 0xffffffff, " |
1159 | "PCI fault or device removal?\n"); | |
06460aea TH |
1160 | goto out; |
1161 | } | |
1162 | ||
edb33667 TH |
1163 | if (!(status & IRQ_STAT_4PORTS)) |
1164 | goto out; | |
1165 | ||
cca3974e | 1166 | spin_lock(&host->lock); |
edb33667 | 1167 | |
cca3974e | 1168 | for (i = 0; i < host->n_ports; i++) |
edb33667 | 1169 | if (status & (1 << i)) { |
3e4ec344 TH |
1170 | sil24_host_intr(host->ports[i]); |
1171 | handled++; | |
edb33667 TH |
1172 | } |
1173 | ||
cca3974e | 1174 | spin_unlock(&host->lock); |
edb33667 TH |
1175 | out: |
1176 | return IRQ_RETVAL(handled); | |
1177 | } | |
1178 | ||
88ce7550 TH |
1179 | static void sil24_error_handler(struct ata_port *ap) |
1180 | { | |
23818034 TH |
1181 | struct sil24_port_priv *pp = ap->private_data; |
1182 | ||
3454dc69 | 1183 | if (sil24_init_port(ap)) |
88ce7550 | 1184 | ata_eh_freeze_port(ap); |
88ce7550 | 1185 | |
a1efdaba | 1186 | sata_pmp_error_handler(ap); |
23818034 TH |
1187 | |
1188 | pp->do_port_rst = 0; | |
88ce7550 TH |
1189 | } |
1190 | ||
1191 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) | |
1192 | { | |
1193 | struct ata_port *ap = qc->ap; | |
1194 | ||
88ce7550 | 1195 | /* make DMA engine forget about the failed command */ |
3454dc69 TH |
1196 | if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) |
1197 | ata_eh_freeze_port(ap); | |
88ce7550 TH |
1198 | } |
1199 | ||
edb33667 TH |
1200 | static int sil24_port_start(struct ata_port *ap) |
1201 | { | |
cca3974e | 1202 | struct device *dev = ap->host->dev; |
edb33667 | 1203 | struct sil24_port_priv *pp; |
69ad185f | 1204 | union sil24_cmd_block *cb; |
aee10a03 | 1205 | size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; |
edb33667 TH |
1206 | dma_addr_t cb_dma; |
1207 | ||
24dc5f33 | 1208 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
edb33667 | 1209 | if (!pp) |
24dc5f33 | 1210 | return -ENOMEM; |
edb33667 | 1211 | |
24dc5f33 | 1212 | cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb | 1213 | if (!cb) |
24dc5f33 | 1214 | return -ENOMEM; |
edb33667 TH |
1215 | memset(cb, 0, cb_size); |
1216 | ||
edb33667 TH |
1217 | pp->cmd_block = cb; |
1218 | pp->cmd_block_dma = cb_dma; | |
1219 | ||
1220 | ap->private_data = pp; | |
1221 | ||
350756f6 TH |
1222 | ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); |
1223 | ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port"); | |
1224 | ||
edb33667 | 1225 | return 0; |
edb33667 TH |
1226 | } |
1227 | ||
4447d351 | 1228 | static void sil24_init_controller(struct ata_host *host) |
2a41a610 | 1229 | { |
4447d351 | 1230 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
2a41a610 TH |
1231 | u32 tmp; |
1232 | int i; | |
1233 | ||
1234 | /* GPIO off */ | |
1235 | writel(0, host_base + HOST_FLASH_CMD); | |
1236 | ||
1237 | /* clear global reset & mask interrupts during initialization */ | |
1238 | writel(0, host_base + HOST_CTRL); | |
1239 | ||
1240 | /* init ports */ | |
4447d351 | 1241 | for (i = 0; i < host->n_ports; i++) { |
23818034 | 1242 | struct ata_port *ap = host->ports[i]; |
350756f6 TH |
1243 | void __iomem *port = sil24_port_base(ap); |
1244 | ||
2a41a610 TH |
1245 | |
1246 | /* Initial PHY setting */ | |
1247 | writel(0x20c, port + PORT_PHY_CFG); | |
1248 | ||
1249 | /* Clear port RST */ | |
1250 | tmp = readl(port + PORT_CTRL_STAT); | |
1251 | if (tmp & PORT_CS_PORT_RST) { | |
1252 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
97750ceb | 1253 | tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT, |
2a41a610 TH |
1254 | PORT_CS_PORT_RST, |
1255 | PORT_CS_PORT_RST, 10, 100); | |
1256 | if (tmp & PORT_CS_PORT_RST) | |
a44fec1f JP |
1257 | dev_err(host->dev, |
1258 | "failed to clear port RST\n"); | |
2a41a610 TH |
1259 | } |
1260 | ||
23818034 TH |
1261 | /* configure port */ |
1262 | sil24_config_port(ap); | |
2a41a610 TH |
1263 | } |
1264 | ||
1265 | /* Turn on interrupts */ | |
1266 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
1267 | } | |
1268 | ||
edb33667 TH |
1269 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1270 | { | |
93e2618e | 1271 | extern int __MARKER__sil24_cmd_block_is_sized_wrongly; |
4447d351 TH |
1272 | struct ata_port_info pi = sil24_port_info[ent->driver_data]; |
1273 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
1274 | void __iomem * const *iomap; | |
1275 | struct ata_host *host; | |
350756f6 | 1276 | int rc; |
37024e8e | 1277 | u32 tmp; |
edb33667 | 1278 | |
93e2618e TH |
1279 | /* cause link error if sil24_cmd_block is sized wrongly */ |
1280 | if (sizeof(union sil24_cmd_block) != PAGE_SIZE) | |
1281 | __MARKER__sil24_cmd_block_is_sized_wrongly = 1; | |
1282 | ||
06296a1e | 1283 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
edb33667 | 1284 | |
4447d351 | 1285 | /* acquire resources */ |
24dc5f33 | 1286 | rc = pcim_enable_device(pdev); |
edb33667 TH |
1287 | if (rc) |
1288 | return rc; | |
1289 | ||
0d5ff566 TH |
1290 | rc = pcim_iomap_regions(pdev, |
1291 | (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), | |
1292 | DRV_NAME); | |
edb33667 | 1293 | if (rc) |
24dc5f33 | 1294 | return rc; |
4447d351 | 1295 | iomap = pcim_iomap_table(pdev); |
edb33667 | 1296 | |
4447d351 TH |
1297 | /* apply workaround for completion IRQ loss on PCI-X errata */ |
1298 | if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { | |
1299 | tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); | |
1300 | if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) | |
a44fec1f JP |
1301 | dev_info(&pdev->dev, |
1302 | "Applying completion IRQ loss on PCI-X errata fix\n"); | |
4447d351 TH |
1303 | else |
1304 | pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; | |
1305 | } | |
edb33667 | 1306 | |
4447d351 TH |
1307 | /* allocate and fill host */ |
1308 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, | |
1309 | SIL24_FLAG2NPORTS(ppi[0]->flags)); | |
1310 | if (!host) | |
1311 | return -ENOMEM; | |
1312 | host->iomap = iomap; | |
edb33667 | 1313 | |
4447d351 | 1314 | /* configure and activate the device */ |
c54c719b QL |
1315 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { |
1316 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
26ec634c | 1317 | if (rc) { |
c54c719b | 1318 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
26ec634c | 1319 | if (rc) { |
a44fec1f JP |
1320 | dev_err(&pdev->dev, |
1321 | "64-bit DMA enable failed\n"); | |
24dc5f33 | 1322 | return rc; |
26ec634c TH |
1323 | } |
1324 | } | |
1325 | } else { | |
c54c719b | 1326 | rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
26ec634c | 1327 | if (rc) { |
a44fec1f | 1328 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
24dc5f33 | 1329 | return rc; |
26ec634c | 1330 | } |
c54c719b | 1331 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
26ec634c | 1332 | if (rc) { |
a44fec1f JP |
1333 | dev_err(&pdev->dev, |
1334 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 1335 | return rc; |
26ec634c | 1336 | } |
edb33667 TH |
1337 | } |
1338 | ||
e8b3b5e9 TH |
1339 | /* Set max read request size to 4096. This slightly increases |
1340 | * write throughput for pci-e variants. | |
1341 | */ | |
1342 | pcie_set_readrq(pdev, 4096); | |
1343 | ||
4447d351 | 1344 | sil24_init_controller(host); |
edb33667 | 1345 | |
dae77214 | 1346 | if (sata_sil24_msi && !pci_enable_msi(pdev)) { |
a44fec1f | 1347 | dev_info(&pdev->dev, "Using MSI\n"); |
dae77214 VM |
1348 | pci_intx(pdev, 0); |
1349 | } | |
1350 | ||
edb33667 | 1351 | pci_set_master(pdev); |
4447d351 TH |
1352 | return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, |
1353 | &sil24_sht); | |
edb33667 TH |
1354 | } |
1355 | ||
58eb8cd5 | 1356 | #ifdef CONFIG_PM_SLEEP |
d2298dca TH |
1357 | static int sil24_pci_device_resume(struct pci_dev *pdev) |
1358 | { | |
0a86e1c8 | 1359 | struct ata_host *host = pci_get_drvdata(pdev); |
0d5ff566 | 1360 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
553c4aa6 | 1361 | int rc; |
d2298dca | 1362 | |
553c4aa6 TH |
1363 | rc = ata_pci_device_do_resume(pdev); |
1364 | if (rc) | |
1365 | return rc; | |
d2298dca TH |
1366 | |
1367 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) | |
0d5ff566 | 1368 | writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); |
d2298dca | 1369 | |
4447d351 | 1370 | sil24_init_controller(host); |
d2298dca | 1371 | |
cca3974e | 1372 | ata_host_resume(host); |
d2298dca TH |
1373 | |
1374 | return 0; | |
1375 | } | |
58eb8cd5 | 1376 | #endif |
3454dc69 | 1377 | |
58eb8cd5 | 1378 | #ifdef CONFIG_PM |
3454dc69 TH |
1379 | static int sil24_port_resume(struct ata_port *ap) |
1380 | { | |
1381 | sil24_config_pmp(ap, ap->nr_pmp_links); | |
1382 | return 0; | |
1383 | } | |
281d426c | 1384 | #endif |
d2298dca | 1385 | |
2fc75da0 | 1386 | module_pci_driver(sil24_pci_driver); |
edb33667 TH |
1387 | |
1388 | MODULE_AUTHOR("Tejun Heo"); | |
1389 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1390 | MODULE_LICENSE("GPL"); | |
1391 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); |