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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
edb33667 TH |
23 | #include <linux/pci.h> |
24 | #include <linux/blkdev.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/dma-mapping.h> | |
a9524a76 | 28 | #include <linux/device.h> |
edb33667 | 29 | #include <scsi/scsi_host.h> |
193515d5 | 30 | #include <scsi/scsi_cmnd.h> |
edb33667 | 31 | #include <linux/libata.h> |
edb33667 TH |
32 | |
33 | #define DRV_NAME "sata_sil24" | |
3454dc69 | 34 | #define DRV_VERSION "1.1" |
edb33667 | 35 | |
edb33667 TH |
36 | /* |
37 | * Port request block (PRB) 32 bytes | |
38 | */ | |
39 | struct sil24_prb { | |
b4772574 AD |
40 | __le16 ctrl; |
41 | __le16 prot; | |
42 | __le32 rx_cnt; | |
edb33667 TH |
43 | u8 fis[6 * 4]; |
44 | }; | |
45 | ||
46 | /* | |
47 | * Scatter gather entry (SGE) 16 bytes | |
48 | */ | |
49 | struct sil24_sge { | |
b4772574 AD |
50 | __le64 addr; |
51 | __le32 cnt; | |
52 | __le32 flags; | |
edb33667 TH |
53 | }; |
54 | ||
edb33667 TH |
55 | |
56 | enum { | |
0d5ff566 TH |
57 | SIL24_HOST_BAR = 0, |
58 | SIL24_PORT_BAR = 2, | |
59 | ||
93e2618e TH |
60 | /* sil24 fetches in chunks of 64bytes. The first block |
61 | * contains the PRB and two SGEs. From the second block, it's | |
62 | * consisted of four SGEs and called SGT. Calculate the | |
63 | * number of SGTs that fit into one page. | |
64 | */ | |
65 | SIL24_PRB_SZ = sizeof(struct sil24_prb) | |
66 | + 2 * sizeof(struct sil24_sge), | |
67 | SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ) | |
68 | / (4 * sizeof(struct sil24_sge)), | |
69 | ||
70 | /* This will give us one unused SGEs for ATA. This extra SGE | |
71 | * will be used to store CDB for ATAPI devices. | |
72 | */ | |
73 | SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1, | |
74 | ||
edb33667 TH |
75 | /* |
76 | * Global controller registers (128 bytes @ BAR0) | |
77 | */ | |
78 | /* 32 bit regs */ | |
79 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
80 | HOST_CTRL = 0x40, | |
81 | HOST_IRQ_STAT = 0x44, | |
82 | HOST_PHY_CFG = 0x48, | |
83 | HOST_BIST_CTRL = 0x50, | |
84 | HOST_BIST_PTRN = 0x54, | |
85 | HOST_BIST_STAT = 0x58, | |
86 | HOST_MEM_BIST_STAT = 0x5c, | |
87 | HOST_FLASH_CMD = 0x70, | |
88 | /* 8 bit regs */ | |
89 | HOST_FLASH_DATA = 0x74, | |
90 | HOST_TRANSITION_DETECT = 0x75, | |
91 | HOST_GPIO_CTRL = 0x76, | |
92 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
93 | HOST_I2C_DATA = 0x7c, | |
94 | HOST_I2C_XFER_CNT = 0x7e, | |
95 | HOST_I2C_CTRL = 0x7f, | |
96 | ||
97 | /* HOST_SLOT_STAT bits */ | |
98 | HOST_SSTAT_ATTN = (1 << 31), | |
99 | ||
7dafc3fd TH |
100 | /* HOST_CTRL bits */ |
101 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ | |
102 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ | |
103 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ | |
104 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ | |
105 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ | |
d2298dca | 106 | HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ |
7dafc3fd | 107 | |
edb33667 TH |
108 | /* |
109 | * Port registers | |
110 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
111 | */ | |
112 | PORT_REGS_SIZE = 0x2000, | |
135da345 | 113 | |
28c8f3b4 | 114 | PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ |
135da345 | 115 | PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ |
edb33667 | 116 | |
28c8f3b4 | 117 | PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ |
c0c55908 TH |
118 | PORT_PMP_STATUS = 0x0000, /* port device status offset */ |
119 | PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ | |
120 | PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ | |
121 | ||
edb33667 | 122 | /* 32 bit regs */ |
83bbecc9 TH |
123 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
124 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
125 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
126 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
127 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 128 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
129 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
130 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
131 | PORT_FIS_CFG = 0x1028, |
132 | PORT_FIFO_THRES = 0x102c, | |
133 | /* 16 bit regs */ | |
134 | PORT_DECODE_ERR_CNT = 0x1040, | |
135 | PORT_DECODE_ERR_THRESH = 0x1042, | |
136 | PORT_CRC_ERR_CNT = 0x1044, | |
137 | PORT_CRC_ERR_THRESH = 0x1046, | |
138 | PORT_HSHK_ERR_CNT = 0x1048, | |
139 | PORT_HSHK_ERR_THRESH = 0x104a, | |
140 | /* 32 bit regs */ | |
141 | PORT_PHY_CFG = 0x1050, | |
142 | PORT_SLOT_STAT = 0x1800, | |
143 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
c0c55908 | 144 | PORT_CONTEXT = 0x1e04, |
edb33667 TH |
145 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
146 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
147 | PORT_SCONTROL = 0x1f00, | |
148 | PORT_SSTATUS = 0x1f04, | |
149 | PORT_SERROR = 0x1f08, | |
150 | PORT_SACTIVE = 0x1f0c, | |
151 | ||
152 | /* PORT_CTRL_STAT bits */ | |
153 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
154 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
155 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
156 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 157 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
28c8f3b4 | 158 | PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ |
e382eb1d | 159 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
28c8f3b4 | 160 | PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ |
e382eb1d | 161 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
edb33667 TH |
162 | |
163 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
164 | /* bits[11:0] are masked */ | |
165 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
166 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
167 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
168 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
169 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
170 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
7dafc3fd TH |
171 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
172 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ | |
173 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ | |
174 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ | |
175 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ | |
3b9f1d0f | 176 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
edb33667 | 177 | |
88ce7550 | 178 | DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
0542925b | 179 | PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | |
854c73a2 | 180 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, |
88ce7550 | 181 | |
edb33667 TH |
182 | /* bits[27:16] are unmasked (raw) */ |
183 | PORT_IRQ_RAW_SHIFT = 16, | |
184 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
185 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
186 | ||
187 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
188 | PORT_IRQ_STEER_SHIFT = 30, | |
189 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
190 | ||
191 | /* PORT_CMD_ERR constants */ | |
192 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
193 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
194 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
195 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
196 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
197 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
198 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
199 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
200 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
201 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
202 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
203 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
204 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
205 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
206 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
207 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
208 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
209 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
210 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
64008802 | 211 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
edb33667 | 212 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
83bbecc9 | 213 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 214 | |
d10cb35a TH |
215 | /* bits of PRB control field */ |
216 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
217 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
218 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
219 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
220 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
221 | ||
222 | /* PRB protocol field */ | |
223 | PRB_PROT_PACKET = (1 << 0), | |
224 | PRB_PROT_TCQ = (1 << 1), | |
225 | PRB_PROT_NCQ = (1 << 2), | |
226 | PRB_PROT_READ = (1 << 3), | |
227 | PRB_PROT_WRITE = (1 << 4), | |
228 | PRB_PROT_TRANSPARENT = (1 << 5), | |
229 | ||
edb33667 TH |
230 | /* |
231 | * Other constants | |
232 | */ | |
233 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
234 | SGE_LNK = (1 << 30), /* linked list |
235 | Points to SGT, not SGE */ | |
236 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
237 | data address ignored */ | |
edb33667 | 238 | |
aee10a03 TH |
239 | SIL24_MAX_CMDS = 31, |
240 | ||
edb33667 TH |
241 | /* board id */ |
242 | BID_SIL3124 = 0, | |
243 | BID_SIL3132 = 1, | |
042c21fd | 244 | BID_SIL3131 = 2, |
edb33667 | 245 | |
9466d85b | 246 | /* host flags */ |
9cbe056f SS |
247 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | |
248 | ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | | |
249 | ATA_FLAG_AN | ATA_FLAG_PMP, | |
37024e8e | 250 | SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ |
9466d85b | 251 | |
edb33667 TH |
252 | IRQ_STAT_4PORTS = 0xf, |
253 | }; | |
254 | ||
69ad185f | 255 | struct sil24_ata_block { |
edb33667 | 256 | struct sil24_prb prb; |
93e2618e | 257 | struct sil24_sge sge[SIL24_MAX_SGE]; |
edb33667 TH |
258 | }; |
259 | ||
69ad185f TH |
260 | struct sil24_atapi_block { |
261 | struct sil24_prb prb; | |
262 | u8 cdb[16]; | |
93e2618e | 263 | struct sil24_sge sge[SIL24_MAX_SGE]; |
69ad185f TH |
264 | }; |
265 | ||
266 | union sil24_cmd_block { | |
267 | struct sil24_ata_block ata; | |
268 | struct sil24_atapi_block atapi; | |
269 | }; | |
270 | ||
fc8cc1d5 | 271 | static const struct sil24_cerr_info { |
88ce7550 TH |
272 | unsigned int err_mask, action; |
273 | const char *desc; | |
274 | } sil24_cerr_db[] = { | |
f90f0828 | 275 | [0] = { AC_ERR_DEV, 0, |
88ce7550 | 276 | "device error" }, |
f90f0828 | 277 | [PORT_CERR_DEV] = { AC_ERR_DEV, 0, |
88ce7550 | 278 | "device error via D2H FIS" }, |
f90f0828 | 279 | [PORT_CERR_SDB] = { AC_ERR_DEV, 0, |
88ce7550 | 280 | "device error via SDB FIS" }, |
cf480626 | 281 | [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
88ce7550 | 282 | "error in data FIS" }, |
cf480626 | 283 | [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
88ce7550 | 284 | "failed to transmit command FIS" }, |
cf480626 | 285 | [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 286 | "protocol mismatch" }, |
cf480626 | 287 | [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 288 | "data directon mismatch" }, |
cf480626 | 289 | [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 290 | "ran out of SGEs while writing" }, |
cf480626 | 291 | [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 292 | "ran out of SGEs while reading" }, |
cf480626 | 293 | [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 294 | "invalid data directon for ATAPI CDB" }, |
cf480626 | 295 | [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
7293fa8f | 296 | "SGT not on qword boundary" }, |
cf480626 | 297 | [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 298 | "PCI target abort while fetching SGT" }, |
cf480626 | 299 | [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 300 | "PCI master abort while fetching SGT" }, |
cf480626 | 301 | [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 302 | "PCI parity error while fetching SGT" }, |
cf480626 | 303 | [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
88ce7550 | 304 | "PRB not on qword boundary" }, |
cf480626 | 305 | [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 306 | "PCI target abort while fetching PRB" }, |
cf480626 | 307 | [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 308 | "PCI master abort while fetching PRB" }, |
cf480626 | 309 | [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 310 | "PCI parity error while fetching PRB" }, |
cf480626 | 311 | [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 312 | "undefined error while transferring data" }, |
cf480626 | 313 | [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 314 | "PCI target abort while transferring data" }, |
cf480626 | 315 | [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 316 | "PCI master abort while transferring data" }, |
cf480626 | 317 | [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 318 | "PCI parity error while transferring data" }, |
cf480626 | 319 | [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 TH |
320 | "FIS received while sending service FIS" }, |
321 | }; | |
322 | ||
edb33667 TH |
323 | /* |
324 | * ap->private_data | |
325 | * | |
326 | * The preview driver always returned 0 for status. We emulate it | |
327 | * here from the previous interrupt. | |
328 | */ | |
329 | struct sil24_port_priv { | |
69ad185f | 330 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 331 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
23818034 | 332 | int do_port_rst; |
edb33667 TH |
333 | }; |
334 | ||
cd0d3bbc | 335 | static void sil24_dev_config(struct ata_device *dev); |
82ef04fb TH |
336 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val); |
337 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val); | |
3454dc69 | 338 | static int sil24_qc_defer(struct ata_queued_cmd *qc); |
edb33667 | 339 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 340 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
79f97dad | 341 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc); |
3454dc69 TH |
342 | static void sil24_pmp_attach(struct ata_port *ap); |
343 | static void sil24_pmp_detach(struct ata_port *ap); | |
88ce7550 TH |
344 | static void sil24_freeze(struct ata_port *ap); |
345 | static void sil24_thaw(struct ata_port *ap); | |
a1efdaba TH |
346 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
347 | unsigned long deadline); | |
348 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, | |
349 | unsigned long deadline); | |
a1efdaba TH |
350 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
351 | unsigned long deadline); | |
88ce7550 TH |
352 | static void sil24_error_handler(struct ata_port *ap); |
353 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); | |
edb33667 | 354 | static int sil24_port_start(struct ata_port *ap); |
edb33667 | 355 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
58eb8cd5 | 356 | #ifdef CONFIG_PM_SLEEP |
d2298dca | 357 | static int sil24_pci_device_resume(struct pci_dev *pdev); |
58eb8cd5 BZ |
358 | #endif |
359 | #ifdef CONFIG_PM | |
3454dc69 | 360 | static int sil24_port_resume(struct ata_port *ap); |
281d426c | 361 | #endif |
edb33667 | 362 | |
3b7d697d | 363 | static const struct pci_device_id sil24_pci_tbl[] = { |
54bb3a94 JG |
364 | { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, |
365 | { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, | |
366 | { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, | |
722d67b6 | 367 | { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, |
464b3286 | 368 | { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 }, |
54bb3a94 JG |
369 | { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, |
370 | { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, | |
371 | ||
1fcce839 | 372 | { } /* terminate list */ |
edb33667 TH |
373 | }; |
374 | ||
375 | static struct pci_driver sil24_pci_driver = { | |
376 | .name = DRV_NAME, | |
377 | .id_table = sil24_pci_tbl, | |
378 | .probe = sil24_init_one, | |
24dc5f33 | 379 | .remove = ata_pci_remove_one, |
58eb8cd5 | 380 | #ifdef CONFIG_PM_SLEEP |
d2298dca TH |
381 | .suspend = ata_pci_device_suspend, |
382 | .resume = sil24_pci_device_resume, | |
281d426c | 383 | #endif |
edb33667 TH |
384 | }; |
385 | ||
193515d5 | 386 | static struct scsi_host_template sil24_sht = { |
68d1d07b | 387 | ATA_NCQ_SHT(DRV_NAME), |
aee10a03 | 388 | .can_queue = SIL24_MAX_CMDS, |
93e2618e | 389 | .sg_tablesize = SIL24_MAX_SGE, |
edb33667 | 390 | .dma_boundary = ATA_DMA_BOUNDARY, |
edb33667 TH |
391 | }; |
392 | ||
029cfd6b TH |
393 | static struct ata_port_operations sil24_ops = { |
394 | .inherits = &sata_pmp_port_ops, | |
69ad185f | 395 | |
3454dc69 | 396 | .qc_defer = sil24_qc_defer, |
edb33667 TH |
397 | .qc_prep = sil24_qc_prep, |
398 | .qc_issue = sil24_qc_issue, | |
79f97dad | 399 | .qc_fill_rtf = sil24_qc_fill_rtf, |
edb33667 | 400 | |
029cfd6b TH |
401 | .freeze = sil24_freeze, |
402 | .thaw = sil24_thaw, | |
a1efdaba TH |
403 | .softreset = sil24_softreset, |
404 | .hardreset = sil24_hardreset, | |
071f44b1 | 405 | .pmp_softreset = sil24_softreset, |
a1efdaba | 406 | .pmp_hardreset = sil24_pmp_hardreset, |
029cfd6b TH |
407 | .error_handler = sil24_error_handler, |
408 | .post_internal_cmd = sil24_post_internal_cmd, | |
409 | .dev_config = sil24_dev_config, | |
edb33667 TH |
410 | |
411 | .scr_read = sil24_scr_read, | |
412 | .scr_write = sil24_scr_write, | |
3454dc69 TH |
413 | .pmp_attach = sil24_pmp_attach, |
414 | .pmp_detach = sil24_pmp_detach, | |
3454dc69 | 415 | |
edb33667 | 416 | .port_start = sil24_port_start, |
3454dc69 TH |
417 | #ifdef CONFIG_PM |
418 | .port_resume = sil24_port_resume, | |
419 | #endif | |
edb33667 TH |
420 | }; |
421 | ||
90ab5ee9 | 422 | static bool sata_sil24_msi; /* Disable MSI */ |
dae77214 VM |
423 | module_param_named(msi, sata_sil24_msi, bool, S_IRUGO); |
424 | MODULE_PARM_DESC(msi, "Enable MSI (Default: false)"); | |
425 | ||
042c21fd | 426 | /* |
cca3974e | 427 | * Use bits 30-31 of port_flags to encode available port numbers. |
042c21fd TH |
428 | * Current maxium is 4. |
429 | */ | |
430 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
431 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
432 | ||
4447d351 | 433 | static const struct ata_port_info sil24_port_info[] = { |
edb33667 TH |
434 | /* sil_3124 */ |
435 | { | |
cca3974e | 436 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | |
37024e8e | 437 | SIL24_FLAG_PCIX_IRQ_WOC, |
14bdef98 EIB |
438 | .pio_mask = ATA_PIO4, |
439 | .mwdma_mask = ATA_MWDMA2, | |
440 | .udma_mask = ATA_UDMA5, | |
edb33667 TH |
441 | .port_ops = &sil24_ops, |
442 | }, | |
2e9edbf8 | 443 | /* sil_3132 */ |
edb33667 | 444 | { |
cca3974e | 445 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
14bdef98 EIB |
446 | .pio_mask = ATA_PIO4, |
447 | .mwdma_mask = ATA_MWDMA2, | |
448 | .udma_mask = ATA_UDMA5, | |
042c21fd TH |
449 | .port_ops = &sil24_ops, |
450 | }, | |
451 | /* sil_3131/sil_3531 */ | |
452 | { | |
cca3974e | 453 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
14bdef98 EIB |
454 | .pio_mask = ATA_PIO4, |
455 | .mwdma_mask = ATA_MWDMA2, | |
456 | .udma_mask = ATA_UDMA5, | |
edb33667 TH |
457 | .port_ops = &sil24_ops, |
458 | }, | |
459 | }; | |
460 | ||
aee10a03 TH |
461 | static int sil24_tag(int tag) |
462 | { | |
463 | if (unlikely(ata_tag_internal(tag))) | |
464 | return 0; | |
465 | return tag; | |
466 | } | |
467 | ||
350756f6 TH |
468 | static unsigned long sil24_port_offset(struct ata_port *ap) |
469 | { | |
470 | return ap->port_no * PORT_REGS_SIZE; | |
471 | } | |
472 | ||
473 | static void __iomem *sil24_port_base(struct ata_port *ap) | |
474 | { | |
475 | return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap); | |
476 | } | |
477 | ||
cd0d3bbc | 478 | static void sil24_dev_config(struct ata_device *dev) |
69ad185f | 479 | { |
350756f6 | 480 | void __iomem *port = sil24_port_base(dev->link->ap); |
69ad185f | 481 | |
6e7846e9 | 482 | if (dev->cdb_len == 16) |
69ad185f TH |
483 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
484 | else | |
485 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
486 | } | |
487 | ||
e59f0dad | 488 | static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf) |
6a575fa9 | 489 | { |
350756f6 | 490 | void __iomem *port = sil24_port_base(ap); |
e59f0dad | 491 | struct sil24_prb __iomem *prb; |
4b4a5eae | 492 | u8 fis[6 * 4]; |
6a575fa9 | 493 | |
e59f0dad TH |
494 | prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ; |
495 | memcpy_fromio(fis, prb->fis, sizeof(fis)); | |
496 | ata_tf_from_fis(fis, tf); | |
6a575fa9 TH |
497 | } |
498 | ||
edb33667 TH |
499 | static int sil24_scr_map[] = { |
500 | [SCR_CONTROL] = 0, | |
501 | [SCR_STATUS] = 1, | |
502 | [SCR_ERROR] = 2, | |
503 | [SCR_ACTIVE] = 3, | |
504 | }; | |
505 | ||
82ef04fb | 506 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) |
edb33667 | 507 | { |
82ef04fb | 508 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
da3dbb17 | 509 | |
edb33667 | 510 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
da3dbb17 TH |
511 | *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); |
512 | return 0; | |
edb33667 | 513 | } |
da3dbb17 | 514 | return -EINVAL; |
edb33667 TH |
515 | } |
516 | ||
82ef04fb | 517 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) |
edb33667 | 518 | { |
82ef04fb | 519 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
da3dbb17 | 520 | |
edb33667 | 521 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
edb33667 | 522 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); |
da3dbb17 | 523 | return 0; |
edb33667 | 524 | } |
da3dbb17 | 525 | return -EINVAL; |
edb33667 TH |
526 | } |
527 | ||
23818034 TH |
528 | static void sil24_config_port(struct ata_port *ap) |
529 | { | |
350756f6 | 530 | void __iomem *port = sil24_port_base(ap); |
23818034 TH |
531 | |
532 | /* configure IRQ WoC */ | |
533 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
534 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); | |
535 | else | |
536 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
537 | ||
538 | /* zero error counters. */ | |
7a4f876b CT |
539 | writew(0x8000, port + PORT_DECODE_ERR_THRESH); |
540 | writew(0x8000, port + PORT_CRC_ERR_THRESH); | |
541 | writew(0x8000, port + PORT_HSHK_ERR_THRESH); | |
542 | writew(0x0000, port + PORT_DECODE_ERR_CNT); | |
543 | writew(0x0000, port + PORT_CRC_ERR_CNT); | |
544 | writew(0x0000, port + PORT_HSHK_ERR_CNT); | |
23818034 TH |
545 | |
546 | /* always use 64bit activation */ | |
547 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); | |
548 | ||
549 | /* clear port multiplier enable and resume bits */ | |
550 | writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); | |
551 | } | |
552 | ||
3454dc69 TH |
553 | static void sil24_config_pmp(struct ata_port *ap, int attached) |
554 | { | |
350756f6 | 555 | void __iomem *port = sil24_port_base(ap); |
3454dc69 TH |
556 | |
557 | if (attached) | |
558 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); | |
559 | else | |
560 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); | |
561 | } | |
562 | ||
563 | static void sil24_clear_pmp(struct ata_port *ap) | |
564 | { | |
350756f6 | 565 | void __iomem *port = sil24_port_base(ap); |
3454dc69 TH |
566 | int i; |
567 | ||
568 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); | |
569 | ||
570 | for (i = 0; i < SATA_PMP_MAX_PORTS; i++) { | |
571 | void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE; | |
572 | ||
573 | writel(0, pmp_base + PORT_PMP_STATUS); | |
574 | writel(0, pmp_base + PORT_PMP_QACTIVE); | |
575 | } | |
576 | } | |
577 | ||
b5bc421c TH |
578 | static int sil24_init_port(struct ata_port *ap) |
579 | { | |
350756f6 | 580 | void __iomem *port = sil24_port_base(ap); |
23818034 | 581 | struct sil24_port_priv *pp = ap->private_data; |
b5bc421c TH |
582 | u32 tmp; |
583 | ||
3454dc69 | 584 | /* clear PMP error status */ |
071f44b1 | 585 | if (sata_pmp_attached(ap)) |
3454dc69 TH |
586 | sil24_clear_pmp(ap); |
587 | ||
b5bc421c | 588 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); |
97750ceb | 589 | ata_wait_register(ap, port + PORT_CTRL_STAT, |
b5bc421c | 590 | PORT_CS_INIT, PORT_CS_INIT, 10, 100); |
97750ceb | 591 | tmp = ata_wait_register(ap, port + PORT_CTRL_STAT, |
b5bc421c TH |
592 | PORT_CS_RDY, 0, 10, 100); |
593 | ||
23818034 TH |
594 | if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { |
595 | pp->do_port_rst = 1; | |
cf480626 | 596 | ap->link.eh_context.i.action |= ATA_EH_RESET; |
b5bc421c | 597 | return -EIO; |
23818034 TH |
598 | } |
599 | ||
b5bc421c TH |
600 | return 0; |
601 | } | |
602 | ||
37b99cba TH |
603 | static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, |
604 | const struct ata_taskfile *tf, | |
605 | int is_cmd, u32 ctrl, | |
606 | unsigned long timeout_msec) | |
edb33667 | 607 | { |
350756f6 | 608 | void __iomem *port = sil24_port_base(ap); |
ca45160d | 609 | struct sil24_port_priv *pp = ap->private_data; |
69ad185f | 610 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d | 611 | dma_addr_t paddr = pp->cmd_block_dma; |
37b99cba TH |
612 | u32 irq_enabled, irq_mask, irq_stat; |
613 | int rc; | |
614 | ||
615 | prb->ctrl = cpu_to_le16(ctrl); | |
616 | ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); | |
617 | ||
618 | /* temporarily plug completion and error interrupts */ | |
619 | irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); | |
620 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); | |
621 | ||
10823452 CM |
622 | /* |
623 | * The barrier is required to ensure that writes to cmd_block reach | |
624 | * the memory before the write to PORT_CMD_ACTIVATE. | |
625 | */ | |
626 | wmb(); | |
37b99cba TH |
627 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
628 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); | |
629 | ||
630 | irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; | |
97750ceb | 631 | irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0, |
37b99cba TH |
632 | 10, timeout_msec); |
633 | ||
634 | writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ | |
635 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
636 | ||
637 | if (irq_stat & PORT_IRQ_COMPLETE) | |
638 | rc = 0; | |
639 | else { | |
640 | /* force port into known state */ | |
641 | sil24_init_port(ap); | |
642 | ||
643 | if (irq_stat & PORT_IRQ_ERROR) | |
644 | rc = -EIO; | |
645 | else | |
646 | rc = -EBUSY; | |
647 | } | |
648 | ||
649 | /* restore IRQ enabled */ | |
650 | writel(irq_enabled, port + PORT_IRQ_ENABLE_SET); | |
651 | ||
652 | return rc; | |
653 | } | |
654 | ||
071f44b1 TH |
655 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
656 | unsigned long deadline) | |
37b99cba | 657 | { |
cc0680a5 | 658 | struct ata_port *ap = link->ap; |
071f44b1 | 659 | int pmp = sata_srst_pmp(link); |
37b99cba | 660 | unsigned long timeout_msec = 0; |
e59f0dad | 661 | struct ata_taskfile tf; |
643be977 | 662 | const char *reason; |
37b99cba | 663 | int rc; |
ca45160d | 664 | |
07b73470 TH |
665 | DPRINTK("ENTER\n"); |
666 | ||
2555d6c2 TH |
667 | /* put the port into known state */ |
668 | if (sil24_init_port(ap)) { | |
5796d1c4 | 669 | reason = "port not ready"; |
2555d6c2 TH |
670 | goto err; |
671 | } | |
672 | ||
0eaa6058 | 673 | /* do SRST */ |
37b99cba TH |
674 | if (time_after(deadline, jiffies)) |
675 | timeout_msec = jiffies_to_msecs(deadline - jiffies); | |
ca45160d | 676 | |
cc0680a5 | 677 | ata_tf_init(link->device, &tf); /* doesn't really matter */ |
975530e8 TH |
678 | rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST, |
679 | timeout_msec); | |
37b99cba TH |
680 | if (rc == -EBUSY) { |
681 | reason = "timeout"; | |
682 | goto err; | |
683 | } else if (rc) { | |
684 | reason = "SRST command error"; | |
643be977 | 685 | goto err; |
07b73470 | 686 | } |
10d996ad | 687 | |
e59f0dad TH |
688 | sil24_read_tf(ap, 0, &tf); |
689 | *class = ata_dev_classify(&tf); | |
10d996ad | 690 | |
07b73470 | 691 | DPRINTK("EXIT, class=%u\n", *class); |
ca45160d | 692 | return 0; |
643be977 TH |
693 | |
694 | err: | |
a9a79dfe | 695 | ata_link_err(link, "softreset failed (%s)\n", reason); |
643be977 | 696 | return -EIO; |
ca45160d TH |
697 | } |
698 | ||
cc0680a5 | 699 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 700 | unsigned long deadline) |
489ff4c7 | 701 | { |
cc0680a5 | 702 | struct ata_port *ap = link->ap; |
350756f6 | 703 | void __iomem *port = sil24_port_base(ap); |
23818034 TH |
704 | struct sil24_port_priv *pp = ap->private_data; |
705 | int did_port_rst = 0; | |
ecc2e2b9 | 706 | const char *reason; |
e8e008e7 | 707 | int tout_msec, rc; |
ecc2e2b9 TH |
708 | u32 tmp; |
709 | ||
23818034 TH |
710 | retry: |
711 | /* Sometimes, DEV_RST is not enough to recover the controller. | |
712 | * This happens often after PM DMA CS errata. | |
713 | */ | |
714 | if (pp->do_port_rst) { | |
a9a79dfe JP |
715 | ata_port_warn(ap, |
716 | "controller in dubious state, performing PORT_RST\n"); | |
23818034 TH |
717 | |
718 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); | |
97750ceb | 719 | ata_msleep(ap, 10); |
23818034 | 720 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); |
97750ceb | 721 | ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0, |
23818034 TH |
722 | 10, 5000); |
723 | ||
724 | /* restore port configuration */ | |
725 | sil24_config_port(ap); | |
726 | sil24_config_pmp(ap, ap->nr_pmp_links); | |
727 | ||
728 | pp->do_port_rst = 0; | |
729 | did_port_rst = 1; | |
730 | } | |
731 | ||
ecc2e2b9 | 732 | /* sil24 does the right thing(tm) without any protection */ |
cc0680a5 | 733 | sata_set_spd(link); |
ecc2e2b9 TH |
734 | |
735 | tout_msec = 100; | |
cc0680a5 | 736 | if (ata_link_online(link)) |
ecc2e2b9 TH |
737 | tout_msec = 5000; |
738 | ||
739 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
97750ceb | 740 | tmp = ata_wait_register(ap, port + PORT_CTRL_STAT, |
5796d1c4 JG |
741 | PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, |
742 | tout_msec); | |
ecc2e2b9 | 743 | |
e8e008e7 TH |
744 | /* SStatus oscillates between zero and valid status after |
745 | * DEV_RST, debounce it. | |
ecc2e2b9 | 746 | */ |
cc0680a5 | 747 | rc = sata_link_debounce(link, sata_deb_timing_long, deadline); |
e8e008e7 TH |
748 | if (rc) { |
749 | reason = "PHY debouncing failed"; | |
750 | goto err; | |
751 | } | |
ecc2e2b9 TH |
752 | |
753 | if (tmp & PORT_CS_DEV_RST) { | |
cc0680a5 | 754 | if (ata_link_offline(link)) |
ecc2e2b9 TH |
755 | return 0; |
756 | reason = "link not ready"; | |
757 | goto err; | |
758 | } | |
759 | ||
e8e008e7 TH |
760 | /* Sil24 doesn't store signature FIS after hardreset, so we |
761 | * can't wait for BSY to clear. Some devices take a long time | |
762 | * to get ready and those devices will choke if we don't wait | |
763 | * for BSY clearance here. Tell libata to perform follow-up | |
764 | * softreset. | |
ecc2e2b9 | 765 | */ |
e8e008e7 | 766 | return -EAGAIN; |
ecc2e2b9 TH |
767 | |
768 | err: | |
23818034 TH |
769 | if (!did_port_rst) { |
770 | pp->do_port_rst = 1; | |
771 | goto retry; | |
772 | } | |
773 | ||
a9a79dfe | 774 | ata_link_err(link, "hardreset failed (%s)\n", reason); |
ecc2e2b9 | 775 | return -EIO; |
489ff4c7 TH |
776 | } |
777 | ||
edb33667 | 778 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
69ad185f | 779 | struct sil24_sge *sge) |
edb33667 | 780 | { |
972c26bd | 781 | struct scatterlist *sg; |
3be6cbd7 | 782 | struct sil24_sge *last_sge = NULL; |
ff2aeb1e | 783 | unsigned int si; |
edb33667 | 784 | |
ff2aeb1e | 785 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
edb33667 TH |
786 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
787 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
3be6cbd7 JG |
788 | sge->flags = 0; |
789 | ||
790 | last_sge = sge; | |
972c26bd | 791 | sge++; |
edb33667 | 792 | } |
3be6cbd7 | 793 | |
ff2aeb1e | 794 | last_sge->flags = cpu_to_le32(SGE_TRM); |
edb33667 TH |
795 | } |
796 | ||
3454dc69 TH |
797 | static int sil24_qc_defer(struct ata_queued_cmd *qc) |
798 | { | |
799 | struct ata_link *link = qc->dev->link; | |
800 | struct ata_port *ap = link->ap; | |
801 | u8 prot = qc->tf.protocol; | |
13cc546b GG |
802 | |
803 | /* | |
804 | * There is a bug in the chip: | |
805 | * Port LRAM Causes the PRB/SGT Data to be Corrupted | |
806 | * If the host issues a read request for LRAM and SActive registers | |
807 | * while active commands are available in the port, PRB/SGT data in | |
808 | * the LRAM can become corrupted. This issue applies only when | |
809 | * reading from, but not writing to, the LRAM. | |
810 | * | |
811 | * Therefore, reading LRAM when there is no particular error [and | |
812 | * other commands may be outstanding] is prohibited. | |
813 | * | |
814 | * To avoid this bug there are two situations where a command must run | |
815 | * exclusive of any other commands on the port: | |
816 | * | |
817 | * - ATAPI commands which check the sense data | |
818 | * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF | |
819 | * set. | |
820 | * | |
821 | */ | |
405e66b3 | 822 | int is_excl = (ata_is_atapi(prot) || |
13cc546b GG |
823 | (qc->flags & ATA_QCFLAG_RESULT_TF)); |
824 | ||
3454dc69 TH |
825 | if (unlikely(ap->excl_link)) { |
826 | if (link == ap->excl_link) { | |
827 | if (ap->nr_active_links) | |
828 | return ATA_DEFER_PORT; | |
829 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
830 | } else | |
831 | return ATA_DEFER_PORT; | |
13cc546b | 832 | } else if (unlikely(is_excl)) { |
3454dc69 TH |
833 | ap->excl_link = link; |
834 | if (ap->nr_active_links) | |
835 | return ATA_DEFER_PORT; | |
836 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
837 | } | |
838 | ||
839 | return ata_std_qc_defer(qc); | |
840 | } | |
841 | ||
edb33667 TH |
842 | static void sil24_qc_prep(struct ata_queued_cmd *qc) |
843 | { | |
844 | struct ata_port *ap = qc->ap; | |
845 | struct sil24_port_priv *pp = ap->private_data; | |
aee10a03 | 846 | union sil24_cmd_block *cb; |
69ad185f TH |
847 | struct sil24_prb *prb; |
848 | struct sil24_sge *sge; | |
bad28a37 | 849 | u16 ctrl = 0; |
edb33667 | 850 | |
aee10a03 TH |
851 | cb = &pp->cmd_block[sil24_tag(qc->tag)]; |
852 | ||
405e66b3 | 853 | if (!ata_is_atapi(qc->tf.protocol)) { |
69ad185f TH |
854 | prb = &cb->ata.prb; |
855 | sge = cb->ata.sge; | |
4f1a0ee1 RH |
856 | if (ata_is_data(qc->tf.protocol)) { |
857 | u16 prot = 0; | |
858 | ctrl = PRB_CTRL_PROTOCOL; | |
859 | if (ata_is_ncq(qc->tf.protocol)) | |
860 | prot |= PRB_PROT_NCQ; | |
861 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
862 | prot |= PRB_PROT_WRITE; | |
863 | else | |
864 | prot |= PRB_PROT_READ; | |
865 | prb->prot = cpu_to_le16(prot); | |
866 | } | |
405e66b3 | 867 | } else { |
69ad185f TH |
868 | prb = &cb->atapi.prb; |
869 | sge = cb->atapi.sge; | |
14e45c15 | 870 | memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb)); |
6e7846e9 | 871 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
69ad185f | 872 | |
405e66b3 | 873 | if (ata_is_data(qc->tf.protocol)) { |
69ad185f | 874 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
bad28a37 | 875 | ctrl = PRB_CTRL_PACKET_WRITE; |
69ad185f | 876 | else |
bad28a37 TH |
877 | ctrl = PRB_CTRL_PACKET_READ; |
878 | } | |
edb33667 TH |
879 | } |
880 | ||
bad28a37 | 881 | prb->ctrl = cpu_to_le16(ctrl); |
3454dc69 | 882 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); |
edb33667 TH |
883 | |
884 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 885 | sil24_fill_sg(qc, sge); |
edb33667 TH |
886 | } |
887 | ||
9a3d9eb0 | 888 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
889 | { |
890 | struct ata_port *ap = qc->ap; | |
891 | struct sil24_port_priv *pp = ap->private_data; | |
350756f6 | 892 | void __iomem *port = sil24_port_base(ap); |
aee10a03 TH |
893 | unsigned int tag = sil24_tag(qc->tag); |
894 | dma_addr_t paddr; | |
895 | void __iomem *activate; | |
edb33667 | 896 | |
aee10a03 TH |
897 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); |
898 | activate = port + PORT_CMD_ACTIVATE + tag * 8; | |
899 | ||
10823452 CM |
900 | /* |
901 | * The barrier is required to ensure that writes to cmd_block reach | |
902 | * the memory before the write to PORT_CMD_ACTIVATE. | |
903 | */ | |
904 | wmb(); | |
aee10a03 TH |
905 | writel((u32)paddr, activate); |
906 | writel((u64)paddr >> 32, activate + 4); | |
26ec634c | 907 | |
edb33667 TH |
908 | return 0; |
909 | } | |
910 | ||
79f97dad TH |
911 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc) |
912 | { | |
913 | sil24_read_tf(qc->ap, qc->tag, &qc->result_tf); | |
914 | return true; | |
915 | } | |
916 | ||
3454dc69 TH |
917 | static void sil24_pmp_attach(struct ata_port *ap) |
918 | { | |
906c1ff4 TH |
919 | u32 *gscr = ap->link.device->gscr; |
920 | ||
3454dc69 TH |
921 | sil24_config_pmp(ap, 1); |
922 | sil24_init_port(ap); | |
906c1ff4 TH |
923 | |
924 | if (sata_pmp_gscr_vendor(gscr) == 0x11ab && | |
925 | sata_pmp_gscr_devid(gscr) == 0x4140) { | |
a9a79dfe | 926 | ata_port_info(ap, |
906c1ff4 TH |
927 | "disabling NCQ support due to sil24-mv4140 quirk\n"); |
928 | ap->flags &= ~ATA_FLAG_NCQ; | |
929 | } | |
3454dc69 TH |
930 | } |
931 | ||
932 | static void sil24_pmp_detach(struct ata_port *ap) | |
933 | { | |
934 | sil24_init_port(ap); | |
935 | sil24_config_pmp(ap, 0); | |
906c1ff4 TH |
936 | |
937 | ap->flags |= ATA_FLAG_NCQ; | |
3454dc69 TH |
938 | } |
939 | ||
3454dc69 TH |
940 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
941 | unsigned long deadline) | |
942 | { | |
943 | int rc; | |
944 | ||
945 | rc = sil24_init_port(link->ap); | |
946 | if (rc) { | |
a9a79dfe | 947 | ata_link_err(link, "hardreset failed (port not ready)\n"); |
3454dc69 TH |
948 | return rc; |
949 | } | |
950 | ||
5958e302 | 951 | return sata_std_hardreset(link, class, deadline); |
3454dc69 TH |
952 | } |
953 | ||
88ce7550 | 954 | static void sil24_freeze(struct ata_port *ap) |
7d1ce682 | 955 | { |
350756f6 | 956 | void __iomem *port = sil24_port_base(ap); |
7d1ce682 | 957 | |
88ce7550 TH |
958 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear |
959 | * PORT_IRQ_ENABLE instead. | |
960 | */ | |
961 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
7d1ce682 TH |
962 | } |
963 | ||
88ce7550 | 964 | static void sil24_thaw(struct ata_port *ap) |
edb33667 | 965 | { |
350756f6 | 966 | void __iomem *port = sil24_port_base(ap); |
edb33667 TH |
967 | u32 tmp; |
968 | ||
88ce7550 TH |
969 | /* clear IRQ */ |
970 | tmp = readl(port + PORT_IRQ_STAT); | |
971 | writel(tmp, port + PORT_IRQ_STAT); | |
edb33667 | 972 | |
88ce7550 TH |
973 | /* turn IRQ back on */ |
974 | writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); | |
edb33667 TH |
975 | } |
976 | ||
88ce7550 | 977 | static void sil24_error_intr(struct ata_port *ap) |
8746618d | 978 | { |
350756f6 | 979 | void __iomem *port = sil24_port_base(ap); |
e59f0dad | 980 | struct sil24_port_priv *pp = ap->private_data; |
3454dc69 TH |
981 | struct ata_queued_cmd *qc = NULL; |
982 | struct ata_link *link; | |
983 | struct ata_eh_info *ehi; | |
984 | int abort = 0, freeze = 0; | |
88ce7550 | 985 | u32 irq_stat; |
8746618d | 986 | |
88ce7550 | 987 | /* on error, we need to clear IRQ explicitly */ |
8746618d | 988 | irq_stat = readl(port + PORT_IRQ_STAT); |
88ce7550 | 989 | writel(irq_stat, port + PORT_IRQ_STAT); |
ad6e90f6 | 990 | |
88ce7550 | 991 | /* first, analyze and record host port events */ |
3454dc69 TH |
992 | link = &ap->link; |
993 | ehi = &link->eh_info; | |
88ce7550 | 994 | ata_ehi_clear_desc(ehi); |
ad6e90f6 | 995 | |
88ce7550 | 996 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
8746618d | 997 | |
854c73a2 | 998 | if (irq_stat & PORT_IRQ_SDB_NOTIFY) { |
854c73a2 | 999 | ata_ehi_push_desc(ehi, "SDB notify"); |
7d77b247 | 1000 | sata_async_notification(ap); |
854c73a2 TH |
1001 | } |
1002 | ||
0542925b TH |
1003 | if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { |
1004 | ata_ehi_hotplugged(ehi); | |
b64bbc39 TH |
1005 | ata_ehi_push_desc(ehi, "%s", |
1006 | irq_stat & PORT_IRQ_PHYRDY_CHG ? | |
1007 | "PHY RDY changed" : "device exchanged"); | |
88ce7550 | 1008 | freeze = 1; |
6a575fa9 TH |
1009 | } |
1010 | ||
88ce7550 TH |
1011 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
1012 | ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 1013 | ehi->action |= ATA_EH_RESET; |
b64bbc39 | 1014 | ata_ehi_push_desc(ehi, "unknown FIS"); |
88ce7550 TH |
1015 | freeze = 1; |
1016 | } | |
1017 | ||
1018 | /* deal with command error */ | |
1019 | if (irq_stat & PORT_IRQ_ERROR) { | |
fc8cc1d5 | 1020 | const struct sil24_cerr_info *ci = NULL; |
88ce7550 | 1021 | unsigned int err_mask = 0, action = 0; |
3454dc69 TH |
1022 | u32 context, cerr; |
1023 | int pmp; | |
1024 | ||
1025 | abort = 1; | |
1026 | ||
1027 | /* DMA Context Switch Failure in Port Multiplier Mode | |
1028 | * errata. If we have active commands to 3 or more | |
1029 | * devices, any error condition on active devices can | |
1030 | * corrupt DMA context switching. | |
1031 | */ | |
1032 | if (ap->nr_active_links >= 3) { | |
1033 | ehi->err_mask |= AC_ERR_OTHER; | |
cf480626 | 1034 | ehi->action |= ATA_EH_RESET; |
3454dc69 | 1035 | ata_ehi_push_desc(ehi, "PMP DMA CS errata"); |
23818034 | 1036 | pp->do_port_rst = 1; |
3454dc69 TH |
1037 | freeze = 1; |
1038 | } | |
1039 | ||
1040 | /* find out the offending link and qc */ | |
071f44b1 | 1041 | if (sata_pmp_attached(ap)) { |
3454dc69 TH |
1042 | context = readl(port + PORT_CONTEXT); |
1043 | pmp = (context >> 5) & 0xf; | |
1044 | ||
1045 | if (pmp < ap->nr_pmp_links) { | |
1046 | link = &ap->pmp_link[pmp]; | |
1047 | ehi = &link->eh_info; | |
1048 | qc = ata_qc_from_tag(ap, link->active_tag); | |
1049 | ||
1050 | ata_ehi_clear_desc(ehi); | |
1051 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", | |
1052 | irq_stat); | |
1053 | } else { | |
1054 | err_mask |= AC_ERR_HSM; | |
cf480626 | 1055 | action |= ATA_EH_RESET; |
3454dc69 TH |
1056 | freeze = 1; |
1057 | } | |
1058 | } else | |
1059 | qc = ata_qc_from_tag(ap, link->active_tag); | |
88ce7550 TH |
1060 | |
1061 | /* analyze CMD_ERR */ | |
1062 | cerr = readl(port + PORT_CMD_ERR); | |
1063 | if (cerr < ARRAY_SIZE(sil24_cerr_db)) | |
1064 | ci = &sil24_cerr_db[cerr]; | |
1065 | ||
1066 | if (ci && ci->desc) { | |
1067 | err_mask |= ci->err_mask; | |
1068 | action |= ci->action; | |
cf480626 | 1069 | if (action & ATA_EH_RESET) |
c2e14f11 | 1070 | freeze = 1; |
b64bbc39 | 1071 | ata_ehi_push_desc(ehi, "%s", ci->desc); |
88ce7550 TH |
1072 | } else { |
1073 | err_mask |= AC_ERR_OTHER; | |
cf480626 | 1074 | action |= ATA_EH_RESET; |
c2e14f11 | 1075 | freeze = 1; |
b64bbc39 | 1076 | ata_ehi_push_desc(ehi, "unknown command error %d", |
88ce7550 TH |
1077 | cerr); |
1078 | } | |
1079 | ||
1080 | /* record error info */ | |
520d06f9 | 1081 | if (qc) |
88ce7550 | 1082 | qc->err_mask |= err_mask; |
520d06f9 | 1083 | else |
88ce7550 TH |
1084 | ehi->err_mask |= err_mask; |
1085 | ||
1086 | ehi->action |= action; | |
3454dc69 TH |
1087 | |
1088 | /* if PMP, resume */ | |
071f44b1 | 1089 | if (sata_pmp_attached(ap)) |
3454dc69 | 1090 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT); |
a22e2eb0 | 1091 | } |
88ce7550 TH |
1092 | |
1093 | /* freeze or abort */ | |
1094 | if (freeze) | |
1095 | ata_port_freeze(ap); | |
3454dc69 TH |
1096 | else if (abort) { |
1097 | if (qc) | |
1098 | ata_link_abort(qc->dev->link); | |
1099 | else | |
1100 | ata_port_abort(ap); | |
1101 | } | |
8746618d TH |
1102 | } |
1103 | ||
edb33667 TH |
1104 | static inline void sil24_host_intr(struct ata_port *ap) |
1105 | { | |
350756f6 | 1106 | void __iomem *port = sil24_port_base(ap); |
aee10a03 TH |
1107 | u32 slot_stat, qc_active; |
1108 | int rc; | |
edb33667 | 1109 | |
228f47b9 TH |
1110 | /* If PCIX_IRQ_WOC, there's an inherent race window between |
1111 | * clearing IRQ pending status and reading PORT_SLOT_STAT | |
1112 | * which may cause spurious interrupts afterwards. This is | |
1113 | * unavoidable and much better than losing interrupts which | |
1114 | * happens if IRQ pending is cleared after reading | |
1115 | * PORT_SLOT_STAT. | |
1116 | */ | |
1117 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
1118 | writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); | |
1119 | ||
edb33667 | 1120 | slot_stat = readl(port + PORT_SLOT_STAT); |
37024e8e | 1121 | |
88ce7550 TH |
1122 | if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { |
1123 | sil24_error_intr(ap); | |
1124 | return; | |
1125 | } | |
1126 | ||
aee10a03 | 1127 | qc_active = slot_stat & ~HOST_SSTAT_ATTN; |
79f97dad | 1128 | rc = ata_qc_complete_multiple(ap, qc_active); |
aee10a03 TH |
1129 | if (rc > 0) |
1130 | return; | |
1131 | if (rc < 0) { | |
9af5c9c9 | 1132 | struct ata_eh_info *ehi = &ap->link.eh_info; |
aee10a03 | 1133 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 1134 | ehi->action |= ATA_EH_RESET; |
aee10a03 | 1135 | ata_port_freeze(ap); |
88ce7550 TH |
1136 | return; |
1137 | } | |
1138 | ||
228f47b9 TH |
1139 | /* spurious interrupts are expected if PCIX_IRQ_WOC */ |
1140 | if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) | |
a9a79dfe JP |
1141 | ata_port_info(ap, |
1142 | "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n", | |
9af5c9c9 | 1143 | slot_stat, ap->link.active_tag, ap->link.sactive); |
edb33667 TH |
1144 | } |
1145 | ||
7d12e780 | 1146 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) |
edb33667 | 1147 | { |
cca3974e | 1148 | struct ata_host *host = dev_instance; |
0d5ff566 | 1149 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
edb33667 TH |
1150 | unsigned handled = 0; |
1151 | u32 status; | |
1152 | int i; | |
1153 | ||
0d5ff566 | 1154 | status = readl(host_base + HOST_IRQ_STAT); |
edb33667 | 1155 | |
06460aea | 1156 | if (status == 0xffffffff) { |
11838230 TS |
1157 | dev_err(host->dev, "IRQ status == 0xffffffff, " |
1158 | "PCI fault or device removal?\n"); | |
06460aea TH |
1159 | goto out; |
1160 | } | |
1161 | ||
edb33667 TH |
1162 | if (!(status & IRQ_STAT_4PORTS)) |
1163 | goto out; | |
1164 | ||
cca3974e | 1165 | spin_lock(&host->lock); |
edb33667 | 1166 | |
cca3974e | 1167 | for (i = 0; i < host->n_ports; i++) |
edb33667 | 1168 | if (status & (1 << i)) { |
3e4ec344 TH |
1169 | sil24_host_intr(host->ports[i]); |
1170 | handled++; | |
edb33667 TH |
1171 | } |
1172 | ||
cca3974e | 1173 | spin_unlock(&host->lock); |
edb33667 TH |
1174 | out: |
1175 | return IRQ_RETVAL(handled); | |
1176 | } | |
1177 | ||
88ce7550 TH |
1178 | static void sil24_error_handler(struct ata_port *ap) |
1179 | { | |
23818034 TH |
1180 | struct sil24_port_priv *pp = ap->private_data; |
1181 | ||
3454dc69 | 1182 | if (sil24_init_port(ap)) |
88ce7550 | 1183 | ata_eh_freeze_port(ap); |
88ce7550 | 1184 | |
a1efdaba | 1185 | sata_pmp_error_handler(ap); |
23818034 TH |
1186 | |
1187 | pp->do_port_rst = 0; | |
88ce7550 TH |
1188 | } |
1189 | ||
1190 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) | |
1191 | { | |
1192 | struct ata_port *ap = qc->ap; | |
1193 | ||
88ce7550 | 1194 | /* make DMA engine forget about the failed command */ |
3454dc69 TH |
1195 | if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) |
1196 | ata_eh_freeze_port(ap); | |
88ce7550 TH |
1197 | } |
1198 | ||
edb33667 TH |
1199 | static int sil24_port_start(struct ata_port *ap) |
1200 | { | |
cca3974e | 1201 | struct device *dev = ap->host->dev; |
edb33667 | 1202 | struct sil24_port_priv *pp; |
69ad185f | 1203 | union sil24_cmd_block *cb; |
aee10a03 | 1204 | size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; |
edb33667 TH |
1205 | dma_addr_t cb_dma; |
1206 | ||
24dc5f33 | 1207 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
edb33667 | 1208 | if (!pp) |
24dc5f33 | 1209 | return -ENOMEM; |
edb33667 | 1210 | |
24dc5f33 | 1211 | cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb | 1212 | if (!cb) |
24dc5f33 | 1213 | return -ENOMEM; |
edb33667 TH |
1214 | memset(cb, 0, cb_size); |
1215 | ||
edb33667 TH |
1216 | pp->cmd_block = cb; |
1217 | pp->cmd_block_dma = cb_dma; | |
1218 | ||
1219 | ap->private_data = pp; | |
1220 | ||
350756f6 TH |
1221 | ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); |
1222 | ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port"); | |
1223 | ||
edb33667 | 1224 | return 0; |
edb33667 TH |
1225 | } |
1226 | ||
4447d351 | 1227 | static void sil24_init_controller(struct ata_host *host) |
2a41a610 | 1228 | { |
4447d351 | 1229 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
2a41a610 TH |
1230 | u32 tmp; |
1231 | int i; | |
1232 | ||
1233 | /* GPIO off */ | |
1234 | writel(0, host_base + HOST_FLASH_CMD); | |
1235 | ||
1236 | /* clear global reset & mask interrupts during initialization */ | |
1237 | writel(0, host_base + HOST_CTRL); | |
1238 | ||
1239 | /* init ports */ | |
4447d351 | 1240 | for (i = 0; i < host->n_ports; i++) { |
23818034 | 1241 | struct ata_port *ap = host->ports[i]; |
350756f6 TH |
1242 | void __iomem *port = sil24_port_base(ap); |
1243 | ||
2a41a610 TH |
1244 | |
1245 | /* Initial PHY setting */ | |
1246 | writel(0x20c, port + PORT_PHY_CFG); | |
1247 | ||
1248 | /* Clear port RST */ | |
1249 | tmp = readl(port + PORT_CTRL_STAT); | |
1250 | if (tmp & PORT_CS_PORT_RST) { | |
1251 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
97750ceb | 1252 | tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT, |
2a41a610 TH |
1253 | PORT_CS_PORT_RST, |
1254 | PORT_CS_PORT_RST, 10, 100); | |
1255 | if (tmp & PORT_CS_PORT_RST) | |
a44fec1f JP |
1256 | dev_err(host->dev, |
1257 | "failed to clear port RST\n"); | |
2a41a610 TH |
1258 | } |
1259 | ||
23818034 TH |
1260 | /* configure port */ |
1261 | sil24_config_port(ap); | |
2a41a610 TH |
1262 | } |
1263 | ||
1264 | /* Turn on interrupts */ | |
1265 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
1266 | } | |
1267 | ||
edb33667 TH |
1268 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1269 | { | |
93e2618e | 1270 | extern int __MARKER__sil24_cmd_block_is_sized_wrongly; |
4447d351 TH |
1271 | struct ata_port_info pi = sil24_port_info[ent->driver_data]; |
1272 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
1273 | void __iomem * const *iomap; | |
1274 | struct ata_host *host; | |
350756f6 | 1275 | int rc; |
37024e8e | 1276 | u32 tmp; |
edb33667 | 1277 | |
93e2618e TH |
1278 | /* cause link error if sil24_cmd_block is sized wrongly */ |
1279 | if (sizeof(union sil24_cmd_block) != PAGE_SIZE) | |
1280 | __MARKER__sil24_cmd_block_is_sized_wrongly = 1; | |
1281 | ||
06296a1e | 1282 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
edb33667 | 1283 | |
4447d351 | 1284 | /* acquire resources */ |
24dc5f33 | 1285 | rc = pcim_enable_device(pdev); |
edb33667 TH |
1286 | if (rc) |
1287 | return rc; | |
1288 | ||
0d5ff566 TH |
1289 | rc = pcim_iomap_regions(pdev, |
1290 | (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), | |
1291 | DRV_NAME); | |
edb33667 | 1292 | if (rc) |
24dc5f33 | 1293 | return rc; |
4447d351 | 1294 | iomap = pcim_iomap_table(pdev); |
edb33667 | 1295 | |
4447d351 TH |
1296 | /* apply workaround for completion IRQ loss on PCI-X errata */ |
1297 | if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { | |
1298 | tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); | |
1299 | if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) | |
a44fec1f JP |
1300 | dev_info(&pdev->dev, |
1301 | "Applying completion IRQ loss on PCI-X errata fix\n"); | |
4447d351 TH |
1302 | else |
1303 | pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; | |
1304 | } | |
edb33667 | 1305 | |
4447d351 TH |
1306 | /* allocate and fill host */ |
1307 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, | |
1308 | SIL24_FLAG2NPORTS(ppi[0]->flags)); | |
1309 | if (!host) | |
1310 | return -ENOMEM; | |
1311 | host->iomap = iomap; | |
edb33667 | 1312 | |
4447d351 | 1313 | /* configure and activate the device */ |
6a35528a YH |
1314 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
1315 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
26ec634c | 1316 | if (rc) { |
284901a9 | 1317 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
26ec634c | 1318 | if (rc) { |
a44fec1f JP |
1319 | dev_err(&pdev->dev, |
1320 | "64-bit DMA enable failed\n"); | |
24dc5f33 | 1321 | return rc; |
26ec634c TH |
1322 | } |
1323 | } | |
1324 | } else { | |
284901a9 | 1325 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
26ec634c | 1326 | if (rc) { |
a44fec1f | 1327 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
24dc5f33 | 1328 | return rc; |
26ec634c | 1329 | } |
284901a9 | 1330 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
26ec634c | 1331 | if (rc) { |
a44fec1f JP |
1332 | dev_err(&pdev->dev, |
1333 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 1334 | return rc; |
26ec634c | 1335 | } |
edb33667 TH |
1336 | } |
1337 | ||
e8b3b5e9 TH |
1338 | /* Set max read request size to 4096. This slightly increases |
1339 | * write throughput for pci-e variants. | |
1340 | */ | |
1341 | pcie_set_readrq(pdev, 4096); | |
1342 | ||
4447d351 | 1343 | sil24_init_controller(host); |
edb33667 | 1344 | |
dae77214 | 1345 | if (sata_sil24_msi && !pci_enable_msi(pdev)) { |
a44fec1f | 1346 | dev_info(&pdev->dev, "Using MSI\n"); |
dae77214 VM |
1347 | pci_intx(pdev, 0); |
1348 | } | |
1349 | ||
edb33667 | 1350 | pci_set_master(pdev); |
4447d351 TH |
1351 | return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, |
1352 | &sil24_sht); | |
edb33667 TH |
1353 | } |
1354 | ||
58eb8cd5 | 1355 | #ifdef CONFIG_PM_SLEEP |
d2298dca TH |
1356 | static int sil24_pci_device_resume(struct pci_dev *pdev) |
1357 | { | |
0a86e1c8 | 1358 | struct ata_host *host = pci_get_drvdata(pdev); |
0d5ff566 | 1359 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
553c4aa6 | 1360 | int rc; |
d2298dca | 1361 | |
553c4aa6 TH |
1362 | rc = ata_pci_device_do_resume(pdev); |
1363 | if (rc) | |
1364 | return rc; | |
d2298dca TH |
1365 | |
1366 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) | |
0d5ff566 | 1367 | writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); |
d2298dca | 1368 | |
4447d351 | 1369 | sil24_init_controller(host); |
d2298dca | 1370 | |
cca3974e | 1371 | ata_host_resume(host); |
d2298dca TH |
1372 | |
1373 | return 0; | |
1374 | } | |
58eb8cd5 | 1375 | #endif |
3454dc69 | 1376 | |
58eb8cd5 | 1377 | #ifdef CONFIG_PM |
3454dc69 TH |
1378 | static int sil24_port_resume(struct ata_port *ap) |
1379 | { | |
1380 | sil24_config_pmp(ap, ap->nr_pmp_links); | |
1381 | return 0; | |
1382 | } | |
281d426c | 1383 | #endif |
d2298dca | 1384 | |
2fc75da0 | 1385 | module_pci_driver(sil24_pci_driver); |
edb33667 TH |
1386 | |
1387 | MODULE_AUTHOR("Tejun Heo"); | |
1388 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1389 | MODULE_LICENSE("GPL"); | |
1390 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); |