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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/dma-mapping.h> | |
a9524a76 | 27 | #include <linux/device.h> |
edb33667 | 28 | #include <scsi/scsi_host.h> |
193515d5 | 29 | #include <scsi/scsi_cmnd.h> |
edb33667 TH |
30 | #include <linux/libata.h> |
31 | #include <asm/io.h> | |
32 | ||
33 | #define DRV_NAME "sata_sil24" | |
8676ce07 | 34 | #define DRV_VERSION "0.3" |
edb33667 | 35 | |
edb33667 TH |
36 | /* |
37 | * Port request block (PRB) 32 bytes | |
38 | */ | |
39 | struct sil24_prb { | |
b4772574 AD |
40 | __le16 ctrl; |
41 | __le16 prot; | |
42 | __le32 rx_cnt; | |
edb33667 TH |
43 | u8 fis[6 * 4]; |
44 | }; | |
45 | ||
46 | /* | |
47 | * Scatter gather entry (SGE) 16 bytes | |
48 | */ | |
49 | struct sil24_sge { | |
b4772574 AD |
50 | __le64 addr; |
51 | __le32 cnt; | |
52 | __le32 flags; | |
edb33667 TH |
53 | }; |
54 | ||
55 | /* | |
56 | * Port multiplier | |
57 | */ | |
58 | struct sil24_port_multiplier { | |
b4772574 AD |
59 | __le32 diag; |
60 | __le32 sactive; | |
edb33667 TH |
61 | }; |
62 | ||
63 | enum { | |
64 | /* | |
65 | * Global controller registers (128 bytes @ BAR0) | |
66 | */ | |
67 | /* 32 bit regs */ | |
68 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
69 | HOST_CTRL = 0x40, | |
70 | HOST_IRQ_STAT = 0x44, | |
71 | HOST_PHY_CFG = 0x48, | |
72 | HOST_BIST_CTRL = 0x50, | |
73 | HOST_BIST_PTRN = 0x54, | |
74 | HOST_BIST_STAT = 0x58, | |
75 | HOST_MEM_BIST_STAT = 0x5c, | |
76 | HOST_FLASH_CMD = 0x70, | |
77 | /* 8 bit regs */ | |
78 | HOST_FLASH_DATA = 0x74, | |
79 | HOST_TRANSITION_DETECT = 0x75, | |
80 | HOST_GPIO_CTRL = 0x76, | |
81 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
82 | HOST_I2C_DATA = 0x7c, | |
83 | HOST_I2C_XFER_CNT = 0x7e, | |
84 | HOST_I2C_CTRL = 0x7f, | |
85 | ||
86 | /* HOST_SLOT_STAT bits */ | |
87 | HOST_SSTAT_ATTN = (1 << 31), | |
88 | ||
7dafc3fd TH |
89 | /* HOST_CTRL bits */ |
90 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ | |
91 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ | |
92 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ | |
93 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ | |
94 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ | |
d2298dca | 95 | HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ |
7dafc3fd | 96 | |
edb33667 TH |
97 | /* |
98 | * Port registers | |
99 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
100 | */ | |
101 | PORT_REGS_SIZE = 0x2000, | |
135da345 | 102 | |
28c8f3b4 | 103 | PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ |
135da345 | 104 | PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ |
edb33667 | 105 | |
28c8f3b4 | 106 | PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ |
c0c55908 TH |
107 | PORT_PMP_STATUS = 0x0000, /* port device status offset */ |
108 | PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ | |
109 | PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ | |
110 | ||
edb33667 | 111 | /* 32 bit regs */ |
83bbecc9 TH |
112 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
113 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
114 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
115 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
116 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 117 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
118 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
119 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
120 | PORT_FIS_CFG = 0x1028, |
121 | PORT_FIFO_THRES = 0x102c, | |
122 | /* 16 bit regs */ | |
123 | PORT_DECODE_ERR_CNT = 0x1040, | |
124 | PORT_DECODE_ERR_THRESH = 0x1042, | |
125 | PORT_CRC_ERR_CNT = 0x1044, | |
126 | PORT_CRC_ERR_THRESH = 0x1046, | |
127 | PORT_HSHK_ERR_CNT = 0x1048, | |
128 | PORT_HSHK_ERR_THRESH = 0x104a, | |
129 | /* 32 bit regs */ | |
130 | PORT_PHY_CFG = 0x1050, | |
131 | PORT_SLOT_STAT = 0x1800, | |
132 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
c0c55908 | 133 | PORT_CONTEXT = 0x1e04, |
edb33667 TH |
134 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
135 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
136 | PORT_SCONTROL = 0x1f00, | |
137 | PORT_SSTATUS = 0x1f04, | |
138 | PORT_SERROR = 0x1f08, | |
139 | PORT_SACTIVE = 0x1f0c, | |
140 | ||
141 | /* PORT_CTRL_STAT bits */ | |
142 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
143 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
144 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
145 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 146 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
28c8f3b4 | 147 | PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ |
e382eb1d | 148 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
28c8f3b4 | 149 | PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ |
e382eb1d | 150 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
edb33667 TH |
151 | |
152 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
153 | /* bits[11:0] are masked */ | |
154 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
155 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
156 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
157 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
158 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
159 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
7dafc3fd TH |
160 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
161 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ | |
162 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ | |
163 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ | |
164 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ | |
3b9f1d0f | 165 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
edb33667 | 166 | |
88ce7550 | 167 | DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
0542925b TH |
168 | PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | |
169 | PORT_IRQ_UNK_FIS, | |
88ce7550 | 170 | |
edb33667 TH |
171 | /* bits[27:16] are unmasked (raw) */ |
172 | PORT_IRQ_RAW_SHIFT = 16, | |
173 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
174 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
175 | ||
176 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
177 | PORT_IRQ_STEER_SHIFT = 30, | |
178 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
179 | ||
180 | /* PORT_CMD_ERR constants */ | |
181 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
182 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
183 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
184 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
185 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
186 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
187 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
188 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
189 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
190 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
191 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
192 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
193 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
194 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
195 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
196 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
197 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
198 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
199 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
64008802 | 200 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
edb33667 | 201 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
83bbecc9 | 202 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 203 | |
d10cb35a TH |
204 | /* bits of PRB control field */ |
205 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
206 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
207 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
208 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
209 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
210 | ||
211 | /* PRB protocol field */ | |
212 | PRB_PROT_PACKET = (1 << 0), | |
213 | PRB_PROT_TCQ = (1 << 1), | |
214 | PRB_PROT_NCQ = (1 << 2), | |
215 | PRB_PROT_READ = (1 << 3), | |
216 | PRB_PROT_WRITE = (1 << 4), | |
217 | PRB_PROT_TRANSPARENT = (1 << 5), | |
218 | ||
edb33667 TH |
219 | /* |
220 | * Other constants | |
221 | */ | |
222 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
223 | SGE_LNK = (1 << 30), /* linked list |
224 | Points to SGT, not SGE */ | |
225 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
226 | data address ignored */ | |
edb33667 | 227 | |
aee10a03 TH |
228 | SIL24_MAX_CMDS = 31, |
229 | ||
edb33667 TH |
230 | /* board id */ |
231 | BID_SIL3124 = 0, | |
232 | BID_SIL3132 = 1, | |
042c21fd | 233 | BID_SIL3131 = 2, |
edb33667 | 234 | |
9466d85b TH |
235 | /* host flags */ |
236 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
aee10a03 | 237 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
0542925b | 238 | ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY, |
37024e8e | 239 | SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ |
9466d85b | 240 | |
edb33667 TH |
241 | IRQ_STAT_4PORTS = 0xf, |
242 | }; | |
243 | ||
69ad185f | 244 | struct sil24_ata_block { |
edb33667 TH |
245 | struct sil24_prb prb; |
246 | struct sil24_sge sge[LIBATA_MAX_PRD]; | |
247 | }; | |
248 | ||
69ad185f TH |
249 | struct sil24_atapi_block { |
250 | struct sil24_prb prb; | |
251 | u8 cdb[16]; | |
252 | struct sil24_sge sge[LIBATA_MAX_PRD - 1]; | |
253 | }; | |
254 | ||
255 | union sil24_cmd_block { | |
256 | struct sil24_ata_block ata; | |
257 | struct sil24_atapi_block atapi; | |
258 | }; | |
259 | ||
88ce7550 TH |
260 | static struct sil24_cerr_info { |
261 | unsigned int err_mask, action; | |
262 | const char *desc; | |
263 | } sil24_cerr_db[] = { | |
264 | [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE, | |
265 | "device error" }, | |
266 | [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE, | |
267 | "device error via D2H FIS" }, | |
268 | [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE, | |
269 | "device error via SDB FIS" }, | |
270 | [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, | |
271 | "error in data FIS" }, | |
272 | [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, | |
273 | "failed to transmit command FIS" }, | |
274 | [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
275 | "protocol mismatch" }, | |
276 | [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
277 | "data directon mismatch" }, | |
278 | [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
279 | "ran out of SGEs while writing" }, | |
280 | [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
281 | "ran out of SGEs while reading" }, | |
282 | [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
283 | "invalid data directon for ATAPI CDB" }, | |
284 | [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, | |
285 | "SGT no on qword boundary" }, | |
286 | [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
287 | "PCI target abort while fetching SGT" }, | |
288 | [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
289 | "PCI master abort while fetching SGT" }, | |
290 | [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
291 | "PCI parity error while fetching SGT" }, | |
292 | [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, | |
293 | "PRB not on qword boundary" }, | |
294 | [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
295 | "PCI target abort while fetching PRB" }, | |
296 | [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
297 | "PCI master abort while fetching PRB" }, | |
298 | [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
299 | "PCI parity error while fetching PRB" }, | |
300 | [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
301 | "undefined error while transferring data" }, | |
302 | [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
303 | "PCI target abort while transferring data" }, | |
304 | [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
305 | "PCI master abort while transferring data" }, | |
306 | [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
307 | "PCI parity error while transferring data" }, | |
308 | [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
309 | "FIS received while sending service FIS" }, | |
310 | }; | |
311 | ||
edb33667 TH |
312 | /* |
313 | * ap->private_data | |
314 | * | |
315 | * The preview driver always returned 0 for status. We emulate it | |
316 | * here from the previous interrupt. | |
317 | */ | |
318 | struct sil24_port_priv { | |
69ad185f | 319 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 320 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
6a575fa9 | 321 | struct ata_taskfile tf; /* Cached taskfile registers */ |
edb33667 TH |
322 | }; |
323 | ||
cca3974e | 324 | /* ap->host->private_data */ |
edb33667 | 325 | struct sil24_host_priv { |
4b4a5eae AV |
326 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ |
327 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ | |
edb33667 TH |
328 | }; |
329 | ||
69ad185f | 330 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
edb33667 | 331 | static u8 sil24_check_status(struct ata_port *ap); |
edb33667 TH |
332 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
333 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); | |
7f726d12 | 334 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
edb33667 | 335 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 336 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
edb33667 | 337 | static void sil24_irq_clear(struct ata_port *ap); |
7d12e780 | 338 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance); |
88ce7550 TH |
339 | static void sil24_freeze(struct ata_port *ap); |
340 | static void sil24_thaw(struct ata_port *ap); | |
341 | static void sil24_error_handler(struct ata_port *ap); | |
342 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); | |
edb33667 TH |
343 | static int sil24_port_start(struct ata_port *ap); |
344 | static void sil24_port_stop(struct ata_port *ap); | |
cca3974e | 345 | static void sil24_host_stop(struct ata_host *host); |
edb33667 | 346 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
281d426c | 347 | #ifdef CONFIG_PM |
d2298dca | 348 | static int sil24_pci_device_resume(struct pci_dev *pdev); |
281d426c | 349 | #endif |
edb33667 | 350 | |
3b7d697d | 351 | static const struct pci_device_id sil24_pci_tbl[] = { |
54bb3a94 JG |
352 | { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, |
353 | { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, | |
354 | { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, | |
355 | { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, | |
356 | { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, | |
357 | ||
1fcce839 | 358 | { } /* terminate list */ |
edb33667 TH |
359 | }; |
360 | ||
361 | static struct pci_driver sil24_pci_driver = { | |
362 | .name = DRV_NAME, | |
363 | .id_table = sil24_pci_tbl, | |
364 | .probe = sil24_init_one, | |
365 | .remove = ata_pci_remove_one, /* safe? */ | |
281d426c | 366 | #ifdef CONFIG_PM |
d2298dca TH |
367 | .suspend = ata_pci_device_suspend, |
368 | .resume = sil24_pci_device_resume, | |
281d426c | 369 | #endif |
edb33667 TH |
370 | }; |
371 | ||
193515d5 | 372 | static struct scsi_host_template sil24_sht = { |
edb33667 TH |
373 | .module = THIS_MODULE, |
374 | .name = DRV_NAME, | |
375 | .ioctl = ata_scsi_ioctl, | |
376 | .queuecommand = ata_scsi_queuecmd, | |
aee10a03 TH |
377 | .change_queue_depth = ata_scsi_change_queue_depth, |
378 | .can_queue = SIL24_MAX_CMDS, | |
edb33667 TH |
379 | .this_id = ATA_SHT_THIS_ID, |
380 | .sg_tablesize = LIBATA_MAX_PRD, | |
edb33667 TH |
381 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
382 | .emulated = ATA_SHT_EMULATED, | |
383 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
384 | .proc_name = DRV_NAME, | |
385 | .dma_boundary = ATA_DMA_BOUNDARY, | |
386 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 387 | .slave_destroy = ata_scsi_slave_destroy, |
edb33667 | 388 | .bios_param = ata_std_bios_param, |
d2298dca TH |
389 | .suspend = ata_scsi_device_suspend, |
390 | .resume = ata_scsi_device_resume, | |
edb33667 TH |
391 | }; |
392 | ||
057ace5e | 393 | static const struct ata_port_operations sil24_ops = { |
edb33667 TH |
394 | .port_disable = ata_port_disable, |
395 | ||
69ad185f TH |
396 | .dev_config = sil24_dev_config, |
397 | ||
edb33667 TH |
398 | .check_status = sil24_check_status, |
399 | .check_altstatus = sil24_check_status, | |
edb33667 TH |
400 | .dev_select = ata_noop_dev_select, |
401 | ||
7f726d12 TH |
402 | .tf_read = sil24_tf_read, |
403 | ||
edb33667 TH |
404 | .qc_prep = sil24_qc_prep, |
405 | .qc_issue = sil24_qc_issue, | |
406 | ||
edb33667 TH |
407 | .irq_handler = sil24_interrupt, |
408 | .irq_clear = sil24_irq_clear, | |
409 | ||
410 | .scr_read = sil24_scr_read, | |
411 | .scr_write = sil24_scr_write, | |
412 | ||
88ce7550 TH |
413 | .freeze = sil24_freeze, |
414 | .thaw = sil24_thaw, | |
415 | .error_handler = sil24_error_handler, | |
416 | .post_internal_cmd = sil24_post_internal_cmd, | |
417 | ||
edb33667 TH |
418 | .port_start = sil24_port_start, |
419 | .port_stop = sil24_port_stop, | |
420 | .host_stop = sil24_host_stop, | |
421 | }; | |
422 | ||
042c21fd | 423 | /* |
cca3974e | 424 | * Use bits 30-31 of port_flags to encode available port numbers. |
042c21fd TH |
425 | * Current maxium is 4. |
426 | */ | |
427 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
428 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
429 | ||
edb33667 TH |
430 | static struct ata_port_info sil24_port_info[] = { |
431 | /* sil_3124 */ | |
432 | { | |
433 | .sht = &sil24_sht, | |
cca3974e | 434 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | |
37024e8e | 435 | SIL24_FLAG_PCIX_IRQ_WOC, |
edb33667 TH |
436 | .pio_mask = 0x1f, /* pio0-4 */ |
437 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
438 | .udma_mask = 0x3f, /* udma0-5 */ | |
439 | .port_ops = &sil24_ops, | |
440 | }, | |
2e9edbf8 | 441 | /* sil_3132 */ |
edb33667 TH |
442 | { |
443 | .sht = &sil24_sht, | |
cca3974e | 444 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
042c21fd TH |
445 | .pio_mask = 0x1f, /* pio0-4 */ |
446 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
447 | .udma_mask = 0x3f, /* udma0-5 */ | |
448 | .port_ops = &sil24_ops, | |
449 | }, | |
450 | /* sil_3131/sil_3531 */ | |
451 | { | |
452 | .sht = &sil24_sht, | |
cca3974e | 453 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
edb33667 TH |
454 | .pio_mask = 0x1f, /* pio0-4 */ |
455 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
456 | .udma_mask = 0x3f, /* udma0-5 */ | |
457 | .port_ops = &sil24_ops, | |
458 | }, | |
459 | }; | |
460 | ||
aee10a03 TH |
461 | static int sil24_tag(int tag) |
462 | { | |
463 | if (unlikely(ata_tag_internal(tag))) | |
464 | return 0; | |
465 | return tag; | |
466 | } | |
467 | ||
69ad185f TH |
468 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
469 | { | |
470 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | |
471 | ||
6e7846e9 | 472 | if (dev->cdb_len == 16) |
69ad185f TH |
473 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
474 | else | |
475 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
476 | } | |
477 | ||
6a575fa9 TH |
478 | static inline void sil24_update_tf(struct ata_port *ap) |
479 | { | |
480 | struct sil24_port_priv *pp = ap->private_data; | |
4b4a5eae AV |
481 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
482 | struct sil24_prb __iomem *prb = port; | |
483 | u8 fis[6 * 4]; | |
6a575fa9 | 484 | |
4b4a5eae AV |
485 | memcpy_fromio(fis, prb->fis, 6 * 4); |
486 | ata_tf_from_fis(fis, &pp->tf); | |
6a575fa9 TH |
487 | } |
488 | ||
edb33667 TH |
489 | static u8 sil24_check_status(struct ata_port *ap) |
490 | { | |
6a575fa9 TH |
491 | struct sil24_port_priv *pp = ap->private_data; |
492 | return pp->tf.command; | |
edb33667 TH |
493 | } |
494 | ||
edb33667 TH |
495 | static int sil24_scr_map[] = { |
496 | [SCR_CONTROL] = 0, | |
497 | [SCR_STATUS] = 1, | |
498 | [SCR_ERROR] = 2, | |
499 | [SCR_ACTIVE] = 3, | |
500 | }; | |
501 | ||
502 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |
503 | { | |
4b4a5eae | 504 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 505 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 506 | void __iomem *addr; |
edb33667 TH |
507 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
508 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); | |
509 | } | |
510 | return 0xffffffffU; | |
511 | } | |
512 | ||
513 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | |
514 | { | |
4b4a5eae | 515 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 516 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 517 | void __iomem *addr; |
edb33667 TH |
518 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
519 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
520 | } | |
521 | } | |
522 | ||
7f726d12 TH |
523 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
524 | { | |
525 | struct sil24_port_priv *pp = ap->private_data; | |
526 | *tf = pp->tf; | |
527 | } | |
528 | ||
b5bc421c TH |
529 | static int sil24_init_port(struct ata_port *ap) |
530 | { | |
531 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | |
532 | u32 tmp; | |
533 | ||
534 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); | |
535 | ata_wait_register(port + PORT_CTRL_STAT, | |
536 | PORT_CS_INIT, PORT_CS_INIT, 10, 100); | |
537 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
538 | PORT_CS_RDY, 0, 10, 100); | |
539 | ||
540 | if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) | |
541 | return -EIO; | |
542 | return 0; | |
543 | } | |
544 | ||
2bf2cb26 | 545 | static int sil24_softreset(struct ata_port *ap, unsigned int *class) |
edb33667 | 546 | { |
ca45160d TH |
547 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
548 | struct sil24_port_priv *pp = ap->private_data; | |
69ad185f | 549 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d | 550 | dma_addr_t paddr = pp->cmd_block_dma; |
88ce7550 | 551 | u32 mask, irq_stat; |
643be977 | 552 | const char *reason; |
ca45160d | 553 | |
07b73470 TH |
554 | DPRINTK("ENTER\n"); |
555 | ||
81952c54 | 556 | if (ata_port_offline(ap)) { |
10d996ad TH |
557 | DPRINTK("PHY reports no device\n"); |
558 | *class = ATA_DEV_NONE; | |
559 | goto out; | |
560 | } | |
561 | ||
2555d6c2 TH |
562 | /* put the port into known state */ |
563 | if (sil24_init_port(ap)) { | |
564 | reason ="port not ready"; | |
565 | goto err; | |
566 | } | |
567 | ||
0eaa6058 | 568 | /* do SRST */ |
bad28a37 | 569 | prb->ctrl = cpu_to_le16(PRB_CTRL_SRST); |
28c8f3b4 | 570 | prb->fis[1] = 0; /* no PMP yet */ |
ca45160d TH |
571 | |
572 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); | |
26ec634c | 573 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); |
ca45160d | 574 | |
7dd29dd6 TH |
575 | mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; |
576 | irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0, | |
577 | 100, ATA_TMOUT_BOOT / HZ * 1000); | |
ca45160d | 578 | |
7dd29dd6 TH |
579 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */ |
580 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
ca45160d | 581 | |
10d996ad | 582 | if (!(irq_stat & PORT_IRQ_COMPLETE)) { |
643be977 TH |
583 | if (irq_stat & PORT_IRQ_ERROR) |
584 | reason = "SRST command error"; | |
585 | else | |
586 | reason = "timeout"; | |
587 | goto err; | |
07b73470 | 588 | } |
10d996ad TH |
589 | |
590 | sil24_update_tf(ap); | |
591 | *class = ata_dev_classify(&pp->tf); | |
592 | ||
07b73470 TH |
593 | if (*class == ATA_DEV_UNKNOWN) |
594 | *class = ATA_DEV_NONE; | |
ca45160d | 595 | |
10d996ad | 596 | out: |
07b73470 | 597 | DPRINTK("EXIT, class=%u\n", *class); |
ca45160d | 598 | return 0; |
643be977 TH |
599 | |
600 | err: | |
f15a1daf | 601 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
643be977 | 602 | return -EIO; |
ca45160d TH |
603 | } |
604 | ||
2bf2cb26 | 605 | static int sil24_hardreset(struct ata_port *ap, unsigned int *class) |
489ff4c7 | 606 | { |
ecc2e2b9 TH |
607 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
608 | const char *reason; | |
e8e008e7 | 609 | int tout_msec, rc; |
ecc2e2b9 TH |
610 | u32 tmp; |
611 | ||
612 | /* sil24 does the right thing(tm) without any protection */ | |
3c567b7d | 613 | sata_set_spd(ap); |
ecc2e2b9 TH |
614 | |
615 | tout_msec = 100; | |
81952c54 | 616 | if (ata_port_online(ap)) |
ecc2e2b9 TH |
617 | tout_msec = 5000; |
618 | ||
619 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
620 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
621 | PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec); | |
622 | ||
e8e008e7 TH |
623 | /* SStatus oscillates between zero and valid status after |
624 | * DEV_RST, debounce it. | |
ecc2e2b9 | 625 | */ |
e9c83914 | 626 | rc = sata_phy_debounce(ap, sata_deb_timing_long); |
e8e008e7 TH |
627 | if (rc) { |
628 | reason = "PHY debouncing failed"; | |
629 | goto err; | |
630 | } | |
ecc2e2b9 TH |
631 | |
632 | if (tmp & PORT_CS_DEV_RST) { | |
81952c54 | 633 | if (ata_port_offline(ap)) |
ecc2e2b9 TH |
634 | return 0; |
635 | reason = "link not ready"; | |
636 | goto err; | |
637 | } | |
638 | ||
e8e008e7 TH |
639 | /* Sil24 doesn't store signature FIS after hardreset, so we |
640 | * can't wait for BSY to clear. Some devices take a long time | |
641 | * to get ready and those devices will choke if we don't wait | |
642 | * for BSY clearance here. Tell libata to perform follow-up | |
643 | * softreset. | |
ecc2e2b9 | 644 | */ |
e8e008e7 | 645 | return -EAGAIN; |
ecc2e2b9 TH |
646 | |
647 | err: | |
f15a1daf | 648 | ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason); |
ecc2e2b9 | 649 | return -EIO; |
489ff4c7 TH |
650 | } |
651 | ||
edb33667 | 652 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
69ad185f | 653 | struct sil24_sge *sge) |
edb33667 | 654 | { |
972c26bd JG |
655 | struct scatterlist *sg; |
656 | unsigned int idx = 0; | |
edb33667 | 657 | |
972c26bd | 658 | ata_for_each_sg(sg, qc) { |
edb33667 TH |
659 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
660 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
972c26bd JG |
661 | if (ata_sg_is_last(sg, qc)) |
662 | sge->flags = cpu_to_le32(SGE_TRM); | |
663 | else | |
664 | sge->flags = 0; | |
665 | ||
666 | sge++; | |
667 | idx++; | |
edb33667 TH |
668 | } |
669 | } | |
670 | ||
671 | static void sil24_qc_prep(struct ata_queued_cmd *qc) | |
672 | { | |
673 | struct ata_port *ap = qc->ap; | |
674 | struct sil24_port_priv *pp = ap->private_data; | |
aee10a03 | 675 | union sil24_cmd_block *cb; |
69ad185f TH |
676 | struct sil24_prb *prb; |
677 | struct sil24_sge *sge; | |
bad28a37 | 678 | u16 ctrl = 0; |
edb33667 | 679 | |
aee10a03 TH |
680 | cb = &pp->cmd_block[sil24_tag(qc->tag)]; |
681 | ||
edb33667 TH |
682 | switch (qc->tf.protocol) { |
683 | case ATA_PROT_PIO: | |
684 | case ATA_PROT_DMA: | |
aee10a03 | 685 | case ATA_PROT_NCQ: |
edb33667 | 686 | case ATA_PROT_NODATA: |
69ad185f TH |
687 | prb = &cb->ata.prb; |
688 | sge = cb->ata.sge; | |
edb33667 | 689 | break; |
69ad185f TH |
690 | |
691 | case ATA_PROT_ATAPI: | |
692 | case ATA_PROT_ATAPI_DMA: | |
693 | case ATA_PROT_ATAPI_NODATA: | |
694 | prb = &cb->atapi.prb; | |
695 | sge = cb->atapi.sge; | |
696 | memset(cb->atapi.cdb, 0, 32); | |
6e7846e9 | 697 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
69ad185f TH |
698 | |
699 | if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { | |
700 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
bad28a37 | 701 | ctrl = PRB_CTRL_PACKET_WRITE; |
69ad185f | 702 | else |
bad28a37 TH |
703 | ctrl = PRB_CTRL_PACKET_READ; |
704 | } | |
69ad185f TH |
705 | break; |
706 | ||
edb33667 | 707 | default: |
69ad185f TH |
708 | prb = NULL; /* shut up, gcc */ |
709 | sge = NULL; | |
edb33667 TH |
710 | BUG(); |
711 | } | |
712 | ||
bad28a37 | 713 | prb->ctrl = cpu_to_le16(ctrl); |
edb33667 TH |
714 | ata_tf_to_fis(&qc->tf, prb->fis, 0); |
715 | ||
716 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 717 | sil24_fill_sg(qc, sge); |
edb33667 TH |
718 | } |
719 | ||
9a3d9eb0 | 720 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
721 | { |
722 | struct ata_port *ap = qc->ap; | |
723 | struct sil24_port_priv *pp = ap->private_data; | |
aee10a03 TH |
724 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
725 | unsigned int tag = sil24_tag(qc->tag); | |
726 | dma_addr_t paddr; | |
727 | void __iomem *activate; | |
edb33667 | 728 | |
aee10a03 TH |
729 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); |
730 | activate = port + PORT_CMD_ACTIVATE + tag * 8; | |
731 | ||
732 | writel((u32)paddr, activate); | |
733 | writel((u64)paddr >> 32, activate + 4); | |
26ec634c | 734 | |
edb33667 TH |
735 | return 0; |
736 | } | |
737 | ||
738 | static void sil24_irq_clear(struct ata_port *ap) | |
739 | { | |
740 | /* unused */ | |
741 | } | |
742 | ||
88ce7550 | 743 | static void sil24_freeze(struct ata_port *ap) |
7d1ce682 | 744 | { |
88ce7550 | 745 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
7d1ce682 | 746 | |
88ce7550 TH |
747 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear |
748 | * PORT_IRQ_ENABLE instead. | |
749 | */ | |
750 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
7d1ce682 TH |
751 | } |
752 | ||
88ce7550 | 753 | static void sil24_thaw(struct ata_port *ap) |
edb33667 | 754 | { |
88ce7550 | 755 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
756 | u32 tmp; |
757 | ||
88ce7550 TH |
758 | /* clear IRQ */ |
759 | tmp = readl(port + PORT_IRQ_STAT); | |
760 | writel(tmp, port + PORT_IRQ_STAT); | |
edb33667 | 761 | |
88ce7550 TH |
762 | /* turn IRQ back on */ |
763 | writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); | |
edb33667 TH |
764 | } |
765 | ||
88ce7550 | 766 | static void sil24_error_intr(struct ata_port *ap) |
8746618d | 767 | { |
4b4a5eae | 768 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
88ce7550 TH |
769 | struct ata_eh_info *ehi = &ap->eh_info; |
770 | int freeze = 0; | |
771 | u32 irq_stat; | |
8746618d | 772 | |
88ce7550 | 773 | /* on error, we need to clear IRQ explicitly */ |
8746618d | 774 | irq_stat = readl(port + PORT_IRQ_STAT); |
88ce7550 | 775 | writel(irq_stat, port + PORT_IRQ_STAT); |
ad6e90f6 | 776 | |
88ce7550 TH |
777 | /* first, analyze and record host port events */ |
778 | ata_ehi_clear_desc(ehi); | |
ad6e90f6 | 779 | |
88ce7550 | 780 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
8746618d | 781 | |
0542925b TH |
782 | if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { |
783 | ata_ehi_hotplugged(ehi); | |
784 | ata_ehi_push_desc(ehi, ", %s", | |
785 | irq_stat & PORT_IRQ_PHYRDY_CHG ? | |
786 | "PHY RDY changed" : "device exchanged"); | |
88ce7550 | 787 | freeze = 1; |
6a575fa9 TH |
788 | } |
789 | ||
88ce7550 TH |
790 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
791 | ehi->err_mask |= AC_ERR_HSM; | |
792 | ehi->action |= ATA_EH_SOFTRESET; | |
793 | ata_ehi_push_desc(ehi , ", unknown FIS"); | |
794 | freeze = 1; | |
795 | } | |
796 | ||
797 | /* deal with command error */ | |
798 | if (irq_stat & PORT_IRQ_ERROR) { | |
799 | struct sil24_cerr_info *ci = NULL; | |
800 | unsigned int err_mask = 0, action = 0; | |
801 | struct ata_queued_cmd *qc; | |
802 | u32 cerr; | |
803 | ||
804 | /* analyze CMD_ERR */ | |
805 | cerr = readl(port + PORT_CMD_ERR); | |
806 | if (cerr < ARRAY_SIZE(sil24_cerr_db)) | |
807 | ci = &sil24_cerr_db[cerr]; | |
808 | ||
809 | if (ci && ci->desc) { | |
810 | err_mask |= ci->err_mask; | |
811 | action |= ci->action; | |
812 | ata_ehi_push_desc(ehi, ", %s", ci->desc); | |
813 | } else { | |
814 | err_mask |= AC_ERR_OTHER; | |
815 | action |= ATA_EH_SOFTRESET; | |
816 | ata_ehi_push_desc(ehi, ", unknown command error %d", | |
817 | cerr); | |
818 | } | |
819 | ||
820 | /* record error info */ | |
821 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
822 | if (qc) { | |
88ce7550 TH |
823 | sil24_update_tf(ap); |
824 | qc->err_mask |= err_mask; | |
825 | } else | |
826 | ehi->err_mask |= err_mask; | |
827 | ||
828 | ehi->action |= action; | |
a22e2eb0 | 829 | } |
88ce7550 TH |
830 | |
831 | /* freeze or abort */ | |
832 | if (freeze) | |
833 | ata_port_freeze(ap); | |
834 | else | |
835 | ata_port_abort(ap); | |
8746618d TH |
836 | } |
837 | ||
aee10a03 TH |
838 | static void sil24_finish_qc(struct ata_queued_cmd *qc) |
839 | { | |
840 | if (qc->flags & ATA_QCFLAG_RESULT_TF) | |
841 | sil24_update_tf(qc->ap); | |
842 | } | |
843 | ||
edb33667 TH |
844 | static inline void sil24_host_intr(struct ata_port *ap) |
845 | { | |
4b4a5eae | 846 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
aee10a03 TH |
847 | u32 slot_stat, qc_active; |
848 | int rc; | |
edb33667 TH |
849 | |
850 | slot_stat = readl(port + PORT_SLOT_STAT); | |
37024e8e | 851 | |
88ce7550 TH |
852 | if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { |
853 | sil24_error_intr(ap); | |
854 | return; | |
855 | } | |
856 | ||
857 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
858 | writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); | |
37024e8e | 859 | |
aee10a03 TH |
860 | qc_active = slot_stat & ~HOST_SSTAT_ATTN; |
861 | rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc); | |
862 | if (rc > 0) | |
863 | return; | |
864 | if (rc < 0) { | |
865 | struct ata_eh_info *ehi = &ap->eh_info; | |
866 | ehi->err_mask |= AC_ERR_HSM; | |
867 | ehi->action |= ATA_EH_SOFTRESET; | |
868 | ata_port_freeze(ap); | |
88ce7550 TH |
869 | return; |
870 | } | |
871 | ||
872 | if (ata_ratelimit()) | |
873 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " | |
aee10a03 TH |
874 | "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", |
875 | slot_stat, ap->active_tag, ap->sactive); | |
edb33667 TH |
876 | } |
877 | ||
7d12e780 | 878 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) |
edb33667 | 879 | { |
cca3974e JG |
880 | struct ata_host *host = dev_instance; |
881 | struct sil24_host_priv *hpriv = host->private_data; | |
edb33667 TH |
882 | unsigned handled = 0; |
883 | u32 status; | |
884 | int i; | |
885 | ||
886 | status = readl(hpriv->host_base + HOST_IRQ_STAT); | |
887 | ||
06460aea TH |
888 | if (status == 0xffffffff) { |
889 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
890 | "PCI fault or device removal?\n"); | |
891 | goto out; | |
892 | } | |
893 | ||
edb33667 TH |
894 | if (!(status & IRQ_STAT_4PORTS)) |
895 | goto out; | |
896 | ||
cca3974e | 897 | spin_lock(&host->lock); |
edb33667 | 898 | |
cca3974e | 899 | for (i = 0; i < host->n_ports; i++) |
edb33667 | 900 | if (status & (1 << i)) { |
cca3974e | 901 | struct ata_port *ap = host->ports[i]; |
198e0fed | 902 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
cca3974e | 903 | sil24_host_intr(host->ports[i]); |
3cc4571c TH |
904 | handled++; |
905 | } else | |
906 | printk(KERN_ERR DRV_NAME | |
907 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
908 | } |
909 | ||
cca3974e | 910 | spin_unlock(&host->lock); |
edb33667 TH |
911 | out: |
912 | return IRQ_RETVAL(handled); | |
913 | } | |
914 | ||
88ce7550 TH |
915 | static void sil24_error_handler(struct ata_port *ap) |
916 | { | |
917 | struct ata_eh_context *ehc = &ap->eh_context; | |
918 | ||
919 | if (sil24_init_port(ap)) { | |
920 | ata_eh_freeze_port(ap); | |
921 | ehc->i.action |= ATA_EH_HARDRESET; | |
922 | } | |
923 | ||
924 | /* perform recovery */ | |
f5914a46 TH |
925 | ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset, |
926 | ata_std_postreset); | |
88ce7550 TH |
927 | } |
928 | ||
929 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) | |
930 | { | |
931 | struct ata_port *ap = qc->ap; | |
932 | ||
933 | if (qc->flags & ATA_QCFLAG_FAILED) | |
934 | qc->err_mask |= AC_ERR_OTHER; | |
935 | ||
936 | /* make DMA engine forget about the failed command */ | |
937 | if (qc->err_mask) | |
938 | sil24_init_port(ap); | |
939 | } | |
940 | ||
6037d6bb JG |
941 | static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev) |
942 | { | |
aee10a03 | 943 | const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS; |
6037d6bb JG |
944 | |
945 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); | |
946 | } | |
947 | ||
edb33667 TH |
948 | static int sil24_port_start(struct ata_port *ap) |
949 | { | |
cca3974e | 950 | struct device *dev = ap->host->dev; |
edb33667 | 951 | struct sil24_port_priv *pp; |
69ad185f | 952 | union sil24_cmd_block *cb; |
aee10a03 | 953 | size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; |
edb33667 | 954 | dma_addr_t cb_dma; |
6037d6bb | 955 | int rc = -ENOMEM; |
edb33667 | 956 | |
6037d6bb | 957 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
edb33667 | 958 | if (!pp) |
6037d6bb | 959 | goto err_out; |
edb33667 | 960 | |
6a575fa9 TH |
961 | pp->tf.command = ATA_DRDY; |
962 | ||
edb33667 | 963 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb JG |
964 | if (!cb) |
965 | goto err_out_pp; | |
edb33667 TH |
966 | memset(cb, 0, cb_size); |
967 | ||
6037d6bb JG |
968 | rc = ata_pad_alloc(ap, dev); |
969 | if (rc) | |
970 | goto err_out_pad; | |
971 | ||
edb33667 TH |
972 | pp->cmd_block = cb; |
973 | pp->cmd_block_dma = cb_dma; | |
974 | ||
975 | ap->private_data = pp; | |
976 | ||
977 | return 0; | |
6037d6bb JG |
978 | |
979 | err_out_pad: | |
980 | sil24_cblk_free(pp, dev); | |
981 | err_out_pp: | |
982 | kfree(pp); | |
983 | err_out: | |
984 | return rc; | |
edb33667 TH |
985 | } |
986 | ||
987 | static void sil24_port_stop(struct ata_port *ap) | |
988 | { | |
cca3974e | 989 | struct device *dev = ap->host->dev; |
edb33667 | 990 | struct sil24_port_priv *pp = ap->private_data; |
edb33667 | 991 | |
6037d6bb | 992 | sil24_cblk_free(pp, dev); |
e9c05afa | 993 | ata_pad_free(ap, dev); |
edb33667 TH |
994 | kfree(pp); |
995 | } | |
996 | ||
cca3974e | 997 | static void sil24_host_stop(struct ata_host *host) |
edb33667 | 998 | { |
cca3974e JG |
999 | struct sil24_host_priv *hpriv = host->private_data; |
1000 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
edb33667 | 1001 | |
142877b0 JG |
1002 | pci_iounmap(pdev, hpriv->host_base); |
1003 | pci_iounmap(pdev, hpriv->port_base); | |
edb33667 TH |
1004 | kfree(hpriv); |
1005 | } | |
1006 | ||
2a41a610 | 1007 | static void sil24_init_controller(struct pci_dev *pdev, int n_ports, |
cca3974e | 1008 | unsigned long port_flags, |
2a41a610 TH |
1009 | void __iomem *host_base, |
1010 | void __iomem *port_base) | |
1011 | { | |
1012 | u32 tmp; | |
1013 | int i; | |
1014 | ||
1015 | /* GPIO off */ | |
1016 | writel(0, host_base + HOST_FLASH_CMD); | |
1017 | ||
1018 | /* clear global reset & mask interrupts during initialization */ | |
1019 | writel(0, host_base + HOST_CTRL); | |
1020 | ||
1021 | /* init ports */ | |
1022 | for (i = 0; i < n_ports; i++) { | |
1023 | void __iomem *port = port_base + i * PORT_REGS_SIZE; | |
1024 | ||
1025 | /* Initial PHY setting */ | |
1026 | writel(0x20c, port + PORT_PHY_CFG); | |
1027 | ||
1028 | /* Clear port RST */ | |
1029 | tmp = readl(port + PORT_CTRL_STAT); | |
1030 | if (tmp & PORT_CS_PORT_RST) { | |
1031 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
1032 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
1033 | PORT_CS_PORT_RST, | |
1034 | PORT_CS_PORT_RST, 10, 100); | |
1035 | if (tmp & PORT_CS_PORT_RST) | |
1036 | dev_printk(KERN_ERR, &pdev->dev, | |
1037 | "failed to clear port RST\n"); | |
1038 | } | |
1039 | ||
1040 | /* Configure IRQ WoC */ | |
cca3974e | 1041 | if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC) |
2a41a610 TH |
1042 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); |
1043 | else | |
1044 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
1045 | ||
1046 | /* Zero error counters. */ | |
1047 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
1048 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
1049 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
1050 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
1051 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
1052 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
1053 | ||
1054 | /* Always use 64bit activation */ | |
1055 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); | |
1056 | ||
1057 | /* Clear port multiplier enable and resume bits */ | |
28c8f3b4 TH |
1058 | writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, |
1059 | port + PORT_CTRL_CLR); | |
2a41a610 TH |
1060 | } |
1061 | ||
1062 | /* Turn on interrupts */ | |
1063 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
1064 | } | |
1065 | ||
edb33667 TH |
1066 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1067 | { | |
1068 | static int printed_version = 0; | |
1069 | unsigned int board_id = (unsigned int)ent->driver_data; | |
042c21fd | 1070 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
edb33667 TH |
1071 | struct ata_probe_ent *probe_ent = NULL; |
1072 | struct sil24_host_priv *hpriv = NULL; | |
4b4a5eae AV |
1073 | void __iomem *host_base = NULL; |
1074 | void __iomem *port_base = NULL; | |
edb33667 | 1075 | int i, rc; |
37024e8e | 1076 | u32 tmp; |
edb33667 TH |
1077 | |
1078 | if (!printed_version++) | |
a9524a76 | 1079 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edb33667 TH |
1080 | |
1081 | rc = pci_enable_device(pdev); | |
1082 | if (rc) | |
1083 | return rc; | |
1084 | ||
1085 | rc = pci_request_regions(pdev, DRV_NAME); | |
1086 | if (rc) | |
1087 | goto out_disable; | |
1088 | ||
1089 | rc = -ENOMEM; | |
142877b0 JG |
1090 | /* map mmio registers */ |
1091 | host_base = pci_iomap(pdev, 0, 0); | |
edb33667 TH |
1092 | if (!host_base) |
1093 | goto out_free; | |
142877b0 | 1094 | port_base = pci_iomap(pdev, 2, 0); |
edb33667 TH |
1095 | if (!port_base) |
1096 | goto out_free; | |
1097 | ||
1098 | /* allocate & init probe_ent and hpriv */ | |
142877b0 | 1099 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
edb33667 TH |
1100 | if (!probe_ent) |
1101 | goto out_free; | |
1102 | ||
142877b0 | 1103 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
edb33667 TH |
1104 | if (!hpriv) |
1105 | goto out_free; | |
1106 | ||
edb33667 TH |
1107 | probe_ent->dev = pci_dev_to_dev(pdev); |
1108 | INIT_LIST_HEAD(&probe_ent->node); | |
1109 | ||
042c21fd | 1110 | probe_ent->sht = pinfo->sht; |
cca3974e | 1111 | probe_ent->port_flags = pinfo->flags; |
042c21fd | 1112 | probe_ent->pio_mask = pinfo->pio_mask; |
fbfda6e7 | 1113 | probe_ent->mwdma_mask = pinfo->mwdma_mask; |
042c21fd TH |
1114 | probe_ent->udma_mask = pinfo->udma_mask; |
1115 | probe_ent->port_ops = pinfo->port_ops; | |
cca3974e | 1116 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags); |
edb33667 TH |
1117 | |
1118 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1119 | probe_ent->irq_flags = IRQF_SHARED; |
edb33667 TH |
1120 | probe_ent->private_data = hpriv; |
1121 | ||
edb33667 TH |
1122 | hpriv->host_base = host_base; |
1123 | hpriv->port_base = port_base; | |
1124 | ||
1125 | /* | |
1126 | * Configure the device | |
1127 | */ | |
26ec634c TH |
1128 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
1129 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1130 | if (rc) { | |
1131 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1132 | if (rc) { | |
1133 | dev_printk(KERN_ERR, &pdev->dev, | |
1134 | "64-bit DMA enable failed\n"); | |
1135 | goto out_free; | |
1136 | } | |
1137 | } | |
1138 | } else { | |
1139 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1140 | if (rc) { | |
1141 | dev_printk(KERN_ERR, &pdev->dev, | |
1142 | "32-bit DMA enable failed\n"); | |
1143 | goto out_free; | |
1144 | } | |
1145 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1146 | if (rc) { | |
1147 | dev_printk(KERN_ERR, &pdev->dev, | |
1148 | "32-bit consistent DMA enable failed\n"); | |
1149 | goto out_free; | |
1150 | } | |
edb33667 TH |
1151 | } |
1152 | ||
37024e8e | 1153 | /* Apply workaround for completion IRQ loss on PCI-X errata */ |
cca3974e | 1154 | if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) { |
37024e8e TH |
1155 | tmp = readl(host_base + HOST_CTRL); |
1156 | if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) | |
1157 | dev_printk(KERN_INFO, &pdev->dev, | |
1158 | "Applying completion IRQ loss on PCI-X " | |
1159 | "errata fix\n"); | |
1160 | else | |
cca3974e | 1161 | probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; |
37024e8e TH |
1162 | } |
1163 | ||
edb33667 | 1164 | for (i = 0; i < probe_ent->n_ports; i++) { |
2a41a610 TH |
1165 | unsigned long portu = |
1166 | (unsigned long)port_base + i * PORT_REGS_SIZE; | |
edb33667 | 1167 | |
135da345 | 1168 | probe_ent->port[i].cmd_addr = portu; |
edb33667 TH |
1169 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
1170 | ||
1171 | ata_std_ports(&probe_ent->port[i]); | |
edb33667 TH |
1172 | } |
1173 | ||
cca3974e | 1174 | sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags, |
2a41a610 | 1175 | host_base, port_base); |
edb33667 TH |
1176 | |
1177 | pci_set_master(pdev); | |
1178 | ||
1483467f | 1179 | /* FIXME: check ata_device_add return value */ |
edb33667 TH |
1180 | ata_device_add(probe_ent); |
1181 | ||
1182 | kfree(probe_ent); | |
1183 | return 0; | |
1184 | ||
1185 | out_free: | |
1186 | if (host_base) | |
142877b0 | 1187 | pci_iounmap(pdev, host_base); |
edb33667 | 1188 | if (port_base) |
142877b0 | 1189 | pci_iounmap(pdev, port_base); |
edb33667 TH |
1190 | kfree(probe_ent); |
1191 | kfree(hpriv); | |
1192 | pci_release_regions(pdev); | |
1193 | out_disable: | |
1194 | pci_disable_device(pdev); | |
1195 | return rc; | |
1196 | } | |
1197 | ||
281d426c | 1198 | #ifdef CONFIG_PM |
d2298dca TH |
1199 | static int sil24_pci_device_resume(struct pci_dev *pdev) |
1200 | { | |
cca3974e JG |
1201 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1202 | struct sil24_host_priv *hpriv = host->private_data; | |
d2298dca TH |
1203 | |
1204 | ata_pci_device_do_resume(pdev); | |
1205 | ||
1206 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) | |
1207 | writel(HOST_CTRL_GLOBAL_RST, hpriv->host_base + HOST_CTRL); | |
1208 | ||
cca3974e | 1209 | sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags, |
d2298dca TH |
1210 | hpriv->host_base, hpriv->port_base); |
1211 | ||
cca3974e | 1212 | ata_host_resume(host); |
d2298dca TH |
1213 | |
1214 | return 0; | |
1215 | } | |
281d426c | 1216 | #endif |
d2298dca | 1217 | |
edb33667 TH |
1218 | static int __init sil24_init(void) |
1219 | { | |
b7887196 | 1220 | return pci_register_driver(&sil24_pci_driver); |
edb33667 TH |
1221 | } |
1222 | ||
1223 | static void __exit sil24_exit(void) | |
1224 | { | |
1225 | pci_unregister_driver(&sil24_pci_driver); | |
1226 | } | |
1227 | ||
1228 | MODULE_AUTHOR("Tejun Heo"); | |
1229 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1230 | MODULE_LICENSE("GPL"); | |
1231 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
1232 | ||
1233 | module_init(sil24_init); | |
1234 | module_exit(sil24_exit); |