Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
1da177e4 LT |
41 | #include <scsi/scsi_host.h> |
42 | #include <linux/libata.h> | |
4bb64fb9 | 43 | #include "sis.h" |
1da177e4 LT |
44 | |
45 | #define DRV_NAME "sata_sis" | |
2a3103ce | 46 | #define DRV_VERSION "1.0" |
1da177e4 LT |
47 | |
48 | enum { | |
49 | sis_180 = 0, | |
50 | SIS_SCR_PCI_BAR = 5, | |
51 | ||
52 | /* PCI configuration registers */ | |
53 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
54 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
55 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
56 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
57 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 58 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
59 | |
60 | /* random bits */ | |
61 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
62 | ||
63 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
64 | }; | |
65 | ||
5796d1c4 | 66 | static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
82ef04fb TH |
67 | static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
68 | static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
1da177e4 | 69 | |
3b7d697d | 70 | static const struct pci_device_id sis_pci_tbl[] = { |
5796d1c4 JG |
71 | { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */ |
72 | { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */ | |
73 | { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */ | |
74 | { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */ | |
75 | { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */ | |
76 | { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */ | |
2d2744fc | 77 | |
1da177e4 LT |
78 | { } /* terminate list */ |
79 | }; | |
80 | ||
1da177e4 LT |
81 | static struct pci_driver sis_pci_driver = { |
82 | .name = DRV_NAME, | |
83 | .id_table = sis_pci_tbl, | |
84 | .probe = sis_init_one, | |
85 | .remove = ata_pci_remove_one, | |
55c82a6c A |
86 | #ifdef CONFIG_PM |
87 | .suspend = ata_pci_device_suspend, | |
88 | .resume = ata_pci_device_resume, | |
89 | #endif | |
1da177e4 LT |
90 | }; |
91 | ||
193515d5 | 92 | static struct scsi_host_template sis_sht = { |
68d1d07b | 93 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
94 | }; |
95 | ||
029cfd6b TH |
96 | static struct ata_port_operations sis_ops = { |
97 | .inherits = &ata_bmdma_port_ops, | |
1da177e4 LT |
98 | .scr_read = sis_scr_read, |
99 | .scr_write = sis_scr_write, | |
1da177e4 LT |
100 | }; |
101 | ||
1626aeb8 | 102 | static const struct ata_port_info sis_port_info = { |
9cbe056f | 103 | .flags = ATA_FLAG_SATA, |
14bdef98 EIB |
104 | .pio_mask = ATA_PIO4, |
105 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 106 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
107 | .port_ops = &sis_ops, |
108 | }; | |
109 | ||
1da177e4 | 110 | MODULE_AUTHOR("Uwe Koziolek"); |
142924cf | 111 | MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller"); |
1da177e4 LT |
112 | MODULE_LICENSE("GPL"); |
113 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
114 | MODULE_VERSION(DRV_VERSION); | |
115 | ||
72fee382 | 116 | static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg) |
1da177e4 | 117 | { |
72fee382 | 118 | struct ata_port *ap = link->ap; |
9b14dec5 | 119 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 120 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); |
9b14dec5 | 121 | u8 pmr; |
1da177e4 | 122 | |
9b14dec5 | 123 | if (ap->port_no) { |
3f3e7313 | 124 | switch (pdev->device) { |
5796d1c4 JG |
125 | case 0x0180: |
126 | case 0x0181: | |
127 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
128 | if ((pmr & SIS_PMR_COMBINED) == 0) | |
129 | addr += SIS180_SATA1_OFS; | |
130 | break; | |
131 | ||
132 | case 0x0182: | |
133 | case 0x0183: | |
134 | case 0x1182: | |
135 | addr += SIS182_SATA1_OFS; | |
136 | break; | |
3f3e7313 | 137 | } |
8add7885 | 138 | } |
72fee382 TH |
139 | if (link->pmp) |
140 | addr += 0x10; | |
141 | ||
1da177e4 LT |
142 | return addr; |
143 | } | |
144 | ||
82ef04fb TH |
145 | static u32 sis_scr_cfg_read(struct ata_link *link, |
146 | unsigned int sc_reg, u32 *val) | |
1da177e4 | 147 | { |
82ef04fb | 148 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); |
72fee382 | 149 | unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); |
1da177e4 LT |
150 | |
151 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
8e5443a0 | 152 | return -EINVAL; |
f2c853bc | 153 | |
aaa092a1 | 154 | pci_read_config_dword(pdev, cfg_addr, val); |
aaa092a1 | 155 | return 0; |
1da177e4 LT |
156 | } |
157 | ||
82ef04fb TH |
158 | static int sis_scr_cfg_write(struct ata_link *link, |
159 | unsigned int sc_reg, u32 val) | |
1da177e4 | 160 | { |
82ef04fb | 161 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); |
72fee382 | 162 | unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); |
8add7885 | 163 | |
1da177e4 | 164 | pci_write_config_dword(pdev, cfg_addr, val); |
8e5443a0 | 165 | return 0; |
1da177e4 LT |
166 | } |
167 | ||
82ef04fb | 168 | static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4 | 169 | { |
82ef04fb | 170 | struct ata_port *ap = link->ap; |
72fee382 | 171 | void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; |
f2c853bc | 172 | |
1da177e4 | 173 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 174 | return -EINVAL; |
1da177e4 LT |
175 | |
176 | if (ap->flags & SIS_FLAG_CFGSCR) | |
82ef04fb | 177 | return sis_scr_cfg_read(link, sc_reg, val); |
f2c853bc | 178 | |
72fee382 | 179 | *val = ioread32(base + sc_reg * 4); |
da3dbb17 | 180 | return 0; |
1da177e4 LT |
181 | } |
182 | ||
82ef04fb | 183 | static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
1da177e4 | 184 | { |
82ef04fb | 185 | struct ata_port *ap = link->ap; |
72fee382 | 186 | void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; |
f2c853bc | 187 | |
1da177e4 | 188 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 189 | return -EINVAL; |
1da177e4 LT |
190 | |
191 | if (ap->flags & SIS_FLAG_CFGSCR) | |
82ef04fb | 192 | return sis_scr_cfg_write(link, sc_reg, val); |
72fee382 TH |
193 | |
194 | iowrite32(val, base + (sc_reg * 4)); | |
195 | return 0; | |
1da177e4 LT |
196 | } |
197 | ||
5796d1c4 | 198 | static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 199 | { |
9a829ccf | 200 | struct ata_port_info pi = sis_port_info; |
ddfc87a0 | 201 | const struct ata_port_info *ppi[] = { &pi, &pi }; |
9a829ccf | 202 | struct ata_host *host; |
4adccf6f | 203 | u32 genctl, val; |
f2c853bc | 204 | u8 pmr; |
3f3e7313 | 205 | u8 port2_start = 0x20; |
72fee382 | 206 | int i, rc; |
1da177e4 | 207 | |
06296a1e | 208 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
a9524a76 | 209 | |
24dc5f33 | 210 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
211 | if (rc) |
212 | return rc; | |
213 | ||
1da177e4 LT |
214 | /* check and see if the SCRs are in IO space or PCI cfg space */ |
215 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
216 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
cf0e812f | 217 | pi.flags |= SIS_FLAG_CFGSCR; |
8a60a071 | 218 | |
1da177e4 LT |
219 | /* if hardware thinks SCRs are in IO space, but there are |
220 | * no IO resources assigned, change to PCI cfg space. | |
221 | */ | |
cf0e812f | 222 | if ((!(pi.flags & SIS_FLAG_CFGSCR)) && |
1da177e4 LT |
223 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || |
224 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
225 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
226 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
cf0e812f | 227 | pi.flags |= SIS_FLAG_CFGSCR; |
1da177e4 LT |
228 | } |
229 | ||
f2c853bc | 230 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
3f3e7313 UK |
231 | switch (ent->device) { |
232 | case 0x0180: | |
233 | case 0x0181: | |
9b14dec5 A |
234 | |
235 | /* The PATA-handling is provided by pata_sis */ | |
236 | switch (pmr & 0x30) { | |
237 | case 0x10: | |
a3cabb27 | 238 | ppi[1] = &sis_info133_for_sata; |
9b14dec5 | 239 | break; |
a84471fe | 240 | |
9b14dec5 | 241 | case 0x30: |
a3cabb27 | 242 | ppi[0] = &sis_info133_for_sata; |
9b14dec5 A |
243 | break; |
244 | } | |
f2c853bc | 245 | if ((pmr & SIS_PMR_COMBINED) == 0) { |
a44fec1f JP |
246 | dev_info(&pdev->dev, |
247 | "Detected SiS 180/181/964 chipset in SATA mode\n"); | |
39eb936c | 248 | port2_start = 64; |
3f3e7313 | 249 | } else { |
a44fec1f JP |
250 | dev_info(&pdev->dev, |
251 | "Detected SiS 180/181 chipset in combined mode\n"); | |
5796d1c4 | 252 | port2_start = 0; |
4adccf6f | 253 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
f2c853bc | 254 | } |
3f3e7313 | 255 | break; |
f20b16ff | 256 | |
3f3e7313 UK |
257 | case 0x0182: |
258 | case 0x0183: | |
5796d1c4 | 259 | pci_read_config_dword(pdev, 0x6C, &val); |
4adccf6f | 260 | if (val & (1L << 31)) { |
a44fec1f | 261 | dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n"); |
4adccf6f | 262 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
3f3e7313 | 263 | } else { |
a44fec1f | 264 | dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n"); |
3f3e7313 UK |
265 | } |
266 | break; | |
267 | ||
268 | case 0x1182: | |
a44fec1f JP |
269 | dev_info(&pdev->dev, |
270 | "Detected SiS 1182/966/680 SATA controller\n"); | |
a3cabb27 UK |
271 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
272 | break; | |
273 | ||
3f3e7313 | 274 | case 0x1183: |
a44fec1f JP |
275 | dev_info(&pdev->dev, |
276 | "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n"); | |
a3cabb27 UK |
277 | ppi[0] = &sis_info133_for_sata; |
278 | ppi[1] = &sis_info133_for_sata; | |
3f3e7313 | 279 | break; |
f2c853bc AP |
280 | } |
281 | ||
1c5afdf7 | 282 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
9a829ccf TH |
283 | if (rc) |
284 | return rc; | |
cf0e812f | 285 | |
72fee382 TH |
286 | for (i = 0; i < 2; i++) { |
287 | struct ata_port *ap = host->ports[i]; | |
288 | ||
289 | if (ap->flags & ATA_FLAG_SATA && | |
290 | ap->flags & ATA_FLAG_SLAVE_POSS) { | |
291 | rc = ata_slave_link_init(ap); | |
292 | if (rc) | |
293 | return rc; | |
294 | } | |
295 | } | |
296 | ||
9a829ccf | 297 | if (!(pi.flags & SIS_FLAG_CFGSCR)) { |
edceec3d | 298 | void __iomem *mmio; |
0d5ff566 | 299 | |
9a829ccf TH |
300 | rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME); |
301 | if (rc) | |
302 | return rc; | |
303 | mmio = host->iomap[SIS_SCR_PCI_BAR]; | |
0d5ff566 | 304 | |
9a829ccf TH |
305 | host->ports[0]->ioaddr.scr_addr = mmio; |
306 | host->ports[1]->ioaddr.scr_addr = mmio + port2_start; | |
1da177e4 LT |
307 | } |
308 | ||
309 | pci_set_master(pdev); | |
a04ce0ff | 310 | pci_intx(pdev, 1); |
c3b28894 | 311 | return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
9363c382 | 312 | IRQF_SHARED, &sis_sht); |
1da177e4 LT |
313 | } |
314 | ||
2fc75da0 | 315 | module_pci_driver(sis_pci_driver); |