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1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
1da177e4 LT |
36 | #include <linux/blkdev.h> |
37 | #include <linux/delay.h> | |
38 | #include <linux/interrupt.h> | |
a9524a76 | 39 | #include <linux/device.h> |
1da177e4 LT |
40 | #include <scsi/scsi_host.h> |
41 | #include <linux/libata.h> | |
4bb64fb9 | 42 | #include "sis.h" |
1da177e4 LT |
43 | |
44 | #define DRV_NAME "sata_sis" | |
2a3103ce | 45 | #define DRV_VERSION "1.0" |
1da177e4 LT |
46 | |
47 | enum { | |
48 | sis_180 = 0, | |
49 | SIS_SCR_PCI_BAR = 5, | |
50 | ||
51 | /* PCI configuration registers */ | |
52 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
53 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
54 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
55 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
56 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 57 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
58 | |
59 | /* random bits */ | |
60 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
61 | ||
62 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
63 | }; | |
64 | ||
5796d1c4 | 65 | static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
82ef04fb TH |
66 | static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
67 | static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
1da177e4 | 68 | |
3b7d697d | 69 | static const struct pci_device_id sis_pci_tbl[] = { |
5796d1c4 JG |
70 | { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */ |
71 | { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */ | |
72 | { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */ | |
73 | { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */ | |
74 | { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */ | |
75 | { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */ | |
2d2744fc | 76 | |
1da177e4 LT |
77 | { } /* terminate list */ |
78 | }; | |
79 | ||
1da177e4 LT |
80 | static struct pci_driver sis_pci_driver = { |
81 | .name = DRV_NAME, | |
82 | .id_table = sis_pci_tbl, | |
83 | .probe = sis_init_one, | |
84 | .remove = ata_pci_remove_one, | |
58eb8cd5 | 85 | #ifdef CONFIG_PM_SLEEP |
55c82a6c A |
86 | .suspend = ata_pci_device_suspend, |
87 | .resume = ata_pci_device_resume, | |
88 | #endif | |
1da177e4 LT |
89 | }; |
90 | ||
193515d5 | 91 | static struct scsi_host_template sis_sht = { |
68d1d07b | 92 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
93 | }; |
94 | ||
029cfd6b TH |
95 | static struct ata_port_operations sis_ops = { |
96 | .inherits = &ata_bmdma_port_ops, | |
1da177e4 LT |
97 | .scr_read = sis_scr_read, |
98 | .scr_write = sis_scr_write, | |
1da177e4 LT |
99 | }; |
100 | ||
1626aeb8 | 101 | static const struct ata_port_info sis_port_info = { |
9cbe056f | 102 | .flags = ATA_FLAG_SATA, |
14bdef98 EIB |
103 | .pio_mask = ATA_PIO4, |
104 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 105 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
106 | .port_ops = &sis_ops, |
107 | }; | |
108 | ||
1da177e4 | 109 | MODULE_AUTHOR("Uwe Koziolek"); |
142924cf | 110 | MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller"); |
1da177e4 LT |
111 | MODULE_LICENSE("GPL"); |
112 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
113 | MODULE_VERSION(DRV_VERSION); | |
114 | ||
72fee382 | 115 | static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg) |
1da177e4 | 116 | { |
72fee382 | 117 | struct ata_port *ap = link->ap; |
9b14dec5 | 118 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 119 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); |
9b14dec5 | 120 | u8 pmr; |
1da177e4 | 121 | |
9b14dec5 | 122 | if (ap->port_no) { |
3f3e7313 | 123 | switch (pdev->device) { |
5796d1c4 JG |
124 | case 0x0180: |
125 | case 0x0181: | |
126 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
127 | if ((pmr & SIS_PMR_COMBINED) == 0) | |
128 | addr += SIS180_SATA1_OFS; | |
129 | break; | |
130 | ||
131 | case 0x0182: | |
132 | case 0x0183: | |
133 | case 0x1182: | |
134 | addr += SIS182_SATA1_OFS; | |
135 | break; | |
3f3e7313 | 136 | } |
8add7885 | 137 | } |
72fee382 TH |
138 | if (link->pmp) |
139 | addr += 0x10; | |
140 | ||
1da177e4 LT |
141 | return addr; |
142 | } | |
143 | ||
82ef04fb TH |
144 | static u32 sis_scr_cfg_read(struct ata_link *link, |
145 | unsigned int sc_reg, u32 *val) | |
1da177e4 | 146 | { |
82ef04fb | 147 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); |
72fee382 | 148 | unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); |
1da177e4 LT |
149 | |
150 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
8e5443a0 | 151 | return -EINVAL; |
f2c853bc | 152 | |
aaa092a1 | 153 | pci_read_config_dword(pdev, cfg_addr, val); |
aaa092a1 | 154 | return 0; |
1da177e4 LT |
155 | } |
156 | ||
82ef04fb TH |
157 | static int sis_scr_cfg_write(struct ata_link *link, |
158 | unsigned int sc_reg, u32 val) | |
1da177e4 | 159 | { |
82ef04fb | 160 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); |
72fee382 | 161 | unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); |
8add7885 | 162 | |
1da177e4 | 163 | pci_write_config_dword(pdev, cfg_addr, val); |
8e5443a0 | 164 | return 0; |
1da177e4 LT |
165 | } |
166 | ||
82ef04fb | 167 | static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4 | 168 | { |
82ef04fb | 169 | struct ata_port *ap = link->ap; |
72fee382 | 170 | void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; |
f2c853bc | 171 | |
1da177e4 | 172 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 173 | return -EINVAL; |
1da177e4 LT |
174 | |
175 | if (ap->flags & SIS_FLAG_CFGSCR) | |
82ef04fb | 176 | return sis_scr_cfg_read(link, sc_reg, val); |
f2c853bc | 177 | |
72fee382 | 178 | *val = ioread32(base + sc_reg * 4); |
da3dbb17 | 179 | return 0; |
1da177e4 LT |
180 | } |
181 | ||
82ef04fb | 182 | static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
1da177e4 | 183 | { |
82ef04fb | 184 | struct ata_port *ap = link->ap; |
72fee382 | 185 | void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; |
f2c853bc | 186 | |
1da177e4 | 187 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 188 | return -EINVAL; |
1da177e4 LT |
189 | |
190 | if (ap->flags & SIS_FLAG_CFGSCR) | |
82ef04fb | 191 | return sis_scr_cfg_write(link, sc_reg, val); |
72fee382 TH |
192 | |
193 | iowrite32(val, base + (sc_reg * 4)); | |
194 | return 0; | |
1da177e4 LT |
195 | } |
196 | ||
5796d1c4 | 197 | static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 198 | { |
9a829ccf | 199 | struct ata_port_info pi = sis_port_info; |
ddfc87a0 | 200 | const struct ata_port_info *ppi[] = { &pi, &pi }; |
9a829ccf | 201 | struct ata_host *host; |
4adccf6f | 202 | u32 genctl, val; |
f2c853bc | 203 | u8 pmr; |
3f3e7313 | 204 | u8 port2_start = 0x20; |
72fee382 | 205 | int i, rc; |
1da177e4 | 206 | |
06296a1e | 207 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
a9524a76 | 208 | |
24dc5f33 | 209 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
210 | if (rc) |
211 | return rc; | |
212 | ||
1da177e4 LT |
213 | /* check and see if the SCRs are in IO space or PCI cfg space */ |
214 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
215 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
cf0e812f | 216 | pi.flags |= SIS_FLAG_CFGSCR; |
8a60a071 | 217 | |
1da177e4 LT |
218 | /* if hardware thinks SCRs are in IO space, but there are |
219 | * no IO resources assigned, change to PCI cfg space. | |
220 | */ | |
cf0e812f | 221 | if ((!(pi.flags & SIS_FLAG_CFGSCR)) && |
1da177e4 LT |
222 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || |
223 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
224 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
225 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
cf0e812f | 226 | pi.flags |= SIS_FLAG_CFGSCR; |
1da177e4 LT |
227 | } |
228 | ||
f2c853bc | 229 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
3f3e7313 UK |
230 | switch (ent->device) { |
231 | case 0x0180: | |
232 | case 0x0181: | |
9b14dec5 A |
233 | |
234 | /* The PATA-handling is provided by pata_sis */ | |
235 | switch (pmr & 0x30) { | |
236 | case 0x10: | |
a3cabb27 | 237 | ppi[1] = &sis_info133_for_sata; |
9b14dec5 | 238 | break; |
a84471fe | 239 | |
9b14dec5 | 240 | case 0x30: |
a3cabb27 | 241 | ppi[0] = &sis_info133_for_sata; |
9b14dec5 A |
242 | break; |
243 | } | |
f2c853bc | 244 | if ((pmr & SIS_PMR_COMBINED) == 0) { |
a44fec1f JP |
245 | dev_info(&pdev->dev, |
246 | "Detected SiS 180/181/964 chipset in SATA mode\n"); | |
39eb936c | 247 | port2_start = 64; |
3f3e7313 | 248 | } else { |
a44fec1f JP |
249 | dev_info(&pdev->dev, |
250 | "Detected SiS 180/181 chipset in combined mode\n"); | |
5796d1c4 | 251 | port2_start = 0; |
4adccf6f | 252 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
f2c853bc | 253 | } |
3f3e7313 | 254 | break; |
f20b16ff | 255 | |
3f3e7313 UK |
256 | case 0x0182: |
257 | case 0x0183: | |
5796d1c4 | 258 | pci_read_config_dword(pdev, 0x6C, &val); |
4adccf6f | 259 | if (val & (1L << 31)) { |
a44fec1f | 260 | dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n"); |
4adccf6f | 261 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
3f3e7313 | 262 | } else { |
a44fec1f | 263 | dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n"); |
3f3e7313 UK |
264 | } |
265 | break; | |
266 | ||
267 | case 0x1182: | |
a44fec1f JP |
268 | dev_info(&pdev->dev, |
269 | "Detected SiS 1182/966/680 SATA controller\n"); | |
a3cabb27 UK |
270 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
271 | break; | |
272 | ||
3f3e7313 | 273 | case 0x1183: |
a44fec1f JP |
274 | dev_info(&pdev->dev, |
275 | "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n"); | |
a3cabb27 UK |
276 | ppi[0] = &sis_info133_for_sata; |
277 | ppi[1] = &sis_info133_for_sata; | |
3f3e7313 | 278 | break; |
f2c853bc AP |
279 | } |
280 | ||
1c5afdf7 | 281 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
9a829ccf TH |
282 | if (rc) |
283 | return rc; | |
cf0e812f | 284 | |
72fee382 TH |
285 | for (i = 0; i < 2; i++) { |
286 | struct ata_port *ap = host->ports[i]; | |
287 | ||
288 | if (ap->flags & ATA_FLAG_SATA && | |
289 | ap->flags & ATA_FLAG_SLAVE_POSS) { | |
290 | rc = ata_slave_link_init(ap); | |
291 | if (rc) | |
292 | return rc; | |
293 | } | |
294 | } | |
295 | ||
9a829ccf | 296 | if (!(pi.flags & SIS_FLAG_CFGSCR)) { |
edceec3d | 297 | void __iomem *mmio; |
0d5ff566 | 298 | |
9a829ccf TH |
299 | rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME); |
300 | if (rc) | |
301 | return rc; | |
302 | mmio = host->iomap[SIS_SCR_PCI_BAR]; | |
0d5ff566 | 303 | |
9a829ccf TH |
304 | host->ports[0]->ioaddr.scr_addr = mmio; |
305 | host->ports[1]->ioaddr.scr_addr = mmio + port2_start; | |
1da177e4 LT |
306 | } |
307 | ||
308 | pci_set_master(pdev); | |
a04ce0ff | 309 | pci_intx(pdev, 1); |
c3b28894 | 310 | return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
9363c382 | 311 | IRQF_SHARED, &sis_sht); |
1da177e4 LT |
312 | } |
313 | ||
2fc75da0 | 314 | module_pci_driver(sis_pci_driver); |