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1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
1da177e4 LT |
41 | #include <scsi/scsi_host.h> |
42 | #include <linux/libata.h> | |
43 | ||
44 | #define DRV_NAME "sata_sis" | |
3f3e7313 | 45 | #define DRV_VERSION "0.7" |
1da177e4 LT |
46 | |
47 | enum { | |
48 | sis_180 = 0, | |
49 | SIS_SCR_PCI_BAR = 5, | |
50 | ||
51 | /* PCI configuration registers */ | |
52 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
53 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
54 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
55 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
56 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 57 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
58 | |
59 | /* random bits */ | |
60 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
61 | ||
62 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
63 | }; | |
64 | ||
65 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
66 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
67 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
68 | ||
3b7d697d | 69 | static const struct pci_device_id sis_pci_tbl[] = { |
3f3e7313 UK |
70 | { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */ |
71 | { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */ | |
72 | { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */ | |
73 | { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */ | |
74 | { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */ | |
75 | { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */ | |
2d2744fc | 76 | |
1da177e4 LT |
77 | { } /* terminate list */ |
78 | }; | |
79 | ||
1da177e4 LT |
80 | static struct pci_driver sis_pci_driver = { |
81 | .name = DRV_NAME, | |
82 | .id_table = sis_pci_tbl, | |
83 | .probe = sis_init_one, | |
84 | .remove = ata_pci_remove_one, | |
85 | }; | |
86 | ||
193515d5 | 87 | static struct scsi_host_template sis_sht = { |
1da177e4 LT |
88 | .module = THIS_MODULE, |
89 | .name = DRV_NAME, | |
90 | .ioctl = ata_scsi_ioctl, | |
91 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
92 | .can_queue = ATA_DEF_QUEUE, |
93 | .this_id = ATA_SHT_THIS_ID, | |
94 | .sg_tablesize = ATA_MAX_PRD, | |
1da177e4 LT |
95 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
96 | .emulated = ATA_SHT_EMULATED, | |
97 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
98 | .proc_name = DRV_NAME, | |
99 | .dma_boundary = ATA_DMA_BOUNDARY, | |
100 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 101 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 102 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
103 | }; |
104 | ||
057ace5e | 105 | static const struct ata_port_operations sis_ops = { |
1da177e4 LT |
106 | .port_disable = ata_port_disable, |
107 | .tf_load = ata_tf_load, | |
108 | .tf_read = ata_tf_read, | |
109 | .check_status = ata_check_status, | |
110 | .exec_command = ata_exec_command, | |
111 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
112 | .bmdma_setup = ata_bmdma_setup, |
113 | .bmdma_start = ata_bmdma_start, | |
114 | .bmdma_stop = ata_bmdma_stop, | |
115 | .bmdma_status = ata_bmdma_status, | |
116 | .qc_prep = ata_qc_prep, | |
117 | .qc_issue = ata_qc_issue_prot, | |
a6b2c5d4 | 118 | .data_xfer = ata_pio_data_xfer, |
d7a80dad TH |
119 | .freeze = ata_bmdma_freeze, |
120 | .thaw = ata_bmdma_thaw, | |
121 | .error_handler = ata_bmdma_error_handler, | |
122 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 LT |
123 | .irq_handler = ata_interrupt, |
124 | .irq_clear = ata_bmdma_irq_clear, | |
125 | .scr_read = sis_scr_read, | |
126 | .scr_write = sis_scr_write, | |
127 | .port_start = ata_port_start, | |
128 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 129 | .host_stop = ata_host_stop, |
1da177e4 LT |
130 | }; |
131 | ||
132 | static struct ata_port_info sis_port_info = { | |
133 | .sht = &sis_sht, | |
cca3974e | 134 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
1da177e4 LT |
135 | .pio_mask = 0x1f, |
136 | .mwdma_mask = 0x7, | |
137 | .udma_mask = 0x7f, | |
138 | .port_ops = &sis_ops, | |
139 | }; | |
140 | ||
141 | ||
142 | MODULE_AUTHOR("Uwe Koziolek"); | |
143 | MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller"); | |
144 | MODULE_LICENSE("GPL"); | |
145 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
146 | MODULE_VERSION(DRV_VERSION); | |
147 | ||
3f3e7313 | 148 | static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, struct pci_dev *pdev) |
1da177e4 LT |
149 | { |
150 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); | |
151 | ||
8add7885 | 152 | if (port_no) { |
3f3e7313 UK |
153 | switch (pdev->device) { |
154 | case 0x0180: | |
155 | case 0x0181: | |
156 | addr += SIS180_SATA1_OFS; | |
157 | break; | |
158 | ||
159 | case 0x0182: | |
160 | case 0x0183: | |
161 | case 0x1182: | |
162 | case 0x1183: | |
163 | addr += SIS182_SATA1_OFS; | |
164 | break; | |
165 | } | |
8add7885 | 166 | } |
1da177e4 LT |
167 | return addr; |
168 | } | |
169 | ||
170 | static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) | |
171 | { | |
cca3974e | 172 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
3f3e7313 | 173 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev); |
668e4bc7 | 174 | u32 val, val2 = 0; |
f2c853bc | 175 | u8 pmr; |
1da177e4 LT |
176 | |
177 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
178 | return 0xffffffff; | |
f2c853bc AP |
179 | |
180 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 181 | |
1da177e4 | 182 | pci_read_config_dword(pdev, cfg_addr, &val); |
f2c853bc | 183 | |
3f3e7313 UK |
184 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
185 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc AP |
186 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); |
187 | ||
4adccf6f | 188 | return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */ |
1da177e4 LT |
189 | } |
190 | ||
191 | static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val) | |
192 | { | |
cca3974e | 193 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
3f3e7313 | 194 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev); |
f2c853bc | 195 | u8 pmr; |
1da177e4 LT |
196 | |
197 | if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
198 | return; | |
f2c853bc AP |
199 | |
200 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 201 | |
1da177e4 | 202 | pci_write_config_dword(pdev, cfg_addr, val); |
f2c853bc | 203 | |
3f3e7313 UK |
204 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
205 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc | 206 | pci_write_config_dword(pdev, cfg_addr+0x10, val); |
1da177e4 LT |
207 | } |
208 | ||
209 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
210 | { | |
cca3974e | 211 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
8add7885 | 212 | u32 val, val2 = 0; |
f2c853bc AP |
213 | u8 pmr; |
214 | ||
1da177e4 LT |
215 | if (sc_reg > SCR_CONTROL) |
216 | return 0xffffffffU; | |
217 | ||
218 | if (ap->flags & SIS_FLAG_CFGSCR) | |
219 | return sis_scr_cfg_read(ap, sc_reg); | |
f2c853bc AP |
220 | |
221 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
222 | ||
223 | val = inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
224 | ||
3f3e7313 UK |
225 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
226 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
8add7885 | 227 | val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
f2c853bc | 228 | |
4adccf6f | 229 | return (val | val2) & 0xfffffffb; |
1da177e4 LT |
230 | } |
231 | ||
232 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
233 | { | |
cca3974e | 234 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
f2c853bc AP |
235 | u8 pmr; |
236 | ||
1da177e4 LT |
237 | if (sc_reg > SCR_CONTROL) |
238 | return; | |
239 | ||
f2c853bc | 240 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
8add7885 | 241 | |
1da177e4 LT |
242 | if (ap->flags & SIS_FLAG_CFGSCR) |
243 | sis_scr_cfg_write(ap, sc_reg, val); | |
f2c853bc | 244 | else { |
1da177e4 | 245 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
3f3e7313 UK |
246 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
247 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc AP |
248 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); |
249 | } | |
1da177e4 LT |
250 | } |
251 | ||
1da177e4 LT |
252 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
253 | { | |
a9524a76 | 254 | static int printed_version; |
1da177e4 LT |
255 | struct ata_probe_ent *probe_ent = NULL; |
256 | int rc; | |
4adccf6f | 257 | u32 genctl, val; |
cf0e812f | 258 | struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi }; |
1da177e4 | 259 | int pci_dev_busy = 0; |
f2c853bc | 260 | u8 pmr; |
3f3e7313 | 261 | u8 port2_start = 0x20; |
1da177e4 | 262 | |
a9524a76 JG |
263 | if (!printed_version++) |
264 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
265 | ||
1da177e4 LT |
266 | rc = pci_enable_device(pdev); |
267 | if (rc) | |
268 | return rc; | |
269 | ||
270 | rc = pci_request_regions(pdev, DRV_NAME); | |
271 | if (rc) { | |
272 | pci_dev_busy = 1; | |
273 | goto err_out; | |
274 | } | |
275 | ||
276 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
277 | if (rc) | |
278 | goto err_out_regions; | |
279 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
280 | if (rc) | |
281 | goto err_out_regions; | |
282 | ||
1da177e4 LT |
283 | /* check and see if the SCRs are in IO space or PCI cfg space */ |
284 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
285 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
cf0e812f | 286 | pi.flags |= SIS_FLAG_CFGSCR; |
8a60a071 | 287 | |
1da177e4 LT |
288 | /* if hardware thinks SCRs are in IO space, but there are |
289 | * no IO resources assigned, change to PCI cfg space. | |
290 | */ | |
cf0e812f | 291 | if ((!(pi.flags & SIS_FLAG_CFGSCR)) && |
1da177e4 LT |
292 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || |
293 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
294 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
295 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
cf0e812f | 296 | pi.flags |= SIS_FLAG_CFGSCR; |
1da177e4 LT |
297 | } |
298 | ||
f2c853bc | 299 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
3f3e7313 UK |
300 | switch (ent->device) { |
301 | case 0x0180: | |
302 | case 0x0181: | |
f2c853bc | 303 | if ((pmr & SIS_PMR_COMBINED) == 0) { |
a9524a76 | 304 | dev_printk(KERN_INFO, &pdev->dev, |
4adccf6f | 305 | "Detected SiS 180/181/964 chipset in SATA mode\n"); |
39eb936c | 306 | port2_start = 64; |
3f3e7313 | 307 | } else { |
a9524a76 JG |
308 | dev_printk(KERN_INFO, &pdev->dev, |
309 | "Detected SiS 180/181 chipset in combined mode\n"); | |
f2c853bc | 310 | port2_start=0; |
4adccf6f | 311 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
f2c853bc | 312 | } |
3f3e7313 UK |
313 | break; |
314 | ||
315 | case 0x0182: | |
316 | case 0x0183: | |
4adccf6f UK |
317 | pci_read_config_dword ( pdev, 0x6C, &val); |
318 | if (val & (1L << 31)) { | |
319 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n"); | |
320 | pi.flags |= ATA_FLAG_SLAVE_POSS; | |
3f3e7313 | 321 | } else { |
4adccf6f | 322 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n"); |
3f3e7313 UK |
323 | } |
324 | break; | |
325 | ||
326 | case 0x1182: | |
327 | case 0x1183: | |
328 | pci_read_config_dword(pdev, 0x64, &val); | |
329 | if (val & 0x10000000) { | |
330 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n"); | |
331 | } else { | |
332 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n"); | |
333 | pi.flags |= ATA_FLAG_SLAVE_POSS; | |
334 | } | |
335 | break; | |
f2c853bc AP |
336 | } |
337 | ||
cf0e812f TH |
338 | probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
339 | if (!probe_ent) { | |
340 | rc = -ENOMEM; | |
341 | goto err_out_regions; | |
342 | } | |
343 | ||
cca3974e | 344 | if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) { |
1da177e4 LT |
345 | probe_ent->port[0].scr_addr = |
346 | pci_resource_start(pdev, SIS_SCR_PCI_BAR); | |
347 | probe_ent->port[1].scr_addr = | |
f2c853bc | 348 | pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start; |
1da177e4 LT |
349 | } |
350 | ||
351 | pci_set_master(pdev); | |
a04ce0ff | 352 | pci_intx(pdev, 1); |
1da177e4 LT |
353 | |
354 | /* FIXME: check ata_device_add return value */ | |
355 | ata_device_add(probe_ent); | |
356 | kfree(probe_ent); | |
357 | ||
358 | return 0; | |
359 | ||
360 | err_out_regions: | |
361 | pci_release_regions(pdev); | |
362 | ||
363 | err_out: | |
364 | if (!pci_dev_busy) | |
365 | pci_disable_device(pdev); | |
366 | return rc; | |
367 | ||
368 | } | |
369 | ||
370 | static int __init sis_init(void) | |
371 | { | |
b7887196 | 372 | return pci_register_driver(&sis_pci_driver); |
1da177e4 LT |
373 | } |
374 | ||
375 | static void __exit sis_exit(void) | |
376 | { | |
377 | pci_unregister_driver(&sis_pci_driver); | |
378 | } | |
379 | ||
380 | module_init(sis_init); | |
381 | module_exit(sis_exit); | |
382 |