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1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
1da177e4 LT |
41 | #include <scsi/scsi_host.h> |
42 | #include <linux/libata.h> | |
4bb64fb9 | 43 | #include "sis.h" |
1da177e4 LT |
44 | |
45 | #define DRV_NAME "sata_sis" | |
2a3103ce | 46 | #define DRV_VERSION "1.0" |
1da177e4 LT |
47 | |
48 | enum { | |
49 | sis_180 = 0, | |
50 | SIS_SCR_PCI_BAR = 5, | |
51 | ||
52 | /* PCI configuration registers */ | |
53 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
54 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
55 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
56 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
57 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 58 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
59 | |
60 | /* random bits */ | |
61 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
62 | ||
63 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
64 | }; | |
65 | ||
5796d1c4 JG |
66 | static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
67 | static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); | |
68 | static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 69 | |
3b7d697d | 70 | static const struct pci_device_id sis_pci_tbl[] = { |
5796d1c4 JG |
71 | { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */ |
72 | { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */ | |
73 | { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */ | |
74 | { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */ | |
75 | { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */ | |
76 | { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */ | |
2d2744fc | 77 | |
1da177e4 LT |
78 | { } /* terminate list */ |
79 | }; | |
80 | ||
1da177e4 LT |
81 | static struct pci_driver sis_pci_driver = { |
82 | .name = DRV_NAME, | |
83 | .id_table = sis_pci_tbl, | |
84 | .probe = sis_init_one, | |
85 | .remove = ata_pci_remove_one, | |
86 | }; | |
87 | ||
193515d5 | 88 | static struct scsi_host_template sis_sht = { |
68d1d07b | 89 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
90 | }; |
91 | ||
029cfd6b TH |
92 | static struct ata_port_operations sis_ops = { |
93 | .inherits = &ata_bmdma_port_ops, | |
1da177e4 LT |
94 | .scr_read = sis_scr_read, |
95 | .scr_write = sis_scr_write, | |
1da177e4 LT |
96 | }; |
97 | ||
1626aeb8 | 98 | static const struct ata_port_info sis_port_info = { |
cca3974e | 99 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
1da177e4 LT |
100 | .pio_mask = 0x1f, |
101 | .mwdma_mask = 0x7, | |
bf6263a8 | 102 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
103 | .port_ops = &sis_ops, |
104 | }; | |
105 | ||
1da177e4 LT |
106 | MODULE_AUTHOR("Uwe Koziolek"); |
107 | MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller"); | |
108 | MODULE_LICENSE("GPL"); | |
109 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
110 | MODULE_VERSION(DRV_VERSION); | |
111 | ||
9b14dec5 | 112 | static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 113 | { |
9b14dec5 | 114 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 115 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); |
9b14dec5 | 116 | u8 pmr; |
1da177e4 | 117 | |
9b14dec5 | 118 | if (ap->port_no) { |
3f3e7313 | 119 | switch (pdev->device) { |
5796d1c4 JG |
120 | case 0x0180: |
121 | case 0x0181: | |
122 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
123 | if ((pmr & SIS_PMR_COMBINED) == 0) | |
124 | addr += SIS180_SATA1_OFS; | |
125 | break; | |
126 | ||
127 | case 0x0182: | |
128 | case 0x0183: | |
129 | case 0x1182: | |
130 | addr += SIS182_SATA1_OFS; | |
131 | break; | |
3f3e7313 | 132 | } |
8add7885 | 133 | } |
1da177e4 LT |
134 | return addr; |
135 | } | |
136 | ||
5796d1c4 | 137 | static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 138 | { |
cca3974e | 139 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
9b14dec5 | 140 | unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg); |
aaa092a1 | 141 | u32 val2 = 0; |
f2c853bc | 142 | u8 pmr; |
1da177e4 LT |
143 | |
144 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
145 | return 0xffffffff; | |
f2c853bc AP |
146 | |
147 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 148 | |
aaa092a1 | 149 | pci_read_config_dword(pdev, cfg_addr, val); |
f2c853bc | 150 | |
a3cabb27 UK |
151 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || |
152 | (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc AP |
153 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); |
154 | ||
aaa092a1 TH |
155 | *val |= val2; |
156 | *val &= 0xfffffffb; /* avoid problems with powerdowned ports */ | |
157 | ||
158 | return 0; | |
1da177e4 LT |
159 | } |
160 | ||
5796d1c4 | 161 | static void sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 162 | { |
cca3974e | 163 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
9b14dec5 | 164 | unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg); |
f2c853bc | 165 | u8 pmr; |
1da177e4 | 166 | |
9b14dec5 | 167 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ |
1da177e4 | 168 | return; |
f2c853bc AP |
169 | |
170 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 171 | |
1da177e4 | 172 | pci_write_config_dword(pdev, cfg_addr, val); |
f2c853bc | 173 | |
a3cabb27 UK |
174 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || |
175 | (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc | 176 | pci_write_config_dword(pdev, cfg_addr+0x10, val); |
1da177e4 LT |
177 | } |
178 | ||
da3dbb17 | 179 | static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 180 | { |
cca3974e | 181 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
f2c853bc AP |
182 | u8 pmr; |
183 | ||
1da177e4 | 184 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 185 | return -EINVAL; |
1da177e4 LT |
186 | |
187 | if (ap->flags & SIS_FLAG_CFGSCR) | |
aaa092a1 | 188 | return sis_scr_cfg_read(ap, sc_reg, val); |
f2c853bc AP |
189 | |
190 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
191 | ||
da3dbb17 | 192 | *val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4)); |
f2c853bc | 193 | |
a3cabb27 UK |
194 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || |
195 | (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED)) | |
da3dbb17 TH |
196 | *val |= ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
197 | ||
198 | *val &= 0xfffffffb; | |
f2c853bc | 199 | |
da3dbb17 | 200 | return 0; |
1da177e4 LT |
201 | } |
202 | ||
da3dbb17 | 203 | static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 204 | { |
cca3974e | 205 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
f2c853bc AP |
206 | u8 pmr; |
207 | ||
1da177e4 | 208 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 209 | return -EINVAL; |
1da177e4 | 210 | |
f2c853bc | 211 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
8add7885 | 212 | |
1da177e4 LT |
213 | if (ap->flags & SIS_FLAG_CFGSCR) |
214 | sis_scr_cfg_write(ap, sc_reg, val); | |
f2c853bc | 215 | else { |
0d5ff566 | 216 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
a3cabb27 UK |
217 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || |
218 | (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED)) | |
0d5ff566 | 219 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); |
f2c853bc | 220 | } |
da3dbb17 | 221 | return 0; |
1da177e4 LT |
222 | } |
223 | ||
5796d1c4 | 224 | static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 225 | { |
a9524a76 | 226 | static int printed_version; |
9a829ccf | 227 | struct ata_port_info pi = sis_port_info; |
ddfc87a0 | 228 | const struct ata_port_info *ppi[] = { &pi, &pi }; |
9a829ccf | 229 | struct ata_host *host; |
4adccf6f | 230 | u32 genctl, val; |
f2c853bc | 231 | u8 pmr; |
3f3e7313 | 232 | u8 port2_start = 0x20; |
9a829ccf | 233 | int rc; |
1da177e4 | 234 | |
a9524a76 JG |
235 | if (!printed_version++) |
236 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
237 | ||
24dc5f33 | 238 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
239 | if (rc) |
240 | return rc; | |
241 | ||
1da177e4 LT |
242 | /* check and see if the SCRs are in IO space or PCI cfg space */ |
243 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
244 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
cf0e812f | 245 | pi.flags |= SIS_FLAG_CFGSCR; |
8a60a071 | 246 | |
1da177e4 LT |
247 | /* if hardware thinks SCRs are in IO space, but there are |
248 | * no IO resources assigned, change to PCI cfg space. | |
249 | */ | |
cf0e812f | 250 | if ((!(pi.flags & SIS_FLAG_CFGSCR)) && |
1da177e4 LT |
251 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || |
252 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
253 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
254 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
cf0e812f | 255 | pi.flags |= SIS_FLAG_CFGSCR; |
1da177e4 LT |
256 | } |
257 | ||
f2c853bc | 258 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
3f3e7313 UK |
259 | switch (ent->device) { |
260 | case 0x0180: | |
261 | case 0x0181: | |
9b14dec5 A |
262 | |
263 | /* The PATA-handling is provided by pata_sis */ | |
264 | switch (pmr & 0x30) { | |
265 | case 0x10: | |
a3cabb27 | 266 | ppi[1] = &sis_info133_for_sata; |
9b14dec5 | 267 | break; |
a84471fe | 268 | |
9b14dec5 | 269 | case 0x30: |
a3cabb27 | 270 | ppi[0] = &sis_info133_for_sata; |
9b14dec5 A |
271 | break; |
272 | } | |
f2c853bc | 273 | if ((pmr & SIS_PMR_COMBINED) == 0) { |
a9524a76 | 274 | dev_printk(KERN_INFO, &pdev->dev, |
4adccf6f | 275 | "Detected SiS 180/181/964 chipset in SATA mode\n"); |
39eb936c | 276 | port2_start = 64; |
3f3e7313 | 277 | } else { |
a9524a76 JG |
278 | dev_printk(KERN_INFO, &pdev->dev, |
279 | "Detected SiS 180/181 chipset in combined mode\n"); | |
5796d1c4 | 280 | port2_start = 0; |
4adccf6f | 281 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
f2c853bc | 282 | } |
3f3e7313 | 283 | break; |
f20b16ff | 284 | |
3f3e7313 UK |
285 | case 0x0182: |
286 | case 0x0183: | |
5796d1c4 | 287 | pci_read_config_dword(pdev, 0x6C, &val); |
4adccf6f | 288 | if (val & (1L << 31)) { |
5796d1c4 JG |
289 | dev_printk(KERN_INFO, &pdev->dev, |
290 | "Detected SiS 182/965 chipset\n"); | |
4adccf6f | 291 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
3f3e7313 | 292 | } else { |
5796d1c4 JG |
293 | dev_printk(KERN_INFO, &pdev->dev, |
294 | "Detected SiS 182/965L chipset\n"); | |
3f3e7313 UK |
295 | } |
296 | break; | |
297 | ||
298 | case 0x1182: | |
5796d1c4 JG |
299 | dev_printk(KERN_INFO, &pdev->dev, |
300 | "Detected SiS 1182/966/680 SATA controller\n"); | |
a3cabb27 UK |
301 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
302 | break; | |
303 | ||
3f3e7313 | 304 | case 0x1183: |
5796d1c4 JG |
305 | dev_printk(KERN_INFO, &pdev->dev, |
306 | "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n"); | |
a3cabb27 UK |
307 | ppi[0] = &sis_info133_for_sata; |
308 | ppi[1] = &sis_info133_for_sata; | |
3f3e7313 | 309 | break; |
f2c853bc AP |
310 | } |
311 | ||
d583bc18 | 312 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
9a829ccf TH |
313 | if (rc) |
314 | return rc; | |
cf0e812f | 315 | |
9a829ccf | 316 | if (!(pi.flags & SIS_FLAG_CFGSCR)) { |
edceec3d | 317 | void __iomem *mmio; |
0d5ff566 | 318 | |
9a829ccf TH |
319 | rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME); |
320 | if (rc) | |
321 | return rc; | |
322 | mmio = host->iomap[SIS_SCR_PCI_BAR]; | |
0d5ff566 | 323 | |
9a829ccf TH |
324 | host->ports[0]->ioaddr.scr_addr = mmio; |
325 | host->ports[1]->ioaddr.scr_addr = mmio + port2_start; | |
1da177e4 LT |
326 | } |
327 | ||
328 | pci_set_master(pdev); | |
a04ce0ff | 329 | pci_intx(pdev, 1); |
9a829ccf TH |
330 | return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, |
331 | &sis_sht); | |
1da177e4 LT |
332 | } |
333 | ||
334 | static int __init sis_init(void) | |
335 | { | |
b7887196 | 336 | return pci_register_driver(&sis_pci_driver); |
1da177e4 LT |
337 | } |
338 | ||
339 | static void __exit sis_exit(void) | |
340 | { | |
341 | pci_unregister_driver(&sis_pci_driver); | |
342 | } | |
343 | ||
344 | module_init(sis_init); | |
345 | module_exit(sis_exit); |