Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_uli.c - ULi Electronics SATA | |
3 | * | |
af36d7f0 JG |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * | |
20 | * libata documentation is available via 'make {ps|pdf}docs', | |
21 | * as Documentation/DocBook/libata.* | |
22 | * | |
23 | * Hardware documentation available under NDA. | |
1da177e4 LT |
24 | * |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/kernel.h> |
28 | #include <linux/module.h> | |
5a0e3ad6 | 29 | #include <linux/gfp.h> |
1da177e4 | 30 | #include <linux/pci.h> |
1da177e4 LT |
31 | #include <linux/blkdev.h> |
32 | #include <linux/delay.h> | |
33 | #include <linux/interrupt.h> | |
a9524a76 | 34 | #include <linux/device.h> |
1da177e4 LT |
35 | #include <scsi/scsi_host.h> |
36 | #include <linux/libata.h> | |
37 | ||
38 | #define DRV_NAME "sata_uli" | |
2a3103ce | 39 | #define DRV_VERSION "1.3" |
1da177e4 LT |
40 | |
41 | enum { | |
42 | uli_5289 = 0, | |
43 | uli_5287 = 1, | |
44 | uli_5281 = 2, | |
45 | ||
50106c5a JG |
46 | uli_max_ports = 4, |
47 | ||
1da177e4 LT |
48 | /* PCI configuration registers */ |
49 | ULI5287_BASE = 0x90, /* sata0 phy SCR registers */ | |
50 | ULI5287_OFFS = 0x10, /* offset from sata0->sata1 phy regs */ | |
51 | ULI5281_BASE = 0x60, /* sata0 phy SCR registers */ | |
52 | ULI5281_OFFS = 0x60, /* offset from sata0->sata1 phy regs */ | |
53 | }; | |
54 | ||
50106c5a JG |
55 | struct uli_priv { |
56 | unsigned int scr_cfg_addr[uli_max_ports]; | |
57 | }; | |
58 | ||
5796d1c4 | 59 | static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
82ef04fb TH |
60 | static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
61 | static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
1da177e4 | 62 | |
3b7d697d | 63 | static const struct pci_device_id uli_pci_tbl[] = { |
54bb3a94 JG |
64 | { PCI_VDEVICE(AL, 0x5289), uli_5289 }, |
65 | { PCI_VDEVICE(AL, 0x5287), uli_5287 }, | |
66 | { PCI_VDEVICE(AL, 0x5281), uli_5281 }, | |
67 | ||
1da177e4 LT |
68 | { } /* terminate list */ |
69 | }; | |
70 | ||
1da177e4 LT |
71 | static struct pci_driver uli_pci_driver = { |
72 | .name = DRV_NAME, | |
73 | .id_table = uli_pci_tbl, | |
74 | .probe = uli_init_one, | |
75 | .remove = ata_pci_remove_one, | |
76 | }; | |
77 | ||
193515d5 | 78 | static struct scsi_host_template uli_sht = { |
68d1d07b | 79 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
80 | }; |
81 | ||
029cfd6b TH |
82 | static struct ata_port_operations uli_ops = { |
83 | .inherits = &ata_bmdma_port_ops, | |
1da177e4 LT |
84 | .scr_read = uli_scr_read, |
85 | .scr_write = uli_scr_write, | |
70a3143a | 86 | .hardreset = ATA_OP_NULL, |
1da177e4 LT |
87 | }; |
88 | ||
1626aeb8 | 89 | static const struct ata_port_info uli_port_info = { |
9cbe056f | 90 | .flags = ATA_FLAG_SATA | ATA_FLAG_IGN_SIMPLEX, |
14bdef98 | 91 | .pio_mask = ATA_PIO4, |
bf6263a8 | 92 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
93 | .port_ops = &uli_ops, |
94 | }; | |
95 | ||
96 | ||
97 | MODULE_AUTHOR("Peer Chen"); | |
98 | MODULE_DESCRIPTION("low-level driver for ULi Electronics SATA controller"); | |
99 | MODULE_LICENSE("GPL"); | |
100 | MODULE_DEVICE_TABLE(pci, uli_pci_tbl); | |
101 | MODULE_VERSION(DRV_VERSION); | |
102 | ||
103 | static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg) | |
104 | { | |
cca3974e | 105 | struct uli_priv *hpriv = ap->host->private_data; |
50106c5a | 106 | return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg); |
1da177e4 LT |
107 | } |
108 | ||
82ef04fb | 109 | static u32 uli_scr_cfg_read(struct ata_link *link, unsigned int sc_reg) |
1da177e4 | 110 | { |
82ef04fb TH |
111 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); |
112 | unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg); | |
1da177e4 LT |
113 | u32 val; |
114 | ||
115 | pci_read_config_dword(pdev, cfg_addr, &val); | |
116 | return val; | |
117 | } | |
118 | ||
82ef04fb | 119 | static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val) |
1da177e4 | 120 | { |
82ef04fb TH |
121 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); |
122 | unsigned int cfg_addr = get_scr_cfg_addr(link->ap, scr); | |
1da177e4 LT |
123 | |
124 | pci_write_config_dword(pdev, cfg_addr, val); | |
125 | } | |
126 | ||
82ef04fb | 127 | static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4 LT |
128 | { |
129 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 130 | return -EINVAL; |
1da177e4 | 131 | |
82ef04fb | 132 | *val = uli_scr_cfg_read(link, sc_reg); |
da3dbb17 | 133 | return 0; |
1da177e4 LT |
134 | } |
135 | ||
82ef04fb | 136 | static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
1da177e4 | 137 | { |
5796d1c4 | 138 | if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0 |
da3dbb17 | 139 | return -EINVAL; |
1da177e4 | 140 | |
82ef04fb | 141 | uli_scr_cfg_write(link, sc_reg, val); |
da3dbb17 | 142 | return 0; |
1da177e4 LT |
143 | } |
144 | ||
5796d1c4 | 145 | static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 146 | { |
9a829ccf | 147 | const struct ata_port_info *ppi[] = { &uli_port_info, NULL }; |
1da177e4 | 148 | unsigned int board_idx = (unsigned int) ent->driver_data; |
9a829ccf | 149 | struct ata_host *host; |
50106c5a | 150 | struct uli_priv *hpriv; |
0d5ff566 | 151 | void __iomem * const *iomap; |
9a829ccf TH |
152 | struct ata_ioports *ioaddr; |
153 | int n_ports, rc; | |
1da177e4 | 154 | |
06296a1e | 155 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
a9524a76 | 156 | |
24dc5f33 | 157 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
158 | if (rc) |
159 | return rc; | |
160 | ||
9a829ccf TH |
161 | n_ports = 2; |
162 | if (board_idx == uli_5287) | |
163 | n_ports = 4; | |
1626aeb8 TH |
164 | |
165 | /* allocate the host */ | |
166 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
167 | if (!host) | |
168 | return -ENOMEM; | |
1da177e4 | 169 | |
24dc5f33 TH |
170 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
171 | if (!hpriv) | |
172 | return -ENOMEM; | |
9a829ccf | 173 | host->private_data = hpriv; |
50106c5a | 174 | |
1626aeb8 | 175 | /* the first two ports are standard SFF */ |
9363c382 | 176 | rc = ata_pci_sff_init_host(host); |
1626aeb8 TH |
177 | if (rc) |
178 | return rc; | |
179 | ||
c7087652 | 180 | ata_pci_bmdma_init(host); |
1626aeb8 | 181 | |
9a829ccf | 182 | iomap = host->iomap; |
0d5ff566 | 183 | |
1da177e4 LT |
184 | switch (board_idx) { |
185 | case uli_5287: | |
1626aeb8 TH |
186 | /* If there are four, the last two live right after |
187 | * the standard SFF ports. | |
188 | */ | |
50106c5a JG |
189 | hpriv->scr_cfg_addr[0] = ULI5287_BASE; |
190 | hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS; | |
1da177e4 | 191 | |
9a829ccf TH |
192 | ioaddr = &host->ports[2]->ioaddr; |
193 | ioaddr->cmd_addr = iomap[0] + 8; | |
194 | ioaddr->altstatus_addr = | |
195 | ioaddr->ctl_addr = (void __iomem *) | |
0d5ff566 | 196 | ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4; |
9a829ccf | 197 | ioaddr->bmdma_addr = iomap[4] + 16; |
50106c5a | 198 | hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4; |
9363c382 | 199 | ata_sff_std_ports(ioaddr); |
1da177e4 | 200 | |
cbcdd875 TH |
201 | ata_port_desc(host->ports[2], |
202 | "cmd 0x%llx ctl 0x%llx bmdma 0x%llx", | |
203 | (unsigned long long)pci_resource_start(pdev, 0) + 8, | |
204 | ((unsigned long long)pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS) + 4, | |
205 | (unsigned long long)pci_resource_start(pdev, 4) + 16); | |
206 | ||
9a829ccf TH |
207 | ioaddr = &host->ports[3]->ioaddr; |
208 | ioaddr->cmd_addr = iomap[2] + 8; | |
209 | ioaddr->altstatus_addr = | |
210 | ioaddr->ctl_addr = (void __iomem *) | |
0d5ff566 | 211 | ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4; |
9a829ccf | 212 | ioaddr->bmdma_addr = iomap[4] + 24; |
50106c5a | 213 | hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5; |
9363c382 | 214 | ata_sff_std_ports(ioaddr); |
cbcdd875 TH |
215 | |
216 | ata_port_desc(host->ports[2], | |
217 | "cmd 0x%llx ctl 0x%llx bmdma 0x%llx", | |
218 | (unsigned long long)pci_resource_start(pdev, 2) + 9, | |
219 | ((unsigned long long)pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS) + 4, | |
220 | (unsigned long long)pci_resource_start(pdev, 4) + 24); | |
221 | ||
1da177e4 LT |
222 | break; |
223 | ||
224 | case uli_5289: | |
50106c5a JG |
225 | hpriv->scr_cfg_addr[0] = ULI5287_BASE; |
226 | hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS; | |
1da177e4 LT |
227 | break; |
228 | ||
229 | case uli_5281: | |
50106c5a JG |
230 | hpriv->scr_cfg_addr[0] = ULI5281_BASE; |
231 | hpriv->scr_cfg_addr[1] = ULI5281_BASE + ULI5281_OFFS; | |
1da177e4 LT |
232 | break; |
233 | ||
234 | default: | |
235 | BUG(); | |
236 | break; | |
237 | } | |
238 | ||
239 | pci_set_master(pdev); | |
a04ce0ff | 240 | pci_intx(pdev, 1); |
c3b28894 | 241 | return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
9363c382 | 242 | IRQF_SHARED, &uli_sht); |
1da177e4 LT |
243 | } |
244 | ||
2fc75da0 | 245 | module_pci_driver(uli_pci_driver); |