Commit | Line | Data |
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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * sata_via.c - VIA Serial ATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
1da177e4 | 6 | on emails. |
af36d7f0 JG |
7 | * |
8 | * Copyright 2003-2004 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2004 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available under NDA. | |
31 | * | |
32 | * | |
33 | * To-do list: | |
34 | * - VT6421 PATA support | |
35 | * | |
1da177e4 LT |
36 | */ |
37 | ||
38 | #include <linux/kernel.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/pci.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/blkdev.h> | |
43 | #include <linux/delay.h> | |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 LT |
45 | #include <scsi/scsi_host.h> |
46 | #include <linux/libata.h> | |
1da177e4 LT |
47 | |
48 | #define DRV_NAME "sata_via" | |
2a3103ce | 49 | #define DRV_VERSION "2.3" |
1da177e4 LT |
50 | |
51 | enum board_ids_enum { | |
52 | vt6420, | |
53 | vt6421, | |
54 | }; | |
55 | ||
56 | enum { | |
57 | SATA_CHAN_ENAB = 0x40, /* SATA channel enable */ | |
58 | SATA_INT_GATE = 0x41, /* SATA interrupt gating */ | |
59 | SATA_NATIVE_MODE = 0x42, /* Native mode enable */ | |
d73f30e1 A |
60 | PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */ |
61 | PATA_PIO_TIMING = 0xAB, /* PATA timing register */ | |
a84471fe | 62 | |
1da177e4 LT |
63 | PORT0 = (1 << 1), |
64 | PORT1 = (1 << 0), | |
65 | ALL_PORTS = PORT0 | PORT1, | |
1da177e4 LT |
66 | |
67 | NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4), | |
68 | ||
69 | SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */ | |
1da177e4 LT |
70 | }; |
71 | ||
72 | static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
da3dbb17 TH |
73 | static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
74 | static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
17234246 | 75 | static void svia_noop_freeze(struct ata_port *ap); |
ac2164d5 | 76 | static void vt6420_error_handler(struct ata_port *ap); |
a0fcdc02 | 77 | static int vt6421_pata_cable_detect(struct ata_port *ap); |
d73f30e1 A |
78 | static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev); |
79 | static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev); | |
1da177e4 | 80 | |
3b7d697d | 81 | static const struct pci_device_id svia_pci_tbl[] = { |
96bc103f | 82 | { PCI_VDEVICE(VIA, 0x5337), vt6420 }, |
2d2744fc JG |
83 | { PCI_VDEVICE(VIA, 0x0591), vt6420 }, |
84 | { PCI_VDEVICE(VIA, 0x3149), vt6420 }, | |
85 | { PCI_VDEVICE(VIA, 0x3249), vt6421 }, | |
52df0ee0 JG |
86 | { PCI_VDEVICE(VIA, 0x5287), vt6420 }, |
87 | { PCI_VDEVICE(VIA, 0x5372), vt6420 }, | |
88 | { PCI_VDEVICE(VIA, 0x7372), vt6420 }, | |
1da177e4 LT |
89 | |
90 | { } /* terminate list */ | |
91 | }; | |
92 | ||
93 | static struct pci_driver svia_pci_driver = { | |
94 | .name = DRV_NAME, | |
95 | .id_table = svia_pci_tbl, | |
96 | .probe = svia_init_one, | |
e1e143cf TH |
97 | #ifdef CONFIG_PM |
98 | .suspend = ata_pci_device_suspend, | |
99 | .resume = ata_pci_device_resume, | |
100 | #endif | |
1da177e4 LT |
101 | .remove = ata_pci_remove_one, |
102 | }; | |
103 | ||
193515d5 | 104 | static struct scsi_host_template svia_sht = { |
1da177e4 LT |
105 | .module = THIS_MODULE, |
106 | .name = DRV_NAME, | |
107 | .ioctl = ata_scsi_ioctl, | |
108 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
109 | .can_queue = ATA_DEF_QUEUE, |
110 | .this_id = ATA_SHT_THIS_ID, | |
111 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
112 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
113 | .emulated = ATA_SHT_EMULATED, | |
114 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
115 | .proc_name = DRV_NAME, | |
116 | .dma_boundary = ATA_DMA_BOUNDARY, | |
117 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 118 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 119 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
120 | }; |
121 | ||
ac2164d5 | 122 | static const struct ata_port_operations vt6420_sata_ops = { |
ac2164d5 TH |
123 | .tf_load = ata_tf_load, |
124 | .tf_read = ata_tf_read, | |
125 | .check_status = ata_check_status, | |
126 | .exec_command = ata_exec_command, | |
127 | .dev_select = ata_std_dev_select, | |
128 | ||
129 | .bmdma_setup = ata_bmdma_setup, | |
130 | .bmdma_start = ata_bmdma_start, | |
131 | .bmdma_stop = ata_bmdma_stop, | |
132 | .bmdma_status = ata_bmdma_status, | |
133 | ||
134 | .qc_prep = ata_qc_prep, | |
135 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 136 | .data_xfer = ata_data_xfer, |
ac2164d5 | 137 | |
17234246 | 138 | .freeze = svia_noop_freeze, |
ac2164d5 TH |
139 | .thaw = ata_bmdma_thaw, |
140 | .error_handler = vt6420_error_handler, | |
141 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
142 | ||
ac2164d5 | 143 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 144 | .irq_on = ata_irq_on, |
ac2164d5 TH |
145 | |
146 | .port_start = ata_port_start, | |
ac2164d5 TH |
147 | }; |
148 | ||
d73f30e1 | 149 | static const struct ata_port_operations vt6421_pata_ops = { |
d73f30e1 A |
150 | .set_piomode = vt6421_set_pio_mode, |
151 | .set_dmamode = vt6421_set_dma_mode, | |
152 | ||
153 | .tf_load = ata_tf_load, | |
154 | .tf_read = ata_tf_read, | |
155 | .check_status = ata_check_status, | |
156 | .exec_command = ata_exec_command, | |
157 | .dev_select = ata_std_dev_select, | |
158 | ||
159 | .bmdma_setup = ata_bmdma_setup, | |
160 | .bmdma_start = ata_bmdma_start, | |
161 | .bmdma_stop = ata_bmdma_stop, | |
162 | .bmdma_status = ata_bmdma_status, | |
163 | ||
164 | .qc_prep = ata_qc_prep, | |
165 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 166 | .data_xfer = ata_data_xfer, |
d73f30e1 A |
167 | |
168 | .freeze = ata_bmdma_freeze, | |
169 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 170 | .error_handler = ata_bmdma_error_handler, |
d73f30e1 | 171 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 172 | .cable_detect = vt6421_pata_cable_detect, |
1da177e4 | 173 | |
d73f30e1 | 174 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 175 | .irq_on = ata_irq_on, |
d73f30e1 | 176 | |
eca25dca | 177 | .port_start = ata_port_start, |
d73f30e1 A |
178 | }; |
179 | ||
180 | static const struct ata_port_operations vt6421_sata_ops = { | |
1da177e4 LT |
181 | .tf_load = ata_tf_load, |
182 | .tf_read = ata_tf_read, | |
183 | .check_status = ata_check_status, | |
184 | .exec_command = ata_exec_command, | |
185 | .dev_select = ata_std_dev_select, | |
186 | ||
1da177e4 LT |
187 | .bmdma_setup = ata_bmdma_setup, |
188 | .bmdma_start = ata_bmdma_start, | |
189 | .bmdma_stop = ata_bmdma_stop, | |
190 | .bmdma_status = ata_bmdma_status, | |
191 | ||
192 | .qc_prep = ata_qc_prep, | |
193 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 194 | .data_xfer = ata_data_xfer, |
1da177e4 | 195 | |
40ef1d8d TH |
196 | .freeze = ata_bmdma_freeze, |
197 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 198 | .error_handler = ata_bmdma_error_handler, |
40ef1d8d | 199 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 200 | .cable_detect = ata_cable_sata, |
1da177e4 | 201 | |
1da177e4 | 202 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 203 | .irq_on = ata_irq_on, |
1da177e4 LT |
204 | |
205 | .scr_read = svia_scr_read, | |
206 | .scr_write = svia_scr_write, | |
207 | ||
eca25dca | 208 | .port_start = ata_port_start, |
1da177e4 LT |
209 | }; |
210 | ||
eca25dca | 211 | static const struct ata_port_info vt6420_port_info = { |
cca3974e | 212 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
1da177e4 LT |
213 | .pio_mask = 0x1f, |
214 | .mwdma_mask = 0x07, | |
bf6263a8 | 215 | .udma_mask = ATA_UDMA6, |
ac2164d5 | 216 | .port_ops = &vt6420_sata_ops, |
1da177e4 LT |
217 | }; |
218 | ||
eca25dca TH |
219 | static struct ata_port_info vt6421_sport_info = { |
220 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, | |
221 | .pio_mask = 0x1f, | |
222 | .mwdma_mask = 0x07, | |
bf6263a8 | 223 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
224 | .port_ops = &vt6421_sata_ops, |
225 | }; | |
226 | ||
227 | static struct ata_port_info vt6421_pport_info = { | |
228 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY, | |
229 | .pio_mask = 0x1f, | |
230 | .mwdma_mask = 0, | |
bf6263a8 | 231 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
232 | .port_ops = &vt6421_pata_ops, |
233 | }; | |
234 | ||
1da177e4 LT |
235 | MODULE_AUTHOR("Jeff Garzik"); |
236 | MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers"); | |
237 | MODULE_LICENSE("GPL"); | |
238 | MODULE_DEVICE_TABLE(pci, svia_pci_tbl); | |
239 | MODULE_VERSION(DRV_VERSION); | |
240 | ||
da3dbb17 | 241 | static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 LT |
242 | { |
243 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 TH |
244 | return -EINVAL; |
245 | *val = ioread32(ap->ioaddr.scr_addr + (4 * sc_reg)); | |
246 | return 0; | |
1da177e4 LT |
247 | } |
248 | ||
da3dbb17 | 249 | static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 LT |
250 | { |
251 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 252 | return -EINVAL; |
0d5ff566 | 253 | iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg)); |
da3dbb17 | 254 | return 0; |
1da177e4 LT |
255 | } |
256 | ||
17234246 TH |
257 | static void svia_noop_freeze(struct ata_port *ap) |
258 | { | |
259 | /* Some VIA controllers choke if ATA_NIEN is manipulated in | |
260 | * certain way. Leave it alone and just clear pending IRQ. | |
261 | */ | |
262 | ata_chk_status(ap); | |
d0259872 | 263 | ata_bmdma_irq_clear(ap); |
17234246 TH |
264 | } |
265 | ||
ac2164d5 TH |
266 | /** |
267 | * vt6420_prereset - prereset for vt6420 | |
cc0680a5 | 268 | * @link: target ATA link |
d4b2bab4 | 269 | * @deadline: deadline jiffies for the operation |
ac2164d5 TH |
270 | * |
271 | * SCR registers on vt6420 are pieces of shit and may hang the | |
272 | * whole machine completely if accessed with the wrong timing. | |
273 | * To avoid such catastrophe, vt6420 doesn't provide generic SCR | |
274 | * access operations, but uses SStatus and SControl only during | |
275 | * boot probing in controlled way. | |
276 | * | |
277 | * As the old (pre EH update) probing code is proven to work, we | |
278 | * strictly follow the access pattern. | |
279 | * | |
280 | * LOCKING: | |
281 | * Kernel thread context (may sleep) | |
282 | * | |
283 | * RETURNS: | |
284 | * 0 on success, -errno otherwise. | |
285 | */ | |
cc0680a5 | 286 | static int vt6420_prereset(struct ata_link *link, unsigned long deadline) |
ac2164d5 | 287 | { |
cc0680a5 | 288 | struct ata_port *ap = link->ap; |
9af5c9c9 | 289 | struct ata_eh_context *ehc = &ap->link.eh_context; |
ac2164d5 TH |
290 | unsigned long timeout = jiffies + (HZ * 5); |
291 | u32 sstatus, scontrol; | |
292 | int online; | |
293 | ||
294 | /* don't do any SCR stuff if we're not loading */ | |
68ff6e8e | 295 | if (!(ap->pflags & ATA_PFLAG_LOADING)) |
ac2164d5 TH |
296 | goto skip_scr; |
297 | ||
a09060ff | 298 | /* Resume phy. This is the old SATA resume sequence */ |
ac2164d5 | 299 | svia_scr_write(ap, SCR_CONTROL, 0x300); |
da3dbb17 | 300 | svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */ |
ac2164d5 TH |
301 | |
302 | /* wait for phy to become ready, if necessary */ | |
303 | do { | |
304 | msleep(200); | |
da3dbb17 TH |
305 | svia_scr_read(ap, SCR_STATUS, &sstatus); |
306 | if ((sstatus & 0xf) != 1) | |
ac2164d5 TH |
307 | break; |
308 | } while (time_before(jiffies, timeout)); | |
309 | ||
310 | /* open code sata_print_link_status() */ | |
da3dbb17 TH |
311 | svia_scr_read(ap, SCR_STATUS, &sstatus); |
312 | svia_scr_read(ap, SCR_CONTROL, &scontrol); | |
ac2164d5 TH |
313 | |
314 | online = (sstatus & 0xf) == 0x3; | |
315 | ||
316 | ata_port_printk(ap, KERN_INFO, | |
317 | "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n", | |
318 | online ? "up" : "down", sstatus, scontrol); | |
319 | ||
320 | /* SStatus is read one more time */ | |
da3dbb17 | 321 | svia_scr_read(ap, SCR_STATUS, &sstatus); |
ac2164d5 TH |
322 | |
323 | if (!online) { | |
324 | /* tell EH to bail */ | |
325 | ehc->i.action &= ~ATA_EH_RESET_MASK; | |
326 | return 0; | |
327 | } | |
328 | ||
329 | skip_scr: | |
330 | /* wait for !BSY */ | |
d4b2bab4 | 331 | ata_wait_ready(ap, deadline); |
ac2164d5 TH |
332 | |
333 | return 0; | |
334 | } | |
335 | ||
336 | static void vt6420_error_handler(struct ata_port *ap) | |
337 | { | |
338 | return ata_bmdma_drive_eh(ap, vt6420_prereset, ata_std_softreset, | |
339 | NULL, ata_std_postreset); | |
340 | } | |
341 | ||
a0fcdc02 | 342 | static int vt6421_pata_cable_detect(struct ata_port *ap) |
d73f30e1 A |
343 | { |
344 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
345 | u8 tmp; | |
346 | ||
347 | pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp); | |
348 | if (tmp & 0x10) | |
a0fcdc02 JG |
349 | return ATA_CBL_PATA40; |
350 | return ATA_CBL_PATA80; | |
d73f30e1 A |
351 | } |
352 | ||
353 | static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev) | |
354 | { | |
355 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
356 | static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 }; | |
357 | pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]); | |
358 | } | |
359 | ||
360 | static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev) | |
361 | { | |
362 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
363 | static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 }; | |
b4154d4a | 364 | pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]); |
d73f30e1 A |
365 | } |
366 | ||
1da177e4 LT |
367 | static const unsigned int svia_bar_sizes[] = { |
368 | 8, 4, 8, 4, 16, 256 | |
369 | }; | |
370 | ||
371 | static const unsigned int vt6421_bar_sizes[] = { | |
372 | 16, 16, 16, 16, 32, 128 | |
373 | }; | |
374 | ||
0d5ff566 | 375 | static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port) |
1da177e4 LT |
376 | { |
377 | return addr + (port * 128); | |
378 | } | |
379 | ||
0d5ff566 | 380 | static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port) |
1da177e4 LT |
381 | { |
382 | return addr + (port * 64); | |
383 | } | |
384 | ||
eca25dca | 385 | static void vt6421_init_addrs(struct ata_port *ap) |
1da177e4 | 386 | { |
eca25dca TH |
387 | void __iomem * const * iomap = ap->host->iomap; |
388 | void __iomem *reg_addr = iomap[ap->port_no]; | |
389 | void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8); | |
390 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
391 | ||
392 | ioaddr->cmd_addr = reg_addr; | |
393 | ioaddr->altstatus_addr = | |
394 | ioaddr->ctl_addr = (void __iomem *) | |
0d5ff566 | 395 | ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS); |
eca25dca TH |
396 | ioaddr->bmdma_addr = bmdma_addr; |
397 | ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no); | |
1da177e4 | 398 | |
eca25dca | 399 | ata_std_ports(ioaddr); |
cbcdd875 TH |
400 | |
401 | ata_port_pbar_desc(ap, ap->port_no, -1, "port"); | |
402 | ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma"); | |
1da177e4 LT |
403 | } |
404 | ||
eca25dca | 405 | static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) |
1da177e4 | 406 | { |
eca25dca TH |
407 | const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL }; |
408 | struct ata_host *host; | |
409 | int rc; | |
f20b16ff | 410 | |
d583bc18 | 411 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
eca25dca TH |
412 | if (rc) |
413 | return rc; | |
414 | *r_host = host; | |
1da177e4 | 415 | |
eca25dca TH |
416 | rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); |
417 | if (rc) { | |
e1be5d73 | 418 | dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n"); |
eca25dca | 419 | return rc; |
e1be5d73 TH |
420 | } |
421 | ||
eca25dca TH |
422 | host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0); |
423 | host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1); | |
1da177e4 | 424 | |
eca25dca | 425 | return 0; |
1da177e4 LT |
426 | } |
427 | ||
eca25dca | 428 | static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) |
1da177e4 | 429 | { |
eca25dca TH |
430 | const struct ata_port_info *ppi[] = |
431 | { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info }; | |
432 | struct ata_host *host; | |
433 | int i, rc; | |
434 | ||
435 | *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi)); | |
436 | if (!host) { | |
437 | dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); | |
438 | return -ENOMEM; | |
439 | } | |
1da177e4 | 440 | |
8fd7d1b1 | 441 | rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); |
eca25dca TH |
442 | if (rc) { |
443 | dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap " | |
444 | "PCI BARs (errno=%d)\n", rc); | |
445 | return rc; | |
446 | } | |
447 | host->iomap = pcim_iomap_table(pdev); | |
e1be5d73 | 448 | |
eca25dca TH |
449 | for (i = 0; i < host->n_ports; i++) |
450 | vt6421_init_addrs(host->ports[i]); | |
1da177e4 | 451 | |
eca25dca TH |
452 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
453 | if (rc) | |
454 | return rc; | |
455 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
456 | if (rc) | |
457 | return rc; | |
458 | ||
459 | return 0; | |
1da177e4 LT |
460 | } |
461 | ||
462 | static void svia_configure(struct pci_dev *pdev) | |
463 | { | |
464 | u8 tmp8; | |
465 | ||
466 | pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8); | |
a9524a76 | 467 | dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n", |
1da177e4 LT |
468 | (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f); |
469 | ||
470 | /* make sure SATA channels are enabled */ | |
471 | pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8); | |
472 | if ((tmp8 & ALL_PORTS) != ALL_PORTS) { | |
a9524a76 JG |
473 | dev_printk(KERN_DEBUG, &pdev->dev, |
474 | "enabling SATA channels (0x%x)\n", | |
475 | (int) tmp8); | |
1da177e4 LT |
476 | tmp8 |= ALL_PORTS; |
477 | pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8); | |
478 | } | |
479 | ||
480 | /* make sure interrupts for each channel sent to us */ | |
481 | pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8); | |
482 | if ((tmp8 & ALL_PORTS) != ALL_PORTS) { | |
a9524a76 JG |
483 | dev_printk(KERN_DEBUG, &pdev->dev, |
484 | "enabling SATA channel interrupts (0x%x)\n", | |
485 | (int) tmp8); | |
1da177e4 LT |
486 | tmp8 |= ALL_PORTS; |
487 | pci_write_config_byte(pdev, SATA_INT_GATE, tmp8); | |
488 | } | |
489 | ||
490 | /* make sure native mode is enabled */ | |
491 | pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8); | |
492 | if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) { | |
a9524a76 JG |
493 | dev_printk(KERN_DEBUG, &pdev->dev, |
494 | "enabling SATA channel native mode (0x%x)\n", | |
495 | (int) tmp8); | |
1da177e4 LT |
496 | tmp8 |= NATIVE_MODE_ALL; |
497 | pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8); | |
498 | } | |
499 | } | |
500 | ||
501 | static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
502 | { | |
503 | static int printed_version; | |
504 | unsigned int i; | |
505 | int rc; | |
eca25dca | 506 | struct ata_host *host; |
1da177e4 | 507 | int board_id = (int) ent->driver_data; |
b4482a4b | 508 | const unsigned *bar_sizes; |
1da177e4 LT |
509 | |
510 | if (!printed_version++) | |
a9524a76 | 511 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 512 | |
24dc5f33 | 513 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
514 | if (rc) |
515 | return rc; | |
516 | ||
b6d6c746 | 517 | if (board_id == vt6420) |
1da177e4 | 518 | bar_sizes = &svia_bar_sizes[0]; |
b6d6c746 | 519 | else |
1da177e4 | 520 | bar_sizes = &vt6421_bar_sizes[0]; |
1da177e4 LT |
521 | |
522 | for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++) | |
523 | if ((pci_resource_start(pdev, i) == 0) || | |
524 | (pci_resource_len(pdev, i) < bar_sizes[i])) { | |
a9524a76 | 525 | dev_printk(KERN_ERR, &pdev->dev, |
e29419ff GKH |
526 | "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n", |
527 | i, | |
528 | (unsigned long long)pci_resource_start(pdev, i), | |
529 | (unsigned long long)pci_resource_len(pdev, i)); | |
24dc5f33 | 530 | return -ENODEV; |
1da177e4 LT |
531 | } |
532 | ||
1da177e4 | 533 | if (board_id == vt6420) |
eca25dca | 534 | rc = vt6420_prepare_host(pdev, &host); |
1da177e4 | 535 | else |
eca25dca TH |
536 | rc = vt6421_prepare_host(pdev, &host); |
537 | if (rc) | |
538 | return rc; | |
1da177e4 LT |
539 | |
540 | svia_configure(pdev); | |
541 | ||
542 | pci_set_master(pdev); | |
eca25dca TH |
543 | return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, |
544 | &svia_sht); | |
1da177e4 LT |
545 | } |
546 | ||
547 | static int __init svia_init(void) | |
548 | { | |
b7887196 | 549 | return pci_register_driver(&svia_pci_driver); |
1da177e4 LT |
550 | } |
551 | ||
552 | static void __exit svia_exit(void) | |
553 | { | |
554 | pci_unregister_driver(&svia_pci_driver); | |
555 | } | |
556 | ||
557 | module_init(svia_init); | |
558 | module_exit(svia_exit); |