[deliverable/linux.git] / drivers / ata / sata_via.c

/*
 *  sata_via.c - VIA Serial ATA controllers
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 * 		   Please ALWAYS copy linux-ide@vger.kernel.org
 		   on emails.
 *
 *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
 *  Copyright 2003-2004 Jeff Garzik
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 *
 *  To-do list:
 *  - VT6421 PATA support
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_via"
#define DRV_VERSION	"2.0"

enum board_ids_enum {
	vt6420,
	vt6421,
};

enum {
	SATA_CHAN_ENAB		= 0x40, /* SATA channel enable */
	SATA_INT_GATE		= 0x41, /* SATA interrupt gating */
	SATA_NATIVE_MODE	= 0x42, /* Native mode enable */
	SATA_PATA_SHARING	= 0x49, /* PATA/SATA sharing func ctrl */
	PATA_UDMA_TIMING	= 0xB3, /* PATA timing for DMA/ cable detect */
	PATA_PIO_TIMING		= 0xAB, /* PATA timing register */
	
	PORT0			= (1 << 1),
	PORT1			= (1 << 0),
	ALL_PORTS		= PORT0 | PORT1,
	PATA_PORT		= 2,	/* PATA is port 2 */
	N_PORTS			= 3,

	NATIVE_MODE_ALL		= (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),

	SATA_EXT_PHY		= (1 << 6), /* 0==use PATA, 1==ext phy */
	SATA_2DEV		= (1 << 5), /* SATA is master/slave */
};

static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static u32 svia_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void svia_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void svia_noop_freeze(struct ata_port *ap);
static void vt6420_error_handler(struct ata_port *ap);
static void vt6421_sata_error_handler(struct ata_port *ap);
static void vt6421_pata_error_handler(struct ata_port *ap);
static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
static int vt6421_port_start(struct ata_port *ap);

static const struct pci_device_id svia_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
	{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
	{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
	{ PCI_VDEVICE(VIA, 0x3249), vt6421 },

	{ }	/* terminate list */
};

static struct pci_driver svia_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= svia_pci_tbl,
	.probe			= svia_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template svia_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations vt6420_sata_ops = {
	.port_disable		= ata_port_disable,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,

	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.freeze			= svia_noop_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= vt6420_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};

static const struct ata_port_operations vt6421_pata_ops = {
	.port_disable		= ata_port_disable,
	
	.set_piomode		= vt6421_set_pio_mode,
	.set_dmamode		= vt6421_set_dma_mode,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,

	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= vt6421_pata_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= vt6421_port_start,
};

static const struct ata_port_operations vt6421_sata_ops = {
	.port_disable		= ata_port_disable,
	
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,

	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= vt6421_sata_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.scr_read		= svia_scr_read,
	.scr_write		= svia_scr_write,

	.port_start		= vt6421_port_start,
};

static struct ata_port_info vt6420_port_info = {
	.sht		= &svia_sht,
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x07,
	.udma_mask	= 0x7f,
	.port_ops	= &vt6420_sata_ops,
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static u32 svia_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;
	return ioread32(ap->ioaddr.scr_addr + (4 * sc_reg));
}

static void svia_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;
	iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
}

static void svia_noop_freeze(struct ata_port *ap)
{
	/* Some VIA controllers choke if ATA_NIEN is manipulated in
	 * certain way.  Leave it alone and just clear pending IRQ.
	 */
	ata_chk_status(ap);
	ata_bmdma_irq_clear(ap);
}

/**
 *	vt6420_prereset - prereset for vt6420
 *	@ap: target ATA port
 *
 *	SCR registers on vt6420 are pieces of shit and may hang the
 *	whole machine completely if accessed with the wrong timing.
 *	To avoid such catastrophe, vt6420 doesn't provide generic SCR
 *	access operations, but uses SStatus and SControl only during
 *	boot probing in controlled way.
 *
 *	As the old (pre EH update) probing code is proven to work, we
 *	strictly follow the access pattern.
 *
 *	LOCKING:
 *	Kernel thread context (may sleep)
 *
 *	RETURNS:
 *	0 on success, -errno otherwise.
 */
static int vt6420_prereset(struct ata_port *ap)
{
	struct ata_eh_context *ehc = &ap->eh_context;
	unsigned long timeout = jiffies + (HZ * 5);
	u32 sstatus, scontrol;
	int online;

	/* don't do any SCR stuff if we're not loading */
	if (!(ap->pflags & ATA_PFLAG_LOADING))
		goto skip_scr;

	/* Resume phy.  This is the old resume sequence from
	 * __sata_phy_reset().
	 */
	svia_scr_write(ap, SCR_CONTROL, 0x300);
	svia_scr_read(ap, SCR_CONTROL); /* flush */

	/* wait for phy to become ready, if necessary */
	do {
		msleep(200);
		if ((svia_scr_read(ap, SCR_STATUS) & 0xf) != 1)
			break;
	} while (time_before(jiffies, timeout));

	/* open code sata_print_link_status() */
	sstatus = svia_scr_read(ap, SCR_STATUS);
	scontrol = svia_scr_read(ap, SCR_CONTROL);

	online = (sstatus & 0xf) == 0x3;

	ata_port_printk(ap, KERN_INFO,
			"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
			online ? "up" : "down", sstatus, scontrol);

	/* SStatus is read one more time */
	svia_scr_read(ap, SCR_STATUS);

	if (!online) {
		/* tell EH to bail */
		ehc->i.action &= ~ATA_EH_RESET_MASK;
		return 0;
	}

 skip_scr:
	/* wait for !BSY */
	ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);

	return 0;
}

static void vt6420_error_handler(struct ata_port *ap)
{
	return ata_bmdma_drive_eh(ap, vt6420_prereset, ata_std_softreset,
				  NULL, ata_std_postreset);
}

static int vt6421_pata_prereset(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;

	pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
	if (tmp & 0x10)
		ap->cbl = ATA_CBL_PATA40;
	else
		ap->cbl = ATA_CBL_PATA80;
	return 0;
}

static void vt6421_pata_error_handler(struct ata_port *ap)
{
	return ata_bmdma_drive_eh(ap, vt6421_pata_prereset, ata_std_softreset,
				  NULL, ata_std_postreset);
}

static int vt6421_sata_prereset(struct ata_port *ap)
{
	ap->cbl = ATA_CBL_SATA;
	return 0;
}

static void vt6421_sata_error_handler(struct ata_port *ap)
{
	return ata_bmdma_drive_eh(ap, vt6421_sata_prereset, ata_std_softreset,
				  NULL, ata_std_postreset);
}

static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
	pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
}

static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
	pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->pio_mode - XFER_UDMA_0]);
}

static int vt6421_port_start(struct ata_port *ap)
{
	if (ap->port_no == PATA_PORT) {
		ap->ops = &vt6421_pata_ops;
		ap->mwdma_mask = 0;
		ap->flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST;
	}
	return ata_port_start(ap);
}

static const unsigned int svia_bar_sizes[] = {
	8, 4, 8, 4, 16, 256
};

static const unsigned int vt6421_bar_sizes[] = {
	16, 16, 16, 16, 32, 128
};

static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port)
{
	return addr + (port * 128);
}

static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port)
{
	return addr + (port * 64);
}

static void vt6421_init_addrs(struct ata_probe_ent *probe_ent,
			      void __iomem * const *iomap, unsigned int port)
{
	void __iomem *reg_addr = iomap[port];
	void __iomem *bmdma_addr = iomap[4] + (port * 8);

	probe_ent->port[port].cmd_addr = reg_addr;
	probe_ent->port[port].altstatus_addr =
	probe_ent->port[port].ctl_addr = (void __iomem *)
		((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
	probe_ent->port[port].bmdma_addr = bmdma_addr;
	probe_ent->port[port].scr_addr = vt6421_scr_addr(iomap[5], port);

	ata_std_ports(&probe_ent->port[port]);
}

static struct ata_probe_ent *vt6420_init_probe_ent(struct pci_dev *pdev)
{
	struct ata_probe_ent *probe_ent;
	struct ata_port_info *ppi[2];
	void __iomem * const *iomap;

	ppi[0] = ppi[1] = &vt6420_port_info;
	probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
	if (!probe_ent)
		return NULL;

	iomap = pcim_iomap_table(pdev);
	probe_ent->port[0].scr_addr = svia_scr_addr(iomap[5], 0);
	probe_ent->port[1].scr_addr = svia_scr_addr(iomap[5], 1);

	return probe_ent;
}

static struct ata_probe_ent *vt6421_init_probe_ent(struct pci_dev *pdev)
{
	struct ata_probe_ent *probe_ent;
	unsigned int i;

	probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
	if (!probe_ent)
		return NULL;

	memset(probe_ent, 0, sizeof(*probe_ent));
	probe_ent->dev = pci_dev_to_dev(pdev);
	INIT_LIST_HEAD(&probe_ent->node);

	probe_ent->sht		= &svia_sht;
	probe_ent->port_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY;
	probe_ent->port_ops	= &vt6421_sata_ops;
	probe_ent->n_ports	= N_PORTS;
	probe_ent->irq		= pdev->irq;
	probe_ent->irq_flags	= IRQF_SHARED;
	probe_ent->pio_mask	= 0x1f;
	probe_ent->mwdma_mask	= 0x07;
	probe_ent->udma_mask	= 0x7f;

	for (i = 0; i < N_PORTS; i++)
		vt6421_init_addrs(probe_ent, pcim_iomap_table(pdev), i);

	return probe_ent;
}

static void svia_configure(struct pci_dev *pdev)
{
	u8 tmp8;

	pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
	dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
	       (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);

	/* make sure SATA channels are enabled */
	pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channels (0x%x)\n",
		           (int) tmp8);
		tmp8 |= ALL_PORTS;
		pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
	}

	/* make sure interrupts for each channel sent to us */
	pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channel interrupts (0x%x)\n",
		           (int) tmp8);
		tmp8 |= ALL_PORTS;
		pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
	}

	/* make sure native mode is enabled */
	pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
	if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channel native mode (0x%x)\n",
		           (int) tmp8);
		tmp8 |= NATIVE_MODE_ALL;
		pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
	}
}

static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	unsigned int i;
	int rc;
	struct ata_probe_ent *probe_ent;
	int board_id = (int) ent->driver_data;
	const int *bar_sizes;
	u8 tmp8;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	rc = pcim_iomap_regions(pdev, 0x1f, DRV_NAME);
	if (rc) {
		pcim_pin_device(pdev);
		return rc;
	}

	if (board_id == vt6420) {
		pci_read_config_byte(pdev, SATA_PATA_SHARING, &tmp8);
		if (tmp8 & SATA_2DEV) {
			dev_printk(KERN_ERR, &pdev->dev,
				   "SATA master/slave not supported (0x%x)\n",
		       		   (int) tmp8);
			return -EIO;
		}

		bar_sizes = &svia_bar_sizes[0];
	} else {
		bar_sizes = &vt6421_bar_sizes[0];
	}

	for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
		if ((pci_resource_start(pdev, i) == 0) ||
		    (pci_resource_len(pdev, i) < bar_sizes[i])) {
			dev_printk(KERN_ERR, &pdev->dev,
				"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
				i,
			        (unsigned long long)pci_resource_start(pdev, i),
			        (unsigned long long)pci_resource_len(pdev, i));
			return -ENODEV;
		}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	if (board_id == vt6420)
		probe_ent = vt6420_init_probe_ent(pdev);
	else
		probe_ent = vt6421_init_probe_ent(pdev);

	if (!probe_ent) {
		dev_printk(KERN_ERR, &pdev->dev, "out of memory\n");
		return -ENOMEM;
	}

	svia_configure(pdev);

	pci_set_master(pdev);

	if (!ata_device_add(probe_ent))
		return -ENODEV;

	devm_kfree(&pdev->dev, probe_ent);
	return 0;
}

static int __init svia_init(void)
{
	return pci_register_driver(&svia_pci_driver);
}

static void __exit svia_exit(void)
{
	pci_unregister_driver(&svia_pci_driver);
}

module_init(svia_init);
module_exit(svia_exit);
Commit	Line	Data
1da177e4	1	/*
af36d7f0 JG	2	* sata_via.c - VIA Serial ATA controllers
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
1da177e4	6	on emails.
af36d7f0 JG	7	*
	8	* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
	9	* Copyright 2003-2004 Jeff Garzik
	10	*
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2, or (at your option)
	15	* any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; see the file COPYING. If not, write to
	24	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
	26	*
	27	* libata documentation is available via 'make {ps\|pdf}docs',
	28	* as Documentation/DocBook/libata.*
	29	*
	30	* Hardware documentation available under NDA.
	31	*
	32	*
	33	* To-do list:
	34	* - VT6421 PATA support
	35	*
1da177e4 LT	36	*/
	37
	38	#include <linux/kernel.h>
	39	#include <linux/module.h>
	40	#include <linux/pci.h>
	41	#include <linux/init.h>
	42	#include <linux/blkdev.h>
	43	#include <linux/delay.h>
a9524a76	44	#include <linux/device.h>
1da177e4 LT	45	#include <scsi/scsi_host.h>
1da177e4 LT	46	#include <linux/libata.h>
1da177e4 LT	47
1da177e4 LT	48	#define DRV_NAME "sata_via"
8676ce07	49	#define DRV_VERSION "2.0"
1da177e4 LT	50
	51	enum board_ids_enum {
	52	vt6420,
	53	vt6421,
	54	};
	55
	56	enum {
	57	SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
	58	SATA_INT_GATE = 0x41, /* SATA interrupt gating */
	59	SATA_NATIVE_MODE = 0x42, /* Native mode enable */
	60	SATA_PATA_SHARING = 0x49, /* PATA/SATA sharing func ctrl */
d73f30e1 A	61	PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
	62	PATA_PIO_TIMING = 0xAB, /* PATA timing register */
	63
1da177e4 LT	64	PORT0 = (1 << 1),
	65	PORT1 = (1 << 0),
	66	ALL_PORTS = PORT0 \| PORT1,
d73f30e1 A	67	PATA_PORT = 2, /* PATA is port 2 */
d73f30e1 A	68	N_PORTS = 3,
1da177e4 LT	69
	70	NATIVE_MODE_ALL = (1 << 7) \| (1 << 6) \| (1 << 5) \| (1 << 4),
	71
	72	SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
	73	SATA_2DEV = (1 << 5), /* SATA is master/slave */
	74	};
	75
	76	static int svia_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	77	static u32 svia_scr_read (struct ata_port *ap, unsigned int sc_reg);
	78	static void svia_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
17234246	79	static void svia_noop_freeze(struct ata_port *ap);
ac2164d5	80	static void vt6420_error_handler(struct ata_port *ap);
d73f30e1 A	81	static void vt6421_sata_error_handler(struct ata_port *ap);
	82	static void vt6421_pata_error_handler(struct ata_port *ap);
	83	static void vt6421_set_pio_mode(struct ata_port ap, struct ata_device adev);
	84	static void vt6421_set_dma_mode(struct ata_port ap, struct ata_device adev);
	85	static int vt6421_port_start(struct ata_port *ap);
1da177e4	86
3b7d697d	87	static const struct pci_device_id svia_pci_tbl[] = {
96bc103f	88	{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
2d2744fc JG	89	{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
	90	{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
	91	{ PCI_VDEVICE(VIA, 0x3249), vt6421 },
1da177e4 LT	92
	93	{ } /* terminate list */
	94	};
	95
	96	static struct pci_driver svia_pci_driver = {
	97	.name = DRV_NAME,
	98	.id_table = svia_pci_tbl,
	99	.probe = svia_init_one,
	100	.remove = ata_pci_remove_one,
	101	};
	102
193515d5	103	static struct scsi_host_template svia_sht = {
1da177e4 LT	104	.module = THIS_MODULE,
	105	.name = DRV_NAME,
	106	.ioctl = ata_scsi_ioctl,
	107	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	108	.can_queue = ATA_DEF_QUEUE,
	109	.this_id = ATA_SHT_THIS_ID,
	110	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	111	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	112	.emulated = ATA_SHT_EMULATED,
	113	.use_clustering = ATA_SHT_USE_CLUSTERING,
	114	.proc_name = DRV_NAME,
	115	.dma_boundary = ATA_DMA_BOUNDARY,
	116	.slave_configure = ata_scsi_slave_config,
ccf68c34	117	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	118	.bios_param = ata_std_bios_param,
1da177e4 LT	119	};
1da177e4 LT	120
ac2164d5 TH	121	static const struct ata_port_operations vt6420_sata_ops = {
	122	.port_disable = ata_port_disable,
	123
	124	.tf_load = ata_tf_load,
	125	.tf_read = ata_tf_read,
	126	.check_status = ata_check_status,
	127	.exec_command = ata_exec_command,
	128	.dev_select = ata_std_dev_select,
	129
	130	.bmdma_setup = ata_bmdma_setup,
	131	.bmdma_start = ata_bmdma_start,
	132	.bmdma_stop = ata_bmdma_stop,
	133	.bmdma_status = ata_bmdma_status,
	134
	135	.qc_prep = ata_qc_prep,
	136	.qc_issue = ata_qc_issue_prot,
0d5ff566	137	.data_xfer = ata_data_xfer,
ac2164d5	138
17234246	139	.freeze = svia_noop_freeze,
ac2164d5 TH	140	.thaw = ata_bmdma_thaw,
	141	.error_handler = vt6420_error_handler,
	142	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	143
	144	.irq_handler = ata_interrupt,
	145	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	146	.irq_on = ata_irq_on,
246ce3b6 AI	147	.irq_ack = ata_irq_ack,
ac2164d5 TH	148
ac2164d5 TH	149	.port_start = ata_port_start,
ac2164d5 TH	150	};
ac2164d5 TH	151
d73f30e1	152	static const struct ata_port_operations vt6421_pata_ops = {
1da177e4	153	.port_disable = ata_port_disable,
d73f30e1 A	154
	155	.set_piomode = vt6421_set_pio_mode,
	156	.set_dmamode = vt6421_set_dma_mode,
	157
	158	.tf_load = ata_tf_load,
	159	.tf_read = ata_tf_read,
	160	.check_status = ata_check_status,
	161	.exec_command = ata_exec_command,
	162	.dev_select = ata_std_dev_select,
	163
	164	.bmdma_setup = ata_bmdma_setup,
	165	.bmdma_start = ata_bmdma_start,
	166	.bmdma_stop = ata_bmdma_stop,
	167	.bmdma_status = ata_bmdma_status,
	168
	169	.qc_prep = ata_qc_prep,
	170	.qc_issue = ata_qc_issue_prot,
0d5ff566	171	.data_xfer = ata_data_xfer,
d73f30e1 A	172
	173	.freeze = ata_bmdma_freeze,
	174	.thaw = ata_bmdma_thaw,
	175	.error_handler = vt6421_pata_error_handler,
	176	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4	177
d73f30e1 A	178	.irq_handler = ata_interrupt,
d73f30e1 A	179	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	180	.irq_on = ata_irq_on,
246ce3b6 AI	181	.irq_ack = ata_irq_ack,
d73f30e1 A	182
d73f30e1 A	183	.port_start = vt6421_port_start,
d73f30e1 A	184	};
	185
	186	static const struct ata_port_operations vt6421_sata_ops = {
	187	.port_disable = ata_port_disable,
	188
1da177e4 LT	189	.tf_load = ata_tf_load,
	190	.tf_read = ata_tf_read,
	191	.check_status = ata_check_status,
	192	.exec_command = ata_exec_command,
	193	.dev_select = ata_std_dev_select,
	194
1da177e4 LT	195	.bmdma_setup = ata_bmdma_setup,
	196	.bmdma_start = ata_bmdma_start,
	197	.bmdma_stop = ata_bmdma_stop,
	198	.bmdma_status = ata_bmdma_status,
	199
	200	.qc_prep = ata_qc_prep,
	201	.qc_issue = ata_qc_issue_prot,
0d5ff566	202	.data_xfer = ata_data_xfer,
1da177e4	203
40ef1d8d TH	204	.freeze = ata_bmdma_freeze,
40ef1d8d TH	205	.thaw = ata_bmdma_thaw,
d73f30e1	206	.error_handler = vt6421_sata_error_handler,
40ef1d8d	207	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 LT	208
	209	.irq_handler = ata_interrupt,
	210	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	211	.irq_on = ata_irq_on,
246ce3b6 AI	212	.irq_ack = ata_irq_ack,
1da177e4 LT	213
	214	.scr_read = svia_scr_read,
	215	.scr_write = svia_scr_write,
	216
d73f30e1	217	.port_start = vt6421_port_start,
1da177e4 LT	218	};
1da177e4 LT	219
ac2164d5	220	static struct ata_port_info vt6420_port_info = {
1da177e4	221	.sht = &svia_sht,
cca3974e	222	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
1da177e4 LT	223	.pio_mask = 0x1f,
	224	.mwdma_mask = 0x07,
	225	.udma_mask = 0x7f,
ac2164d5	226	.port_ops = &vt6420_sata_ops,
1da177e4 LT	227	};
	228
	229	MODULE_AUTHOR("Jeff Garzik");
	230	MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
	231	MODULE_LICENSE("GPL");
	232	MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
	233	MODULE_VERSION(DRV_VERSION);
	234
	235	static u32 svia_scr_read (struct ata_port *ap, unsigned int sc_reg)
	236	{
	237	if (sc_reg > SCR_CONTROL)
	238	return 0xffffffffU;
0d5ff566	239	return ioread32(ap->ioaddr.scr_addr + (4 * sc_reg));
1da177e4 LT	240	}
	241
	242	static void svia_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	243	{
	244	if (sc_reg > SCR_CONTROL)
	245	return;
0d5ff566	246	iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
1da177e4 LT	247	}
1da177e4 LT	248
17234246 TH	249	static void svia_noop_freeze(struct ata_port *ap)
	250	{
	251	/* Some VIA controllers choke if ATA_NIEN is manipulated in
	252	* certain way. Leave it alone and just clear pending IRQ.
	253	*/
	254	ata_chk_status(ap);
d0259872	255	ata_bmdma_irq_clear(ap);
17234246 TH	256	}
17234246 TH	257
ac2164d5 TH	258	/**
	259	* vt6420_prereset - prereset for vt6420
	260	* @ap: target ATA port
	261	*
	262	* SCR registers on vt6420 are pieces of shit and may hang the
	263	* whole machine completely if accessed with the wrong timing.
	264	* To avoid such catastrophe, vt6420 doesn't provide generic SCR
	265	* access operations, but uses SStatus and SControl only during
	266	* boot probing in controlled way.
	267	*
	268	* As the old (pre EH update) probing code is proven to work, we
	269	* strictly follow the access pattern.
	270	*
	271	* LOCKING:
	272	* Kernel thread context (may sleep)
	273	*
	274	* RETURNS:
	275	* 0 on success, -errno otherwise.
	276	*/
	277	static int vt6420_prereset(struct ata_port *ap)
	278	{
	279	struct ata_eh_context *ehc = &ap->eh_context;
	280	unsigned long timeout = jiffies + (HZ * 5);
	281	u32 sstatus, scontrol;
	282	int online;
	283
	284	/* don't do any SCR stuff if we're not loading */
68ff6e8e	285	if (!(ap->pflags & ATA_PFLAG_LOADING))
ac2164d5 TH	286	goto skip_scr;
	287
	288	/* Resume phy. This is the old resume sequence from
	289	* __sata_phy_reset().
	290	*/
	291	svia_scr_write(ap, SCR_CONTROL, 0x300);
	292	svia_scr_read(ap, SCR_CONTROL); /* flush */
	293
	294	/* wait for phy to become ready, if necessary */
	295	do {
	296	msleep(200);
	297	if ((svia_scr_read(ap, SCR_STATUS) & 0xf) != 1)
	298	break;
	299	} while (time_before(jiffies, timeout));
	300
	301	/* open code sata_print_link_status() */
	302	sstatus = svia_scr_read(ap, SCR_STATUS);
	303	scontrol = svia_scr_read(ap, SCR_CONTROL);
	304
	305	online = (sstatus & 0xf) == 0x3;
	306
	307	ata_port_printk(ap, KERN_INFO,
	308	"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
	309	online ? "up" : "down", sstatus, scontrol);
	310
	311	/* SStatus is read one more time */
	312	svia_scr_read(ap, SCR_STATUS);
	313
	314	if (!online) {
	315	/* tell EH to bail */
	316	ehc->i.action &= ~ATA_EH_RESET_MASK;
	317	return 0;
	318	}
	319
	320	skip_scr:
	321	/* wait for !BSY */
	322	ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
	323
	324	return 0;
	325	}
	326
	327	static void vt6420_error_handler(struct ata_port *ap)
	328	{
	329	return ata_bmdma_drive_eh(ap, vt6420_prereset, ata_std_softreset,
	330	NULL, ata_std_postreset);
	331	}
	332
d73f30e1 A	333	static int vt6421_pata_prereset(struct ata_port *ap)
	334	{
	335	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	336	u8 tmp;
	337
	338	pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
	339	if (tmp & 0x10)
	340	ap->cbl = ATA_CBL_PATA40;
	341	else
	342	ap->cbl = ATA_CBL_PATA80;
	343	return 0;
	344	}
	345
	346	static void vt6421_pata_error_handler(struct ata_port *ap)
	347	{
	348	return ata_bmdma_drive_eh(ap, vt6421_pata_prereset, ata_std_softreset,
	349	NULL, ata_std_postreset);
	350	}
	351
	352	static int vt6421_sata_prereset(struct ata_port *ap)
	353	{
	354	ap->cbl = ATA_CBL_SATA;
	355	return 0;
	356	}
	357
	358	static void vt6421_sata_error_handler(struct ata_port *ap)
	359	{
	360	return ata_bmdma_drive_eh(ap, vt6421_sata_prereset, ata_std_softreset,
	361	NULL, ata_std_postreset);
	362	}
	363
	364	static void vt6421_set_pio_mode(struct ata_port ap, struct ata_device adev)
	365	{
	366	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	367	static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
	368	pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
	369	}
	370
	371	static void vt6421_set_dma_mode(struct ata_port ap, struct ata_device adev)
	372	{
	373	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	374	static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
	375	pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->pio_mode - XFER_UDMA_0]);
	376	}
	377
	378	static int vt6421_port_start(struct ata_port *ap)
	379	{
	380	if (ap->port_no == PATA_PORT) {
	381	ap->ops = &vt6421_pata_ops;
	382	ap->mwdma_mask = 0;
	383	ap->flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_NO_LEGACY \| ATA_FLAG_SRST;
	384	}
	385	return ata_port_start(ap);
	386	}
	387
1da177e4 LT	388	static const unsigned int svia_bar_sizes[] = {
	389	8, 4, 8, 4, 16, 256
	390	};
	391
	392	static const unsigned int vt6421_bar_sizes[] = {
	393	16, 16, 16, 16, 32, 128
	394	};
	395
0d5ff566	396	static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port)
1da177e4 LT	397	{
	398	return addr + (port * 128);
	399	}
	400
0d5ff566	401	static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port)
1da177e4 LT	402	{
	403	return addr + (port * 64);
	404	}
	405
	406	static void vt6421_init_addrs(struct ata_probe_ent *probe_ent,
0d5ff566	407	void __iomem * const *iomap, unsigned int port)
1da177e4	408	{
0d5ff566 TH	409	void __iomem *reg_addr = iomap[port];
0d5ff566 TH	410	void __iomem bmdma_addr = iomap[4] + (port 8);
1da177e4 LT	411
	412	probe_ent->port[port].cmd_addr = reg_addr;
	413	probe_ent->port[port].altstatus_addr =
0d5ff566 TH	414	probe_ent->port[port].ctl_addr = (void __iomem *)
0d5ff566 TH	415	((unsigned long)(reg_addr + 8) \| ATA_PCI_CTL_OFS);
1da177e4	416	probe_ent->port[port].bmdma_addr = bmdma_addr;
0d5ff566	417	probe_ent->port[port].scr_addr = vt6421_scr_addr(iomap[5], port);
1da177e4 LT	418
	419	ata_std_ports(&probe_ent->port[port]);
	420	}
	421
	422	static struct ata_probe_ent vt6420_init_probe_ent(struct pci_dev pdev)
	423	{
	424	struct ata_probe_ent *probe_ent;
29da9f6d	425	struct ata_port_info *ppi[2];
0d5ff566	426	void __iomem * const *iomap;
f20b16ff	427
29da9f6d JG	428	ppi[0] = ppi[1] = &vt6420_port_info;
29da9f6d JG	429	probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY \| ATA_PORT_SECONDARY);
1da177e4 LT	430	if (!probe_ent)
	431	return NULL;
	432
0d5ff566 TH	433	iomap = pcim_iomap_table(pdev);
	434	probe_ent->port[0].scr_addr = svia_scr_addr(iomap[5], 0);
	435	probe_ent->port[1].scr_addr = svia_scr_addr(iomap[5], 1);
1da177e4 LT	436
	437	return probe_ent;
	438	}
	439
	440	static struct ata_probe_ent vt6421_init_probe_ent(struct pci_dev pdev)
	441	{
	442	struct ata_probe_ent *probe_ent;
	443	unsigned int i;
	444
24dc5f33	445	probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
1da177e4 LT	446	if (!probe_ent)
	447	return NULL;
	448
	449	memset(probe_ent, 0, sizeof(*probe_ent));
	450	probe_ent->dev = pci_dev_to_dev(pdev);
	451	INIT_LIST_HEAD(&probe_ent->node);
	452
	453	probe_ent->sht = &svia_sht;
cca3974e	454	probe_ent->port_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY;
ac2164d5	455	probe_ent->port_ops = &vt6421_sata_ops;
1da177e4 LT	456	probe_ent->n_ports = N_PORTS;
1da177e4 LT	457	probe_ent->irq = pdev->irq;
1d6f359a	458	probe_ent->irq_flags = IRQF_SHARED;
1da177e4 LT	459	probe_ent->pio_mask = 0x1f;
	460	probe_ent->mwdma_mask = 0x07;
	461	probe_ent->udma_mask = 0x7f;
	462
	463	for (i = 0; i < N_PORTS; i++)
0d5ff566	464	vt6421_init_addrs(probe_ent, pcim_iomap_table(pdev), i);
1da177e4 LT	465
	466	return probe_ent;
	467	}
	468
	469	static void svia_configure(struct pci_dev *pdev)
	470	{
	471	u8 tmp8;
	472
	473	pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
a9524a76	474	dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
1da177e4 LT	475	(int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
	476
	477	/* make sure SATA channels are enabled */
	478	pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
	479	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
a9524a76 JG	480	dev_printk(KERN_DEBUG, &pdev->dev,
	481	"enabling SATA channels (0x%x)\n",
	482	(int) tmp8);
1da177e4 LT	483	tmp8 \|= ALL_PORTS;
	484	pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
	485	}
	486
	487	/* make sure interrupts for each channel sent to us */
	488	pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
	489	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
a9524a76 JG	490	dev_printk(KERN_DEBUG, &pdev->dev,
	491	"enabling SATA channel interrupts (0x%x)\n",
	492	(int) tmp8);
1da177e4 LT	493	tmp8 \|= ALL_PORTS;
	494	pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
	495	}
	496
	497	/* make sure native mode is enabled */
	498	pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
	499	if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
a9524a76 JG	500	dev_printk(KERN_DEBUG, &pdev->dev,
	501	"enabling SATA channel native mode (0x%x)\n",
	502	(int) tmp8);
1da177e4 LT	503	tmp8 \|= NATIVE_MODE_ALL;
	504	pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
	505	}
	506	}
	507
	508	static int svia_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	509	{
	510	static int printed_version;
	511	unsigned int i;
	512	int rc;
	513	struct ata_probe_ent *probe_ent;
	514	int board_id = (int) ent->driver_data;
	515	const int *bar_sizes;
1da177e4 LT	516	u8 tmp8;
	517
	518	if (!printed_version++)
a9524a76	519	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4	520
24dc5f33	521	rc = pcim_enable_device(pdev);
1da177e4 LT	522	if (rc)
	523	return rc;
	524
0d5ff566	525	rc = pcim_iomap_regions(pdev, 0x1f, DRV_NAME);
1da177e4	526	if (rc) {
24dc5f33 TH	527	pcim_pin_device(pdev);
24dc5f33 TH	528	return rc;
1da177e4 LT	529	}
	530
	531	if (board_id == vt6420) {
	532	pci_read_config_byte(pdev, SATA_PATA_SHARING, &tmp8);
	533	if (tmp8 & SATA_2DEV) {
a9524a76 JG	534	dev_printk(KERN_ERR, &pdev->dev,
	535	"SATA master/slave not supported (0x%x)\n",
	536	(int) tmp8);
24dc5f33	537	return -EIO;
1da177e4 LT	538	}
	539
	540	bar_sizes = &svia_bar_sizes[0];
	541	} else {
	542	bar_sizes = &vt6421_bar_sizes[0];
	543	}
	544
	545	for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
	546	if ((pci_resource_start(pdev, i) == 0) \|\|
	547	(pci_resource_len(pdev, i) < bar_sizes[i])) {
a9524a76	548	dev_printk(KERN_ERR, &pdev->dev,
e29419ff GKH	549	"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
	550	i,
	551	(unsigned long long)pci_resource_start(pdev, i),
	552	(unsigned long long)pci_resource_len(pdev, i));
24dc5f33	553	return -ENODEV;
1da177e4 LT	554	}
	555
	556	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	557	if (rc)
24dc5f33	558	return rc;
1da177e4 LT	559	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1da177e4 LT	560	if (rc)
24dc5f33	561	return rc;
1da177e4 LT	562
	563	if (board_id == vt6420)
	564	probe_ent = vt6420_init_probe_ent(pdev);
	565	else
	566	probe_ent = vt6421_init_probe_ent(pdev);
8a60a071	567
1da177e4	568	if (!probe_ent) {
a9524a76	569	dev_printk(KERN_ERR, &pdev->dev, "out of memory\n");
24dc5f33	570	return -ENOMEM;
1da177e4 LT	571	}
	572
	573	svia_configure(pdev);
	574
	575	pci_set_master(pdev);
	576
24dc5f33 TH	577	if (!ata_device_add(probe_ent))
24dc5f33 TH	578	return -ENODEV;
1da177e4	579
24dc5f33	580	devm_kfree(&pdev->dev, probe_ent);
1da177e4	581	return 0;
1da177e4 LT	582	}
	583
	584	static int __init svia_init(void)
	585	{
b7887196	586	return pci_register_driver(&svia_pci_driver);
1da177e4 LT	587	}
	588
	589	static void __exit svia_exit(void)
	590	{
	591	pci_unregister_driver(&svia_pci_driver);
	592	}
	593
	594	module_init(svia_init);
	595	module_exit(svia_exit);