[deliverable/linux.git] / drivers / ata / sata_via.c

/*
 *  sata_via.c - VIA Serial ATA controllers
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 * 		   Please ALWAYS copy linux-ide@vger.kernel.org
 *		   on emails.
 *
 *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
 *  Copyright 2003-2004 Jeff Garzik
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 *
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_via"
#define DRV_VERSION	"2.3"

enum board_ids_enum {
	vt6420,
	vt6421,
};

enum {
	SATA_CHAN_ENAB		= 0x40, /* SATA channel enable */
	SATA_INT_GATE		= 0x41, /* SATA interrupt gating */
	SATA_NATIVE_MODE	= 0x42, /* Native mode enable */
	PATA_UDMA_TIMING	= 0xB3, /* PATA timing for DMA/ cable detect */
	PATA_PIO_TIMING		= 0xAB, /* PATA timing register */

	PORT0			= (1 << 1),
	PORT1			= (1 << 0),
	ALL_PORTS		= PORT0 | PORT1,

	NATIVE_MODE_ALL		= (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),

	SATA_EXT_PHY		= (1 << 6), /* 0==use PATA, 1==ext phy */
};

static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
static void svia_noop_freeze(struct ata_port *ap);
static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
static int vt6421_pata_cable_detect(struct ata_port *ap);
static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);

static const struct pci_device_id svia_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
	{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
	{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
	{ PCI_VDEVICE(VIA, 0x3249), vt6421 },
	{ PCI_VDEVICE(VIA, 0x5287), vt6420 },
	{ PCI_VDEVICE(VIA, 0x5372), vt6420 },
	{ PCI_VDEVICE(VIA, 0x7372), vt6420 },

	{ }	/* terminate list */
};

static struct pci_driver svia_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= svia_pci_tbl,
	.probe			= svia_init_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template svia_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations vt6420_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.freeze			= svia_noop_freeze,
	.prereset		= vt6420_prereset,
};

static struct ata_port_operations vt6421_pata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= vt6421_pata_cable_detect,
	.set_piomode		= vt6421_set_pio_mode,
	.set_dmamode		= vt6421_set_dma_mode,
};

static struct ata_port_operations vt6421_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.scr_read		= svia_scr_read,
	.scr_write		= svia_scr_write,
};

static const struct ata_port_info vt6420_port_info = {
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x07,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &vt6420_sata_ops,
};

static struct ata_port_info vt6421_sport_info = {
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x07,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &vt6421_sata_ops,
};

static struct ata_port_info vt6421_pport_info = {
	.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &vt6421_pata_ops,
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = ioread32(ap->ioaddr.scr_addr + (4 * sc_reg));
	return 0;
}

static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
	return 0;
}

static void svia_noop_freeze(struct ata_port *ap)
{
	/* Some VIA controllers choke if ATA_NIEN is manipulated in
	 * certain way.  Leave it alone and just clear pending IRQ.
	 */
	ap->ops->sff_check_status(ap);
	ata_sff_irq_clear(ap);
}

/**
 *	vt6420_prereset - prereset for vt6420
 *	@link: target ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	SCR registers on vt6420 are pieces of shit and may hang the
 *	whole machine completely if accessed with the wrong timing.
 *	To avoid such catastrophe, vt6420 doesn't provide generic SCR
 *	access operations, but uses SStatus and SControl only during
 *	boot probing in controlled way.
 *
 *	As the old (pre EH update) probing code is proven to work, we
 *	strictly follow the access pattern.
 *
 *	LOCKING:
 *	Kernel thread context (may sleep)
 *
 *	RETURNS:
 *	0 on success, -errno otherwise.
 */
static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ata_eh_context *ehc = &ap->link.eh_context;
	unsigned long timeout = jiffies + (HZ * 5);
	u32 sstatus, scontrol;
	int online;

	/* don't do any SCR stuff if we're not loading */
	if (!(ap->pflags & ATA_PFLAG_LOADING))
		goto skip_scr;

	/* Resume phy.  This is the old SATA resume sequence */
	svia_scr_write(ap, SCR_CONTROL, 0x300);
	svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */

	/* wait for phy to become ready, if necessary */
	do {
		msleep(200);
		svia_scr_read(ap, SCR_STATUS, &sstatus);
		if ((sstatus & 0xf) != 1)
			break;
	} while (time_before(jiffies, timeout));

	/* open code sata_print_link_status() */
	svia_scr_read(ap, SCR_STATUS, &sstatus);
	svia_scr_read(ap, SCR_CONTROL, &scontrol);

	online = (sstatus & 0xf) == 0x3;

	ata_port_printk(ap, KERN_INFO,
			"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
			online ? "up" : "down", sstatus, scontrol);

	/* SStatus is read one more time */
	svia_scr_read(ap, SCR_STATUS, &sstatus);

	if (!online) {
		/* tell EH to bail */
		ehc->i.action &= ~ATA_EH_RESET;
		return 0;
	}

 skip_scr:
	/* wait for !BSY */
	ata_sff_wait_ready(link, deadline);

	return 0;
}

static int vt6421_pata_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;

	pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
	if (tmp & 0x10)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
	pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
}

static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
	pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]);
}

static const unsigned int svia_bar_sizes[] = {
	8, 4, 8, 4, 16, 256
};

static const unsigned int vt6421_bar_sizes[] = {
	16, 16, 16, 16, 32, 128
};

static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
{
	return addr + (port * 128);
}

static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
{
	return addr + (port * 64);
}

static void vt6421_init_addrs(struct ata_port *ap)
{
	void __iomem * const * iomap = ap->host->iomap;
	void __iomem *reg_addr = iomap[ap->port_no];
	void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
	struct ata_ioports *ioaddr = &ap->ioaddr;

	ioaddr->cmd_addr = reg_addr;
	ioaddr->altstatus_addr =
	ioaddr->ctl_addr = (void __iomem *)
		((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
	ioaddr->bmdma_addr = bmdma_addr;
	ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);

	ata_sff_std_ports(ioaddr);

	ata_port_pbar_desc(ap, ap->port_no, -1, "port");
	ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
}

static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
{
	const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
	struct ata_host *host;
	int rc;

	rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
	if (rc)
		return rc;
	*r_host = host;

	rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
	if (rc) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n");
		return rc;
	}

	host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
	host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);

	return 0;
}

static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
{
	const struct ata_port_info *ppi[] =
		{ &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
	struct ata_host *host;
	int i, rc;

	*r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
	if (!host) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
		return -ENOMEM;
	}

	rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
	if (rc) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap "
			   "PCI BARs (errno=%d)\n", rc);
		return rc;
	}
	host->iomap = pcim_iomap_table(pdev);

	for (i = 0; i < host->n_ports; i++)
		vt6421_init_addrs(host->ports[i]);

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	return 0;
}

static void svia_configure(struct pci_dev *pdev)
{
	u8 tmp8;

	pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
	dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
	       (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);

	/* make sure SATA channels are enabled */
	pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channels (0x%x)\n",
			   (int) tmp8);
		tmp8 |= ALL_PORTS;
		pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
	}

	/* make sure interrupts for each channel sent to us */
	pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channel interrupts (0x%x)\n",
			   (int) tmp8);
		tmp8 |= ALL_PORTS;
		pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
	}

	/* make sure native mode is enabled */
	pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
	if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channel native mode (0x%x)\n",
			   (int) tmp8);
		tmp8 |= NATIVE_MODE_ALL;
		pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
	}
}

static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	unsigned int i;
	int rc;
	struct ata_host *host;
	int board_id = (int) ent->driver_data;
	const unsigned *bar_sizes;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (board_id == vt6420)
		bar_sizes = &svia_bar_sizes[0];
	else
		bar_sizes = &vt6421_bar_sizes[0];

	for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
		if ((pci_resource_start(pdev, i) == 0) ||
		    (pci_resource_len(pdev, i) < bar_sizes[i])) {
			dev_printk(KERN_ERR, &pdev->dev,
				"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
				i,
				(unsigned long long)pci_resource_start(pdev, i),
				(unsigned long long)pci_resource_len(pdev, i));
			return -ENODEV;
		}

	if (board_id == vt6420)
		rc = vt6420_prepare_host(pdev, &host);
	else
		rc = vt6421_prepare_host(pdev, &host);
	if (rc)
		return rc;

	svia_configure(pdev);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
				 IRQF_SHARED, &svia_sht);
}

static int __init svia_init(void)
{
	return pci_register_driver(&svia_pci_driver);
}

static void __exit svia_exit(void)
{
	pci_unregister_driver(&svia_pci_driver);
}

module_init(svia_init);
module_exit(svia_exit);
Commit	Line	Data
1da177e4	1	/*
af36d7f0 JG	2	* sata_via.c - VIA Serial ATA controllers
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
5796d1c4	6	* on emails.
af36d7f0 JG	7	*
	8	* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
	9	* Copyright 2003-2004 Jeff Garzik
	10	*
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2, or (at your option)
	15	* any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; see the file COPYING. If not, write to
	24	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
	26	*
	27	* libata documentation is available via 'make {ps\|pdf}docs',
	28	* as Documentation/DocBook/libata.*
	29	*
	30	* Hardware documentation available under NDA.
	31	*
	32	*
af36d7f0	33	*
1da177e4 LT	34	*/
	35
	36	#include <linux/kernel.h>
	37	#include <linux/module.h>
	38	#include <linux/pci.h>
	39	#include <linux/init.h>
	40	#include <linux/blkdev.h>
	41	#include <linux/delay.h>
a9524a76	42	#include <linux/device.h>
1da177e4 LT	43	#include <scsi/scsi_host.h>
1da177e4 LT	44	#include <linux/libata.h>
1da177e4 LT	45
1da177e4 LT	46	#define DRV_NAME "sata_via"
2a3103ce	47	#define DRV_VERSION "2.3"
1da177e4 LT	48
	49	enum board_ids_enum {
	50	vt6420,
	51	vt6421,
	52	};
	53
	54	enum {
	55	SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
	56	SATA_INT_GATE = 0x41, /* SATA interrupt gating */
	57	SATA_NATIVE_MODE = 0x42, /* Native mode enable */
d73f30e1 A	58	PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
d73f30e1 A	59	PATA_PIO_TIMING = 0xAB, /* PATA timing register */
a84471fe	60
1da177e4 LT	61	PORT0 = (1 << 1),
	62	PORT1 = (1 << 0),
	63	ALL_PORTS = PORT0 \| PORT1,
1da177e4 LT	64
	65	NATIVE_MODE_ALL = (1 << 7) \| (1 << 6) \| (1 << 5) \| (1 << 4),
	66
	67	SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
1da177e4 LT	68	};
1da177e4 LT	69
5796d1c4	70	static int svia_init_one(struct pci_dev pdev, const struct pci_device_id ent);
da3dbb17 TH	71	static int svia_scr_read(struct ata_port ap, unsigned int sc_reg, u32 val);
da3dbb17 TH	72	static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
17234246	73	static void svia_noop_freeze(struct ata_port *ap);
a1efdaba	74	static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
a0fcdc02	75	static int vt6421_pata_cable_detect(struct ata_port *ap);
d73f30e1 A	76	static void vt6421_set_pio_mode(struct ata_port ap, struct ata_device adev);
d73f30e1 A	77	static void vt6421_set_dma_mode(struct ata_port ap, struct ata_device adev);
1da177e4	78
3b7d697d	79	static const struct pci_device_id svia_pci_tbl[] = {
96bc103f	80	{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
2d2744fc JG	81	{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
	82	{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
	83	{ PCI_VDEVICE(VIA, 0x3249), vt6421 },
52df0ee0 JG	84	{ PCI_VDEVICE(VIA, 0x5287), vt6420 },
	85	{ PCI_VDEVICE(VIA, 0x5372), vt6420 },
	86	{ PCI_VDEVICE(VIA, 0x7372), vt6420 },
1da177e4 LT	87
	88	{ } /* terminate list */
	89	};
	90
	91	static struct pci_driver svia_pci_driver = {
	92	.name = DRV_NAME,
	93	.id_table = svia_pci_tbl,
	94	.probe = svia_init_one,
e1e143cf TH	95	#ifdef CONFIG_PM
	96	.suspend = ata_pci_device_suspend,
	97	.resume = ata_pci_device_resume,
	98	#endif
1da177e4 LT	99	.remove = ata_pci_remove_one,
	100	};
	101
193515d5	102	static struct scsi_host_template svia_sht = {
68d1d07b	103	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	104	};
1da177e4 LT	105
029cfd6b TH	106	static struct ata_port_operations vt6420_sata_ops = {
029cfd6b TH	107	.inherits = &ata_bmdma_port_ops,
17234246	108	.freeze = svia_noop_freeze,
a1efdaba	109	.prereset = vt6420_prereset,
ac2164d5 TH	110	};
ac2164d5 TH	111
029cfd6b TH	112	static struct ata_port_operations vt6421_pata_ops = {
	113	.inherits = &ata_bmdma_port_ops,
	114	.cable_detect = vt6421_pata_cable_detect,
d73f30e1 A	115	.set_piomode = vt6421_set_pio_mode,
d73f30e1 A	116	.set_dmamode = vt6421_set_dma_mode,
d73f30e1 A	117	};
d73f30e1 A	118
029cfd6b TH	119	static struct ata_port_operations vt6421_sata_ops = {
029cfd6b TH	120	.inherits = &ata_bmdma_port_ops,
1da177e4 LT	121	.scr_read = svia_scr_read,
1da177e4 LT	122	.scr_write = svia_scr_write,
1da177e4 LT	123	};
1da177e4 LT	124
eca25dca	125	static const struct ata_port_info vt6420_port_info = {
cca3974e	126	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
1da177e4 LT	127	.pio_mask = 0x1f,
1da177e4 LT	128	.mwdma_mask = 0x07,
bf6263a8	129	.udma_mask = ATA_UDMA6,
ac2164d5	130	.port_ops = &vt6420_sata_ops,
1da177e4 LT	131	};
1da177e4 LT	132
eca25dca TH	133	static struct ata_port_info vt6421_sport_info = {
	134	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
	135	.pio_mask = 0x1f,
	136	.mwdma_mask = 0x07,
bf6263a8	137	.udma_mask = ATA_UDMA6,
eca25dca TH	138	.port_ops = &vt6421_sata_ops,
	139	};
	140
	141	static struct ata_port_info vt6421_pport_info = {
	142	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_NO_LEGACY,
	143	.pio_mask = 0x1f,
	144	.mwdma_mask = 0,
bf6263a8	145	.udma_mask = ATA_UDMA6,
eca25dca TH	146	.port_ops = &vt6421_pata_ops,
	147	};
	148
1da177e4 LT	149	MODULE_AUTHOR("Jeff Garzik");
	150	MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
	151	MODULE_LICENSE("GPL");
	152	MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
	153	MODULE_VERSION(DRV_VERSION);
	154
da3dbb17	155	static int svia_scr_read(struct ata_port ap, unsigned int sc_reg, u32 val)
1da177e4 LT	156	{
1da177e4 LT	157	if (sc_reg > SCR_CONTROL)
da3dbb17 TH	158	return -EINVAL;
	159	val = ioread32(ap->ioaddr.scr_addr + (4 sc_reg));
	160	return 0;
1da177e4 LT	161	}
1da177e4 LT	162
da3dbb17	163	static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4 LT	164	{
1da177e4 LT	165	if (sc_reg > SCR_CONTROL)
da3dbb17	166	return -EINVAL;
0d5ff566	167	iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
da3dbb17	168	return 0;
1da177e4 LT	169	}
1da177e4 LT	170
17234246 TH	171	static void svia_noop_freeze(struct ata_port *ap)
	172	{
	173	/* Some VIA controllers choke if ATA_NIEN is manipulated in
	174	* certain way. Leave it alone and just clear pending IRQ.
	175	*/
5682ed33	176	ap->ops->sff_check_status(ap);
9363c382	177	ata_sff_irq_clear(ap);
17234246 TH	178	}
17234246 TH	179
ac2164d5 TH	180	/**
ac2164d5 TH	181	* vt6420_prereset - prereset for vt6420
cc0680a5	182	* @link: target ATA link
d4b2bab4	183	* @deadline: deadline jiffies for the operation
ac2164d5 TH	184	*
	185	* SCR registers on vt6420 are pieces of shit and may hang the
	186	* whole machine completely if accessed with the wrong timing.
	187	* To avoid such catastrophe, vt6420 doesn't provide generic SCR
	188	* access operations, but uses SStatus and SControl only during
	189	* boot probing in controlled way.
	190	*
	191	* As the old (pre EH update) probing code is proven to work, we
	192	* strictly follow the access pattern.
	193	*
	194	* LOCKING:
	195	* Kernel thread context (may sleep)
	196	*
	197	* RETURNS:
	198	* 0 on success, -errno otherwise.
	199	*/
cc0680a5	200	static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
ac2164d5	201	{
cc0680a5	202	struct ata_port *ap = link->ap;
9af5c9c9	203	struct ata_eh_context *ehc = &ap->link.eh_context;
ac2164d5 TH	204	unsigned long timeout = jiffies + (HZ * 5);
	205	u32 sstatus, scontrol;
	206	int online;
	207
	208	/* don't do any SCR stuff if we're not loading */
68ff6e8e	209	if (!(ap->pflags & ATA_PFLAG_LOADING))
ac2164d5 TH	210	goto skip_scr;
ac2164d5 TH	211
a09060ff	212	/* Resume phy. This is the old SATA resume sequence */
ac2164d5	213	svia_scr_write(ap, SCR_CONTROL, 0x300);
da3dbb17	214	svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */
ac2164d5 TH	215
	216	/* wait for phy to become ready, if necessary */
	217	do {
	218	msleep(200);
da3dbb17 TH	219	svia_scr_read(ap, SCR_STATUS, &sstatus);
da3dbb17 TH	220	if ((sstatus & 0xf) != 1)
ac2164d5 TH	221	break;
	222	} while (time_before(jiffies, timeout));
	223
	224	/* open code sata_print_link_status() */
da3dbb17 TH	225	svia_scr_read(ap, SCR_STATUS, &sstatus);
da3dbb17 TH	226	svia_scr_read(ap, SCR_CONTROL, &scontrol);
ac2164d5 TH	227
	228	online = (sstatus & 0xf) == 0x3;
	229
	230	ata_port_printk(ap, KERN_INFO,
	231	"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
	232	online ? "up" : "down", sstatus, scontrol);
	233
	234	/* SStatus is read one more time */
da3dbb17	235	svia_scr_read(ap, SCR_STATUS, &sstatus);
ac2164d5 TH	236
	237	if (!online) {
	238	/* tell EH to bail */
cf480626	239	ehc->i.action &= ~ATA_EH_RESET;
ac2164d5 TH	240	return 0;
	241	}
	242
	243	skip_scr:
	244	/* wait for !BSY */
705e76be	245	ata_sff_wait_ready(link, deadline);
ac2164d5 TH	246
	247	return 0;
	248	}
	249
a0fcdc02	250	static int vt6421_pata_cable_detect(struct ata_port *ap)
d73f30e1 A	251	{
	252	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	253	u8 tmp;
	254
	255	pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
	256	if (tmp & 0x10)
a0fcdc02 JG	257	return ATA_CBL_PATA40;
a0fcdc02 JG	258	return ATA_CBL_PATA80;
d73f30e1 A	259	}
	260
	261	static void vt6421_set_pio_mode(struct ata_port ap, struct ata_device adev)
	262	{
	263	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	264	static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
	265	pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
	266	}
	267
	268	static void vt6421_set_dma_mode(struct ata_port ap, struct ata_device adev)
	269	{
	270	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	271	static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
b4154d4a	272	pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]);
d73f30e1 A	273	}
d73f30e1 A	274
1da177e4 LT	275	static const unsigned int svia_bar_sizes[] = {
	276	8, 4, 8, 4, 16, 256
	277	};
	278
	279	static const unsigned int vt6421_bar_sizes[] = {
	280	16, 16, 16, 16, 32, 128
	281	};
	282
5796d1c4	283	static void __iomem svia_scr_addr(void __iomem addr, unsigned int port)
1da177e4 LT	284	{
	285	return addr + (port * 128);
	286	}
	287
5796d1c4	288	static void __iomem vt6421_scr_addr(void __iomem addr, unsigned int port)
1da177e4 LT	289	{
	290	return addr + (port * 64);
	291	}
	292
eca25dca	293	static void vt6421_init_addrs(struct ata_port *ap)
1da177e4	294	{
eca25dca TH	295	void __iomem * const * iomap = ap->host->iomap;
	296	void __iomem *reg_addr = iomap[ap->port_no];
	297	void __iomem bmdma_addr = iomap[4] + (ap->port_no 8);
	298	struct ata_ioports *ioaddr = &ap->ioaddr;
	299
	300	ioaddr->cmd_addr = reg_addr;
	301	ioaddr->altstatus_addr =
	302	ioaddr->ctl_addr = (void __iomem *)
0d5ff566	303	((unsigned long)(reg_addr + 8) \| ATA_PCI_CTL_OFS);
eca25dca TH	304	ioaddr->bmdma_addr = bmdma_addr;
eca25dca TH	305	ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
1da177e4	306
9363c382	307	ata_sff_std_ports(ioaddr);
cbcdd875 TH	308
	309	ata_port_pbar_desc(ap, ap->port_no, -1, "port");
	310	ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
1da177e4 LT	311	}
1da177e4 LT	312
eca25dca	313	static int vt6420_prepare_host(struct pci_dev pdev, struct ata_host *r_host)
1da177e4	314	{
eca25dca TH	315	const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
	316	struct ata_host *host;
	317	int rc;
f20b16ff	318
9363c382	319	rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
eca25dca TH	320	if (rc)
	321	return rc;
	322	*r_host = host;
1da177e4	323
eca25dca TH	324	rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
eca25dca TH	325	if (rc) {
e1be5d73	326	dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n");
eca25dca	327	return rc;
e1be5d73 TH	328	}
e1be5d73 TH	329
eca25dca TH	330	host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
eca25dca TH	331	host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
1da177e4	332
eca25dca	333	return 0;
1da177e4 LT	334	}
1da177e4 LT	335
eca25dca	336	static int vt6421_prepare_host(struct pci_dev pdev, struct ata_host *r_host)
1da177e4	337	{
eca25dca TH	338	const struct ata_port_info *ppi[] =
	339	{ &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
	340	struct ata_host *host;
	341	int i, rc;
	342
	343	*r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
	344	if (!host) {
	345	dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
	346	return -ENOMEM;
	347	}
1da177e4	348
8fd7d1b1	349	rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
eca25dca TH	350	if (rc) {
	351	dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap "
	352	"PCI BARs (errno=%d)\n", rc);
	353	return rc;
	354	}
	355	host->iomap = pcim_iomap_table(pdev);
e1be5d73	356
eca25dca TH	357	for (i = 0; i < host->n_ports; i++)
eca25dca TH	358	vt6421_init_addrs(host->ports[i]);
1da177e4	359
eca25dca TH	360	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	361	if (rc)
	362	return rc;
	363	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	364	if (rc)
	365	return rc;
	366
	367	return 0;
1da177e4 LT	368	}
	369
	370	static void svia_configure(struct pci_dev *pdev)
	371	{
	372	u8 tmp8;
	373
	374	pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
a9524a76	375	dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
1da177e4 LT	376	(int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
	377
	378	/* make sure SATA channels are enabled */
	379	pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
	380	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
a9524a76 JG	381	dev_printk(KERN_DEBUG, &pdev->dev,
a9524a76 JG	382	"enabling SATA channels (0x%x)\n",
5796d1c4	383	(int) tmp8);
1da177e4 LT	384	tmp8 \|= ALL_PORTS;
	385	pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
	386	}
	387
	388	/* make sure interrupts for each channel sent to us */
	389	pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
	390	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
a9524a76 JG	391	dev_printk(KERN_DEBUG, &pdev->dev,
a9524a76 JG	392	"enabling SATA channel interrupts (0x%x)\n",
5796d1c4	393	(int) tmp8);
1da177e4 LT	394	tmp8 \|= ALL_PORTS;
	395	pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
	396	}
	397
	398	/* make sure native mode is enabled */
	399	pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
	400	if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
a9524a76 JG	401	dev_printk(KERN_DEBUG, &pdev->dev,
a9524a76 JG	402	"enabling SATA channel native mode (0x%x)\n",
5796d1c4	403	(int) tmp8);
1da177e4 LT	404	tmp8 \|= NATIVE_MODE_ALL;
	405	pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
	406	}
	407	}
	408
5796d1c4	409	static int svia_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4 LT	410	{
	411	static int printed_version;
	412	unsigned int i;
	413	int rc;
eca25dca	414	struct ata_host *host;
1da177e4	415	int board_id = (int) ent->driver_data;
b4482a4b	416	const unsigned *bar_sizes;
1da177e4 LT	417
1da177e4 LT	418	if (!printed_version++)
a9524a76	419	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4	420
24dc5f33	421	rc = pcim_enable_device(pdev);
1da177e4 LT	422	if (rc)
	423	return rc;
	424
b6d6c746	425	if (board_id == vt6420)
1da177e4	426	bar_sizes = &svia_bar_sizes[0];
b6d6c746	427	else
1da177e4	428	bar_sizes = &vt6421_bar_sizes[0];
1da177e4 LT	429
	430	for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
	431	if ((pci_resource_start(pdev, i) == 0) \|\|
	432	(pci_resource_len(pdev, i) < bar_sizes[i])) {
a9524a76	433	dev_printk(KERN_ERR, &pdev->dev,
e29419ff GKH	434	"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
e29419ff GKH	435	i,
5796d1c4 JG	436	(unsigned long long)pci_resource_start(pdev, i),
5796d1c4 JG	437	(unsigned long long)pci_resource_len(pdev, i));
24dc5f33	438	return -ENODEV;
1da177e4 LT	439	}
1da177e4 LT	440
1da177e4	441	if (board_id == vt6420)
eca25dca	442	rc = vt6420_prepare_host(pdev, &host);
1da177e4	443	else
eca25dca TH	444	rc = vt6421_prepare_host(pdev, &host);
	445	if (rc)
	446	return rc;
1da177e4 LT	447
	448	svia_configure(pdev);
	449
	450	pci_set_master(pdev);
9363c382 TH	451	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
9363c382 TH	452	IRQF_SHARED, &svia_sht);
1da177e4 LT	453	}
	454
	455	static int __init svia_init(void)
	456	{
b7887196	457	return pci_register_driver(&svia_pci_driver);
1da177e4 LT	458	}
	459
	460	static void __exit svia_exit(void)
	461	{
	462	pci_unregister_driver(&svia_pci_driver);
	463	}
	464
	465	module_init(svia_init);
	466	module_exit(svia_exit);