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1da177e4 LT |
1 | /****************************************************************************** |
2 | * | |
3 | * nicstar.h | |
4 | * | |
5 | * Header file for the nicstar device driver. | |
6 | * | |
7 | * Author: Rui Prior (rprior@inescn.pt) | |
8 | * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 | |
9 | * | |
10 | * (C) INESC 1998 | |
11 | * | |
12 | ******************************************************************************/ | |
13 | ||
14 | ||
15 | #ifndef _LINUX_NICSTAR_H_ | |
16 | #define _LINUX_NICSTAR_H_ | |
17 | ||
18 | ||
19 | /* Includes *******************************************************************/ | |
20 | ||
21 | #include <linux/types.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/uio.h> | |
24 | #include <linux/skbuff.h> | |
25 | #include <linux/atmdev.h> | |
26 | #include <linux/atm_nicstar.h> | |
27 | ||
28 | ||
29 | /* Options ********************************************************************/ | |
30 | ||
31 | #undef NS_DEBUG_SPINLOCKS | |
32 | ||
33 | #define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards | |
34 | controlled by the device driver. Must | |
35 | be <= 5 */ | |
36 | ||
37 | #undef RCQ_SUPPORT /* Do not define this for now */ | |
38 | ||
39 | #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */ | |
40 | #define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */ | |
41 | ||
42 | #define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */ | |
43 | #define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */ | |
44 | #define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */ | |
45 | #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */ | |
46 | ||
47 | #define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384. | |
48 | Define 4096 only if (all) your card(s) | |
49 | have 32K x 32bit SRAM, in which case | |
50 | setting this to 16384 will just waste a | |
51 | lot of memory. | |
52 | Setting this to 4096 for a card with | |
53 | 128K x 32bit SRAM will limit the maximum | |
54 | VCI. */ | |
55 | ||
56 | /*#define NS_PCI_LATENCY 64*/ /* Must be a multiple of 32 */ | |
57 | ||
58 | /* Number of buffers initially allocated */ | |
59 | #define NUM_SB 32 /* Must be even */ | |
60 | #define NUM_LB 24 /* Must be even */ | |
61 | #define NUM_HB 8 /* Pre-allocated huge buffers */ | |
62 | #define NUM_IOVB 48 /* Iovec buffers */ | |
63 | ||
64 | /* Lower level for count of buffers */ | |
65 | #define MIN_SB 8 /* Must be even */ | |
66 | #define MIN_LB 8 /* Must be even */ | |
67 | #define MIN_HB 6 | |
68 | #define MIN_IOVB 8 | |
69 | ||
70 | /* Upper level for count of buffers */ | |
71 | #define MAX_SB 64 /* Must be even, <= 508 */ | |
72 | #define MAX_LB 48 /* Must be even, <= 508 */ | |
73 | #define MAX_HB 10 | |
74 | #define MAX_IOVB 80 | |
75 | ||
76 | /* These are the absolute maximum allowed for the ioctl() */ | |
77 | #define TOP_SB 256 /* Must be even, <= 508 */ | |
78 | #define TOP_LB 128 /* Must be even, <= 508 */ | |
79 | #define TOP_HB 64 | |
80 | #define TOP_IOVB 256 | |
81 | ||
82 | ||
83 | #define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */ | |
84 | #define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */ | |
85 | ||
86 | #undef ENABLE_TSQFIE | |
87 | ||
88 | #define SCQFULL_TIMEOUT (5 * HZ) | |
89 | ||
90 | #define NS_POLL_PERIOD (HZ) | |
91 | ||
92 | #define PCR_TOLERANCE (1.0001) | |
93 | ||
94 | ||
95 | ||
96 | /* ESI stuff ******************************************************************/ | |
97 | ||
98 | #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C | |
99 | #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6 | |
100 | ||
101 | ||
102 | /* #defines *******************************************************************/ | |
103 | ||
104 | #define NS_IOREMAP_SIZE 4096 | |
105 | ||
106 | #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */ | |
107 | #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */ | |
108 | ||
109 | #define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */ | |
110 | #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \ | |
111 | (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48))) | |
112 | #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec))) | |
113 | ||
114 | #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48) | |
115 | #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48) | |
116 | ||
117 | #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */ | |
118 | ||
119 | #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER) | |
120 | #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE) | |
121 | ||
122 | ||
123 | /* NICStAR structures located in host memory **********************************/ | |
124 | ||
125 | ||
126 | ||
127 | /* RSQ - Receive Status Queue | |
128 | * | |
129 | * Written by the NICStAR, read by the device driver. | |
130 | */ | |
131 | ||
132 | typedef struct ns_rsqe | |
133 | { | |
134 | u32 word_1; | |
135 | u32 buffer_handle; | |
136 | u32 final_aal5_crc32; | |
137 | u32 word_4; | |
138 | } ns_rsqe; | |
139 | ||
140 | #define ns_rsqe_vpi(ns_rsqep) \ | |
141 | ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16) | |
142 | #define ns_rsqe_vci(ns_rsqep) \ | |
143 | (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF) | |
144 | ||
145 | #define NS_RSQE_VALID 0x80000000 | |
146 | #define NS_RSQE_NZGFC 0x00004000 | |
147 | #define NS_RSQE_EOPDU 0x00002000 | |
148 | #define NS_RSQE_BUFSIZE 0x00001000 | |
149 | #define NS_RSQE_CONGESTION 0x00000800 | |
150 | #define NS_RSQE_CLP 0x00000400 | |
151 | #define NS_RSQE_CRCERR 0x00000200 | |
152 | ||
153 | #define NS_RSQE_BUFSIZE_SM 0x00000000 | |
154 | #define NS_RSQE_BUFSIZE_LG 0x00001000 | |
155 | ||
156 | #define ns_rsqe_valid(ns_rsqep) \ | |
157 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID) | |
158 | #define ns_rsqe_nzgfc(ns_rsqep) \ | |
159 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC) | |
160 | #define ns_rsqe_eopdu(ns_rsqep) \ | |
161 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU) | |
162 | #define ns_rsqe_bufsize(ns_rsqep) \ | |
163 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE) | |
164 | #define ns_rsqe_congestion(ns_rsqep) \ | |
165 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION) | |
166 | #define ns_rsqe_clp(ns_rsqep) \ | |
167 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP) | |
168 | #define ns_rsqe_crcerr(ns_rsqep) \ | |
169 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR) | |
170 | ||
171 | #define ns_rsqe_cellcount(ns_rsqep) \ | |
172 | (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF) | |
173 | #define ns_rsqe_init(ns_rsqep) \ | |
174 | ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000)) | |
175 | ||
176 | #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16) | |
177 | #define NS_RSQ_ALIGNMENT NS_RSQSIZE | |
178 | ||
179 | ||
180 | ||
181 | /* RCQ - Raw Cell Queue | |
182 | * | |
183 | * Written by the NICStAR, read by the device driver. | |
184 | */ | |
185 | ||
186 | typedef struct cell_payload | |
187 | { | |
188 | u32 word[12]; | |
189 | } cell_payload; | |
190 | ||
191 | typedef struct ns_rcqe | |
192 | { | |
193 | u32 word_1; | |
194 | u32 word_2; | |
195 | u32 word_3; | |
196 | u32 word_4; | |
197 | cell_payload payload; | |
198 | } ns_rcqe; | |
199 | ||
200 | #define NS_RCQE_SIZE 64 /* bytes */ | |
201 | ||
202 | #define ns_rcqe_islast(ns_rcqep) \ | |
203 | (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000) | |
204 | #define ns_rcqe_cellheader(ns_rcqep) \ | |
205 | (le32_to_cpu((ns_rcqep)->word_1)) | |
206 | #define ns_rcqe_nextbufhandle(ns_rcqep) \ | |
207 | (le32_to_cpu((ns_rcqep)->word_2)) | |
208 | ||
209 | ||
210 | ||
211 | /* SCQ - Segmentation Channel Queue | |
212 | * | |
213 | * Written by the device driver, read by the NICStAR. | |
214 | */ | |
215 | ||
216 | typedef struct ns_scqe | |
217 | { | |
218 | u32 word_1; | |
219 | u32 word_2; | |
220 | u32 word_3; | |
221 | u32 word_4; | |
222 | } ns_scqe; | |
223 | ||
224 | /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors) | |
225 | or TSR (Transmit Status Requests) */ | |
226 | ||
227 | #define NS_SCQE_TYPE_TBD 0x00000000 | |
228 | #define NS_SCQE_TYPE_TSR 0x80000000 | |
229 | ||
230 | ||
231 | #define NS_TBD_EOPDU 0x40000000 | |
232 | #define NS_TBD_AAL0 0x00000000 | |
233 | #define NS_TBD_AAL34 0x04000000 | |
234 | #define NS_TBD_AAL5 0x08000000 | |
235 | ||
236 | #define NS_TBD_VPI_MASK 0x0FF00000 | |
237 | #define NS_TBD_VCI_MASK 0x000FFFF0 | |
238 | #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK) | |
239 | ||
240 | #define NS_TBD_VPI_SHIFT 20 | |
241 | #define NS_TBD_VCI_SHIFT 4 | |
242 | ||
243 | #define ns_tbd_mkword_1(flags, m, n, buflen) \ | |
244 | (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen))) | |
245 | #define ns_tbd_mkword_1_novbr(flags, buflen) \ | |
246 | (cpu_to_le32((flags) | (buflen) | 0x00810000)) | |
247 | #define ns_tbd_mkword_3(control, pdulen) \ | |
248 | (cpu_to_le32((control) << 16 | (pdulen))) | |
249 | #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \ | |
250 | (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp))) | |
251 | ||
252 | ||
253 | #define NS_TSR_INTENABLE 0x20000000 | |
254 | ||
255 | #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */ | |
256 | ||
257 | #define ns_tsr_mkword_1(flags) \ | |
258 | (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags))) | |
259 | #define ns_tsr_mkword_2(scdi, scqi) \ | |
260 | (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi))) | |
261 | ||
262 | #define ns_scqe_is_tsr(ns_scqep) \ | |
263 | (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR) | |
264 | ||
265 | #define VBR_SCQ_NUM_ENTRIES 512 | |
266 | #define VBR_SCQSIZE 8192 | |
267 | #define CBR_SCQ_NUM_ENTRIES 64 | |
268 | #define CBR_SCQSIZE 1024 | |
269 | ||
270 | #define NS_SCQE_SIZE 16 | |
271 | ||
272 | ||
273 | ||
274 | /* TSQ - Transmit Status Queue | |
275 | * | |
276 | * Written by the NICStAR, read by the device driver. | |
277 | */ | |
278 | ||
279 | typedef struct ns_tsi | |
280 | { | |
281 | u32 word_1; | |
282 | u32 word_2; | |
283 | } ns_tsi; | |
284 | ||
285 | /* NOTE: The first word can be a status word copied from the TSR which | |
286 | originated the TSI, or a timer overflow indicator. In this last | |
287 | case, the value of the first word is all zeroes. */ | |
288 | ||
289 | #define NS_TSI_EMPTY 0x80000000 | |
290 | #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF | |
291 | ||
292 | #define ns_tsi_isempty(ns_tsip) \ | |
293 | (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY) | |
294 | #define ns_tsi_gettimestamp(ns_tsip) \ | |
295 | (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK) | |
296 | ||
297 | #define ns_tsi_init(ns_tsip) \ | |
298 | ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY)) | |
299 | ||
300 | ||
301 | #define NS_TSQSIZE 8192 | |
302 | #define NS_TSQ_NUM_ENTRIES 1024 | |
303 | #define NS_TSQ_ALIGNMENT 8192 | |
304 | ||
305 | ||
306 | #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR | |
307 | ||
308 | #define ns_tsi_tmrof(ns_tsip) \ | |
309 | (le32_to_cpu((ns_tsip)->word_1) == 0x00000000) | |
310 | #define ns_tsi_getscdindex(ns_tsip) \ | |
311 | ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16) | |
312 | #define ns_tsi_getscqpos(ns_tsip) \ | |
313 | (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF) | |
314 | ||
315 | ||
316 | ||
317 | /* NICStAR structures located in local SRAM ***********************************/ | |
318 | ||
319 | ||
320 | ||
321 | /* RCT - Receive Connection Table | |
322 | * | |
323 | * Written by both the NICStAR and the device driver. | |
324 | */ | |
325 | ||
326 | typedef struct ns_rcte | |
327 | { | |
328 | u32 word_1; | |
329 | u32 buffer_handle; | |
330 | u32 dma_address; | |
331 | u32 aal5_crc32; | |
332 | } ns_rcte; | |
333 | ||
334 | #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */ | |
335 | #define NS_RCTE_NZGFC 0x00100000 | |
336 | #define NS_RCTE_CONNECTOPEN 0x00080000 | |
337 | #define NS_RCTE_AALMASK 0x00070000 | |
338 | #define NS_RCTE_AAL0 0x00000000 | |
339 | #define NS_RCTE_AAL34 0x00010000 | |
340 | #define NS_RCTE_AAL5 0x00020000 | |
341 | #define NS_RCTE_RCQ 0x00030000 | |
342 | #define NS_RCTE_RAWCELLINTEN 0x00008000 | |
343 | #define NS_RCTE_RXCONSTCELLADDR 0x00004000 | |
344 | #define NS_RCTE_BUFFVALID 0x00002000 | |
345 | #define NS_RCTE_FBDSIZE 0x00001000 | |
346 | #define NS_RCTE_EFCI 0x00000800 | |
347 | #define NS_RCTE_CLP 0x00000400 | |
348 | #define NS_RCTE_CRCERROR 0x00000200 | |
349 | #define NS_RCTE_CELLCOUNT_MASK 0x000001FF | |
350 | ||
351 | #define NS_RCTE_FBDSIZE_SM 0x00000000 | |
352 | #define NS_RCTE_FBDSIZE_LG 0x00001000 | |
353 | ||
354 | #define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */ | |
355 | ||
356 | /* NOTE: We could make macros to contruct the first word of the RCTE, | |
357 | but that doesn't seem to make much sense... */ | |
358 | ||
359 | ||
360 | ||
361 | /* FBD - Free Buffer Descriptor | |
362 | * | |
363 | * Written by the device driver using via the command register. | |
364 | */ | |
365 | ||
366 | typedef struct ns_fbd | |
367 | { | |
368 | u32 buffer_handle; | |
369 | u32 dma_address; | |
370 | } ns_fbd; | |
371 | ||
372 | ||
373 | ||
374 | ||
375 | /* TST - Transmit Schedule Table | |
376 | * | |
377 | * Written by the device driver. | |
378 | */ | |
379 | ||
380 | typedef u32 ns_tste; | |
381 | ||
382 | #define NS_TST_OPCODE_MASK 0x60000000 | |
383 | ||
384 | #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */ | |
385 | #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */ | |
386 | #define NS_TST_OPCODE_VARIABLE 0x40000000 | |
387 | #define NS_TST_OPCODE_END 0x60000000 /* Jump */ | |
388 | ||
389 | #define ns_tste_make(opcode, sramad) (opcode | sramad) | |
390 | ||
391 | /* NOTE: | |
392 | ||
393 | - When the opcode is FIXED, sramad specifies the SRAM address of the | |
394 | SCD for that fixed rate channel. | |
395 | - When the opcode is END, sramad specifies the SRAM address of the | |
396 | location of the next TST entry to read. | |
397 | */ | |
398 | ||
399 | ||
400 | ||
401 | /* SCD - Segmentation Channel Descriptor | |
402 | * | |
403 | * Written by both the device driver and the NICStAR | |
404 | */ | |
405 | ||
406 | typedef struct ns_scd | |
407 | { | |
408 | u32 word_1; | |
409 | u32 word_2; | |
410 | u32 partial_aal5_crc; | |
411 | u32 reserved; | |
412 | ns_scqe cache_a; | |
413 | ns_scqe cache_b; | |
414 | } ns_scd; | |
415 | ||
416 | #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */ | |
417 | #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */ | |
418 | #define NS_SCD_TAIL_MASK_VAR 0x00001FF0 | |
419 | #define NS_SCD_TAIL_MASK_FIX 0x000003F0 | |
420 | #define NS_SCD_HEAD_MASK_VAR 0x00001FF0 | |
421 | #define NS_SCD_HEAD_MASK_FIX 0x000003F0 | |
422 | #define NS_SCD_XMITFOREVER 0x02000000 | |
423 | ||
424 | /* NOTE: There are other fields in word 2 of the SCD, but as they should | |
425 | not be needed in the device driver they are not defined here. */ | |
426 | ||
427 | ||
428 | ||
429 | ||
430 | /* NICStAR local SRAM memory map **********************************************/ | |
431 | ||
432 | ||
433 | #define NS_RCT 0x00000 | |
434 | #define NS_RCT_32_END 0x03FFF | |
435 | #define NS_RCT_128_END 0x0FFFF | |
436 | #define NS_UNUSED_32 0x04000 | |
437 | #define NS_UNUSED_128 0x10000 | |
438 | #define NS_UNUSED_END 0x1BFFF | |
439 | #define NS_TST_FRSCD 0x1C000 | |
440 | #define NS_TST_FRSCD_END 0x1E7DB | |
441 | #define NS_VRSCD2 0x1E7DC | |
442 | #define NS_VRSCD2_END 0x1E7E7 | |
443 | #define NS_VRSCD1 0x1E7E8 | |
444 | #define NS_VRSCD1_END 0x1E7F3 | |
445 | #define NS_VRSCD0 0x1E7F4 | |
446 | #define NS_VRSCD0_END 0x1E7FF | |
447 | #define NS_RXFIFO 0x1E800 | |
448 | #define NS_RXFIFO_END 0x1F7FF | |
449 | #define NS_SMFBQ 0x1F800 | |
450 | #define NS_SMFBQ_END 0x1FBFF | |
451 | #define NS_LGFBQ 0x1FC00 | |
452 | #define NS_LGFBQ_END 0x1FFFF | |
453 | ||
454 | ||
455 | ||
456 | /* NISCtAR operation registers ************************************************/ | |
457 | ||
458 | ||
459 | /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */ | |
460 | ||
461 | enum ns_regs | |
462 | { | |
463 | DR0 = 0x00, /* Data Register 0 R/W*/ | |
464 | DR1 = 0x04, /* Data Register 1 W */ | |
465 | DR2 = 0x08, /* Data Register 2 W */ | |
466 | DR3 = 0x0C, /* Data Register 3 W */ | |
467 | CMD = 0x10, /* Command W */ | |
468 | CFG = 0x14, /* Configuration R/W */ | |
469 | STAT = 0x18, /* Status R/W */ | |
470 | RSQB = 0x1C, /* Receive Status Queue Base W */ | |
471 | RSQT = 0x20, /* Receive Status Queue Tail R */ | |
472 | RSQH = 0x24, /* Receive Status Queue Head W */ | |
473 | CDC = 0x28, /* Cell Drop Counter R/clear */ | |
474 | VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */ | |
475 | ICC = 0x30, /* Invalid Cell Count R/clear */ | |
476 | RAWCT = 0x34, /* Raw Cell Tail R */ | |
477 | TMR = 0x38, /* Timer R */ | |
478 | TSTB = 0x3C, /* Transmit Schedule Table Base R/W */ | |
479 | TSQB = 0x40, /* Transmit Status Queue Base W */ | |
480 | TSQT = 0x44, /* Transmit Status Queue Tail R */ | |
481 | TSQH = 0x48, /* Transmit Status Queue Head W */ | |
482 | GP = 0x4C, /* General Purpose R/W */ | |
483 | VPM = 0x50 /* VPI/VCI Mask W */ | |
484 | }; | |
485 | ||
486 | ||
487 | /* NICStAR commands issued to the CMD register ********************************/ | |
488 | ||
489 | ||
490 | /* Top 4 bits are command opcode, lower 28 are parameters. */ | |
491 | ||
492 | #define NS_CMD_NO_OPERATION 0x00000000 | |
493 | /* params always 0 */ | |
494 | ||
495 | #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000 | |
496 | /* b19{1=open,0=close} b18-2{SRAM addr} */ | |
497 | ||
498 | #define NS_CMD_WRITE_SRAM 0x40000000 | |
499 | /* b18-2{SRAM addr} b1-0{burst size} */ | |
500 | ||
501 | #define NS_CMD_READ_SRAM 0x50000000 | |
502 | /* b18-2{SRAM addr} */ | |
503 | ||
504 | #define NS_CMD_WRITE_FREEBUFQ 0x60000000 | |
505 | /* b0{large buf indicator} */ | |
506 | ||
507 | #define NS_CMD_READ_UTILITY 0x80000000 | |
508 | /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ | |
509 | ||
510 | #define NS_CMD_WRITE_UTILITY 0x90000000 | |
511 | /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ | |
512 | ||
513 | #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000) | |
514 | #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION | |
515 | ||
516 | ||
517 | /* NICStAR configuration bits *************************************************/ | |
518 | ||
519 | #define NS_CFG_SWRST 0x80000000 /* Software Reset */ | |
520 | #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */ | |
521 | #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */ | |
522 | #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */ | |
523 | #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue | |
524 | Interrupt Enable */ | |
525 | #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */ | |
526 | #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */ | |
527 | #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */ | |
528 | #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */ | |
529 | #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */ | |
530 | #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */ | |
531 | #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt | |
532 | Handling */ | |
533 | #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */ | |
534 | #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full | |
535 | Interrupt Enable */ | |
536 | #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */ | |
537 | #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt | |
538 | Enable */ | |
539 | #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */ | |
540 | #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt | |
541 | Enable */ | |
542 | #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt | |
543 | Enable */ | |
544 | #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */ | |
545 | #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full | |
546 | Interrupt Enable */ | |
547 | #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */ | |
548 | ||
549 | #define NS_CFG_SMBUFSIZE_48 0x00000000 | |
550 | #define NS_CFG_SMBUFSIZE_96 0x08000000 | |
551 | #define NS_CFG_SMBUFSIZE_240 0x10000000 | |
552 | #define NS_CFG_SMBUFSIZE_2048 0x18000000 | |
553 | ||
554 | #define NS_CFG_LGBUFSIZE_2048 0x00000000 | |
555 | #define NS_CFG_LGBUFSIZE_4096 0x02000000 | |
556 | #define NS_CFG_LGBUFSIZE_8192 0x04000000 | |
557 | #define NS_CFG_LGBUFSIZE_16384 0x06000000 | |
558 | ||
559 | #define NS_CFG_RSQSIZE_2048 0x00000000 | |
560 | #define NS_CFG_RSQSIZE_4096 0x00400000 | |
561 | #define NS_CFG_RSQSIZE_8192 0x00800000 | |
562 | ||
563 | #define NS_CFG_VPIBITS_0 0x00000000 | |
564 | #define NS_CFG_VPIBITS_1 0x00040000 | |
565 | #define NS_CFG_VPIBITS_2 0x00080000 | |
566 | #define NS_CFG_VPIBITS_8 0x000C0000 | |
567 | ||
568 | #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000 | |
569 | #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000 | |
570 | #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000 | |
571 | ||
572 | #define NS_CFG_RXINT_NOINT 0x00000000 | |
573 | #define NS_CFG_RXINT_NODELAY 0x00001000 | |
574 | #define NS_CFG_RXINT_314US 0x00002000 | |
575 | #define NS_CFG_RXINT_624US 0x00003000 | |
576 | #define NS_CFG_RXINT_899US 0x00004000 | |
577 | ||
578 | ||
579 | /* NICStAR STATus bits ********************************************************/ | |
580 | ||
581 | #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */ | |
582 | #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */ | |
583 | #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */ | |
584 | #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */ | |
585 | #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */ | |
586 | #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */ | |
587 | #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */ | |
588 | #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */ | |
589 | #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */ | |
590 | #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */ | |
591 | #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */ | |
592 | #define NS_STAT_EOPDU 0x00000020 /* End of PDU */ | |
593 | #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ | |
594 | #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */ | |
595 | #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */ | |
596 | #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */ | |
597 | ||
598 | #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23) | |
599 | #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15) | |
600 | ||
601 | ||
602 | ||
603 | /* #defines which depend on other #defines ************************************/ | |
604 | ||
605 | ||
606 | #define NS_TST0 NS_TST_FRSCD | |
607 | #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1) | |
608 | ||
609 | #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1) | |
610 | #define NS_FRSCD_SIZE 12 /* 12 dwords */ | |
611 | #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE) | |
612 | ||
613 | #if (NS_SMBUFSIZE == 48) | |
614 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48 | |
615 | #elif (NS_SMBUFSIZE == 96) | |
616 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96 | |
617 | #elif (NS_SMBUFSIZE == 240) | |
618 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240 | |
619 | #elif (NS_SMBUFSIZE == 2048) | |
620 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048 | |
621 | #else | |
622 | #error NS_SMBUFSIZE is incorrect in nicstar.h | |
623 | #endif /* NS_SMBUFSIZE */ | |
624 | ||
625 | #if (NS_LGBUFSIZE == 2048) | |
626 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048 | |
627 | #elif (NS_LGBUFSIZE == 4096) | |
628 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096 | |
629 | #elif (NS_LGBUFSIZE == 8192) | |
630 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192 | |
631 | #elif (NS_LGBUFSIZE == 16384) | |
632 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384 | |
633 | #else | |
634 | #error NS_LGBUFSIZE is incorrect in nicstar.h | |
635 | #endif /* NS_LGBUFSIZE */ | |
636 | ||
637 | #if (NS_RSQSIZE == 2048) | |
638 | #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048 | |
639 | #elif (NS_RSQSIZE == 4096) | |
640 | #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096 | |
641 | #elif (NS_RSQSIZE == 8192) | |
642 | #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192 | |
643 | #else | |
644 | #error NS_RSQSIZE is incorrect in nicstar.h | |
645 | #endif /* NS_RSQSIZE */ | |
646 | ||
647 | #if (NS_VPIBITS == 0) | |
648 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0 | |
649 | #elif (NS_VPIBITS == 1) | |
650 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1 | |
651 | #elif (NS_VPIBITS == 2) | |
652 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2 | |
653 | #elif (NS_VPIBITS == 8) | |
654 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8 | |
655 | #else | |
656 | #error NS_VPIBITS is incorrect in nicstar.h | |
657 | #endif /* NS_VPIBITS */ | |
658 | ||
659 | #ifdef RCQ_SUPPORT | |
660 | #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE | |
661 | #else | |
662 | #define NS_CFG_RAWIE_OPT 0x00000000 | |
663 | #endif /* RCQ_SUPPORT */ | |
664 | ||
665 | #ifdef ENABLE_TSQFIE | |
666 | #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE | |
667 | #else | |
668 | #define NS_CFG_TSQFIE_OPT 0x00000000 | |
669 | #endif /* ENABLE_TSQFIE */ | |
670 | ||
671 | ||
672 | /* PCI stuff ******************************************************************/ | |
673 | ||
674 | #ifndef PCI_VENDOR_ID_IDT | |
675 | #define PCI_VENDOR_ID_IDT 0x111D | |
676 | #endif /* PCI_VENDOR_ID_IDT */ | |
677 | ||
678 | #ifndef PCI_DEVICE_ID_IDT_IDT77201 | |
679 | #define PCI_DEVICE_ID_IDT_IDT77201 0x0001 | |
680 | #endif /* PCI_DEVICE_ID_IDT_IDT77201 */ | |
681 | ||
682 | ||
683 | ||
684 | /* Device driver structures ***************************************************/ | |
685 | ||
686 | ||
687 | typedef struct tsq_info | |
688 | { | |
689 | void *org; | |
690 | ns_tsi *base; | |
691 | ns_tsi *next; | |
692 | ns_tsi *last; | |
693 | } tsq_info; | |
694 | ||
695 | ||
696 | typedef struct scq_info | |
697 | { | |
698 | void *org; | |
699 | ns_scqe *base; | |
700 | ns_scqe *last; | |
701 | ns_scqe *next; | |
702 | volatile ns_scqe *tail; /* Not related to the nicstar register */ | |
703 | unsigned num_entries; | |
704 | struct sk_buff **skb; /* Pointer to an array of pointers | |
705 | to the sk_buffs used for tx */ | |
706 | u32 scd; /* SRAM address of the corresponding | |
707 | SCD */ | |
708 | int tbd_count; /* Only meaningful on variable rate */ | |
709 | wait_queue_head_t scqfull_waitq; | |
710 | volatile char full; /* SCQ full indicator */ | |
711 | spinlock_t lock; /* SCQ spinlock */ | |
712 | #ifdef NS_DEBUG_SPINLOCKS | |
713 | volatile long has_lock; | |
714 | volatile int cpu_lock; | |
715 | #endif /* NS_DEBUG_SPINLOCKS */ | |
716 | } scq_info; | |
717 | ||
718 | ||
719 | ||
720 | typedef struct rsq_info | |
721 | { | |
722 | void *org; | |
723 | ns_rsqe *base; | |
724 | ns_rsqe *next; | |
725 | ns_rsqe *last; | |
726 | } rsq_info; | |
727 | ||
728 | ||
729 | typedef struct skb_pool | |
730 | { | |
731 | volatile int count; /* number of buffers in the queue */ | |
732 | struct sk_buff_head queue; | |
733 | } skb_pool; | |
734 | ||
735 | /* NOTE: for small and large buffer pools, the count is not used, as the | |
736 | actual value used for buffer management is the one read from the | |
737 | card. */ | |
738 | ||
739 | ||
740 | typedef struct vc_map | |
741 | { | |
742 | volatile unsigned int tx:1; /* TX vc? */ | |
743 | volatile unsigned int rx:1; /* RX vc? */ | |
744 | struct atm_vcc *tx_vcc, *rx_vcc; | |
745 | struct sk_buff *rx_iov; /* RX iovector skb */ | |
746 | scq_info *scq; /* To keep track of the SCQ */ | |
747 | u32 cbr_scd; /* SRAM address of the corresponding | |
748 | SCD. 0x00000000 for UBR/VBR/ABR */ | |
749 | int tbd_count; | |
750 | } vc_map; | |
751 | ||
752 | ||
753 | struct ns_skb_data | |
754 | { | |
755 | struct atm_vcc *vcc; | |
756 | int iovcnt; | |
757 | }; | |
758 | ||
759 | #define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb)) | |
760 | ||
761 | ||
762 | typedef struct ns_dev | |
763 | { | |
764 | int index; /* Card ID to the device driver */ | |
765 | int sram_size; /* In k x 32bit words. 32 or 128 */ | |
766 | void __iomem *membase; /* Card's memory base address */ | |
767 | unsigned long max_pcr; | |
768 | int rct_size; /* Number of entries */ | |
769 | int vpibits; | |
770 | int vcibits; | |
771 | struct pci_dev *pcidev; | |
772 | struct atm_dev *atmdev; | |
773 | tsq_info tsq; | |
774 | rsq_info rsq; | |
775 | scq_info *scq0, *scq1, *scq2; /* VBR SCQs */ | |
776 | skb_pool sbpool; /* Small buffers */ | |
777 | skb_pool lbpool; /* Large buffers */ | |
778 | skb_pool hbpool; /* Pre-allocated huge buffers */ | |
779 | skb_pool iovpool; /* iovector buffers */ | |
780 | volatile int efbie; /* Empty free buf. queue int. enabled */ | |
781 | volatile u32 tst_addr; /* SRAM address of the TST in use */ | |
782 | volatile int tst_free_entries; | |
783 | vc_map vcmap[NS_MAX_RCTSIZE]; | |
784 | vc_map *tste2vc[NS_TST_NUM_ENTRIES]; | |
785 | vc_map *scd2vc[NS_FRSCD_NUM]; | |
786 | buf_nr sbnr; | |
787 | buf_nr lbnr; | |
788 | buf_nr hbnr; | |
789 | buf_nr iovnr; | |
790 | int sbfqc; | |
791 | int lbfqc; | |
792 | u32 sm_handle; | |
793 | u32 sm_addr; | |
794 | u32 lg_handle; | |
795 | u32 lg_addr; | |
796 | struct sk_buff *rcbuf; /* Current raw cell buffer */ | |
797 | u32 rawch; /* Raw cell queue head */ | |
798 | unsigned intcnt; /* Interrupt counter */ | |
799 | spinlock_t int_lock; /* Interrupt lock */ | |
800 | spinlock_t res_lock; /* Card resource lock */ | |
801 | #ifdef NS_DEBUG_SPINLOCKS | |
802 | volatile long has_int_lock; | |
803 | volatile int cpu_int; | |
804 | volatile long has_res_lock; | |
805 | volatile int cpu_res; | |
806 | #endif /* NS_DEBUG_SPINLOCKS */ | |
807 | } ns_dev; | |
808 | ||
809 | ||
810 | /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding | |
811 | CBR vc. If the entry is not allocated, it must be NULL. | |
812 | ||
813 | There are two TSTs so the driver can modify them on the fly | |
814 | without stopping the transmission. | |
815 | ||
816 | scd2vc allows us to find out unused fixed rate SCDs, because | |
817 | they must have a NULL pointer here. */ | |
818 | ||
819 | ||
820 | #endif /* _LINUX_NICSTAR_H_ */ |