Commit | Line | Data |
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9fabe24e DP |
1 | /* |
2 | * Register cache access API | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/slab.h> | |
1b6bc32f | 14 | #include <linux/export.h> |
51990e82 | 15 | #include <linux/device.h> |
9fabe24e | 16 | #include <trace/events/regmap.h> |
f094fea6 | 17 | #include <linux/bsearch.h> |
c08604b8 | 18 | #include <linux/sort.h> |
9fabe24e DP |
19 | |
20 | #include "internal.h" | |
21 | ||
22 | static const struct regcache_ops *cache_types[] = { | |
28644c80 | 23 | ®cache_rbtree_ops, |
2cbbb579 | 24 | ®cache_lzo_ops, |
9fabe24e DP |
25 | }; |
26 | ||
27 | static int regcache_hw_init(struct regmap *map) | |
28 | { | |
29 | int i, j; | |
30 | int ret; | |
31 | int count; | |
32 | unsigned int val; | |
33 | void *tmp_buf; | |
34 | ||
35 | if (!map->num_reg_defaults_raw) | |
36 | return -EINVAL; | |
37 | ||
38 | if (!map->reg_defaults_raw) { | |
df00c79f | 39 | u32 cache_bypass = map->cache_bypass; |
9fabe24e | 40 | dev_warn(map->dev, "No cache defaults, reading back from HW\n"); |
df00c79f LD |
41 | |
42 | /* Bypass the cache access till data read from HW*/ | |
43 | map->cache_bypass = 1; | |
9fabe24e DP |
44 | tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); |
45 | if (!tmp_buf) | |
46 | return -EINVAL; | |
47 | ret = regmap_bulk_read(map, 0, tmp_buf, | |
48 | map->num_reg_defaults_raw); | |
df00c79f | 49 | map->cache_bypass = cache_bypass; |
9fabe24e DP |
50 | if (ret < 0) { |
51 | kfree(tmp_buf); | |
52 | return ret; | |
53 | } | |
54 | map->reg_defaults_raw = tmp_buf; | |
55 | map->cache_free = 1; | |
56 | } | |
57 | ||
58 | /* calculate the size of reg_defaults */ | |
59 | for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) { | |
60 | val = regcache_get_val(map->reg_defaults_raw, | |
61 | i, map->cache_word_size); | |
f01ee60f | 62 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e DP |
63 | continue; |
64 | count++; | |
65 | } | |
66 | ||
67 | map->reg_defaults = kmalloc(count * sizeof(struct reg_default), | |
68 | GFP_KERNEL); | |
021cd616 LPC |
69 | if (!map->reg_defaults) { |
70 | ret = -ENOMEM; | |
71 | goto err_free; | |
72 | } | |
9fabe24e DP |
73 | |
74 | /* fill the reg_defaults */ | |
75 | map->num_reg_defaults = count; | |
76 | for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { | |
77 | val = regcache_get_val(map->reg_defaults_raw, | |
78 | i, map->cache_word_size); | |
f01ee60f | 79 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e | 80 | continue; |
f01ee60f | 81 | map->reg_defaults[j].reg = i * map->reg_stride; |
9fabe24e DP |
82 | map->reg_defaults[j].def = val; |
83 | j++; | |
84 | } | |
85 | ||
86 | return 0; | |
021cd616 LPC |
87 | |
88 | err_free: | |
89 | if (map->cache_free) | |
90 | kfree(map->reg_defaults_raw); | |
91 | ||
92 | return ret; | |
9fabe24e DP |
93 | } |
94 | ||
e5e3b8ab | 95 | int regcache_init(struct regmap *map, const struct regmap_config *config) |
9fabe24e DP |
96 | { |
97 | int ret; | |
98 | int i; | |
99 | void *tmp_buf; | |
100 | ||
f01ee60f SW |
101 | for (i = 0; i < config->num_reg_defaults; i++) |
102 | if (config->reg_defaults[i].reg % map->reg_stride) | |
103 | return -EINVAL; | |
104 | ||
e7a6db30 MB |
105 | if (map->cache_type == REGCACHE_NONE) { |
106 | map->cache_bypass = true; | |
9fabe24e | 107 | return 0; |
e7a6db30 | 108 | } |
9fabe24e DP |
109 | |
110 | for (i = 0; i < ARRAY_SIZE(cache_types); i++) | |
111 | if (cache_types[i]->type == map->cache_type) | |
112 | break; | |
113 | ||
114 | if (i == ARRAY_SIZE(cache_types)) { | |
115 | dev_err(map->dev, "Could not match compress type: %d\n", | |
116 | map->cache_type); | |
117 | return -EINVAL; | |
118 | } | |
119 | ||
e5e3b8ab LPC |
120 | map->num_reg_defaults = config->num_reg_defaults; |
121 | map->num_reg_defaults_raw = config->num_reg_defaults_raw; | |
122 | map->reg_defaults_raw = config->reg_defaults_raw; | |
064d4db1 LPC |
123 | map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); |
124 | map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; | |
e5e3b8ab | 125 | |
9fabe24e DP |
126 | map->cache = NULL; |
127 | map->cache_ops = cache_types[i]; | |
128 | ||
129 | if (!map->cache_ops->read || | |
130 | !map->cache_ops->write || | |
131 | !map->cache_ops->name) | |
132 | return -EINVAL; | |
133 | ||
134 | /* We still need to ensure that the reg_defaults | |
135 | * won't vanish from under us. We'll need to make | |
136 | * a copy of it. | |
137 | */ | |
720e4616 | 138 | if (config->reg_defaults) { |
9fabe24e DP |
139 | if (!map->num_reg_defaults) |
140 | return -EINVAL; | |
720e4616 | 141 | tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * |
9fabe24e DP |
142 | sizeof(struct reg_default), GFP_KERNEL); |
143 | if (!tmp_buf) | |
144 | return -ENOMEM; | |
145 | map->reg_defaults = tmp_buf; | |
8528bdd4 | 146 | } else if (map->num_reg_defaults_raw) { |
5fcd2560 | 147 | /* Some devices such as PMICs don't have cache defaults, |
9fabe24e DP |
148 | * we cope with this by reading back the HW registers and |
149 | * crafting the cache defaults by hand. | |
150 | */ | |
151 | ret = regcache_hw_init(map); | |
152 | if (ret < 0) | |
153 | return ret; | |
154 | } | |
155 | ||
156 | if (!map->max_register) | |
157 | map->max_register = map->num_reg_defaults_raw; | |
158 | ||
159 | if (map->cache_ops->init) { | |
160 | dev_dbg(map->dev, "Initializing %s cache\n", | |
161 | map->cache_ops->name); | |
bd061c78 LPC |
162 | ret = map->cache_ops->init(map); |
163 | if (ret) | |
164 | goto err_free; | |
9fabe24e DP |
165 | } |
166 | return 0; | |
bd061c78 LPC |
167 | |
168 | err_free: | |
169 | kfree(map->reg_defaults); | |
170 | if (map->cache_free) | |
171 | kfree(map->reg_defaults_raw); | |
172 | ||
173 | return ret; | |
9fabe24e DP |
174 | } |
175 | ||
176 | void regcache_exit(struct regmap *map) | |
177 | { | |
178 | if (map->cache_type == REGCACHE_NONE) | |
179 | return; | |
180 | ||
181 | BUG_ON(!map->cache_ops); | |
182 | ||
183 | kfree(map->reg_defaults); | |
184 | if (map->cache_free) | |
185 | kfree(map->reg_defaults_raw); | |
186 | ||
187 | if (map->cache_ops->exit) { | |
188 | dev_dbg(map->dev, "Destroying %s cache\n", | |
189 | map->cache_ops->name); | |
190 | map->cache_ops->exit(map); | |
191 | } | |
192 | } | |
193 | ||
194 | /** | |
195 | * regcache_read: Fetch the value of a given register from the cache. | |
196 | * | |
197 | * @map: map to configure. | |
198 | * @reg: The register index. | |
199 | * @value: The value to be returned. | |
200 | * | |
201 | * Return a negative value on failure, 0 on success. | |
202 | */ | |
203 | int regcache_read(struct regmap *map, | |
204 | unsigned int reg, unsigned int *value) | |
205 | { | |
bc7ee556 MB |
206 | int ret; |
207 | ||
9fabe24e DP |
208 | if (map->cache_type == REGCACHE_NONE) |
209 | return -ENOSYS; | |
210 | ||
211 | BUG_ON(!map->cache_ops); | |
212 | ||
bc7ee556 MB |
213 | if (!regmap_volatile(map, reg)) { |
214 | ret = map->cache_ops->read(map, reg, value); | |
215 | ||
216 | if (ret == 0) | |
217 | trace_regmap_reg_read_cache(map->dev, reg, *value); | |
218 | ||
219 | return ret; | |
220 | } | |
9fabe24e DP |
221 | |
222 | return -EINVAL; | |
223 | } | |
9fabe24e DP |
224 | |
225 | /** | |
226 | * regcache_write: Set the value of a given register in the cache. | |
227 | * | |
228 | * @map: map to configure. | |
229 | * @reg: The register index. | |
230 | * @value: The new register value. | |
231 | * | |
232 | * Return a negative value on failure, 0 on success. | |
233 | */ | |
234 | int regcache_write(struct regmap *map, | |
235 | unsigned int reg, unsigned int value) | |
236 | { | |
237 | if (map->cache_type == REGCACHE_NONE) | |
238 | return 0; | |
239 | ||
240 | BUG_ON(!map->cache_ops); | |
241 | ||
242 | if (!regmap_writeable(map, reg)) | |
243 | return -EIO; | |
244 | ||
245 | if (!regmap_volatile(map, reg)) | |
246 | return map->cache_ops->write(map, reg, value); | |
247 | ||
248 | return 0; | |
249 | } | |
9fabe24e DP |
250 | |
251 | /** | |
252 | * regcache_sync: Sync the register cache with the hardware. | |
253 | * | |
254 | * @map: map to configure. | |
255 | * | |
256 | * Any registers that should not be synced should be marked as | |
257 | * volatile. In general drivers can choose not to use the provided | |
258 | * syncing functionality if they so require. | |
259 | * | |
260 | * Return a negative value on failure, 0 on success. | |
261 | */ | |
262 | int regcache_sync(struct regmap *map) | |
263 | { | |
954757d7 | 264 | int ret = 0; |
954757d7 | 265 | unsigned int i; |
59360089 | 266 | const char *name; |
beb1a10f | 267 | unsigned int bypass; |
59360089 | 268 | |
c3ec2328 | 269 | BUG_ON(!map->cache_ops || !map->cache_ops->sync); |
9fabe24e | 270 | |
bacdbe07 | 271 | map->lock(map); |
beb1a10f DP |
272 | /* Remember the initial bypass state */ |
273 | bypass = map->cache_bypass; | |
954757d7 DP |
274 | dev_dbg(map->dev, "Syncing %s cache\n", |
275 | map->cache_ops->name); | |
276 | name = map->cache_ops->name; | |
277 | trace_regcache_sync(map->dev, name, "start"); | |
22f0d90a | 278 | |
8ae0d7e8 MB |
279 | if (!map->cache_dirty) |
280 | goto out; | |
d9db7627 | 281 | |
22f0d90a | 282 | /* Apply any patch first */ |
8a892d69 | 283 | map->cache_bypass = 1; |
22f0d90a | 284 | for (i = 0; i < map->patch_regs; i++) { |
f01ee60f SW |
285 | if (map->patch[i].reg % map->reg_stride) { |
286 | ret = -EINVAL; | |
287 | goto out; | |
288 | } | |
22f0d90a MB |
289 | ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); |
290 | if (ret != 0) { | |
291 | dev_err(map->dev, "Failed to write %x = %x: %d\n", | |
292 | map->patch[i].reg, map->patch[i].def, ret); | |
293 | goto out; | |
294 | } | |
295 | } | |
8a892d69 | 296 | map->cache_bypass = 0; |
22f0d90a | 297 | |
ac8d91c8 | 298 | ret = map->cache_ops->sync(map, 0, map->max_register); |
954757d7 | 299 | |
6ff73738 MB |
300 | if (ret == 0) |
301 | map->cache_dirty = false; | |
954757d7 | 302 | |
954757d7 DP |
303 | out: |
304 | trace_regcache_sync(map->dev, name, "stop"); | |
beb1a10f DP |
305 | /* Restore the bypass state */ |
306 | map->cache_bypass = bypass; | |
bacdbe07 | 307 | map->unlock(map); |
954757d7 DP |
308 | |
309 | return ret; | |
9fabe24e DP |
310 | } |
311 | EXPORT_SYMBOL_GPL(regcache_sync); | |
312 | ||
4d4cfd16 MB |
313 | /** |
314 | * regcache_sync_region: Sync part of the register cache with the hardware. | |
315 | * | |
316 | * @map: map to sync. | |
317 | * @min: first register to sync | |
318 | * @max: last register to sync | |
319 | * | |
320 | * Write all non-default register values in the specified region to | |
321 | * the hardware. | |
322 | * | |
323 | * Return a negative value on failure, 0 on success. | |
324 | */ | |
325 | int regcache_sync_region(struct regmap *map, unsigned int min, | |
326 | unsigned int max) | |
327 | { | |
328 | int ret = 0; | |
329 | const char *name; | |
330 | unsigned int bypass; | |
331 | ||
332 | BUG_ON(!map->cache_ops || !map->cache_ops->sync); | |
333 | ||
bacdbe07 | 334 | map->lock(map); |
4d4cfd16 MB |
335 | |
336 | /* Remember the initial bypass state */ | |
337 | bypass = map->cache_bypass; | |
338 | ||
339 | name = map->cache_ops->name; | |
340 | dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); | |
341 | ||
342 | trace_regcache_sync(map->dev, name, "start region"); | |
343 | ||
344 | if (!map->cache_dirty) | |
345 | goto out; | |
346 | ||
347 | ret = map->cache_ops->sync(map, min, max); | |
348 | ||
349 | out: | |
350 | trace_regcache_sync(map->dev, name, "stop region"); | |
351 | /* Restore the bypass state */ | |
352 | map->cache_bypass = bypass; | |
bacdbe07 | 353 | map->unlock(map); |
4d4cfd16 MB |
354 | |
355 | return ret; | |
356 | } | |
e466de05 | 357 | EXPORT_SYMBOL_GPL(regcache_sync_region); |
4d4cfd16 | 358 | |
92afb286 MB |
359 | /** |
360 | * regcache_cache_only: Put a register map into cache only mode | |
361 | * | |
362 | * @map: map to configure | |
363 | * @cache_only: flag if changes should be written to the hardware | |
364 | * | |
365 | * When a register map is marked as cache only writes to the register | |
366 | * map API will only update the register cache, they will not cause | |
367 | * any hardware changes. This is useful for allowing portions of | |
368 | * drivers to act as though the device were functioning as normal when | |
369 | * it is disabled for power saving reasons. | |
370 | */ | |
371 | void regcache_cache_only(struct regmap *map, bool enable) | |
372 | { | |
bacdbe07 | 373 | map->lock(map); |
ac77a765 | 374 | WARN_ON(map->cache_bypass && enable); |
92afb286 | 375 | map->cache_only = enable; |
5d5b7d4f | 376 | trace_regmap_cache_only(map->dev, enable); |
bacdbe07 | 377 | map->unlock(map); |
92afb286 MB |
378 | } |
379 | EXPORT_SYMBOL_GPL(regcache_cache_only); | |
380 | ||
8ae0d7e8 MB |
381 | /** |
382 | * regcache_mark_dirty: Mark the register cache as dirty | |
383 | * | |
384 | * @map: map to mark | |
385 | * | |
386 | * Mark the register cache as dirty, for example due to the device | |
387 | * having been powered down for suspend. If the cache is not marked | |
388 | * as dirty then the cache sync will be suppressed. | |
389 | */ | |
390 | void regcache_mark_dirty(struct regmap *map) | |
391 | { | |
bacdbe07 | 392 | map->lock(map); |
8ae0d7e8 | 393 | map->cache_dirty = true; |
bacdbe07 | 394 | map->unlock(map); |
8ae0d7e8 MB |
395 | } |
396 | EXPORT_SYMBOL_GPL(regcache_mark_dirty); | |
397 | ||
6eb0f5e0 DP |
398 | /** |
399 | * regcache_cache_bypass: Put a register map into cache bypass mode | |
400 | * | |
401 | * @map: map to configure | |
0eef6b04 | 402 | * @cache_bypass: flag if changes should not be written to the hardware |
6eb0f5e0 DP |
403 | * |
404 | * When a register map is marked with the cache bypass option, writes | |
405 | * to the register map API will only update the hardware and not the | |
406 | * the cache directly. This is useful when syncing the cache back to | |
407 | * the hardware. | |
408 | */ | |
409 | void regcache_cache_bypass(struct regmap *map, bool enable) | |
410 | { | |
bacdbe07 | 411 | map->lock(map); |
ac77a765 | 412 | WARN_ON(map->cache_only && enable); |
6eb0f5e0 | 413 | map->cache_bypass = enable; |
5d5b7d4f | 414 | trace_regmap_cache_bypass(map->dev, enable); |
bacdbe07 | 415 | map->unlock(map); |
6eb0f5e0 DP |
416 | } |
417 | EXPORT_SYMBOL_GPL(regcache_cache_bypass); | |
418 | ||
9fabe24e DP |
419 | bool regcache_set_val(void *base, unsigned int idx, |
420 | unsigned int val, unsigned int word_size) | |
421 | { | |
422 | switch (word_size) { | |
423 | case 1: { | |
424 | u8 *cache = base; | |
425 | if (cache[idx] == val) | |
426 | return true; | |
427 | cache[idx] = val; | |
428 | break; | |
429 | } | |
430 | case 2: { | |
431 | u16 *cache = base; | |
432 | if (cache[idx] == val) | |
433 | return true; | |
434 | cache[idx] = val; | |
435 | break; | |
436 | } | |
7d5e525b MB |
437 | case 4: { |
438 | u32 *cache = base; | |
439 | if (cache[idx] == val) | |
440 | return true; | |
441 | cache[idx] = val; | |
442 | break; | |
443 | } | |
9fabe24e DP |
444 | default: |
445 | BUG(); | |
446 | } | |
9fabe24e DP |
447 | return false; |
448 | } | |
449 | ||
450 | unsigned int regcache_get_val(const void *base, unsigned int idx, | |
451 | unsigned int word_size) | |
452 | { | |
453 | if (!base) | |
454 | return -EINVAL; | |
455 | ||
456 | switch (word_size) { | |
457 | case 1: { | |
458 | const u8 *cache = base; | |
459 | return cache[idx]; | |
460 | } | |
461 | case 2: { | |
462 | const u16 *cache = base; | |
463 | return cache[idx]; | |
464 | } | |
7d5e525b MB |
465 | case 4: { |
466 | const u32 *cache = base; | |
467 | return cache[idx]; | |
468 | } | |
9fabe24e DP |
469 | default: |
470 | BUG(); | |
471 | } | |
472 | /* unreachable */ | |
473 | return -1; | |
474 | } | |
475 | ||
f094fea6 | 476 | static int regcache_default_cmp(const void *a, const void *b) |
c08604b8 DP |
477 | { |
478 | const struct reg_default *_a = a; | |
479 | const struct reg_default *_b = b; | |
480 | ||
481 | return _a->reg - _b->reg; | |
482 | } | |
483 | ||
f094fea6 MB |
484 | int regcache_lookup_reg(struct regmap *map, unsigned int reg) |
485 | { | |
486 | struct reg_default key; | |
487 | struct reg_default *r; | |
488 | ||
489 | key.reg = reg; | |
490 | key.def = 0; | |
491 | ||
492 | r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, | |
493 | sizeof(struct reg_default), regcache_default_cmp); | |
494 | ||
495 | if (r) | |
496 | return r - map->reg_defaults; | |
497 | else | |
6e6ace00 | 498 | return -ENOENT; |
f094fea6 | 499 | } |