Commit | Line | Data |
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9fabe24e DP |
1 | /* |
2 | * Register cache access API | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/slab.h> | |
1b6bc32f | 14 | #include <linux/export.h> |
51990e82 | 15 | #include <linux/device.h> |
9fabe24e | 16 | #include <trace/events/regmap.h> |
f094fea6 | 17 | #include <linux/bsearch.h> |
c08604b8 | 18 | #include <linux/sort.h> |
9fabe24e DP |
19 | |
20 | #include "internal.h" | |
21 | ||
22 | static const struct regcache_ops *cache_types[] = { | |
28644c80 | 23 | ®cache_rbtree_ops, |
2cbbb579 | 24 | ®cache_lzo_ops, |
2ac902ce | 25 | ®cache_flat_ops, |
9fabe24e DP |
26 | }; |
27 | ||
28 | static int regcache_hw_init(struct regmap *map) | |
29 | { | |
30 | int i, j; | |
31 | int ret; | |
32 | int count; | |
33 | unsigned int val; | |
34 | void *tmp_buf; | |
35 | ||
36 | if (!map->num_reg_defaults_raw) | |
37 | return -EINVAL; | |
38 | ||
39 | if (!map->reg_defaults_raw) { | |
df00c79f | 40 | u32 cache_bypass = map->cache_bypass; |
9fabe24e | 41 | dev_warn(map->dev, "No cache defaults, reading back from HW\n"); |
df00c79f LD |
42 | |
43 | /* Bypass the cache access till data read from HW*/ | |
44 | map->cache_bypass = 1; | |
9fabe24e DP |
45 | tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); |
46 | if (!tmp_buf) | |
47 | return -EINVAL; | |
eb4cb76f MB |
48 | ret = regmap_raw_read(map, 0, tmp_buf, |
49 | map->num_reg_defaults_raw); | |
df00c79f | 50 | map->cache_bypass = cache_bypass; |
9fabe24e DP |
51 | if (ret < 0) { |
52 | kfree(tmp_buf); | |
53 | return ret; | |
54 | } | |
55 | map->reg_defaults_raw = tmp_buf; | |
56 | map->cache_free = 1; | |
57 | } | |
58 | ||
59 | /* calculate the size of reg_defaults */ | |
60 | for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) { | |
879082c9 | 61 | val = regcache_get_val(map, map->reg_defaults_raw, i); |
f01ee60f | 62 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e DP |
63 | continue; |
64 | count++; | |
65 | } | |
66 | ||
67 | map->reg_defaults = kmalloc(count * sizeof(struct reg_default), | |
68 | GFP_KERNEL); | |
021cd616 LPC |
69 | if (!map->reg_defaults) { |
70 | ret = -ENOMEM; | |
71 | goto err_free; | |
72 | } | |
9fabe24e DP |
73 | |
74 | /* fill the reg_defaults */ | |
75 | map->num_reg_defaults = count; | |
76 | for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { | |
879082c9 | 77 | val = regcache_get_val(map, map->reg_defaults_raw, i); |
f01ee60f | 78 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e | 79 | continue; |
f01ee60f | 80 | map->reg_defaults[j].reg = i * map->reg_stride; |
9fabe24e DP |
81 | map->reg_defaults[j].def = val; |
82 | j++; | |
83 | } | |
84 | ||
85 | return 0; | |
021cd616 LPC |
86 | |
87 | err_free: | |
88 | if (map->cache_free) | |
89 | kfree(map->reg_defaults_raw); | |
90 | ||
91 | return ret; | |
9fabe24e DP |
92 | } |
93 | ||
e5e3b8ab | 94 | int regcache_init(struct regmap *map, const struct regmap_config *config) |
9fabe24e DP |
95 | { |
96 | int ret; | |
97 | int i; | |
98 | void *tmp_buf; | |
99 | ||
f01ee60f SW |
100 | for (i = 0; i < config->num_reg_defaults; i++) |
101 | if (config->reg_defaults[i].reg % map->reg_stride) | |
102 | return -EINVAL; | |
103 | ||
e7a6db30 MB |
104 | if (map->cache_type == REGCACHE_NONE) { |
105 | map->cache_bypass = true; | |
9fabe24e | 106 | return 0; |
e7a6db30 | 107 | } |
9fabe24e DP |
108 | |
109 | for (i = 0; i < ARRAY_SIZE(cache_types); i++) | |
110 | if (cache_types[i]->type == map->cache_type) | |
111 | break; | |
112 | ||
113 | if (i == ARRAY_SIZE(cache_types)) { | |
114 | dev_err(map->dev, "Could not match compress type: %d\n", | |
115 | map->cache_type); | |
116 | return -EINVAL; | |
117 | } | |
118 | ||
e5e3b8ab LPC |
119 | map->num_reg_defaults = config->num_reg_defaults; |
120 | map->num_reg_defaults_raw = config->num_reg_defaults_raw; | |
121 | map->reg_defaults_raw = config->reg_defaults_raw; | |
064d4db1 LPC |
122 | map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); |
123 | map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; | |
78493f2d MB |
124 | map->cache_present = NULL; |
125 | map->cache_present_nbits = 0; | |
e5e3b8ab | 126 | |
9fabe24e DP |
127 | map->cache = NULL; |
128 | map->cache_ops = cache_types[i]; | |
129 | ||
130 | if (!map->cache_ops->read || | |
131 | !map->cache_ops->write || | |
132 | !map->cache_ops->name) | |
133 | return -EINVAL; | |
134 | ||
135 | /* We still need to ensure that the reg_defaults | |
136 | * won't vanish from under us. We'll need to make | |
137 | * a copy of it. | |
138 | */ | |
720e4616 | 139 | if (config->reg_defaults) { |
9fabe24e DP |
140 | if (!map->num_reg_defaults) |
141 | return -EINVAL; | |
720e4616 | 142 | tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * |
9fabe24e DP |
143 | sizeof(struct reg_default), GFP_KERNEL); |
144 | if (!tmp_buf) | |
145 | return -ENOMEM; | |
146 | map->reg_defaults = tmp_buf; | |
8528bdd4 | 147 | } else if (map->num_reg_defaults_raw) { |
5fcd2560 | 148 | /* Some devices such as PMICs don't have cache defaults, |
9fabe24e DP |
149 | * we cope with this by reading back the HW registers and |
150 | * crafting the cache defaults by hand. | |
151 | */ | |
152 | ret = regcache_hw_init(map); | |
153 | if (ret < 0) | |
154 | return ret; | |
155 | } | |
156 | ||
157 | if (!map->max_register) | |
158 | map->max_register = map->num_reg_defaults_raw; | |
159 | ||
160 | if (map->cache_ops->init) { | |
161 | dev_dbg(map->dev, "Initializing %s cache\n", | |
162 | map->cache_ops->name); | |
bd061c78 LPC |
163 | ret = map->cache_ops->init(map); |
164 | if (ret) | |
165 | goto err_free; | |
9fabe24e DP |
166 | } |
167 | return 0; | |
bd061c78 LPC |
168 | |
169 | err_free: | |
170 | kfree(map->reg_defaults); | |
171 | if (map->cache_free) | |
172 | kfree(map->reg_defaults_raw); | |
173 | ||
174 | return ret; | |
9fabe24e DP |
175 | } |
176 | ||
177 | void regcache_exit(struct regmap *map) | |
178 | { | |
179 | if (map->cache_type == REGCACHE_NONE) | |
180 | return; | |
181 | ||
182 | BUG_ON(!map->cache_ops); | |
183 | ||
78493f2d | 184 | kfree(map->cache_present); |
9fabe24e DP |
185 | kfree(map->reg_defaults); |
186 | if (map->cache_free) | |
187 | kfree(map->reg_defaults_raw); | |
188 | ||
189 | if (map->cache_ops->exit) { | |
190 | dev_dbg(map->dev, "Destroying %s cache\n", | |
191 | map->cache_ops->name); | |
192 | map->cache_ops->exit(map); | |
193 | } | |
194 | } | |
195 | ||
196 | /** | |
197 | * regcache_read: Fetch the value of a given register from the cache. | |
198 | * | |
199 | * @map: map to configure. | |
200 | * @reg: The register index. | |
201 | * @value: The value to be returned. | |
202 | * | |
203 | * Return a negative value on failure, 0 on success. | |
204 | */ | |
205 | int regcache_read(struct regmap *map, | |
206 | unsigned int reg, unsigned int *value) | |
207 | { | |
bc7ee556 MB |
208 | int ret; |
209 | ||
9fabe24e DP |
210 | if (map->cache_type == REGCACHE_NONE) |
211 | return -ENOSYS; | |
212 | ||
213 | BUG_ON(!map->cache_ops); | |
214 | ||
bc7ee556 MB |
215 | if (!regmap_volatile(map, reg)) { |
216 | ret = map->cache_ops->read(map, reg, value); | |
217 | ||
218 | if (ret == 0) | |
219 | trace_regmap_reg_read_cache(map->dev, reg, *value); | |
220 | ||
221 | return ret; | |
222 | } | |
9fabe24e DP |
223 | |
224 | return -EINVAL; | |
225 | } | |
9fabe24e DP |
226 | |
227 | /** | |
228 | * regcache_write: Set the value of a given register in the cache. | |
229 | * | |
230 | * @map: map to configure. | |
231 | * @reg: The register index. | |
232 | * @value: The new register value. | |
233 | * | |
234 | * Return a negative value on failure, 0 on success. | |
235 | */ | |
236 | int regcache_write(struct regmap *map, | |
237 | unsigned int reg, unsigned int value) | |
238 | { | |
239 | if (map->cache_type == REGCACHE_NONE) | |
240 | return 0; | |
241 | ||
242 | BUG_ON(!map->cache_ops); | |
243 | ||
244 | if (!regmap_writeable(map, reg)) | |
245 | return -EIO; | |
246 | ||
247 | if (!regmap_volatile(map, reg)) | |
248 | return map->cache_ops->write(map, reg, value); | |
249 | ||
250 | return 0; | |
251 | } | |
9fabe24e DP |
252 | |
253 | /** | |
254 | * regcache_sync: Sync the register cache with the hardware. | |
255 | * | |
256 | * @map: map to configure. | |
257 | * | |
258 | * Any registers that should not be synced should be marked as | |
259 | * volatile. In general drivers can choose not to use the provided | |
260 | * syncing functionality if they so require. | |
261 | * | |
262 | * Return a negative value on failure, 0 on success. | |
263 | */ | |
264 | int regcache_sync(struct regmap *map) | |
265 | { | |
954757d7 | 266 | int ret = 0; |
954757d7 | 267 | unsigned int i; |
59360089 | 268 | const char *name; |
beb1a10f | 269 | unsigned int bypass; |
59360089 | 270 | |
c3ec2328 | 271 | BUG_ON(!map->cache_ops || !map->cache_ops->sync); |
9fabe24e | 272 | |
bacdbe07 | 273 | map->lock(map); |
beb1a10f DP |
274 | /* Remember the initial bypass state */ |
275 | bypass = map->cache_bypass; | |
954757d7 DP |
276 | dev_dbg(map->dev, "Syncing %s cache\n", |
277 | map->cache_ops->name); | |
278 | name = map->cache_ops->name; | |
279 | trace_regcache_sync(map->dev, name, "start"); | |
22f0d90a | 280 | |
8ae0d7e8 MB |
281 | if (!map->cache_dirty) |
282 | goto out; | |
d9db7627 | 283 | |
22f0d90a | 284 | /* Apply any patch first */ |
8a892d69 | 285 | map->cache_bypass = 1; |
22f0d90a | 286 | for (i = 0; i < map->patch_regs; i++) { |
f01ee60f SW |
287 | if (map->patch[i].reg % map->reg_stride) { |
288 | ret = -EINVAL; | |
289 | goto out; | |
290 | } | |
22f0d90a MB |
291 | ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); |
292 | if (ret != 0) { | |
293 | dev_err(map->dev, "Failed to write %x = %x: %d\n", | |
294 | map->patch[i].reg, map->patch[i].def, ret); | |
295 | goto out; | |
296 | } | |
297 | } | |
8a892d69 | 298 | map->cache_bypass = 0; |
22f0d90a | 299 | |
ac8d91c8 | 300 | ret = map->cache_ops->sync(map, 0, map->max_register); |
954757d7 | 301 | |
6ff73738 MB |
302 | if (ret == 0) |
303 | map->cache_dirty = false; | |
954757d7 | 304 | |
954757d7 DP |
305 | out: |
306 | trace_regcache_sync(map->dev, name, "stop"); | |
beb1a10f DP |
307 | /* Restore the bypass state */ |
308 | map->cache_bypass = bypass; | |
bacdbe07 | 309 | map->unlock(map); |
954757d7 DP |
310 | |
311 | return ret; | |
9fabe24e DP |
312 | } |
313 | EXPORT_SYMBOL_GPL(regcache_sync); | |
314 | ||
4d4cfd16 MB |
315 | /** |
316 | * regcache_sync_region: Sync part of the register cache with the hardware. | |
317 | * | |
318 | * @map: map to sync. | |
319 | * @min: first register to sync | |
320 | * @max: last register to sync | |
321 | * | |
322 | * Write all non-default register values in the specified region to | |
323 | * the hardware. | |
324 | * | |
325 | * Return a negative value on failure, 0 on success. | |
326 | */ | |
327 | int regcache_sync_region(struct regmap *map, unsigned int min, | |
328 | unsigned int max) | |
329 | { | |
330 | int ret = 0; | |
331 | const char *name; | |
332 | unsigned int bypass; | |
333 | ||
334 | BUG_ON(!map->cache_ops || !map->cache_ops->sync); | |
335 | ||
bacdbe07 | 336 | map->lock(map); |
4d4cfd16 MB |
337 | |
338 | /* Remember the initial bypass state */ | |
339 | bypass = map->cache_bypass; | |
340 | ||
341 | name = map->cache_ops->name; | |
342 | dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); | |
343 | ||
344 | trace_regcache_sync(map->dev, name, "start region"); | |
345 | ||
346 | if (!map->cache_dirty) | |
347 | goto out; | |
348 | ||
349 | ret = map->cache_ops->sync(map, min, max); | |
350 | ||
351 | out: | |
352 | trace_regcache_sync(map->dev, name, "stop region"); | |
353 | /* Restore the bypass state */ | |
354 | map->cache_bypass = bypass; | |
bacdbe07 | 355 | map->unlock(map); |
4d4cfd16 MB |
356 | |
357 | return ret; | |
358 | } | |
e466de05 | 359 | EXPORT_SYMBOL_GPL(regcache_sync_region); |
4d4cfd16 | 360 | |
697e85bc MB |
361 | /** |
362 | * regcache_drop_region: Discard part of the register cache | |
363 | * | |
364 | * @map: map to operate on | |
365 | * @min: first register to discard | |
366 | * @max: last register to discard | |
367 | * | |
368 | * Discard part of the register cache. | |
369 | * | |
370 | * Return a negative value on failure, 0 on success. | |
371 | */ | |
372 | int regcache_drop_region(struct regmap *map, unsigned int min, | |
373 | unsigned int max) | |
374 | { | |
375 | unsigned int reg; | |
376 | int ret = 0; | |
377 | ||
378 | if (!map->cache_present && !(map->cache_ops && map->cache_ops->drop)) | |
379 | return -EINVAL; | |
380 | ||
381 | map->lock(map); | |
382 | ||
383 | trace_regcache_drop_region(map->dev, min, max); | |
384 | ||
385 | if (map->cache_present) | |
386 | for (reg = min; reg < max + 1; reg++) | |
387 | clear_bit(reg, map->cache_present); | |
388 | ||
389 | if (map->cache_ops && map->cache_ops->drop) | |
390 | ret = map->cache_ops->drop(map, min, max); | |
391 | ||
392 | map->unlock(map); | |
393 | ||
394 | return ret; | |
395 | } | |
396 | EXPORT_SYMBOL_GPL(regcache_drop_region); | |
397 | ||
92afb286 MB |
398 | /** |
399 | * regcache_cache_only: Put a register map into cache only mode | |
400 | * | |
401 | * @map: map to configure | |
402 | * @cache_only: flag if changes should be written to the hardware | |
403 | * | |
404 | * When a register map is marked as cache only writes to the register | |
405 | * map API will only update the register cache, they will not cause | |
406 | * any hardware changes. This is useful for allowing portions of | |
407 | * drivers to act as though the device were functioning as normal when | |
408 | * it is disabled for power saving reasons. | |
409 | */ | |
410 | void regcache_cache_only(struct regmap *map, bool enable) | |
411 | { | |
bacdbe07 | 412 | map->lock(map); |
ac77a765 | 413 | WARN_ON(map->cache_bypass && enable); |
92afb286 | 414 | map->cache_only = enable; |
5d5b7d4f | 415 | trace_regmap_cache_only(map->dev, enable); |
bacdbe07 | 416 | map->unlock(map); |
92afb286 MB |
417 | } |
418 | EXPORT_SYMBOL_GPL(regcache_cache_only); | |
419 | ||
8ae0d7e8 MB |
420 | /** |
421 | * regcache_mark_dirty: Mark the register cache as dirty | |
422 | * | |
423 | * @map: map to mark | |
424 | * | |
425 | * Mark the register cache as dirty, for example due to the device | |
426 | * having been powered down for suspend. If the cache is not marked | |
427 | * as dirty then the cache sync will be suppressed. | |
428 | */ | |
429 | void regcache_mark_dirty(struct regmap *map) | |
430 | { | |
bacdbe07 | 431 | map->lock(map); |
8ae0d7e8 | 432 | map->cache_dirty = true; |
bacdbe07 | 433 | map->unlock(map); |
8ae0d7e8 MB |
434 | } |
435 | EXPORT_SYMBOL_GPL(regcache_mark_dirty); | |
436 | ||
6eb0f5e0 DP |
437 | /** |
438 | * regcache_cache_bypass: Put a register map into cache bypass mode | |
439 | * | |
440 | * @map: map to configure | |
0eef6b04 | 441 | * @cache_bypass: flag if changes should not be written to the hardware |
6eb0f5e0 DP |
442 | * |
443 | * When a register map is marked with the cache bypass option, writes | |
444 | * to the register map API will only update the hardware and not the | |
445 | * the cache directly. This is useful when syncing the cache back to | |
446 | * the hardware. | |
447 | */ | |
448 | void regcache_cache_bypass(struct regmap *map, bool enable) | |
449 | { | |
bacdbe07 | 450 | map->lock(map); |
ac77a765 | 451 | WARN_ON(map->cache_only && enable); |
6eb0f5e0 | 452 | map->cache_bypass = enable; |
5d5b7d4f | 453 | trace_regmap_cache_bypass(map->dev, enable); |
bacdbe07 | 454 | map->unlock(map); |
6eb0f5e0 DP |
455 | } |
456 | EXPORT_SYMBOL_GPL(regcache_cache_bypass); | |
457 | ||
78493f2d MB |
458 | int regcache_set_reg_present(struct regmap *map, unsigned int reg) |
459 | { | |
460 | unsigned long *cache_present; | |
461 | unsigned int cache_present_size; | |
462 | unsigned int nregs; | |
463 | int i; | |
464 | ||
465 | nregs = reg + 1; | |
466 | cache_present_size = BITS_TO_LONGS(nregs); | |
467 | cache_present_size *= sizeof(long); | |
468 | ||
469 | if (!map->cache_present) { | |
470 | cache_present = kmalloc(cache_present_size, GFP_KERNEL); | |
471 | if (!cache_present) | |
472 | return -ENOMEM; | |
473 | bitmap_zero(cache_present, nregs); | |
474 | map->cache_present = cache_present; | |
475 | map->cache_present_nbits = nregs; | |
476 | } | |
477 | ||
478 | if (nregs > map->cache_present_nbits) { | |
479 | cache_present = krealloc(map->cache_present, | |
480 | cache_present_size, GFP_KERNEL); | |
481 | if (!cache_present) | |
482 | return -ENOMEM; | |
483 | for (i = 0; i < nregs; i++) | |
484 | if (i >= map->cache_present_nbits) | |
485 | clear_bit(i, cache_present); | |
486 | map->cache_present = cache_present; | |
487 | map->cache_present_nbits = nregs; | |
488 | } | |
489 | ||
490 | set_bit(reg, map->cache_present); | |
491 | return 0; | |
492 | } | |
493 | ||
879082c9 MB |
494 | bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, |
495 | unsigned int val) | |
9fabe24e | 496 | { |
325acab4 MB |
497 | if (regcache_get_val(map, base, idx) == val) |
498 | return true; | |
499 | ||
eb4cb76f MB |
500 | /* Use device native format if possible */ |
501 | if (map->format.format_val) { | |
502 | map->format.format_val(base + (map->cache_word_size * idx), | |
503 | val, 0); | |
504 | return false; | |
505 | } | |
506 | ||
879082c9 | 507 | switch (map->cache_word_size) { |
9fabe24e DP |
508 | case 1: { |
509 | u8 *cache = base; | |
9fabe24e DP |
510 | cache[idx] = val; |
511 | break; | |
512 | } | |
513 | case 2: { | |
514 | u16 *cache = base; | |
9fabe24e DP |
515 | cache[idx] = val; |
516 | break; | |
517 | } | |
7d5e525b MB |
518 | case 4: { |
519 | u32 *cache = base; | |
7d5e525b MB |
520 | cache[idx] = val; |
521 | break; | |
522 | } | |
9fabe24e DP |
523 | default: |
524 | BUG(); | |
525 | } | |
9fabe24e DP |
526 | return false; |
527 | } | |
528 | ||
879082c9 MB |
529 | unsigned int regcache_get_val(struct regmap *map, const void *base, |
530 | unsigned int idx) | |
9fabe24e DP |
531 | { |
532 | if (!base) | |
533 | return -EINVAL; | |
534 | ||
eb4cb76f MB |
535 | /* Use device native format if possible */ |
536 | if (map->format.parse_val) | |
8817796b MB |
537 | return map->format.parse_val(regcache_get_val_addr(map, base, |
538 | idx)); | |
eb4cb76f | 539 | |
879082c9 | 540 | switch (map->cache_word_size) { |
9fabe24e DP |
541 | case 1: { |
542 | const u8 *cache = base; | |
543 | return cache[idx]; | |
544 | } | |
545 | case 2: { | |
546 | const u16 *cache = base; | |
547 | return cache[idx]; | |
548 | } | |
7d5e525b MB |
549 | case 4: { |
550 | const u32 *cache = base; | |
551 | return cache[idx]; | |
552 | } | |
9fabe24e DP |
553 | default: |
554 | BUG(); | |
555 | } | |
556 | /* unreachable */ | |
557 | return -1; | |
558 | } | |
559 | ||
f094fea6 | 560 | static int regcache_default_cmp(const void *a, const void *b) |
c08604b8 DP |
561 | { |
562 | const struct reg_default *_a = a; | |
563 | const struct reg_default *_b = b; | |
564 | ||
565 | return _a->reg - _b->reg; | |
566 | } | |
567 | ||
f094fea6 MB |
568 | int regcache_lookup_reg(struct regmap *map, unsigned int reg) |
569 | { | |
570 | struct reg_default key; | |
571 | struct reg_default *r; | |
572 | ||
573 | key.reg = reg; | |
574 | key.def = 0; | |
575 | ||
576 | r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, | |
577 | sizeof(struct reg_default), regcache_default_cmp); | |
578 | ||
579 | if (r) | |
580 | return r - map->reg_defaults; | |
581 | else | |
6e6ace00 | 582 | return -ENOENT; |
f094fea6 | 583 | } |
f8bd822c | 584 | |
cfdeb8c3 MB |
585 | static int regcache_sync_block_single(struct regmap *map, void *block, |
586 | unsigned int block_base, | |
587 | unsigned int start, unsigned int end) | |
588 | { | |
589 | unsigned int i, regtmp, val; | |
590 | int ret; | |
591 | ||
592 | for (i = start; i < end; i++) { | |
593 | regtmp = block_base + (i * map->reg_stride); | |
594 | ||
595 | if (!regcache_reg_present(map, regtmp)) | |
596 | continue; | |
597 | ||
598 | val = regcache_get_val(map, block, i); | |
599 | ||
600 | /* Is this the hardware default? If so skip. */ | |
601 | ret = regcache_lookup_reg(map, regtmp); | |
602 | if (ret >= 0 && val == map->reg_defaults[ret].def) | |
603 | continue; | |
604 | ||
605 | map->cache_bypass = 1; | |
606 | ||
607 | ret = _regmap_write(map, regtmp, val); | |
608 | ||
609 | map->cache_bypass = 0; | |
610 | if (ret != 0) | |
611 | return ret; | |
612 | dev_dbg(map->dev, "Synced register %#x, value %#x\n", | |
613 | regtmp, val); | |
614 | } | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
75a5f89f MB |
619 | static int regcache_sync_block_raw_flush(struct regmap *map, const void **data, |
620 | unsigned int base, unsigned int cur) | |
621 | { | |
622 | size_t val_bytes = map->format.val_bytes; | |
623 | int ret, count; | |
624 | ||
625 | if (*data == NULL) | |
626 | return 0; | |
627 | ||
628 | count = cur - base; | |
629 | ||
9659293c | 630 | dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n", |
75a5f89f MB |
631 | count * val_bytes, count, base, cur - 1); |
632 | ||
633 | map->cache_bypass = 1; | |
634 | ||
635 | ret = _regmap_raw_write(map, base, *data, count * val_bytes, | |
636 | false); | |
637 | ||
638 | map->cache_bypass = 0; | |
639 | ||
640 | *data = NULL; | |
641 | ||
642 | return ret; | |
643 | } | |
644 | ||
f52687af | 645 | static int regcache_sync_block_raw(struct regmap *map, void *block, |
cfdeb8c3 MB |
646 | unsigned int block_base, unsigned int start, |
647 | unsigned int end) | |
f8bd822c | 648 | { |
75a5f89f MB |
649 | unsigned int i, val; |
650 | unsigned int regtmp = 0; | |
651 | unsigned int base = 0; | |
652 | const void *data = NULL; | |
f8bd822c MB |
653 | int ret; |
654 | ||
655 | for (i = start; i < end; i++) { | |
656 | regtmp = block_base + (i * map->reg_stride); | |
657 | ||
75a5f89f MB |
658 | if (!regcache_reg_present(map, regtmp)) { |
659 | ret = regcache_sync_block_raw_flush(map, &data, | |
660 | base, regtmp); | |
661 | if (ret != 0) | |
662 | return ret; | |
f8bd822c | 663 | continue; |
75a5f89f | 664 | } |
f8bd822c MB |
665 | |
666 | val = regcache_get_val(map, block, i); | |
667 | ||
668 | /* Is this the hardware default? If so skip. */ | |
669 | ret = regcache_lookup_reg(map, regtmp); | |
75a5f89f MB |
670 | if (ret >= 0 && val == map->reg_defaults[ret].def) { |
671 | ret = regcache_sync_block_raw_flush(map, &data, | |
672 | base, regtmp); | |
673 | if (ret != 0) | |
674 | return ret; | |
f8bd822c | 675 | continue; |
75a5f89f | 676 | } |
f8bd822c | 677 | |
75a5f89f MB |
678 | if (!data) { |
679 | data = regcache_get_val_addr(map, block, i); | |
680 | base = regtmp; | |
681 | } | |
f8bd822c MB |
682 | } |
683 | ||
75a5f89f | 684 | return regcache_sync_block_raw_flush(map, &data, base, regtmp); |
f8bd822c | 685 | } |
cfdeb8c3 MB |
686 | |
687 | int regcache_sync_block(struct regmap *map, void *block, | |
688 | unsigned int block_base, unsigned int start, | |
689 | unsigned int end) | |
690 | { | |
691 | if (regmap_can_raw_write(map)) | |
692 | return regcache_sync_block_raw(map, block, block_base, | |
693 | start, end); | |
694 | else | |
695 | return regcache_sync_block_single(map, block, block_base, | |
696 | start, end); | |
697 | } |