Commit | Line | Data |
---|---|---|
9fabe24e DP |
1 | /* |
2 | * Register cache access API | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/slab.h> | |
1b6bc32f | 14 | #include <linux/export.h> |
51990e82 | 15 | #include <linux/device.h> |
9fabe24e | 16 | #include <trace/events/regmap.h> |
f094fea6 | 17 | #include <linux/bsearch.h> |
c08604b8 | 18 | #include <linux/sort.h> |
9fabe24e DP |
19 | |
20 | #include "internal.h" | |
21 | ||
22 | static const struct regcache_ops *cache_types[] = { | |
28644c80 | 23 | ®cache_rbtree_ops, |
2cbbb579 | 24 | ®cache_lzo_ops, |
2ac902ce | 25 | ®cache_flat_ops, |
9fabe24e DP |
26 | }; |
27 | ||
28 | static int regcache_hw_init(struct regmap *map) | |
29 | { | |
30 | int i, j; | |
31 | int ret; | |
32 | int count; | |
33 | unsigned int val; | |
34 | void *tmp_buf; | |
35 | ||
36 | if (!map->num_reg_defaults_raw) | |
37 | return -EINVAL; | |
38 | ||
39 | if (!map->reg_defaults_raw) { | |
df00c79f | 40 | u32 cache_bypass = map->cache_bypass; |
9fabe24e | 41 | dev_warn(map->dev, "No cache defaults, reading back from HW\n"); |
df00c79f LD |
42 | |
43 | /* Bypass the cache access till data read from HW*/ | |
44 | map->cache_bypass = 1; | |
9fabe24e DP |
45 | tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); |
46 | if (!tmp_buf) | |
47 | return -EINVAL; | |
48 | ret = regmap_bulk_read(map, 0, tmp_buf, | |
49 | map->num_reg_defaults_raw); | |
df00c79f | 50 | map->cache_bypass = cache_bypass; |
9fabe24e DP |
51 | if (ret < 0) { |
52 | kfree(tmp_buf); | |
53 | return ret; | |
54 | } | |
55 | map->reg_defaults_raw = tmp_buf; | |
56 | map->cache_free = 1; | |
57 | } | |
58 | ||
59 | /* calculate the size of reg_defaults */ | |
60 | for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) { | |
879082c9 | 61 | val = regcache_get_val(map, map->reg_defaults_raw, i); |
f01ee60f | 62 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e DP |
63 | continue; |
64 | count++; | |
65 | } | |
66 | ||
67 | map->reg_defaults = kmalloc(count * sizeof(struct reg_default), | |
68 | GFP_KERNEL); | |
021cd616 LPC |
69 | if (!map->reg_defaults) { |
70 | ret = -ENOMEM; | |
71 | goto err_free; | |
72 | } | |
9fabe24e DP |
73 | |
74 | /* fill the reg_defaults */ | |
75 | map->num_reg_defaults = count; | |
76 | for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { | |
879082c9 | 77 | val = regcache_get_val(map, map->reg_defaults_raw, i); |
f01ee60f | 78 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e | 79 | continue; |
f01ee60f | 80 | map->reg_defaults[j].reg = i * map->reg_stride; |
9fabe24e DP |
81 | map->reg_defaults[j].def = val; |
82 | j++; | |
83 | } | |
84 | ||
85 | return 0; | |
021cd616 LPC |
86 | |
87 | err_free: | |
88 | if (map->cache_free) | |
89 | kfree(map->reg_defaults_raw); | |
90 | ||
91 | return ret; | |
9fabe24e DP |
92 | } |
93 | ||
e5e3b8ab | 94 | int regcache_init(struct regmap *map, const struct regmap_config *config) |
9fabe24e DP |
95 | { |
96 | int ret; | |
97 | int i; | |
98 | void *tmp_buf; | |
99 | ||
f01ee60f SW |
100 | for (i = 0; i < config->num_reg_defaults; i++) |
101 | if (config->reg_defaults[i].reg % map->reg_stride) | |
102 | return -EINVAL; | |
103 | ||
e7a6db30 MB |
104 | if (map->cache_type == REGCACHE_NONE) { |
105 | map->cache_bypass = true; | |
9fabe24e | 106 | return 0; |
e7a6db30 | 107 | } |
9fabe24e DP |
108 | |
109 | for (i = 0; i < ARRAY_SIZE(cache_types); i++) | |
110 | if (cache_types[i]->type == map->cache_type) | |
111 | break; | |
112 | ||
113 | if (i == ARRAY_SIZE(cache_types)) { | |
114 | dev_err(map->dev, "Could not match compress type: %d\n", | |
115 | map->cache_type); | |
116 | return -EINVAL; | |
117 | } | |
118 | ||
e5e3b8ab LPC |
119 | map->num_reg_defaults = config->num_reg_defaults; |
120 | map->num_reg_defaults_raw = config->num_reg_defaults_raw; | |
121 | map->reg_defaults_raw = config->reg_defaults_raw; | |
064d4db1 LPC |
122 | map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); |
123 | map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; | |
e5e3b8ab | 124 | |
9fabe24e DP |
125 | map->cache = NULL; |
126 | map->cache_ops = cache_types[i]; | |
127 | ||
128 | if (!map->cache_ops->read || | |
129 | !map->cache_ops->write || | |
130 | !map->cache_ops->name) | |
131 | return -EINVAL; | |
132 | ||
133 | /* We still need to ensure that the reg_defaults | |
134 | * won't vanish from under us. We'll need to make | |
135 | * a copy of it. | |
136 | */ | |
720e4616 | 137 | if (config->reg_defaults) { |
9fabe24e DP |
138 | if (!map->num_reg_defaults) |
139 | return -EINVAL; | |
720e4616 | 140 | tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * |
9fabe24e DP |
141 | sizeof(struct reg_default), GFP_KERNEL); |
142 | if (!tmp_buf) | |
143 | return -ENOMEM; | |
144 | map->reg_defaults = tmp_buf; | |
8528bdd4 | 145 | } else if (map->num_reg_defaults_raw) { |
5fcd2560 | 146 | /* Some devices such as PMICs don't have cache defaults, |
9fabe24e DP |
147 | * we cope with this by reading back the HW registers and |
148 | * crafting the cache defaults by hand. | |
149 | */ | |
150 | ret = regcache_hw_init(map); | |
151 | if (ret < 0) | |
152 | return ret; | |
153 | } | |
154 | ||
155 | if (!map->max_register) | |
156 | map->max_register = map->num_reg_defaults_raw; | |
157 | ||
158 | if (map->cache_ops->init) { | |
159 | dev_dbg(map->dev, "Initializing %s cache\n", | |
160 | map->cache_ops->name); | |
bd061c78 LPC |
161 | ret = map->cache_ops->init(map); |
162 | if (ret) | |
163 | goto err_free; | |
9fabe24e DP |
164 | } |
165 | return 0; | |
bd061c78 LPC |
166 | |
167 | err_free: | |
168 | kfree(map->reg_defaults); | |
169 | if (map->cache_free) | |
170 | kfree(map->reg_defaults_raw); | |
171 | ||
172 | return ret; | |
9fabe24e DP |
173 | } |
174 | ||
175 | void regcache_exit(struct regmap *map) | |
176 | { | |
177 | if (map->cache_type == REGCACHE_NONE) | |
178 | return; | |
179 | ||
180 | BUG_ON(!map->cache_ops); | |
181 | ||
182 | kfree(map->reg_defaults); | |
183 | if (map->cache_free) | |
184 | kfree(map->reg_defaults_raw); | |
185 | ||
186 | if (map->cache_ops->exit) { | |
187 | dev_dbg(map->dev, "Destroying %s cache\n", | |
188 | map->cache_ops->name); | |
189 | map->cache_ops->exit(map); | |
190 | } | |
191 | } | |
192 | ||
193 | /** | |
194 | * regcache_read: Fetch the value of a given register from the cache. | |
195 | * | |
196 | * @map: map to configure. | |
197 | * @reg: The register index. | |
198 | * @value: The value to be returned. | |
199 | * | |
200 | * Return a negative value on failure, 0 on success. | |
201 | */ | |
202 | int regcache_read(struct regmap *map, | |
203 | unsigned int reg, unsigned int *value) | |
204 | { | |
bc7ee556 MB |
205 | int ret; |
206 | ||
9fabe24e DP |
207 | if (map->cache_type == REGCACHE_NONE) |
208 | return -ENOSYS; | |
209 | ||
210 | BUG_ON(!map->cache_ops); | |
211 | ||
bc7ee556 MB |
212 | if (!regmap_volatile(map, reg)) { |
213 | ret = map->cache_ops->read(map, reg, value); | |
214 | ||
215 | if (ret == 0) | |
216 | trace_regmap_reg_read_cache(map->dev, reg, *value); | |
217 | ||
218 | return ret; | |
219 | } | |
9fabe24e DP |
220 | |
221 | return -EINVAL; | |
222 | } | |
9fabe24e DP |
223 | |
224 | /** | |
225 | * regcache_write: Set the value of a given register in the cache. | |
226 | * | |
227 | * @map: map to configure. | |
228 | * @reg: The register index. | |
229 | * @value: The new register value. | |
230 | * | |
231 | * Return a negative value on failure, 0 on success. | |
232 | */ | |
233 | int regcache_write(struct regmap *map, | |
234 | unsigned int reg, unsigned int value) | |
235 | { | |
236 | if (map->cache_type == REGCACHE_NONE) | |
237 | return 0; | |
238 | ||
239 | BUG_ON(!map->cache_ops); | |
240 | ||
241 | if (!regmap_writeable(map, reg)) | |
242 | return -EIO; | |
243 | ||
244 | if (!regmap_volatile(map, reg)) | |
245 | return map->cache_ops->write(map, reg, value); | |
246 | ||
247 | return 0; | |
248 | } | |
9fabe24e DP |
249 | |
250 | /** | |
251 | * regcache_sync: Sync the register cache with the hardware. | |
252 | * | |
253 | * @map: map to configure. | |
254 | * | |
255 | * Any registers that should not be synced should be marked as | |
256 | * volatile. In general drivers can choose not to use the provided | |
257 | * syncing functionality if they so require. | |
258 | * | |
259 | * Return a negative value on failure, 0 on success. | |
260 | */ | |
261 | int regcache_sync(struct regmap *map) | |
262 | { | |
954757d7 | 263 | int ret = 0; |
954757d7 | 264 | unsigned int i; |
59360089 | 265 | const char *name; |
beb1a10f | 266 | unsigned int bypass; |
59360089 | 267 | |
c3ec2328 | 268 | BUG_ON(!map->cache_ops || !map->cache_ops->sync); |
9fabe24e | 269 | |
bacdbe07 | 270 | map->lock(map); |
beb1a10f DP |
271 | /* Remember the initial bypass state */ |
272 | bypass = map->cache_bypass; | |
954757d7 DP |
273 | dev_dbg(map->dev, "Syncing %s cache\n", |
274 | map->cache_ops->name); | |
275 | name = map->cache_ops->name; | |
276 | trace_regcache_sync(map->dev, name, "start"); | |
22f0d90a | 277 | |
8ae0d7e8 MB |
278 | if (!map->cache_dirty) |
279 | goto out; | |
d9db7627 | 280 | |
22f0d90a | 281 | /* Apply any patch first */ |
8a892d69 | 282 | map->cache_bypass = 1; |
22f0d90a | 283 | for (i = 0; i < map->patch_regs; i++) { |
f01ee60f SW |
284 | if (map->patch[i].reg % map->reg_stride) { |
285 | ret = -EINVAL; | |
286 | goto out; | |
287 | } | |
22f0d90a MB |
288 | ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); |
289 | if (ret != 0) { | |
290 | dev_err(map->dev, "Failed to write %x = %x: %d\n", | |
291 | map->patch[i].reg, map->patch[i].def, ret); | |
292 | goto out; | |
293 | } | |
294 | } | |
8a892d69 | 295 | map->cache_bypass = 0; |
22f0d90a | 296 | |
ac8d91c8 | 297 | ret = map->cache_ops->sync(map, 0, map->max_register); |
954757d7 | 298 | |
6ff73738 MB |
299 | if (ret == 0) |
300 | map->cache_dirty = false; | |
954757d7 | 301 | |
954757d7 DP |
302 | out: |
303 | trace_regcache_sync(map->dev, name, "stop"); | |
beb1a10f DP |
304 | /* Restore the bypass state */ |
305 | map->cache_bypass = bypass; | |
bacdbe07 | 306 | map->unlock(map); |
954757d7 DP |
307 | |
308 | return ret; | |
9fabe24e DP |
309 | } |
310 | EXPORT_SYMBOL_GPL(regcache_sync); | |
311 | ||
4d4cfd16 MB |
312 | /** |
313 | * regcache_sync_region: Sync part of the register cache with the hardware. | |
314 | * | |
315 | * @map: map to sync. | |
316 | * @min: first register to sync | |
317 | * @max: last register to sync | |
318 | * | |
319 | * Write all non-default register values in the specified region to | |
320 | * the hardware. | |
321 | * | |
322 | * Return a negative value on failure, 0 on success. | |
323 | */ | |
324 | int regcache_sync_region(struct regmap *map, unsigned int min, | |
325 | unsigned int max) | |
326 | { | |
327 | int ret = 0; | |
328 | const char *name; | |
329 | unsigned int bypass; | |
330 | ||
331 | BUG_ON(!map->cache_ops || !map->cache_ops->sync); | |
332 | ||
bacdbe07 | 333 | map->lock(map); |
4d4cfd16 MB |
334 | |
335 | /* Remember the initial bypass state */ | |
336 | bypass = map->cache_bypass; | |
337 | ||
338 | name = map->cache_ops->name; | |
339 | dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); | |
340 | ||
341 | trace_regcache_sync(map->dev, name, "start region"); | |
342 | ||
343 | if (!map->cache_dirty) | |
344 | goto out; | |
345 | ||
346 | ret = map->cache_ops->sync(map, min, max); | |
347 | ||
348 | out: | |
349 | trace_regcache_sync(map->dev, name, "stop region"); | |
350 | /* Restore the bypass state */ | |
351 | map->cache_bypass = bypass; | |
bacdbe07 | 352 | map->unlock(map); |
4d4cfd16 MB |
353 | |
354 | return ret; | |
355 | } | |
e466de05 | 356 | EXPORT_SYMBOL_GPL(regcache_sync_region); |
4d4cfd16 | 357 | |
92afb286 MB |
358 | /** |
359 | * regcache_cache_only: Put a register map into cache only mode | |
360 | * | |
361 | * @map: map to configure | |
362 | * @cache_only: flag if changes should be written to the hardware | |
363 | * | |
364 | * When a register map is marked as cache only writes to the register | |
365 | * map API will only update the register cache, they will not cause | |
366 | * any hardware changes. This is useful for allowing portions of | |
367 | * drivers to act as though the device were functioning as normal when | |
368 | * it is disabled for power saving reasons. | |
369 | */ | |
370 | void regcache_cache_only(struct regmap *map, bool enable) | |
371 | { | |
bacdbe07 | 372 | map->lock(map); |
ac77a765 | 373 | WARN_ON(map->cache_bypass && enable); |
92afb286 | 374 | map->cache_only = enable; |
5d5b7d4f | 375 | trace_regmap_cache_only(map->dev, enable); |
bacdbe07 | 376 | map->unlock(map); |
92afb286 MB |
377 | } |
378 | EXPORT_SYMBOL_GPL(regcache_cache_only); | |
379 | ||
8ae0d7e8 MB |
380 | /** |
381 | * regcache_mark_dirty: Mark the register cache as dirty | |
382 | * | |
383 | * @map: map to mark | |
384 | * | |
385 | * Mark the register cache as dirty, for example due to the device | |
386 | * having been powered down for suspend. If the cache is not marked | |
387 | * as dirty then the cache sync will be suppressed. | |
388 | */ | |
389 | void regcache_mark_dirty(struct regmap *map) | |
390 | { | |
bacdbe07 | 391 | map->lock(map); |
8ae0d7e8 | 392 | map->cache_dirty = true; |
bacdbe07 | 393 | map->unlock(map); |
8ae0d7e8 MB |
394 | } |
395 | EXPORT_SYMBOL_GPL(regcache_mark_dirty); | |
396 | ||
6eb0f5e0 DP |
397 | /** |
398 | * regcache_cache_bypass: Put a register map into cache bypass mode | |
399 | * | |
400 | * @map: map to configure | |
0eef6b04 | 401 | * @cache_bypass: flag if changes should not be written to the hardware |
6eb0f5e0 DP |
402 | * |
403 | * When a register map is marked with the cache bypass option, writes | |
404 | * to the register map API will only update the hardware and not the | |
405 | * the cache directly. This is useful when syncing the cache back to | |
406 | * the hardware. | |
407 | */ | |
408 | void regcache_cache_bypass(struct regmap *map, bool enable) | |
409 | { | |
bacdbe07 | 410 | map->lock(map); |
ac77a765 | 411 | WARN_ON(map->cache_only && enable); |
6eb0f5e0 | 412 | map->cache_bypass = enable; |
5d5b7d4f | 413 | trace_regmap_cache_bypass(map->dev, enable); |
bacdbe07 | 414 | map->unlock(map); |
6eb0f5e0 DP |
415 | } |
416 | EXPORT_SYMBOL_GPL(regcache_cache_bypass); | |
417 | ||
879082c9 MB |
418 | bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, |
419 | unsigned int val) | |
9fabe24e | 420 | { |
879082c9 | 421 | switch (map->cache_word_size) { |
9fabe24e DP |
422 | case 1: { |
423 | u8 *cache = base; | |
424 | if (cache[idx] == val) | |
425 | return true; | |
426 | cache[idx] = val; | |
427 | break; | |
428 | } | |
429 | case 2: { | |
430 | u16 *cache = base; | |
431 | if (cache[idx] == val) | |
432 | return true; | |
433 | cache[idx] = val; | |
434 | break; | |
435 | } | |
7d5e525b MB |
436 | case 4: { |
437 | u32 *cache = base; | |
438 | if (cache[idx] == val) | |
439 | return true; | |
440 | cache[idx] = val; | |
441 | break; | |
442 | } | |
9fabe24e DP |
443 | default: |
444 | BUG(); | |
445 | } | |
9fabe24e DP |
446 | return false; |
447 | } | |
448 | ||
879082c9 MB |
449 | unsigned int regcache_get_val(struct regmap *map, const void *base, |
450 | unsigned int idx) | |
9fabe24e DP |
451 | { |
452 | if (!base) | |
453 | return -EINVAL; | |
454 | ||
879082c9 | 455 | switch (map->cache_word_size) { |
9fabe24e DP |
456 | case 1: { |
457 | const u8 *cache = base; | |
458 | return cache[idx]; | |
459 | } | |
460 | case 2: { | |
461 | const u16 *cache = base; | |
462 | return cache[idx]; | |
463 | } | |
7d5e525b MB |
464 | case 4: { |
465 | const u32 *cache = base; | |
466 | return cache[idx]; | |
467 | } | |
9fabe24e DP |
468 | default: |
469 | BUG(); | |
470 | } | |
471 | /* unreachable */ | |
472 | return -1; | |
473 | } | |
474 | ||
f094fea6 | 475 | static int regcache_default_cmp(const void *a, const void *b) |
c08604b8 DP |
476 | { |
477 | const struct reg_default *_a = a; | |
478 | const struct reg_default *_b = b; | |
479 | ||
480 | return _a->reg - _b->reg; | |
481 | } | |
482 | ||
f094fea6 MB |
483 | int regcache_lookup_reg(struct regmap *map, unsigned int reg) |
484 | { | |
485 | struct reg_default key; | |
486 | struct reg_default *r; | |
487 | ||
488 | key.reg = reg; | |
489 | key.def = 0; | |
490 | ||
491 | r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, | |
492 | sizeof(struct reg_default), regcache_default_cmp); | |
493 | ||
494 | if (r) | |
495 | return r - map->reg_defaults; | |
496 | else | |
6e6ace00 | 497 | return -ENOENT; |
f094fea6 | 498 | } |