regmap: Skip hardware defaults for LZO caches
[deliverable/linux.git] / drivers / base / regmap / regcache.c
CommitLineData
9fabe24e
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1/*
2 * Register cache access API
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/slab.h>
1b6bc32f 14#include <linux/export.h>
9fabe24e 15#include <trace/events/regmap.h>
f094fea6 16#include <linux/bsearch.h>
c08604b8 17#include <linux/sort.h>
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18
19#include "internal.h"
20
21static const struct regcache_ops *cache_types[] = {
28644c80 22 &regcache_rbtree_ops,
2cbbb579 23 &regcache_lzo_ops,
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24};
25
26static int regcache_hw_init(struct regmap *map)
27{
28 int i, j;
29 int ret;
30 int count;
31 unsigned int val;
32 void *tmp_buf;
33
34 if (!map->num_reg_defaults_raw)
35 return -EINVAL;
36
37 if (!map->reg_defaults_raw) {
38 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
39 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
40 if (!tmp_buf)
41 return -EINVAL;
42 ret = regmap_bulk_read(map, 0, tmp_buf,
43 map->num_reg_defaults_raw);
44 if (ret < 0) {
45 kfree(tmp_buf);
46 return ret;
47 }
48 map->reg_defaults_raw = tmp_buf;
49 map->cache_free = 1;
50 }
51
52 /* calculate the size of reg_defaults */
53 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) {
54 val = regcache_get_val(map->reg_defaults_raw,
55 i, map->cache_word_size);
56 if (!val)
57 continue;
58 count++;
59 }
60
61 map->reg_defaults = kmalloc(count * sizeof(struct reg_default),
62 GFP_KERNEL);
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63 if (!map->reg_defaults) {
64 ret = -ENOMEM;
65 goto err_free;
66 }
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67
68 /* fill the reg_defaults */
69 map->num_reg_defaults = count;
70 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
71 val = regcache_get_val(map->reg_defaults_raw,
72 i, map->cache_word_size);
73 if (!val)
74 continue;
75 map->reg_defaults[j].reg = i;
76 map->reg_defaults[j].def = val;
77 j++;
78 }
79
80 return 0;
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81
82err_free:
83 if (map->cache_free)
84 kfree(map->reg_defaults_raw);
85
86 return ret;
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87}
88
e5e3b8ab 89int regcache_init(struct regmap *map, const struct regmap_config *config)
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90{
91 int ret;
92 int i;
93 void *tmp_buf;
94
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95 if (map->cache_type == REGCACHE_NONE) {
96 map->cache_bypass = true;
9fabe24e 97 return 0;
e7a6db30 98 }
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99
100 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
101 if (cache_types[i]->type == map->cache_type)
102 break;
103
104 if (i == ARRAY_SIZE(cache_types)) {
105 dev_err(map->dev, "Could not match compress type: %d\n",
106 map->cache_type);
107 return -EINVAL;
108 }
109
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110 map->num_reg_defaults = config->num_reg_defaults;
111 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
112 map->reg_defaults_raw = config->reg_defaults_raw;
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113 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
114 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
e5e3b8ab 115
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116 map->cache = NULL;
117 map->cache_ops = cache_types[i];
118
119 if (!map->cache_ops->read ||
120 !map->cache_ops->write ||
121 !map->cache_ops->name)
122 return -EINVAL;
123
124 /* We still need to ensure that the reg_defaults
125 * won't vanish from under us. We'll need to make
126 * a copy of it.
127 */
720e4616 128 if (config->reg_defaults) {
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129 if (!map->num_reg_defaults)
130 return -EINVAL;
720e4616 131 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
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132 sizeof(struct reg_default), GFP_KERNEL);
133 if (!tmp_buf)
134 return -ENOMEM;
135 map->reg_defaults = tmp_buf;
8528bdd4 136 } else if (map->num_reg_defaults_raw) {
5fcd2560 137 /* Some devices such as PMICs don't have cache defaults,
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138 * we cope with this by reading back the HW registers and
139 * crafting the cache defaults by hand.
140 */
141 ret = regcache_hw_init(map);
142 if (ret < 0)
143 return ret;
144 }
145
146 if (!map->max_register)
147 map->max_register = map->num_reg_defaults_raw;
148
149 if (map->cache_ops->init) {
150 dev_dbg(map->dev, "Initializing %s cache\n",
151 map->cache_ops->name);
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152 ret = map->cache_ops->init(map);
153 if (ret)
154 goto err_free;
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155 }
156 return 0;
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157
158err_free:
159 kfree(map->reg_defaults);
160 if (map->cache_free)
161 kfree(map->reg_defaults_raw);
162
163 return ret;
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164}
165
166void regcache_exit(struct regmap *map)
167{
168 if (map->cache_type == REGCACHE_NONE)
169 return;
170
171 BUG_ON(!map->cache_ops);
172
173 kfree(map->reg_defaults);
174 if (map->cache_free)
175 kfree(map->reg_defaults_raw);
176
177 if (map->cache_ops->exit) {
178 dev_dbg(map->dev, "Destroying %s cache\n",
179 map->cache_ops->name);
180 map->cache_ops->exit(map);
181 }
182}
183
184/**
185 * regcache_read: Fetch the value of a given register from the cache.
186 *
187 * @map: map to configure.
188 * @reg: The register index.
189 * @value: The value to be returned.
190 *
191 * Return a negative value on failure, 0 on success.
192 */
193int regcache_read(struct regmap *map,
194 unsigned int reg, unsigned int *value)
195{
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196 int ret;
197
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198 if (map->cache_type == REGCACHE_NONE)
199 return -ENOSYS;
200
201 BUG_ON(!map->cache_ops);
202
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203 if (!regmap_volatile(map, reg)) {
204 ret = map->cache_ops->read(map, reg, value);
205
206 if (ret == 0)
207 trace_regmap_reg_read_cache(map->dev, reg, *value);
208
209 return ret;
210 }
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211
212 return -EINVAL;
213}
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214
215/**
216 * regcache_write: Set the value of a given register in the cache.
217 *
218 * @map: map to configure.
219 * @reg: The register index.
220 * @value: The new register value.
221 *
222 * Return a negative value on failure, 0 on success.
223 */
224int regcache_write(struct regmap *map,
225 unsigned int reg, unsigned int value)
226{
227 if (map->cache_type == REGCACHE_NONE)
228 return 0;
229
230 BUG_ON(!map->cache_ops);
231
232 if (!regmap_writeable(map, reg))
233 return -EIO;
234
235 if (!regmap_volatile(map, reg))
236 return map->cache_ops->write(map, reg, value);
237
238 return 0;
239}
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240
241/**
242 * regcache_sync: Sync the register cache with the hardware.
243 *
244 * @map: map to configure.
245 *
246 * Any registers that should not be synced should be marked as
247 * volatile. In general drivers can choose not to use the provided
248 * syncing functionality if they so require.
249 *
250 * Return a negative value on failure, 0 on success.
251 */
252int regcache_sync(struct regmap *map)
253{
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254 int ret = 0;
255 unsigned int val;
256 unsigned int i;
59360089 257 const char *name;
beb1a10f 258 unsigned int bypass;
59360089 259
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260 BUG_ON(!map->cache_ops);
261
13753a90 262 mutex_lock(&map->lock);
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263 /* Remember the initial bypass state */
264 bypass = map->cache_bypass;
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265 dev_dbg(map->dev, "Syncing %s cache\n",
266 map->cache_ops->name);
267 name = map->cache_ops->name;
268 trace_regcache_sync(map->dev, name, "start");
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269 if (!map->cache_dirty)
270 goto out;
9fabe24e 271 if (map->cache_ops->sync) {
59360089 272 ret = map->cache_ops->sync(map);
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273 } else {
274 for (i = 0; i < map->num_reg_defaults; i++) {
275 ret = regcache_read(map, i, &val);
276 if (ret < 0)
277 goto out;
ec8a365f 278 map->cache_bypass = 1;
13753a90 279 ret = _regmap_write(map, i, val);
ec8a365f 280 map->cache_bypass = 0;
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281 if (ret < 0)
282 goto out;
283 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
284 map->reg_defaults[i].reg,
285 map->reg_defaults[i].def);
286 }
287
9fabe24e 288 }
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289out:
290 trace_regcache_sync(map->dev, name, "stop");
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291 /* Restore the bypass state */
292 map->cache_bypass = bypass;
13753a90 293 mutex_unlock(&map->lock);
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294
295 return ret;
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296}
297EXPORT_SYMBOL_GPL(regcache_sync);
298
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299/**
300 * regcache_cache_only: Put a register map into cache only mode
301 *
302 * @map: map to configure
303 * @cache_only: flag if changes should be written to the hardware
304 *
305 * When a register map is marked as cache only writes to the register
306 * map API will only update the register cache, they will not cause
307 * any hardware changes. This is useful for allowing portions of
308 * drivers to act as though the device were functioning as normal when
309 * it is disabled for power saving reasons.
310 */
311void regcache_cache_only(struct regmap *map, bool enable)
312{
2cd148f1 313 mutex_lock(&map->lock);
ac77a765 314 WARN_ON(map->cache_bypass && enable);
92afb286 315 map->cache_only = enable;
2cd148f1 316 mutex_unlock(&map->lock);
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317}
318EXPORT_SYMBOL_GPL(regcache_cache_only);
319
8ae0d7e8
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320/**
321 * regcache_mark_dirty: Mark the register cache as dirty
322 *
323 * @map: map to mark
324 *
325 * Mark the register cache as dirty, for example due to the device
326 * having been powered down for suspend. If the cache is not marked
327 * as dirty then the cache sync will be suppressed.
328 */
329void regcache_mark_dirty(struct regmap *map)
330{
331 mutex_lock(&map->lock);
332 map->cache_dirty = true;
333 mutex_unlock(&map->lock);
334}
335EXPORT_SYMBOL_GPL(regcache_mark_dirty);
336
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337/**
338 * regcache_cache_bypass: Put a register map into cache bypass mode
339 *
340 * @map: map to configure
0eef6b04 341 * @cache_bypass: flag if changes should not be written to the hardware
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342 *
343 * When a register map is marked with the cache bypass option, writes
344 * to the register map API will only update the hardware and not the
345 * the cache directly. This is useful when syncing the cache back to
346 * the hardware.
347 */
348void regcache_cache_bypass(struct regmap *map, bool enable)
349{
350 mutex_lock(&map->lock);
ac77a765 351 WARN_ON(map->cache_only && enable);
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352 map->cache_bypass = enable;
353 mutex_unlock(&map->lock);
354}
355EXPORT_SYMBOL_GPL(regcache_cache_bypass);
356
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357bool regcache_set_val(void *base, unsigned int idx,
358 unsigned int val, unsigned int word_size)
359{
360 switch (word_size) {
361 case 1: {
362 u8 *cache = base;
363 if (cache[idx] == val)
364 return true;
365 cache[idx] = val;
366 break;
367 }
368 case 2: {
369 u16 *cache = base;
370 if (cache[idx] == val)
371 return true;
372 cache[idx] = val;
373 break;
374 }
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375 case 4: {
376 u32 *cache = base;
377 if (cache[idx] == val)
378 return true;
379 cache[idx] = val;
380 break;
381 }
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382 default:
383 BUG();
384 }
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385 return false;
386}
387
388unsigned int regcache_get_val(const void *base, unsigned int idx,
389 unsigned int word_size)
390{
391 if (!base)
392 return -EINVAL;
393
394 switch (word_size) {
395 case 1: {
396 const u8 *cache = base;
397 return cache[idx];
398 }
399 case 2: {
400 const u16 *cache = base;
401 return cache[idx];
402 }
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403 case 4: {
404 const u32 *cache = base;
405 return cache[idx];
406 }
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407 default:
408 BUG();
409 }
410 /* unreachable */
411 return -1;
412}
413
f094fea6 414static int regcache_default_cmp(const void *a, const void *b)
c08604b8
DP
415{
416 const struct reg_default *_a = a;
417 const struct reg_default *_b = b;
418
419 return _a->reg - _b->reg;
420}
421
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422int regcache_lookup_reg(struct regmap *map, unsigned int reg)
423{
424 struct reg_default key;
425 struct reg_default *r;
426
427 key.reg = reg;
428 key.def = 0;
429
430 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
431 sizeof(struct reg_default), regcache_default_cmp);
432
433 if (r)
434 return r - map->reg_defaults;
435 else
6e6ace00 436 return -ENOENT;
f094fea6 437}
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