[deliverable/linux.git] / drivers / bcma / driver_chipcommon_pmu.c

/*
 * Broadcom specific AMBA
 * ChipCommon Power Management Unit driver
 *
 * Copyright 2009, Michael Buesch <m@bues.ch>
 * Copyright 2007, Broadcom Corporation
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/export.h>
#include <linux/bcma/bcma.h>

static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
}

void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);

void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
			     u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);

void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
				 u32 offset, u32 mask, u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);

void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
				u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);

static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case 0x4313:
	case 0x4331:
	case 43224:
	case 43225:
		break;
	default:
		pr_err("PLL init unknown for device 0x%04X\n",
			bus->chipinfo.id);
	}
}

static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 min_msk = 0, max_msk = 0;

	switch (bus->chipinfo.id) {
	case 0x4313:
		min_msk = 0x200D;
		max_msk = 0xFFFF;
		break;
	case 0x4331:
	case 43224:
	case 43225:
		break;
	default:
		pr_err("PMU resource config unknown for device 0x%04X\n",
			bus->chipinfo.id);
	}

	/* Set the resource masks. */
	if (min_msk)
		bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
	if (max_msk)
		bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
}

void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case 0x4313:
	case 0x4331:
	case 43224:
	case 43225:
		break;
	default:
		pr_err("PMU switch/regulators init unknown for device "
			"0x%04X\n", bus->chipinfo.id);
	}
}

/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 val;

	val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
	if (enable) {
		val |= BCMA_CHIPCTL_4331_EXTPA_EN;
		if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
			val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	} else {
		val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
		val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	}
	bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
}

void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case 0x4313:
		bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
		break;
	case 0x4331:
	case 43431:
		/* Ext PA lines must be enabled for tx on BCM4331 */
		bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
		break;
	case 43224:
		if (bus->chipinfo.rev == 0) {
			pr_err("Workarounds for 43224 rev 0 not fully "
				"implemented\n");
			bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
		} else {
			bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
		}
		break;
	case 43225:
		break;
	default:
		pr_err("Workarounds unknown for device 0x%04X\n",
			bus->chipinfo.id);
	}
}

void bcma_pmu_init(struct bcma_drv_cc *cc)
{
	u32 pmucap;

	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);

	pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
		 pmucap);

	if (cc->pmu.rev == 1)
		bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
			      ~BCMA_CC_PMU_CTL_NOILPONW);
	else
		bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
			     BCMA_CC_PMU_CTL_NOILPONW);

	if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
		pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");

	bcma_pmu_pll_init(cc);
	bcma_pmu_resources_init(cc);
	bcma_pmu_swreg_init(cc);
	bcma_pmu_workarounds(cc);
}

u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case 0x4716:
	case 0x4748:
	case 47162:
	case 0x4313:
	case 0x5357:
	case 0x4749:
	case 53572:
		/* always 20Mhz */
		return 20000 * 1000;
	case 0x5356:
	case 0x5300:
		/* always 25Mhz */
		return 25000 * 1000;
	default:
		pr_warn("No ALP clock specified for %04X device, "
			"pmu rev. %d, using default %d Hz\n",
			bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
	}
	return BCMA_CC_PMU_ALP_CLOCK;
}

/* Find the output of the "m" pll divider given pll controls that start with
 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 */
static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
{
	u32 tmp, div, ndiv, p1, p2, fc;
	struct bcma_bus *bus = cc->core->bus;

	BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));

	BUG_ON(!m || m > 4);

	if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
		/* Detect failure in clock setting */
		tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
		if (tmp & 0x40000)
			return 133 * 1000000;
	}

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
	p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
	p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
	div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
		BCMA_CC_PPL_MDIV_MASK;

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;

	/* Do calculation in Mhz */
	fc = bcma_pmu_alp_clock(cc) / 1000000;
	fc = (p1 * ndiv * fc) / p2;

	/* Return clock in Hertz */
	return (fc / div) * 1000000;
}

/* query bus clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case 0x4716:
	case 0x4748:
	case 47162:
		return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
				      BCMA_CC_PMU5_MAINPLL_SSB);
	case 0x5356:
		return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
				      BCMA_CC_PMU5_MAINPLL_SSB);
	case 0x5357:
	case 0x4749:
		return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
				      BCMA_CC_PMU5_MAINPLL_SSB);
	case 0x5300:
		return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
				      BCMA_CC_PMU5_MAINPLL_SSB);
	case 53572:
		return 75000000;
	default:
		pr_warn("No backplane clock specified for %04X device, "
			"pmu rev. %d, using default %d Hz\n",
			bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
	}
	return BCMA_CC_PMU_HT_CLOCK;
}

/* query cpu clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	if (bus->chipinfo.id == 53572)
		return 300000000;

	if (cc->pmu.rev >= 5) {
		u32 pll;
		switch (bus->chipinfo.id) {
		case 0x5356:
			pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
			break;
		case 0x5357:
		case 0x4749:
			pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
			break;
		default:
			pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
			break;
		}

		/* TODO: if (bus->chipinfo.id == 0x5300)
		  return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
		return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
	}

	return bcma_pmu_get_clockcontrol(cc);
}
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* ChipCommon Power Management Unit driver
	4	*
eb032b98	5	* Copyright 2009, Michael Buesch <m@bues.ch>
8369ae33 RM	6	* Copyright 2007, Broadcom Corporation
	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
	11	#include "bcma_private.h"
44a8e377	12	#include <linux/export.h>
8369ae33 RM	13	#include <linux/bcma/bcma.h>
8369ae33 RM	14
908debc8 HM	15	static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
	16	{
	17	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	18	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	19	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
	20	}
	21
3861b2c5	22	void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
8369ae33	23	{
3861b2c5 RM	24	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	25	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	26	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
	27	}
	28	EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
8369ae33	29
3861b2c5 RM	30	void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
	31	u32 set)
	32	{
	33	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	34	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	35	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
	36	}
	37	EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
	38
	39	void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
	40	u32 offset, u32 mask, u32 set)
	41	{
8369ae33 RM	42	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
8369ae33 RM	43	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
3861b2c5 RM	44	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
	45	}
	46	EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
	47
	48	void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
	49	u32 set)
	50	{
	51	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
	52	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
	53	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
8369ae33	54	}
3861b2c5	55	EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
8369ae33 RM	56
	57	static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
	58	{
	59	struct bcma_bus *bus = cc->core->bus;
	60
	61	switch (bus->chipinfo.id) {
	62	case 0x4313:
	63	case 0x4331:
	64	case 43224:
	65	case 43225:
	66	break;
	67	default:
	68	pr_err("PLL init unknown for device 0x%04X\n",
	69	bus->chipinfo.id);
	70	}
	71	}
	72
	73	static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
	74	{
	75	struct bcma_bus *bus = cc->core->bus;
	76	u32 min_msk = 0, max_msk = 0;
	77
	78	switch (bus->chipinfo.id) {
	79	case 0x4313:
	80	min_msk = 0x200D;
	81	max_msk = 0xFFFF;
	82	break;
0d33cd78	83	case 0x4331:
8369ae33	84	case 43224:
91fa4b0a	85	case 43225:
8369ae33 RM	86	break;
	87	default:
	88	pr_err("PMU resource config unknown for device 0x%04X\n",
	89	bus->chipinfo.id);
	90	}
	91
	92	/* Set the resource masks. */
	93	if (min_msk)
	94	bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
	95	if (max_msk)
	96	bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
	97	}
	98
	99	void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
	100	{
	101	struct bcma_bus *bus = cc->core->bus;
	102
	103	switch (bus->chipinfo.id) {
	104	case 0x4313:
	105	case 0x4331:
	106	case 43224:
91fa4b0a	107	case 43225:
8369ae33 RM	108	break;
	109	default:
	110	pr_err("PMU switch/regulators init unknown for device "
	111	"0x%04X\n", bus->chipinfo.id);
	112	}
	113	}
	114
984e5bef RM	115	/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
	116	void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
	117	{
	118	struct bcma_bus *bus = cc->core->bus;
	119	u32 val;
	120
	121	val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
	122	if (enable) {
	123	val \|= BCMA_CHIPCTL_4331_EXTPA_EN;
	124	if (bus->chipinfo.pkg == 9 \|\| bus->chipinfo.pkg == 11)
	125	val \|= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	126	} else {
	127	val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
	128	val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	129	}
	130	bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
	131	}
	132
8369ae33 RM	133	void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
	134	{
	135	struct bcma_bus *bus = cc->core->bus;
	136
	137	switch (bus->chipinfo.id) {
	138	case 0x4313:
	139	bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
	140	break;
	141	case 0x4331:
69aaedd3 SF	142	case 43431:
	143	/* Ext PA lines must be enabled for tx on BCM4331 */
	144	bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
8369ae33 RM	145	break;
	146	case 43224:
	147	if (bus->chipinfo.rev == 0) {
	148	pr_err("Workarounds for 43224 rev 0 not fully "
	149	"implemented\n");
898f699e	150	bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
8369ae33 RM	151	} else {
	152	bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
	153	}
	154	break;
91fa4b0a RM	155	case 43225:
91fa4b0a RM	156	break;
8369ae33 RM	157	default:
	158	pr_err("Workarounds unknown for device 0x%04X\n",
	159	bus->chipinfo.id);
	160	}
	161	}
	162
	163	void bcma_pmu_init(struct bcma_drv_cc *cc)
	164	{
	165	u32 pmucap;
	166
	167	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
	168	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
	169
	170	pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
	171	pmucap);
	172
	173	if (cc->pmu.rev == 1)
	174	bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
	175	~BCMA_CC_PMU_CTL_NOILPONW);
	176	else
	177	bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
	178	BCMA_CC_PMU_CTL_NOILPONW);
	179
	180	if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
	181	pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
	182
	183	bcma_pmu_pll_init(cc);
	184	bcma_pmu_resources_init(cc);
	185	bcma_pmu_swreg_init(cc);
	186	bcma_pmu_workarounds(cc);
	187	}
e3afe0e5 HM	188
	189	u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
	190	{
	191	struct bcma_bus *bus = cc->core->bus;
	192
	193	switch (bus->chipinfo.id) {
	194	case 0x4716:
	195	case 0x4748:
	196	case 47162:
	197	case 0x4313:
	198	case 0x5357:
	199	case 0x4749:
	200	case 53572:
	201	/* always 20Mhz */
	202	return 20000 * 1000;
	203	case 0x5356:
	204	case 0x5300:
	205	/* always 25Mhz */
	206	return 25000 * 1000;
	207	default:
	208	pr_warn("No ALP clock specified for %04X device, "
	209	"pmu rev. %d, using default %d Hz\n",
	210	bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
	211	}
	212	return BCMA_CC_PMU_ALP_CLOCK;
	213	}
908debc8 HM	214
	215	/* Find the output of the "m" pll divider given pll controls that start with
	216	* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
	217	*/
	218	static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
	219	{
	220	u32 tmp, div, ndiv, p1, p2, fc;
	221	struct bcma_bus *bus = cc->core->bus;
	222
	223	BUG_ON((pll0 & 3) \|\| (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
	224
	225	BUG_ON(!m \|\| m > 4);
	226
	227	if (bus->chipinfo.id == 0x5357 \|\| bus->chipinfo.id == 0x4749) {
	228	/* Detect failure in clock setting */
	229	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	230	if (tmp & 0x40000)
	231	return 133 * 1000000;
	232	}
	233
	234	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
	235	p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
	236	p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
	237
	238	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
	239	div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
	240	BCMA_CC_PPL_MDIV_MASK;
	241
	242	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
	243	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
	244
	245	/* Do calculation in Mhz */
	246	fc = bcma_pmu_alp_clock(cc) / 1000000;
	247	fc = (p1 * ndiv * fc) / p2;
	248
	249	/* Return clock in Hertz */
	250	return (fc / div) * 1000000;
	251	}
	252
	253	/* query bus clock frequency for PMU-enabled chipcommon */
	254	u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
	255	{
	256	struct bcma_bus *bus = cc->core->bus;
	257
	258	switch (bus->chipinfo.id) {
	259	case 0x4716:
	260	case 0x4748:
	261	case 47162:
	262	return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
	263	BCMA_CC_PMU5_MAINPLL_SSB);
	264	case 0x5356:
	265	return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
	266	BCMA_CC_PMU5_MAINPLL_SSB);
	267	case 0x5357:
	268	case 0x4749:
	269	return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
	270	BCMA_CC_PMU5_MAINPLL_SSB);
	271	case 0x5300:
	272	return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
	273	BCMA_CC_PMU5_MAINPLL_SSB);
	274	case 53572:
	275	return 75000000;
	276	default:
	277	pr_warn("No backplane clock specified for %04X device, "
278	"pmu rev. %d, using default %d Hz\n",
279	bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
280	}
281	return BCMA_CC_PMU_HT_CLOCK;
282	}
283
284	/* query cpu clock frequency for PMU-enabled chipcommon */
285	u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
286	{
287	struct bcma_bus *bus = cc->core->bus;
288
289	if (bus->chipinfo.id == 53572)
290	return 300000000;
291
292	if (cc->pmu.rev >= 5) {
293	u32 pll;
294	switch (bus->chipinfo.id) {
295	case 0x5356:
296	pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
297	break;
298	case 0x5357:
299	case 0x4749:
300	pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
301	break;
302	default:
303	pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
304	break;
305	}
306
307	/* TODO: if (bus->chipinfo.id == 0x5300)
308	return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
309	return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
310	}
311
312	return bcma_pmu_get_clockcontrol(cc);
313	}