[deliverable/linux.git] / drivers / bcma / driver_pci.c

/*
 * Broadcom specific AMBA
 * PCI Core
 *
 * Copyright 2005, 2011, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/export.h>
#include <linux/bcma/bcma.h>

/**************************************************
 * R/W ops.
 **************************************************/

u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
{
	pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
	pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
	return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
}

static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
{
	pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
	pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
	pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
}

static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
{
	u32 v;
	int i;

	v = BCMA_CORE_PCI_MDIODATA_START;
	v |= BCMA_CORE_PCI_MDIODATA_WRITE;
	v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
	      BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
	v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
	      BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
	v |= BCMA_CORE_PCI_MDIODATA_TA;
	v |= (phy << 4);
	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);

	udelay(10);
	for (i = 0; i < 200; i++) {
		v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
		if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
			break;
		usleep_range(1000, 2000);
	}
}

static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
{
	int max_retries = 10;
	u16 ret = 0;
	u32 v;
	int i;

	/* enable mdio access to SERDES */
	v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
	v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);

	if (pc->core->id.rev >= 10) {
		max_retries = 200;
		bcma_pcie_mdio_set_phy(pc, device);
		v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
		     BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
		v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
	} else {
		v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
		v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
	}

	v = BCMA_CORE_PCI_MDIODATA_START;
	v |= BCMA_CORE_PCI_MDIODATA_READ;
	v |= BCMA_CORE_PCI_MDIODATA_TA;

	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
	/* Wait for the device to complete the transaction */
	udelay(10);
	for (i = 0; i < max_retries; i++) {
		v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
		if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
			udelay(10);
			ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
			break;
		}
		usleep_range(1000, 2000);
	}
	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
	return ret;
}

static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
				u8 address, u16 data)
{
	int max_retries = 10;
	u32 v;
	int i;

	/* enable mdio access to SERDES */
	v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
	v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);

	if (pc->core->id.rev >= 10) {
		max_retries = 200;
		bcma_pcie_mdio_set_phy(pc, device);
		v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
		     BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
		v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
	} else {
		v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
		v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
	}

	v = BCMA_CORE_PCI_MDIODATA_START;
	v |= BCMA_CORE_PCI_MDIODATA_WRITE;
	v |= BCMA_CORE_PCI_MDIODATA_TA;
	v |= data;
	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
	/* Wait for the device to complete the transaction */
	udelay(10);
	for (i = 0; i < max_retries; i++) {
		v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
		if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
			break;
		usleep_range(1000, 2000);
	}
	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
}

static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
				    u8 address, u16 data)
{
	bcma_pcie_mdio_write(pc, device, address, data);
	return bcma_pcie_mdio_read(pc, device, address);
}

/**************************************************
 * Workarounds.
 **************************************************/

static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
{
	u32 tmp;

	tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
	if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
		return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
		       BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
	else
		return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
}

static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
{
	u16 tmp;

	bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
	                     BCMA_CORE_PCI_SERDES_RX_CTRL,
			     bcma_pcicore_polarity_workaround(pc));
	tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
	                          BCMA_CORE_PCI_SERDES_PLL_CTRL);
	if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
		bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
		                     BCMA_CORE_PCI_SERDES_PLL_CTRL,
		                     tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
}

static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
{
	struct bcma_device *core = pc->core;
	u16 val16, core_index;
	uint regoff;

	regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
	core_index = (u16)core->core_index;

	val16 = pcicore_read16(pc, regoff);
	if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
	     != core_index) {
		val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
			(val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
		pcicore_write16(pc, regoff, val16);
	}
}

/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
/* Needs to happen when coming out of 'standby'/'hibernate' */
static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
{
	u16 val16;
	uint regoff;

	regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);

	val16 = pcicore_read16(pc, regoff);

	if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
		val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
		pcicore_write16(pc, regoff, val16);
	}
}

static void bcma_core_pci_power_save(struct bcma_drv_pci *pc, bool up)
{
	u16 data;

	if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
		data = up ? 0x74 : 0x7C;
		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
					 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
					 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
	} else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
		data = up ? 0x75 : 0x7D;
		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
					 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
					 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
	}
}

/**************************************************
 * Init.
 **************************************************/

static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
{
	bcma_core_pci_fixcfg(pc);
	bcma_pcicore_serdes_workaround(pc);
	bcma_core_pci_config_fixup(pc);
}

void bcma_core_pci_init(struct bcma_drv_pci *pc)
{
	if (pc->setup_done)
		return;

#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
	pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
	if (pc->hostmode)
		bcma_core_pci_hostmode_init(pc);
#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */

	if (!pc->hostmode)
		bcma_core_pci_clientmode_init(pc);
}

int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
			  bool enable)
{
	struct pci_dev *pdev;
	u32 coremask, tmp;
	int err = 0;

	if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
		/* This bcma device is not on a PCI host-bus. So the IRQs are
		 * not routed through the PCI core.
		 * So we must not enable routing through the PCI core. */
		goto out;
	}

	pdev = pc->core->bus->host_pci;

	err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
	if (err)
		goto out;

	coremask = BIT(core->core_index) << 8;
	if (enable)
		tmp |= coremask;
	else
		tmp &= ~coremask;

	err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);

out:
	return err;
}
EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);

static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
{
	u32 w;

	w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
	if (extend)
		w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
	else
		w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
	bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
	bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
}

void bcma_core_pci_up(struct bcma_bus *bus)
{
	struct bcma_drv_pci *pc;

	if (bus->hosttype != BCMA_HOSTTYPE_PCI)
		return;

	pc = &bus->drv_pci[0];

	bcma_core_pci_power_save(pc, true);

	bcma_core_pci_extend_L1timer(pc, true);
}
EXPORT_SYMBOL_GPL(bcma_core_pci_up);

void bcma_core_pci_down(struct bcma_bus *bus)
{
	struct bcma_drv_pci *pc;

	if (bus->hosttype != BCMA_HOSTTYPE_PCI)
		return;

	pc = &bus->drv_pci[0];

	bcma_core_pci_extend_L1timer(pc, false);

	bcma_core_pci_power_save(pc, false);
}
EXPORT_SYMBOL_GPL(bcma_core_pci_down);
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* PCI Core
	4	*
49dc9577	5	* Copyright 2005, 2011, Broadcom Corporation
eb032b98	6	* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2be25cac	7	* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
8369ae33 RM	8	*
	9	* Licensed under the GNU/GPL. See COPYING for details.
	10	*/
	11
	12	#include "bcma_private.h"
44a8e377	13	#include <linux/export.h>
8369ae33 RM	14	#include <linux/bcma/bcma.h>
	15
	16	/**************************************************
	17	* R/W ops.
	18	**************************************************/
	19
4b259a5c	20	u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
8369ae33	21	{
2be25cac HM	22	pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
	23	pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
	24	return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
8369ae33 RM	25	}
8369ae33 RM	26
8369ae33 RM	27	static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
8369ae33 RM	28	{
2be25cac HM	29	pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
	30	pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
	31	pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
8369ae33	32	}
8369ae33	33
521deea6	34	static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
8369ae33	35	{
8369ae33 RM	36	u32 v;
	37	int i;
	38
2be25cac HM	39	v = BCMA_CORE_PCI_MDIODATA_START;
	40	v \|= BCMA_CORE_PCI_MDIODATA_WRITE;
	41	v \|= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
	42	BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
	43	v \|= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
	44	BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
	45	v \|= BCMA_CORE_PCI_MDIODATA_TA;
8369ae33	46	v \|= (phy << 4);
2be25cac	47	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
8369ae33 RM	48
	49	udelay(10);
	50	for (i = 0; i < 200; i++) {
2be25cac HM	51	v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
2be25cac HM	52	if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
8369ae33	53	break;
1fd41a65	54	usleep_range(1000, 2000);
8369ae33 RM	55	}
	56	}
	57
521deea6	58	static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
8369ae33	59	{
8369ae33 RM	60	int max_retries = 10;
	61	u16 ret = 0;
	62	u32 v;
	63	int i;
	64
2be25cac HM	65	/* enable mdio access to SERDES */
	66	v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
	67	v \|= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
	68	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
8369ae33 RM	69
	70	if (pc->core->id.rev >= 10) {
	71	max_retries = 200;
	72	bcma_pcie_mdio_set_phy(pc, device);
2be25cac HM	73	v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
	74	BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
	75	v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
	76	} else {
	77	v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
	78	v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
8369ae33 RM	79	}
8369ae33 RM	80
2be25cac HM	81	v = BCMA_CORE_PCI_MDIODATA_START;
	82	v \|= BCMA_CORE_PCI_MDIODATA_READ;
	83	v \|= BCMA_CORE_PCI_MDIODATA_TA;
	84
	85	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
8369ae33 RM	86	/* Wait for the device to complete the transaction */
8369ae33 RM	87	udelay(10);
f1a9c1e6	88	for (i = 0; i < max_retries; i++) {
2be25cac HM	89	v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
2be25cac HM	90	if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
8369ae33	91	udelay(10);
2be25cac	92	ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
8369ae33 RM	93	break;
8369ae33 RM	94	}
1fd41a65	95	usleep_range(1000, 2000);
8369ae33	96	}
2be25cac	97	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
8369ae33 RM	98	return ret;
	99	}
	100
521deea6	101	static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
8369ae33 RM	102	u8 address, u16 data)
8369ae33 RM	103	{
8369ae33 RM	104	int max_retries = 10;
	105	u32 v;
	106	int i;
	107
2be25cac HM	108	/* enable mdio access to SERDES */
	109	v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
	110	v \|= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
	111	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
8369ae33 RM	112
	113	if (pc->core->id.rev >= 10) {
	114	max_retries = 200;
	115	bcma_pcie_mdio_set_phy(pc, device);
2be25cac HM	116	v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
	117	BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
	118	v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
	119	} else {
	120	v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
	121	v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
8369ae33 RM	122	}
8369ae33 RM	123
2be25cac HM	124	v = BCMA_CORE_PCI_MDIODATA_START;
	125	v \|= BCMA_CORE_PCI_MDIODATA_WRITE;
	126	v \|= BCMA_CORE_PCI_MDIODATA_TA;
8369ae33	127	v \|= data;
2be25cac	128	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
8369ae33 RM	129	/* Wait for the device to complete the transaction */
	130	udelay(10);
	131	for (i = 0; i < max_retries; i++) {
2be25cac HM	132	v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
2be25cac HM	133	if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
8369ae33	134	break;
1fd41a65	135	usleep_range(1000, 2000);
8369ae33	136	}
2be25cac	137	pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
8369ae33 RM	138	}
8369ae33 RM	139
521deea6 HM	140	static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
	141	u8 address, u16 data)
	142	{
	143	bcma_pcie_mdio_write(pc, device, address, data);
	144	return bcma_pcie_mdio_read(pc, device, address);
	145	}
	146
8369ae33 RM	147	/**************************************************
	148	* Workarounds.
	149	**************************************************/
	150
	151	static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
	152	{
2be25cac HM	153	u32 tmp;
	154
	155	tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
	156	if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
	157	return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE \|
	158	BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
	159	else
	160	return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
8369ae33 RM	161	}
	162
	163	static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
	164	{
8369ae33 RM	165	u16 tmp;
8369ae33 RM	166
2be25cac HM	167	bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
	168	BCMA_CORE_PCI_SERDES_RX_CTRL,
	169	bcma_pcicore_polarity_workaround(pc));
	170	tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
	171	BCMA_CORE_PCI_SERDES_PLL_CTRL);
	172	if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
	173	bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
	174	BCMA_CORE_PCI_SERDES_PLL_CTRL,
	175	tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
8369ae33 RM	176	}
8369ae33 RM	177
ec00f373 HM	178	static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
	179	{
	180	struct bcma_device *core = pc->core;
	181	u16 val16, core_index;
	182	uint regoff;
	183
	184	regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
	185	core_index = (u16)core->core_index;
	186
	187	val16 = pcicore_read16(pc, regoff);
	188	if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
	189	!= core_index) {
	190	val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) \|
	191	(val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
	192	pcicore_write16(pc, regoff, val16);
	193	}
	194	}
	195
2b2715b8 HM	196	/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
	197	/* Needs to happen when coming out of 'standby'/'hibernate' */
	198	static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
	199	{
	200	u16 val16;
	201	uint regoff;
	202
	203	regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
	204
	205	val16 = pcicore_read16(pc, regoff);
	206
	207	if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
	208	val16 \|= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
	209	pcicore_write16(pc, regoff, val16);
	210	}
	211	}
	212
521deea6 HM	213	static void bcma_core_pci_power_save(struct bcma_drv_pci *pc, bool up)
	214	{
	215	u16 data;
	216
	217	if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
	218	data = up ? 0x74 : 0x7C;
	219	bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
	220	BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
	221	bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
	222	BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
	223	} else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
	224	data = up ? 0x75 : 0x7D;
	225	bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
	226	BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
	227	bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
	228	BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
	229	}
	230	}
	231
8369ae33 RM	232	/**************************************************
	233	* Init.
	234	**************************************************/
	235
0f58a01d	236	static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
8369ae33	237	{
ec00f373	238	bcma_core_pci_fixcfg(pc);
8369ae33	239	bcma_pcicore_serdes_workaround(pc);
2b2715b8	240	bcma_core_pci_config_fixup(pc);
8369ae33	241	}
1de520f4	242
0f58a01d	243	void bcma_core_pci_init(struct bcma_drv_pci *pc)
9352f69c	244	{
517f43e5 HM	245	if (pc->setup_done)
	246	return;
	247
9352f69c	248	#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
49dc9577 HM	249	pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
49dc9577 HM	250	if (pc->hostmode)
9352f69c	251	bcma_core_pci_hostmode_init(pc);
9352f69c	252	#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
517f43e5	253
49dc9577 HM	254	if (!pc->hostmode)
49dc9577 HM	255	bcma_core_pci_clientmode_init(pc);
9352f69c RM	256	}
9352f69c RM	257
1de520f4 RM	258	int bcma_core_pci_irq_ctl(struct bcma_drv_pci pc, struct bcma_device core,
	259	bool enable)
	260	{
e7027075	261	struct pci_dev *pdev;
1de520f4	262	u32 coremask, tmp;
ecd177c2 HM	263	int err = 0;
ecd177c2 HM	264
e7027075	265	if (!pc \|\| core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
ecd177c2 HM	266	/* This bcma device is not on a PCI host-bus. So the IRQs are
	267	* not routed through the PCI core.
	268	* So we must not enable routing through the PCI core. */
	269	goto out;
	270	}
1de520f4	271
e7027075 HM	272	pdev = pc->core->bus->host_pci;
e7027075 HM	273
1de520f4 RM	274	err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
	275	if (err)
	276	goto out;
	277
	278	coremask = BIT(core->core_index) << 8;
	279	if (enable)
	280	tmp \|= coremask;
	281	else
	282	tmp &= ~coremask;
	283
	284	err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
	285
	286	out:
	287	return err;
	288	}
440ca98f	289	EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
29f6b3d8	290
780335ac	291	static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
29f6b3d8 HM	292	{
	293	u32 w;
	294
	295	w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
	296	if (extend)
	297	w \|= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
	298	else
	299	w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
	300	bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
	301	bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
	302	}
cfe51ec1 HM	303
	304	void bcma_core_pci_up(struct bcma_bus *bus)
	305	{
	306	struct bcma_drv_pci *pc;
	307
	308	if (bus->hosttype != BCMA_HOSTTYPE_PCI)
	309	return;
	310
	311	pc = &bus->drv_pci[0];
	312
521deea6 HM	313	bcma_core_pci_power_save(pc, true);
521deea6 HM	314
cfe51ec1 HM	315	bcma_core_pci_extend_L1timer(pc, true);
	316	}
	317	EXPORT_SYMBOL_GPL(bcma_core_pci_up);
	318
	319	void bcma_core_pci_down(struct bcma_bus *bus)
	320	{
	321	struct bcma_drv_pci *pc;
	322
	323	if (bus->hosttype != BCMA_HOSTTYPE_PCI)
	324	return;
	325
	326	pc = &bus->drv_pci[0];
	327
	328	bcma_core_pci_extend_L1timer(pc, false);
521deea6 HM	329
521deea6 HM	330	bcma_core_pci_power_save(pc, false);
cfe51ec1 HM	331	}
cfe51ec1 HM	332	EXPORT_SYMBOL_GPL(bcma_core_pci_down);